Packaging structure for efficient heat dissipation

Abstract

The invention relates to a packaging structure for efficient heat dissipation. In an example, a package (104) includes a substrate (211) including a conductive member (212) coupled to a conductive terminal (214), where the conductive terminal is exposed to an exterior of the package. The package also includes a first semiconductor die (200) having a first device side and a first non-device side, where the first device side is coupled to the substrate and the first non-device side is opposite the first device side, and where the first device side has circuitry formed therein. The package also includes a second semiconductor die (202) having a second device side and a second non-device side, where the second device side is coupled to the substrate and the second non-device side is opposite the second device side, and where the second device side has circuitry formed therein. The package also includes a first adhesive layer (217) and a second adhesive layer (216) contacting the first non-device side and the second non-device side, respectively. The package also includes: a passivated overcoat PO layer (218) contacting the first adhesive layer and the second adhesive layer; and a semiconductor layer (220) contacting the PO layer and exposed to the outside of the package.

Description

Technical Field

[0001] The present disclosure relates to a packaging structure for efficient heat dissipation. Background Art

[0002] A semiconductor wafer is a circular piece of semiconductor material, such as silicon, used to make semiconductor chips. In general, complex manufacturing processes are used to form many integrated circuits on a single wafer. Forming such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is cut into multiple pieces, called semiconductor dies, where each die contains one of the circuits. Cutting or sawing the wafer into individual dies is called singulation. The dies can then be coupled to a lead frame, covered by a molding compound, and sawn into individual packages. Summary of the invention

[0003] In an example, a package includes a substrate including a conductive member coupled to a conductive terminal, wherein the conductive terminal is exposed to the outside of the package. The package also includes a first semiconductor die having a first device side and a first non-device side, wherein the first device side is coupled to the substrate and the first non-device side is opposite to the first device side, and wherein the first device side has a circuit system formed therein. The package also includes a second semiconductor die having a second device side and a second non-device side, wherein the second device side is coupled to the substrate and the second non-device side is opposite to the second device side, and wherein the second device side has a circuit system formed therein. The package also includes a first adhesive layer and a second adhesive layer contacting the first non-device side and the second non-device side, respectively. The package also includes: a passivation overcoat (PO) layer contacting the first adhesive layer and the second adhesive layer; and a semiconductor layer contacting the PO layer and exposed to the outside of the package.

[0004] In an example, a method of manufacturing a package includes coupling a device side of a semiconductor die to a substrate, wherein the device side has a circuit system formed therein, and wherein the substrate includes a conductive terminal exposed to the outside of the substrate. The method includes applying an adhesive layer on a non-device side of the die opposite the device side of the die. The method also includes applying a passivation overcoat (PO) layer on the adhesive layer, wherein the semiconductor layer contacts the PO layer. The method also includes covering the substrate, the semiconductor die, the PO layer, and the semiconductor layer with a molding compound, wherein a top surface of the semiconductor layer is exposed to a top surface of the molding compound. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an electronic device including a package having a structure that provides efficient heat dissipation according to various examples.

[0006] Figure 2A is a cutaway, cross-sectional view of a package having a structure that provides efficient heat dissipation according to various examples.

[0007] Figure 2B A top-down view of a package having a structure providing efficient heat dissipation according to various embodiments.

[0008] Figure 2C is a perspective view of a package having a structure providing efficient heat dissipation according to various examples.

[0009] Figure 2D is another perspective view of a package having a structure providing efficient heat dissipation according to various embodiments.

[0010] Figure 3A Cutaway, cross-sectional views of packages with structures providing efficient heat dissipation according to various examples.

[0011] Figure 3B A top-down view of a package having a structure providing efficient heat dissipation according to various embodiments.

[0012] Figure 3C is a perspective view of a package having a structure providing efficient heat dissipation according to various examples.

[0013] Figure 3D is another perspective view of a package having a structure providing efficient heat dissipation according to various embodiments.

[0014] Figure 4 is a flow chart of a method for manufacturing a package having a structure providing efficient heat dissipation according to various examples.

[0015] Figures 5A1 to 5D3 A process flow for manufacturing a package having a structure that provides efficient heat dissipation according to various examples is provided. DETAILED DESCRIPTION

[0016] Semiconductor dies generate a lot of heat. For example, some dies may be used as high-side or low-side field effect transistor (FET) switches, and the fast switching action of such switches and the high currents passing through the switches may generate a lot of heat. Other types of dies, such as those that include controller circuitry, may also generate a lot of heat during operation. Dissipating this heat from the package may be challenging because the die inside the package is covered by a molding compound and may be surrounded by various other package components. If not removed from the package, the heat may compromise the structural and functional integrity of the package. In some cases, the heat level is not high enough to cause package damage, but reducing heat is still useful because technical advantages such as compensated increases in die power and performance or compensated reductions in die and package size may be achieved.

[0017] Some solutions require the use of a metal heat sink coupled to the non-device side of the die. The heat sink is coupled to the die through a thermal interface material (TIM). This solution has a large number of technical disadvantages and challenges. First, the size of the die limits how many heat sinks can be used to dissipate heat. This is because the TIM has a poor thermal conductivity (e.g., 1 to 10 watts per meter per Kelvin) and a significant thickness (roughly 500 microns). Secondly, expanding the size of the die to increase the contact area between the die and the TIM is not a feasible method to increase heat dissipation. This is because increasing the die size is inefficient, costly, and takes up excess space. Third, the combination of the TIM and the heat sink is sufficiently conductive that it cannot be coupled to multiple die in the package to prevent the die from establishing electrical contact with each other, thereby causing electrical shorts and functional damage. Therefore, if there are multiple die in the package that generates heat, only one of the die can be coupled to the heat sink for heat dissipation.

[0018] The present disclosure describes various examples of packages with structures for efficient heat dissipation. In some examples, the package includes a substrate, the substrate including a conductive member coupled to a conductive terminal. The conductive terminal is exposed to the outside of the package. The package also includes a first semiconductor die having a first device side and a first non-device side, wherein the first device side is coupled to the substrate and the first non-device side is opposite to the first device side. The first device side has a circuit system formed therein. The package also includes a second semiconductor die having a second device side and a second non-device side. The second device side is coupled to the substrate and the second non-device side is opposite to the second device side. The second device side has a circuit system formed therein. The package includes a first adhesive layer and a second adhesive layer contacting the first non-device side and the second non-device side, respectively. The package includes a passivation outer coating (PO) layer contacting the first adhesive layer and the second adhesive layer. The package includes a semiconductor layer contacting the PO layer and exposed to the outside of the package.

[0019] Figure 1 1 is a block diagram of an electronic device 100 containing a package having a structure providing efficient heat dissipation according to various examples. More specifically, the electronic device 100 includes a printed circuit board (PCB) 102 on which a semiconductor package 104 is mounted, such as a semiconductor package including a structure providing efficient heat dissipation. The electronic device 100 may be any suitable type of device, such as a computer (e.g., a laptop computer, a desktop computer, a notebook computer, a tablet computer, a smartphone), a consumer electronic device (e.g., a television, an audio device, a security system), an electrical device, an automobile, an aircraft, a spacecraft, etc., but the scope of the present disclosure is not limited thereto, and the semiconductor package 104 may be used in any of the various situations not explicitly mentioned herein.

[0020] Figure 2A1 is a cross-sectional, cross-sectional view of a semiconductor package 104 having a structure that provides efficient heat dissipation according to various examples. The example semiconductor package 104 includes semiconductor dies (sometimes referred to as "dies") 200 and 202. The semiconductor package 104 may include additional dies, examples of which are described in Figure 2B . The description provided herein with reference to die 200 and 202 also applies to other one or more dies that may be included in semiconductor package 104. Dies 200 and 202 may be of any suitable type and may be configured to perform any of a variety of operations. In an example, die 200, 202 may be gallium nitride FET dies, such as high-side FET or low-side FET switches. Dies 200, 202 may be used for power applications. Dies 200, 202 may contain controller circuitry and may include silicon and / or gallium nitride controller dies. For example, die 200 may be a gallium nitride or silicon controller die that is configured to control the operation (e.g., switching action) of die 202, which may be a gallium nitride or silicon die. Dies 200, 202 may perform the same or different operations and may contain the same or different types of semiconductor materials (e.g., silicon, gallium nitride).

[0021] Dies 200, 202 include a device side and a non-device side. The device side of dies 200, 202 includes circuitry formed on and / or in the device side. The non-device side does not contain circuitry and is opposite the device side. Figure 2A , the dies 200, 202 are oriented such that the device sides of the dies are facing downward and the non-device sides are facing upward.

[0022] The device sides of the dies 200, 202 are coupled to metal pillars 204 and 208, respectively. Each of the dies 200, 202 may be coupled to a plurality of such metal pillars. The metal pillars 204, 208 may be coupled to the circuitry of the dies 200, 202, respectively. Solder bumps 206, 210 couple the metal pillars 204, 208 to a network of conductive members 212 located within a substrate 211. The network of conductive members 212 is coupled to conductive terminals 214, which are exposed to one or more external surfaces of the semiconductor package 104. In this manner, an electrical path is established between the circuitry of the dies 200, 202 to the conductive terminals 214. Not all portions of the conductive terminals 214 are visible in the drawing because the conductive terminals 214 extend in various directions and not all such directions are visible in the cross-sectional slice. In addition, the substrate 211 is at least Figure 2B and 2C The substrate 211 includes an insulating material 213 (eg, Aggregate film (ABF).

[0023] The die 200, 202 may be solder bumped and ground so that the non-device sides (i.e., surfaces) of the die 200, 202 are horizontally coplanar. In other words, the non-device sides (i.e., surfaces) of the die 200, 202 are at the same height relative to the top surface of the substrate 211. This may be achieved by controlling the thickness of the solder bumps 206, 210 to be the same; the thickness of the metal pillars 204, 208 to be the same; and the thickness of the die 200, 202 to be the same. Alternatively, the various thicknesses of these structures may vary, but the combined thickness of each set of solder bumps, metal pillars, and die may still be the same as the combined thickness of another set of solder bumps, metal pillars, and die.

[0024] In an example, semiconductor package 104 includes adhesive layers 216, 217. Adhesive layer 216 contacts the non-device side of die 202. Adhesive layer 217 contacts the non-device side of die 200. Adhesive layers 216, 217 may include any suitable thermally conductive adhesive. Preferably, adhesive layers 216, 217 are highly thermally conductive and minimally electrically conductive. In an example, adhesive layers 216 and / or 217 are thermally conductive epoxy materials, solder, or silver sintered materials. Adhesive layer 216 may be different from adhesive layer 217. The thickness of each adhesive layer 216, 217 is in the range of 10 microns to 50 microns, wherein a thickness below this range is disadvantageous because it is unacceptable to use an adhesive layer to compensate for thickness variations in the die stack of package 104 (e.g., a stack comprising die 200, metal pillars 204, solder bumps 206, etc.; a stack comprising die 202, metal pillars 208, solder bumps 210, etc.; etc.), and wherein a thickness above this range is disadvantageous due to the thermal degradation caused within package 104.

[0025] Semiconductor package 104 includes a heat dissipation member (HDM) 218. HDM 218 contacts both adhesive layers 216, 217, as well as any other adhesive layers that may be present in semiconductor package 104 and contact the die in semiconductor package 104. However, in some examples, multiple HDMs 218 may be used, wherein each HDM 218 contacts at least one adhesive layer within semiconductor package 104. The remainder of this description assumes the inclusion of a single HDM 218, but the scope of the present disclosure is not limited thereto. HDM 218 may be a passivation overcoat (PO) layer such as silicon nitride, silicon oxide, silicon dioxide, polymer film, silicon oxynitride, and other suitable materials. HDM 218 preferably has high thermal conductivity and minimal electrical conductivity. Depending on the electrical isolation voltage (and resistivity) required to electrically isolate die 200, 202 from each other, the critical range of thickness of HDM 218 is between 1 micron and 4 microns. If only one die in semiconductor package 104 is coupled to HDM 218, the thickness of HDM 218 may be at the lower end of the critical range, such as 1 micron. If multiple die in semiconductor package 104 are coupled to HDM 218, there is a risk of shorting between the die, and the thickness of HDM 218 may be at the upper end of the critical range, such as at 3 microns or 4 microns. Compared to a TIM that is typically about 500 microns thick as described above, a HDM 218 between 1 and 4 microns thick exhibits significantly greater thermal conductivity.

[0026] The semiconductor package 104 includes a heat dissipation member (HDM) 220. The HDM 220 contacts the HDM 218. If there are multiple HDMs 218, the HDM 220 contacts one or more of these HDMs 218. In an example, the semiconductor package 104 includes multiple HDMs 220. In this example, each HDM 220 contacts one or more HDMs 218. The remainder of this description assumes that a single HDM 220 is included, but the scope of the present disclosure is not limited to this. The HDM 220 can be a bulk (i.e., without other non-semiconductor materials formed or deposited) semiconductor material, such as silicon or gallium nitride. If the HDM 220 is a semiconductor material, its electrical conductivity is relatively low, while its thermal conductivity remains relatively high (at least 150 watts per meter per Kelvin (W / mK)). This enables the HDM 220 to effectively and efficiently dissipate heat while helping to maintain electrical isolation between the dies (e.g., dies 200, 202). In instances where semiconductor package 104 includes only one die or HDM 220 is coupled to only one die, HDM 220 may be a metal with high thermal and electrical conductivity, such as copper or aluminum. The increased conductivity does not pose a risk to the electrical isolation between the dies of semiconductor package 104 because, in such instances, HDM 220 is coupled to only a single die.

[0027] Still refer to Figure 2AIn operation, the die 200, 202 generates heat during operation. At least some of this heat is transferred to the bonding layers 216, 217. The bonding layers 216, 217 are strong thermal conductors and transfer the heat to the HDM 218. The HDM 218 is relatively thin, as described above within a critical thickness range of 1 micron to 4 microns. Therefore, the heat is efficiently transferred to the HDM 220 through the HDM 218. The HDM 220 is a strong thermal conductor and therefore radiates the heat into the atmosphere of the semiconductor package 104. Because the HDM 218 is so thin and therefore conducts heat efficiently, and because the HDM 220 is a strong thermal conductor, the heat generated by the die having even a small non-device side surface area can be spread across most or all of the HDMs 218 and 220, thus providing more effective and efficient cooling of the die 200, 202. Furthermore, because the HDMs 218 , 220 are not strong electrical conductors, and because the HDM 218 is sufficiently thick, the dies 200 , 202 maintain their respective electrical isolation, just like any other dies that may be present within the semiconductor package 104 .

[0028] Figure 2B Based on various examples Figure 2A 1. A top-down view of semiconductor package 104 of FIG. 104 includes a third die, as shown, and this third die may be configured similarly to dies 200, 202 as described above. Any number of dies may be included in semiconductor package 104. Figure 2B , the substrate 211 is opaque for easy understanding. Figure 2C Based on various examples Figure 2A A perspective view of a semiconductor package 104 is shown. Figure 2C , the substrate 211 is opaque for easy understanding. Figure 2D Based on various examples Figure 2A Another perspective view of semiconductor package 104 is shown.

[0029] Figure 3A FIG. 1 is a cross-sectional, cross-sectional view of a semiconductor package 104 having a structure that provides efficient heat dissipation according to various embodiments. The semiconductor package 104 may be Figures 2A to 2D 202, except that semiconductor package 104 contains only one die 202. In this example, as shown, the area of ​​HDM 218 is reduced. In addition, in this example, it is advantageous to position die 202 under the center or approximately the center of HDM 220 so that as much surface area of ​​HDM 220 as possible is available to die 202 to maximize heat dissipation from die 202. However, it is also possible to place die 202 under a non-center of HDM 220, such as Figure 3ABecause only one die 202 is included in semiconductor package 104, die 202 does not need to be electrically isolated from any other die. Therefore, HDM 218 can be as thin as 1 micron to facilitate heat dissipation from die 202. In addition, HDM 220 can be metal to facilitate heat dissipation from HDM 218 because electrical isolation between multiple dies is not a concern in this example.

[0030] Figure 3B Based on various examples Figure 3A FIG. 1 is a top-down view of a semiconductor package 104 . Figure 3C Based on various examples Figure 3A 1 is a perspective view of a semiconductor package 104. Figure 3D Based on various examples Figure 3A Another perspective view of semiconductor package 104 is shown.

[0031] Figure 4 4 is a flow chart of a method 400 for fabricating a package (eg, the example semiconductor package 104 described above) having a structure that provides efficient heat dissipation according to various examples. Figures 5A1 to 5D3 1 is a process flow for manufacturing a package having a structure that provides efficient heat dissipation (eg, the example semiconductor package 104 described above) according to various examples. Figure 4 and 5A1 To 5D3.

[0032] The method 400 includes controlling a first die bump height and a second die bump height (e.g., including metal pillars and solder bumps) and die thickness to be the same (402). The method 400 also includes coupling the first die and the second die to a substrate, wherein the device sides of the die face the substrate (404). More specifically, assuming that multiple die are included in a single semiconductor package 104, such as die 200, 202, the solder bumps 206, 210 may be controlled to be a consistent thickness; the metal pillars 204, 208 may be controlled to be a consistent thickness; and one or more of the die 200, 202 are ground so that the thickness of the die 200, 202 is also consistent. In this manner, when the die 200, 202 are coupled to the substrate 211, the non-device sides (i.e., surfaces) of the die 200, 202 will be coplanar with each other (i.e., have the same height relative to the top surface of the substrate 211). Figure 5A1 Dies 200 , 202 are depicted coupled to a substrate 211 with the aid of metal pillars 204 , 208 and solder bumps 206 , 210 , with the thickness of the solder bumps 206 , 210 , metal pillars 204 , 208 , and dies 200 , 202 being such that non-device surfaces of the dies 200 , 202 are coplanar. Figure 5A2 Based on various examples Figure 5A1 A top-down view of the structure. Figure 5A3Based on various examples Figure 5A1 perspective view of the structure.

[0033] The method 400 includes applying an adhesive on non-device sides of the first die and the second die ( 406 ). Figure 5B1 exhibit Figure 5A1 , but wherein adhesive layers 216, 217 are applied to the dies 202, 200, respectively. Figure 5B2 Based on various examples Figure 5B1 A top-down view of the structure. Figure 5B3 Based on various examples Figure 5B1 perspective view of the structure.

[0034] The method 400 includes coupling a HDM (eg, a semiconductor layer) to an adhesion layer using another HDM (eg, a PO layer) (408). Fig.5C1 exhibit Figure 5B1 216, 217. In one example, HDM 218 is applied to adhesive layers 216, 217 followed by HDM 220. In other examples, HDM 218 is coupled to HDM 220, and then the combined structure of HDMs 218, 220 is coupled to adhesive layers 216, 217. Fig.5C2 Based on various examples Fig.5C1 A top-down view of the structure. Fig.5C3 Based on various examples Fig.5C2 perspective view of the structure.

[0035] The method 400 includes applying a molding compound ( 410 ). Fig.5D1 exhibit Fig.5C1 , but with molding compound 222 added thereto. The molding compound 222 may be applied using any suitable technique, such as a mold injection technique. The molding compound 222 covers various structures of the semiconductor package 104 as shown, such as the substrate 211, metal pillars 204, 208, solder bumps 206, 210, dies 200, 202, adhesive layers 216, 217, HDM 218, and HDM 220. In an example, the molding compound 222 contacts all surfaces of the HDM 220 except the top surface of the HDM 220, which is all exposed to the top surface of the semiconductor package 104. In an example, the top surface of the HDM 220 is substantially flush with the top surface of the semiconductor package 104. Fig.5D2 Based on various examples Fig.5D1 A top-down view of the structure. Fig.5D3 Based on various examples Fig.5D1 perspective view of the structure.

[0036] Similar to Figures 5D1 to 5D3The multiple structures shown in the drawings may be connected together during manufacturing and singulated after the molding compound application. For example, mechanical or laser sawing may be used to singulate such structures into individual, complete semiconductor packages 104. To avoid cutting into structures of the semiconductor package 104 that are difficult to cut or that may introduce harmful mechanical stresses into the semiconductor package 104, in some examples, the HDMs 218, 220 (and in some examples, all other structures within the semiconductor package 104 except the molding compound 222 and the insulating material 213) may be located a distance, such as 300 microns, from the perimeter of the semiconductor package 104 (i.e., from the sawing location).

[0037] Experimental data supports the heat dissipation effect of the semiconductor package 104 described herein:

[0038] parameter Ambient temperature First die temperature Second die temperature Third die temperature Baseline 55 degrees Celsius 114.96 degrees Celsius 101.16 degrees Celsius 102.61 degrees Celsius Package 104 55 degrees Celsius 99.5 degrees Celsius 92.8 degrees Celsius 93.4 degrees Celsius

[0039] As shown, semiconductor package 104 significantly reduces die temperature relative to a baseline level in which the packaged die is exposed to the top surface of the package and coupled to a TIM and a heat sink. Semiconductor package 104 reduces thermal resistance by 26%. Therefore, die power can be increased by 26% to improve performance while maintaining the same die temperature as the baseline. Alternatively, die size can be reduced by 26% while maintaining the same die temperature as the baseline.

[0040] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0041] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnection of the device, or a combination thereof.

[0042] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within a + / -10% range of the parameter. Modifications may be made in the described examples, and other examples may be made within the scope of the claims.

Claims

1. A package comprising: a substrate including a conductive member coupled to a conductive terminal, the conductive terminal being exposed to the exterior of the package; a first semiconductor die having a first device side coupled to the substrate and a first non-device side opposite the first device side, the first device side having circuitry formed therein; a second semiconductor die having a second device side coupled to the substrate and a second non-device side opposite the second device side, the second device side having circuitry formed therein; a first adhesive layer and a second adhesive layer contacting the first non-device side and the second non-device side, respectively; A passivated outer PO coating layer, which contacts the first adhesive layer and the second adhesive layer; and A semiconductor layer contacts the PO layer and is exposed to the outside of the package. 2 . The package of claim 1 , wherein the PO layer has a thickness ranging between 1 micron and 4 microns. 3 . The package of claim 1 , further comprising a molding compound covering all surfaces of the semiconductor layer except a top surface of the semiconductor layer. The package of claim 1 , wherein the semiconductor layer comprises silicon nitride or silicon oxide.

5. The package of claim 1, wherein the semiconductor layer has a thermal conductivity of at least 150 Watts per meter per Kelvin. 6 . The package of claim 1 , wherein the PO layer has a resistivity sufficient to electrically isolate the first semiconductor die and the second semiconductor die from each other. 7 . The package of claim 1 , wherein the first adhesive layer and the second adhesive layer are composed of a material selected from the group consisting of: epoxy resin, solder, and silver sintering material. 8 . The package of claim 1 , wherein the first semiconductor die is a gallium nitride device configured to control an operation of the second semiconductor die.

9. A package comprising: a substrate including a conductive member coupled to a conductive terminal, the conductive terminal being exposed to the exterior of the package; a semiconductor die including a device side facing the substrate and coupled to the substrate and a non-device side opposite the device side, the device side having circuitry formed therein; a first heat dissipation member coupled to the non-device side, having a thickness in a range between 1 micron and 4 microns and having a resistivity sufficient to electrically isolate the semiconductor die; and A second heat sink member has a bottom surface contacting the first heat sink member, a plurality of lateral surfaces contacting the molding compound, a top surface substantially flush with the top surface of the package, and a thermal conductivity of at least 150 Watts per meter per Kelvin.

10. The package of claim 9, wherein the first heat dissipation member is a passivation overcoat PO layer. 11 . The package of claim 9 , wherein the first heat dissipation member has a thickness in a range between 1 micrometer and 4 micrometers. 12 . The package of claim 9 , further comprising a molding compound covering all surfaces of the second heat dissipation member except a top surface of the second heat dissipation member. 13 . The package of claim 9 , wherein the second heat dissipation member comprises a semiconductor layer. The package of claim 13 , wherein the semiconductor layer comprises silicon nitride or silicon oxide.

15. The package of claim 9, further comprising an adhesive layer between the non-device side of the die and the first heat dissipation means, the adhesive layer being composed of a material selected from the group consisting of: epoxy, solder, and silver sintering material.

16. The package of claim 9, further comprising a second semiconductor die having a second device side having a circuit system formed therein and a second non-device side opposite the second device side, wherein the second device side and the second non-device side are horizontally aligned with each other.

17. The package of claim 9, wherein the semiconductor die is a gallium nitride device.

18. A method of manufacturing a package, comprising: coupling a device side of a semiconductor die to a substrate, the device side having circuitry formed therein, the substrate including conductive terminals exposed to an exterior of the substrate; applying an adhesive layer on a non-device side of the die opposite the device side of the die; Applying a passivating overcoat PO layer on the adhesive layer, with the semiconductor layer in contact with the PO layer; and The substrate, the semiconductor die, the PO layer, and the semiconductor layer are covered with a molding compound, and a top surface of the semiconductor layer is exposed to a top surface of the molding compound.

19. The method of claim 18, wherein the PO layer has a thickness ranging between 1 micron and 4 microns.

20. The method of claim 18, wherein the PO layer is configured to electrically isolate the semiconductor die.

21. The method of claim 18, wherein the semiconductor layer comprises silicon nitride or silicon oxide.

22. The method of claim 18, wherein the adhesive layer is comprised of a material selected from the group consisting of: epoxy, solder, and silver sintering material.

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