Packaging structure, manufacturing method thereof and packaging device

Abstract

The invention discloses a packaging structure, a manufacturing method thereof and a packaging device. The packaging structure comprises a first interconnection layer; the chip is located on the first interconnection layer; the filling layer is positioned on the first interconnection layer and is filled between the first interconnection layer and the chip; the first interconnection layer, the chip and the filling layer are covered with the plastic packaging layer, the width of the plastic packaging layer is larger than that of the first interconnection layer, and the width of the filling layer is smaller than that of the plastic packaging layer. The packaging structure is good in performance.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a packaging structure and a manufacturing method thereof, and a packaging device. Background Art

[0002] Recently, the demand for portable devices in the electronic product market has increased rapidly, and therefore, miniaturization and lightness of electronic components mounted on electronic products are constantly required. With the requirements for excellent performance, high speed and compactness of electronic products, packaging structures need good performance. Summary of the invention

[0003] According to a first aspect of an embodiment of the present disclosure, there is provided a packaging structure, including:

[0004] a first interconnect layer;

[0005] A chip located on the first interconnection layer;

[0006] a filling layer, located on the first interconnection layer and filled between the first interconnection layer and the chip;

[0007] A plastic encapsulation layer covers the first interconnection layer, the chip and the filling layer. The width of the plastic encapsulation layer is greater than the width of the first interconnection layer, and the width of the filling layer is less than the width of the plastic encapsulation layer.

[0008] In some embodiments, the width of the first interconnect layer is greater than the width of the filling layer.

[0009] In some embodiments, a second interconnect layer is further included, the second interconnect layer is located on the first interconnect layer, the chip is located on the second interconnect layer, wherein the width of the first interconnect layer is greater than the width of the second interconnect layer.

[0010] In some embodiments, the filling layer is located on the second interconnect layer and is filled between the second interconnect layer and the chip, and a width of the filling layer is smaller than a width of the second interconnect layer.

[0011] In some embodiments, blocking walls are disposed on the edge of the first interconnect layer and the edge of the second interconnect layer.

[0012] In some embodiments, the molding layer covers a side edge of the first interconnect layer and a side edge of the second interconnect layer.

[0013] In some embodiments, a bottom surface of the molding layer is coplanar with a bottom surface of the first interconnect layer.

[0014] In some embodiments, a difference between a width of the first interconnect layer and a width of the second interconnect layer is smaller than a difference between a width of the first interconnect layer and a width of the molding layer.

[0015] In some embodiments, a difference between a width of the second interconnect layer and a width of the filling layer is smaller than a difference between a width of the first interconnect layer and a width of the second interconnect layer.

[0016] According to a second aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a packaging structure, comprising:

[0017] Providing a temporary substrate, the temporary substrate comprising a patch area and a scribing area, wherein the scribing area is located between the patch areas;

[0018] forming a first interconnect layer on the temporary substrate, wherein the first interconnect layer is located in the patch area;

[0019] placing a chip on the first interconnect layer;

[0020] forming a filling layer on the first interconnect layer, wherein the filling layer is also located between the first interconnect layer and the chip;

[0021] A plastic encapsulation layer is formed, the plastic encapsulation layer covers the first interconnection layer, the chip and the filling layer, the width of the plastic encapsulation layer is greater than the width of the first interconnection layer, and the width of the filling layer is less than the width of the plastic encapsulation layer.

[0022] In some embodiments, the step of forming the first interconnect layer includes:

[0023] forming a first initial layer on the temporary substrate, wherein the first initial layer covers the patch area and the scribing area;

[0024] removing the first initial layer located in the scribing area;

[0025] Curing the first initial layer

[0026] A first interconnection line is formed on the first initial layer to form the first interconnection layer.

[0027] In some embodiments, after forming the first interconnect layer, a second interconnect layer is further formed on the first interconnect layer, and the step of forming the second interconnect layer includes:

[0028] forming a second initial layer on the first interconnect layer, the second initial layer also being located in the dicing region;

[0029] removing the second initial layer in the scribing area, and removing a portion of the second initial layer on both sides of the scribing area, so that the width of the second initial layer is smaller than the width of the first interconnection layer;

[0030] curing the second initial layer;

[0031] A second interconnection line is formed in the second initial layer to form the second interconnection layer.

[0032] In some embodiments, the step of forming the plastic encapsulation layer includes:

[0033] Covering the temporary substrate with a plastic encapsulation material, wherein the plastic encapsulation material covers the first interconnection layer, the second interconnection layer, the chip and the filling layer;

[0034] Wherein, the plastic encapsulation material also covers the dicing area.

[0035] In some embodiments, the method for manufacturing the packaging structure further includes:

[0036] removing the temporary substrate;

[0037] The molding material in the dicing area is cut so that the molding material covers the side edge of the first interconnection layer and the side edge of the second interconnection layer.

[0038] In some embodiments, during the process of curing the first initial layer and the second initial layer, a barrier wall is formed at an edge of the first initial layer and an edge of the second initial layer.

[0039] In some embodiments, the step of forming the filling layer includes:

[0040] injecting a filling material onto the first interconnect layer, wherein the filling material also enters between the first interconnect layer and the chip;

[0041] The blocking wall blocks the filling material on the first interconnection layer, so that the width of the filling layer is smaller than the width of the first interconnection layer.

[0042] According to a third aspect of an embodiment of the present disclosure, there is provided a packaging device, including:

[0043] A substrate and the above-mentioned packaging structure, wherein the packaging structure is arranged on the substrate.

[0044] In summary, the embodiments of the present disclosure provide a packaging structure and a manufacturing method thereof, as well as a packaging device. First, a chip is placed on a first interconnection layer, and then a filling layer is formed on the first interconnection layer, and then a plastic encapsulation layer is covered on the first interconnection layer, the chip and the filling layer, and at the same time, the width of the plastic encapsulation layer is greater than the width of the first interconnection layer. In the embodiments of the present disclosure, since the width of the plastic encapsulation layer is greater than the width of the first interconnection layer, the plastic encapsulation layer can cover the side edge of the first interconnection layer. At the same time, since the width of the filling layer is less than the width of the plastic encapsulation layer, multiple interfaces of the plastic encapsulation layer, the filling layer and the first interconnection layer will not be formed on the side wall of the packaging structure, that is, there is only one material, the plastic encapsulation layer, on the outer surface of the packaging structure, so the delamination problem caused by the different thermal expansion coefficients of the various materials can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a flow chart of a method for manufacturing a packaging structure according to an exemplary embodiment;

[0046] Figure 2 is a schematic diagram of a temporary substrate according to an exemplary embodiment;

[0047] Figure 3 is a schematic diagram of a first initial layer according to an exemplary embodiment;

[0048] Figure 4 is a schematic diagram showing removal of a portion of the first initial layer according to an exemplary embodiment;

[0049] Figure 5 According to an exemplary embodiment, Figure 4 An enlarged schematic diagram of the dashed box in the middle;

[0050] Figure 6 is a schematic diagram of a first interconnection layer according to an exemplary embodiment;

[0051] Figure 7 is a schematic diagram of a second initial layer according to an exemplary embodiment;

[0052] Figure 8 is a schematic diagram showing removal of a portion of the second initial layer according to an exemplary embodiment;

[0053] Fig. 9 is a schematic diagram of a second interconnect layer according to an exemplary embodiment;

[0054] Fig.10 is a schematic diagram of a pad according to an exemplary embodiment;

[0055] Fig.11 is a schematic diagram of a filling layer according to an exemplary embodiment;

[0056] Fig.12 is a schematic diagram of a plastic packaging layer according to an exemplary embodiment;

[0057] Fig.13 is a schematic diagram of a packaging structure after a temporary substrate is removed according to an exemplary embodiment;

[0058] Fig.14A is a schematic diagram of a package structure after cutting according to an exemplary embodiment;

[0059] Fig. 14B is a schematic diagram of another package structure after cutting according to an exemplary embodiment;

[0060] Fig.15 According to an exemplary embodiment, Fig.14A It is a simple top view;

[0061] Fig.16 is a simplified schematic diagram showing a filling layer on a second interconnect layer according to an exemplary embodiment;

[0062] Fig.17 is a simplified schematic diagram showing a filling layer on a first interconnect layer according to an exemplary embodiment;

[0063] Fig.18 is a schematic diagram of another packaging structure according to an exemplary embodiment;

[0064] Fig.19 According to an exemplary embodiment, the cut Fig.18 A top view of

[0065] Fig. 20 is another schematic diagram of a second interconnect layer according to an exemplary embodiment;

[0066] Fig.21 According to an exemplary embodiment, Fig. 20 Schematic diagram in the AA direction;

[0067] Fig. 22 According to an exemplary embodiment, Fig. 20 Another schematic diagram in the AA direction;

[0068] Fig.23 is a schematic diagram of a packaging device according to an exemplary embodiment; DETAILED DESCRIPTION

[0069] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0070] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0071] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0072] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0073] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0074] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0075] Generally, in the back-end process of making a packaging structure, the entire packaging structure needs to be cut to obtain individual packaging particles. The applicant found that during the cutting process, the PI glue will not be completely cut off, resulting in a decrease in yield. At the same time, since the sidewalls of the packaging structure will have multiple interfaces composed of multiple materials, it is easy to cause material stratification, further reducing the yield.

[0076] To solve the above problems, the present disclosure provides a method for manufacturing a packaging structure, which can make the sidewall of the packaging structure free of multiple interfaces composed of multiple materials, thereby improving the material stratification problem. At the same time, when cutting, the PI glue will not be cut, so the yield can be improved.

[0077] like Figure 1 As shown, the embodiment of the present disclosure provides a method for manufacturing a packaging structure, the manufacturing method comprising:

[0078] S1: providing a temporary substrate, the temporary substrate comprising a patch area and a scribing area, wherein the scribing area is located between the patch areas;

[0079] S2: forming a first interconnect layer on the temporary substrate, wherein the first interconnect layer is located in the patch area;

[0080] S3: forming a second interconnect layer on the first interconnect layer, wherein a width of the second interconnect layer is smaller than a width of the first interconnect layer;

[0081] S4: placing the chip on the second interconnection layer;

[0082] S5: forming a filling layer on the second interconnect layer, wherein the filling layer is also located between the second interconnect layer and the chip;

[0083] S6: forming a plastic encapsulation layer, the plastic encapsulation layer covers the first interconnection layer, the second interconnection layer, the chip and the filling layer, the width of the plastic encapsulation layer is greater than the width of the first interconnection layer, and the width of the plastic encapsulation layer is greater than the width of the filling layer.

[0084] It should be noted that, in some embodiments, step S3 may be omitted, that is, after forming the first interconnection layer, the chip is directly placed on the first interconnection layer, and then a filling layer is formed on the first interconnection layer, and then plastic packaging is performed.

[0085] like Figure 2 As shown, in step S1, a temporary substrate 101 is first provided, and the temporary substrate 101 is divided into multiple areas, namely, multiple patch areas 1011 and multiple scribing areas 1012. The slicing areas 1011 and the scribing areas 1012 are arranged in an array, and the patch areas 1011 and the scribing areas 1012 are arranged at intervals, and the two patch areas 1011 are separated by the scribing areas 1012. The packaging structure can be formed on the patch area 1011, and the scribing area 1012 is used to cut the overall packaging structure into multiple small packaging structures. In the embodiment of the present disclosure, the temporary substrate 101 can be a glass substrate or a ceramic substrate.

[0086] like Figure 3-Figure 4As shown, in step S2, first, a first initial layer 102 is formed on the temporary substrate 101, that is, the first initial layer 102 covers the entire surface of the temporary substrate 101, that is, the first initial layer 102 covers both the patch area 1011 and the scribing area 1012. Then, part of the first initial layer 102 is removed by developing, that is, the first initial layer 102 located on the scribing area 1012 is developed away, and at this time, the first initial layer 102 is only located on the patch area 1011. In the embodiment of the present disclosure, the material of the first initial layer 102 can be PI glue, and the first initial layer 102 can be a negative photoresist. Since the first initial layer 102 located directly above the scribing area 1012 is not exposed, the part of the first initial layer 102 is removed.

[0087] like Figure 5 As shown, Figure 5 Display as Figure 4 After the first initial layer 102 is developed, the remaining first initial layer 102 is cured. Since the first initial layer 102 is a colloid, it will shrink, so a bulge will be formed on the edge of the first initial layer 102, that is, a blocking wall 1021 will be formed on the edge of the first initial layer 102. The blocking wall 1021 surrounds the edge of the first initial layer 102.

[0088] Of course, in some embodiments, the blocking wall 1021 may be formed separately on the edge of the first initial layer 102 , for example, an insulating dielectric layer (silicon oxide) may be formed on the edge of the first initial layer 102 to form the blocking wall 1021 .

[0089] like Figure 6 As shown, after forming the first initial layer 102, a first interconnection line 103 may be formed on the first initial layer 102. The material of the first interconnection line 103 may be other metals such as copper, nickel or gold, and the first interconnection line 103 may be used to transmit signals. Of course, in some embodiments, the first interconnection line 103 may also be located in the first initial layer 102, that is, the first initial layer 102 is etched to form an interconnection groove, and then the first interconnection line 103 is formed in the interconnection groove. In the embodiment of the present disclosure, the first initial layer 102 and the first interconnection line 103 form a first interconnection layer 104. The first interconnection layer 104 may also be an RDL layer.

[0090] like Figure 7-Figure 8As shown, in step S3, after forming the first interconnection layer 104, the second initial layer 105 is spin-coated on the temporary substrate 101, and the second initial layer 105 can cover the first initial layer 102 and also cover the scribing area 1012. The material of the first initial layer 102 is the same as that of the second initial layer 105, and then part of the second initial layer 105 is removed, that is, the second initial layer 105 located directly above the scribing area 1012 and the part of the second initial layer 105 located on both sides of the scribing area 1012 are removed, so that the second initial layer 105 is only located on the first initial layer 102, that is, the second initial layer 105 does not contact the temporary substrate 101. At the same time, the second initial layer 105 also covers the first interconnection line 103, and the width d2 of the second initial layer 105 is less than the width d1 of the first initial layer 102, that is, the first initial layer 102 and the second initial layer 103 form a step shape. Of course, the width d1 of the first initial layer 102 can also be understood as the width of the first interconnection layer 104. That is, the width d2 of the second initial layer 105 is smaller than the width d1 of the first interconnection layer 104 .

[0091] like Fig. 9 As shown, after removing part of the second initial layer 105, a second interconnection line 106 is formed in the remaining second initial layer 105, and the second interconnection line 106 is also connected to the first interconnection line 103. Of course, in some embodiments, the second interconnection line 106 can be formed on the second initial layer 105, and at this time, an insulating layer needs to be formed again on the second interconnection line 106 to cover the second interconnection line 106. The material of the first interconnection line 103 can be the same as that of the second interconnection line 106. The material of the second interconnection line 106 can be other metals such as copper, gold or nickel. The second interconnection line 106 is also used to transmit signals. The second interconnection line 106 and the second initial layer 105 constitute a second interconnection layer 107. The second interconnection layer 107 can be an RDL layer.

[0092] like Figure 8-Figure 9 As shown, in the embodiment of the present disclosure, the width d2 of the second initial layer 105 can be the width d2 of the second interconnect layer 107, that is, the width d2 of the second interconnect layer 107 is smaller than the width d1 of the first interconnect layer 104. That is, the first interconnect layer 104 and the second interconnect layer 107 form a step shape. The first interconnect layer 104 and the second interconnect layer 107 can constitute an interconnect structure. Of course, a third interconnect layer, a fourth interconnect layer, etc. can also be formed on the second interconnect layer 107. At this time, the width of the third interconnect layer is smaller than the width of the second interconnect layer 107, and the width of the fourth interconnect layer is smaller than the width of the third interconnect layer.

[0093] It should be noted that after the second initial layer 105 is solidified, a barrier wall 1021 is also formed on the edge of the second initial layer 105 , and the barrier wall 1021 surrounds the edge of the second initial layer 105 .

[0094] like Figure 10-11 As shown, in steps S4-S5, first, a pad 108 is formed on the second initial layer 105, and the pad 108 is located on the second interconnect line 106, that is, the pad 108 is located on the second interconnect layer 107. Then the chip 109 is placed on the pad 108, that is, the chip 109 is soldered to the pad 108 through a conductive bump. In some embodiments, a plurality of chips 109 are arranged on the second interconnect layer 107, for example, two, four or more chips 109 are arranged, and the chip 109 can be other memory chips such as DRAM, SRAM, etc. After the chip 109 is placed on the second interconnect layer 107, a filling material is injected into the second interconnect layer 107, and the filling material will flow under the chip 109, that is, flow between the second interconnect layer 107 and the chip 109, thereby forming a filling layer 110 on the second interconnect layer 107. At the same time, since there is a blocking wall 1021 ( Figure 5 ), the blocking wall 1021 can also block the filling material from flowing onto the first interconnection layer 104, that is, block the filling material on the second interconnection layer 107, so the width d3 of the filling layer 110 is smaller than the width d2 of the second interconnection layer 107, and at the same time, the width d3 of the filling layer 110 is also smaller than the width of the first interconnection layer 107. Since the blocking wall 1021 blocks the filling layer 110 on the second interconnection layer 107, the filling layer 110 will not flow onto the first interconnection layer 104, and will not flow onto the dicing area 1012 of the temporary substrate 101. In this embodiment, the material of the filling layer 110 can be a bottom filling material (underfill).

[0095] In some embodiments, when forming the filling layer 110, the filling layer 110 may flow over the second interconnect layer 107 to the first interconnect layer 104. Since the first interconnect layer 104 also has the blocking wall 1021 and the volume of the filling layer 110 flowing onto the first interconnect layer 104 is relatively small, the filling layer 110 will not flow over the blocking wall 1021 on the first interconnect layer 104 to the dicing area 1012 on the temporary substrate 101. At this time, the width d1 of the first interconnect layer 104 is greater than the width d3 of the filling layer 110.

[0096] like Fig.12As shown, in step S6, after forming the filling layer 110, a plastic encapsulation material is injected onto the temporary substrate 101, thereby forming a plastic encapsulation layer 111 on the temporary substrate 101. The plastic encapsulation layer 110 can cover the chip 109, the filling layer 110, the second interconnection layer 107 and the first interconnection layer 104. The plastic encapsulation layer 111 will also flow onto the scribing area 1012 on the temporary substrate 101, that is, fill the scribing area 1012 between two adjacent patch areas 1011, so that the plastic encapsulation layer 111 can cover the side edge of the first interconnection layer 104 and the side edge of the second interconnection layer 107, so that the width d4 of the plastic encapsulation layer 111 can be greater than the width d1 of the first interconnection layer 104. Since the filling layer 110 does not flow into the scribing area 1012, the width of the plastic encapsulation layer 111 can also be greater than the width d3 of the filling layer 110.

[0097] like Figure 12-14A As shown, after the plastic encapsulation layer 111 is formed, the temporary substrate 101 can be removed by laser debonding, and then the overall package structure can be cut, so that a large number of package structures can be obtained. Since the temporary substrate 101 includes the patch area 1011 and the dicing area 1012. The package structure has been formed on the patch area 1011, and the dicing area 1012 is filled with the plastic encapsulation layer 111. After removing the temporary substrate 101, the area between the two adjacent first interconnection layers 104 is the dicing area 1012, that is, Fig.13 The position pointed by the arrow in the scribe area 1012 is then cut by laser cutting to obtain a large number of packaging structures 100. At the same time, during the cutting process, since there is only a plastic encapsulation layer 111 in the scribe area 1012, that is, a stacked structure of PI glue (the material of the first initial layer 102), a filling layer 110 and a plastic encapsulation layer 111 will not be formed in the scribe area 1012, it is easier to cut only the plastic encapsulation layer 111 than to cut three materials, and the yield rate can be improved. At the same time, since there is no PI glue in the scribe area 1012, there will be no problem of PI glue wire drawing (PI glue is pulled, making it difficult to cut off the PI glue). At the same time, after cutting, the side surface of the packaging structure 100 is the plastic encapsulation layer 111, and there will be no material interface of PI glue, the filling layer 110 and the plastic encapsulation layer 111, so water vapor will not enter the packaging structure, and there will be no problem of material stratification.

[0098] like Fig.14AAs shown, the embodiment of the present disclosure provides a packaging structure 100, which may include a first interconnection layer 104, a second interconnection layer 107, a chip 109, a filling layer 110, and a plastic layer 111. The first interconnection layer 104 may include a first initial layer 102 and a first interconnection line 103, and the first interconnection line 103 is located on the first initial layer 102, or the first interconnection line 103 is located in the first initial layer 102. The first initial layer 102 may be PI glue or PBO glue. The first interconnection line 103 may be a metal such as copper, nickel, or gold. The first interconnection line 103 may be used to transmit signals.

[0099] like Fig.14A As shown, the second interconnection layer 107 is located on the first interconnection layer 104, and the structure of the second interconnection layer 107 can be substantially the same as that of the first interconnection layer 104. The second interconnection layer 107 may include a second initial layer 105 and a second interconnection line 106. The second initial layer 105 is located on the first initial layer 102 and covers the first interconnection line 103, and the second interconnection line 106 is located in the second initial layer 105 and connected to the first interconnection line 103. The material of the first initial layer 102 is the same as that of the second initial layer 105, and the material of the second interconnection line 106 is the same as that of the first interconnection line 103.

[0100] like Fig.14A , Fig.15 As shown, Fig.15 Display as Fig.14A A simplified top view of the first interconnect layer 107. In this embodiment, the second interconnect layer 107 is located on the first interconnect layer 104, and the width d1 of the first interconnect layer 104 is greater than the width d2 of the second interconnect layer 107, that is, the first interconnect layer 104 and the second interconnect layer 107 can form a step shape. From the top view, the projection area of ​​the second interconnect layer 107 on the first interconnect layer 104 is completely within the projection area of ​​the first interconnect layer 104, so in the X direction (horizontal direction) and the Y direction (vertical direction), the width of the first interconnect layer 104 is greater than the width of the second interconnect layer 107. The embodiment of the present disclosure takes the X direction as an example, that is, in the X direction, the width d1 of the first interconnect layer 104 is greater than the width of the second interconnect layer 107.

[0101] like Fig.14A , Fig.15 As shown, a chip 109 is disposed on the second interconnect layer 107. For example, a pad 108 ( Fig. 910), and then the chip 109 is welded to the pad 108 through the conductive bump, so that the chip 109 is fixed on the second interconnection layer 107. At the same time, there is a filling layer 110 on the second interconnection layer 107, and the filling layer 110 is also located between the second interconnection layer 107 and the chip 109. The filling layer 110 can fill the gap between the second interconnection layer 107 and the chip 109, so as to protect the stability of the chip 109. At the same time, there is a blocking wall 1021 on the edge of the second initial layer 105, and the blocking wall 1021 can surround the chip 109, that is, the blocking wall 1021 is a ring structure, so the filling layer 110 can be blocked by the blocking wall 1021 on the second initial layer 105, that is, the blocking wall 1021 blocks the filling layer 110 on the second interconnection layer 107, so that the width d3 of the filling layer 110 is smaller than the width d2 of the second interconnection layer 107, that is, in the X direction or the Y direction, the width of the filling layer 110 is smaller than the width of the second interconnection layer 107.

[0102] like Fig.15 As shown, in this embodiment, the filling layer 110 is located on the second interconnection layer 107, and the second interconnection layer 107 is located on the first interconnection layer 104. The width d2 of the second interconnection layer 107 is greater than the width d3 of the filling layer 110, the width d2 of the second interconnection layer 107 is less than the width d1 of the first interconnection layer 104, and the difference between the width d1 of the first interconnection layer 104 and the width d2 of the second interconnection layer 107 is greater than the difference between the width d2 of the second interconnection layer 107 and the width d3 of the filling layer 110, that is, the width d1 of the first interconnection layer 104 is much greater than the width d2 of the second interconnection layer 107. When forming the filling layer 110, part of the filling layer 110 may flow over the blocking wall 1021 to the first interconnect layer 104. Since the width d1 of the first interconnect layer 104 is larger and the volume of the filling layer 110 flowing to the first interconnect layer 104 is small, this part of the filling layer 110 will not flow into the dicing area 1012 of the temporary base 101, thereby ensuring that there is no filling layer 110 in the dicing area 1012, thereby improving the cutting yield.

[0103] like Fig.14A , Fig.15As shown, in this embodiment, the plastic encapsulation layer 111 can completely cover the chip 109, the filling layer 110, the second interconnection layer 107 and the first interconnection layer 104, thereby forming a coating structure. At the same time, the plastic encapsulation layer 111 also covers the side edge of the first interconnection layer 104 and the side edge of the second interconnection layer 107, thereby making the width d4 of the plastic encapsulation layer 111 greater than the width d1 of the first interconnection layer 104, that is, in the X direction or the Y direction, the width of the plastic encapsulation layer 111 is greater than the width of the first interconnection layer 104. Because the plastic encapsulation layer 111 and the first interconnection layer 104 are both located on the temporary substrate 101 before cutting, the bottom surface of the plastic encapsulation layer 111 can be made coplanar with the bottom surface of the first interconnection layer 104, that is, the plastic encapsulation layer 111 will not cover the bottom surface of the first interconnection layer 104, and the bottom surface of the first interconnection layer 104 can also be transplanted with solder balls in the subsequent process, and then soldered with the PCB.

[0104] like Fig.14A , Fig.15 As shown, the second interconnection layer 107 is located on the first interconnection layer 104, and the two are in a step shape, and the plastic encapsulation layer 111 covers the side edge of the first interconnection layer 104, so the width d1 of the first interconnection layer 104 is less than the width d4 of the plastic encapsulation layer 111, and the width d1 of the first interconnection layer 104 is greater than the width d2 of the second interconnection layer 107. At the same time, the difference between the width d4 of the plastic encapsulation layer 111 and the width d1 of the first interconnection layer 104 is greater than the difference between the width d1 of the first interconnection layer 104 and the width d2 of the second interconnection layer 107, that is, the width d4 of the plastic encapsulation layer 111 is much larger than the width d1 of the first interconnection layer 104, that is, there is a large gap between the side edge of the plastic encapsulation layer 111 and the side edge of the first interconnection layer 104, that is, during the cutting process, the first interconnection layer 104 is prevented from being cut, thereby preventing the first interconnection layer 104 from being pulled during the cutting process. At the same time, after cutting, it can be ensured that the side edge of the packaging structure 100 has only the plastic packaging layer 111, that is, there will be no stacking of multiple materials and no interface between multiple materials. Therefore, the packaging structure 100 will not have stratification problems between multiple materials.

[0105] like Figure 14A-14B As shown, Fig. 14B and Fig.14A The difference is that Fig. 14B The first interconnection line 103 in the circuit board is located in the first initial layer 102, and a metal bump 112 and a solder ball 113 are formed on the bottom surface of the first initial layer 102. The solder ball 113 can be soldered on the PCB. Fig.14A Other structures in Fig. 14B The other structures in are the same. Fig. 14B Can and Fig.14A Share the same top view ( Fig.15 ).

[0106] like Fig. 14B and Fig.15 As shown, the width d1 of the first interconnection layer 104 is smaller than the width d4 of the plastic layer 111, the width d2 of the second interconnection layer 107 is smaller than the width d1 of the first interconnection layer 104, and the width d4 of the filling layer 110 is smaller than the width d2 of the second interconnection layer 107. The first interconnection layer 104 and the second interconnection layer 107 are stepped, and the filling layer 110 on the second interconnection layer 107 flows on the first interconnection layer 104. Since the side walls of the package structure 100 are all plastic layers, the delamination problem can be improved.

[0107] like Fig.14A and Fig.16 As shown, Fig.16 It is a simplified schematic diagram showing a filling layer 110 on the second interconnection layer 107. In this embodiment, the filling layer 110 is located on the second interconnection layer 107, and at the same time, there is a blocking wall 1021 on the edge of the second interconnection layer 107. The blocking wall 1021 surrounds the chip 109. The blocking wall 1021 can block the filling layer 110 on the second interconnection layer 107, that is, the blocking wall 1021 can prevent the filling layer 110 from flowing onto the first interconnection layer 104. Fig.16 As can be seen from the figure, the thickness of the filling layer 110 gradually decreases in the direction from the chip 109 to the blocking wall 1021, that is, the closer to the blocking wall 1021, the smaller the thickness of the filling layer 110, so that the blocking wall 1021 can block the filling layer 110. Of course, the blocking wall 1021 can be in contact with the filling layer 110. There can also be a certain distance between the blocking wall 1021 and the filling layer 110, that is, the width of the filling layer 110 is less than the width of the second interconnect layer 107.

[0108] like Fig.16 and Fig.17 As shown, Fig.17It is a simplified schematic diagram showing the filling layer 110 flowing onto the first interconnection layer 104. In some embodiments, when the volume of the filling layer 110 is relatively large, part of the filling layer 110 may flow over the barrier wall 1021 on the second interconnection layer 107 and flow onto the first interconnection layer 104, that is, part of the filling layer 110 flows along the side wall of the second interconnection layer 107 onto the first interconnection layer 104. Since there is also a barrier wall 1021 on the edge of the first interconnection layer 104, the width of the first interconnection layer 104 is much larger than that of the second interconnection layer 107, and the volume of the filling layer 110 flowing onto the first interconnection layer 104 is relatively small, these filling layers 110 flowing onto the first interconnection layer 104 will not cross the barrier wall 1021 on the first interconnection layer 104, that is, these filling layers 110 will be blocked on the first interconnection layer 104. At this time, the width of the filling layer 104 will be greater than the width of the second interconnection layer 107, but less than the width of the first interconnection layer 104. At the same time, since the width of the first interconnection layer 104 is smaller than the width of the molding layer 111 , the width of the filling layer 110 is also smaller than the width of the molding layer 111 .

[0109] like Figure 18-19 As shown, the present disclosure further provides a packaging structure 100. The common steps for forming the packaging structure 100 can refer to the above steps. Fig.14A The difference is that Fig.18 The package structure 100 in the embodiment does not reflect the second interconnection layer, that is, it only includes one interconnection layer structure. The package structure 100 may include a first interconnection layer 104. The first interconnection layer 104 includes a first initial layer 102 and a first interconnection line 103, the first interconnection line 103 is located in the first initial layer 102, and the first interconnection line 103 is used to realize signal transmission. The first interconnection layer 104 may also be called an RDL layer. There is also a pad 108 on the first interconnection layer 104, and the pad 108 can be used to form the first interconnection line 103 and the chip 109, so as to transmit the signal to the chip 109. There is a filling layer 110 on the first interconnection layer 104, and the filling layer 104 fills under the chip 109, so as to better fix the chip 109. At the same time, in the top view direction, the projection area of ​​the filling layer 110 on the first interconnection layer 104 completely falls inside the projection area of ​​the first interconnection layer 104, so that the width d3 of the filling layer 110 is less than the width d1 of the first interconnection layer 104. At the same time, since a barrier wall 1021 ( Fig.17 ), so the blocking wall 1021 can also block the filling layer 110 on the first initial layer 102, that is, the filling layer 110 will not go over the blocking wall 1021 and flow onto the sidewall of the first initial layer 102. It should be noted that the step of forming the filling layer 110 on the first interconnect layer 104 is the same as the step of forming the filling layer 110 on the second interconnect layer.

[0110] like Figure 18-19 As shown, after forming the filling layer 110, a plastic encapsulation process is performed to form a plastic encapsulation layer 111. The plastic encapsulation layer 111 can cover the chip 109, the filling layer 110, and the first interconnection layer 104. The plastic encapsulation layer 111 can also cover the side edge of the first interconnection layer 104, so that the projection area of ​​the plastic encapsulation layer 111 can also cover the projection area of ​​the first interconnection layer 104, and thus the width of the plastic encapsulation layer 111 is greater than the width of the first interconnection layer 104. In this embodiment, the bottom surface of the first interconnection layer 104 is also coplanar with the bottom surface of the plastic encapsulation layer 104, and there are metal bumps 112 and solder balls 113 on the bottom surface of the first interconnection layer 104, and the metal bumps 112 and solder balls 113 are used for soldering with the PCB.

[0111] like Fig.18 As shown, in this embodiment, since the plastic encapsulation layer 111 covers the side edge of the first interconnection layer 104, the width of the first interconnection layer 104 is smaller than the width of the plastic encapsulation layer 111. Since the filling layer 110 is blocked on the first interconnection layer 104, the width of the first interconnection layer 104 is greater than the width of the filling layer 110, thereby making the width of the filling layer 110 smaller than the width of the plastic encapsulation layer 111, and the difference between the width of the filling layer 110 and the width of the first interconnection layer 104 is smaller than the difference between the width of the first interconnection layer 104 and the width of the plastic encapsulation layer 111, so that the filling layer 110 will not be cut during the cutting process. Since the side edges of the packaging structure 100 are all plastic encapsulation layers 111, there will be no delamination problem of multiple materials.

[0112] like Fig. 20 As shown, the embodiment of the present disclosure further proposes another second interconnect layer 107 , which can be applied to the above-mentioned packaging structure 100 . Fig.18It is shown as a simplified top view of the second interconnection layer 107. There is a blocking wall 1021 on the edge of the second initial layer 105, and the blocking wall 1021 can surround the edge of the second initial layer 105, so that the blocking wall 1021 can surround the chip on the second interconnection layer 107. There are also a plurality of receiving grooves 112 on the second initial layer 105, and these receiving grooves 112 are arranged at intervals on the surface of the second initial layer 105. From the blocking wall 1021 to the center of the second interconnection layer 107, the distance between two adjacent receiving grooves 112 gradually increases. The receiving grooves 112 include, for example, a first receiving groove 1121, a second receiving groove 1122, a third receiving groove 1123 and a fourth receiving groove 1124. The first receiving groove 1121, the second receiving groove 1122, the third receiving groove 1123 and the fourth receiving groove 1124 are arranged in sequence along the B direction. The spacing between the first receiving groove 1121 and the second receiving groove 1122, the spacing between the second receiving groove 1122 and the third receiving groove 1123, and the spacing between the third receiving groove 1123 and the fourth receiving groove 1124 gradually increase. When forming the filling layer 110, the filling material can be injected from the position of the first receiving groove 1121 onto the second interconnection layer 107, and then enter the bottom of the chip 109 through the capillary effect. At the same time, some filling materials will also move toward the blocking wall 1021. Therefore, by reducing the spacing between the receiving grooves 112 close to the blocking wall 1021, the filling material can flow into these receiving grooves 112, thereby preventing some filling materials from crossing the blocking wall 1021 and then flowing onto the first interconnection layer 104.

[0113] like Figure 21-22 As shown, Fig.21 and Fig. 22 for Fig. 20 The first receiving groove 1121 , the second receiving groove 1122 , the third receiving groove 1123 and the fourth receiving groove 1124 may have the same depth or different depths. Fig.21 In the embodiment, the depths of the first receiving groove 1121 to the fourth receiving groove 1124 are the same. Fig. 22 In the embodiment, the depths of the first receiving groove 1121 to the fourth receiving groove 1124 gradually decrease. The first receiving groove 1121 to the fourth receiving groove 1124 can all be filled with the filling layer 110. Fig.21 In the embodiment, the depths of the first receiving groove 1121 to the fourth receiving groove 1124 are the same and small, so that the filling material will not flow toward the chip 109. Fig. 22 Since the first receiving groove 1121 has the largest depth, it can accommodate more filling materials and reduce the filling materials from crossing the blocking wall 1021. Since the fourth receiving groove 1124 has the smallest depth, the influence of the fourth receiving groove 1124 on the flow of the filling materials can be reduced.

[0114] like Fig.23 As shown, the embodiment of the present disclosure proposes a packaging device 10, which may include a substrate 11 and a packaging structure 12. The substrate 200 is, for example, a PCB, a flexible substrate or a strip substrate, and the packaging structure 12 may refer to the above packaging structure. The packaging device 10 may be applied to an electronic device. The electronic device may include one or more of the following: for example, a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MPEG-1 audio layer 3 (MP3) player, a mobile medical device, a camera, a household appliance, a medical device, an Internet of Things (IoT) device, and a wearable device. The wearable device may be an accessory type, a fabric or clothing type, a body attachment type, or an implantable circuit type. The accessory wearable device may be, for example, a watch, a ring, a bracelet, an anklet, a necklace, glasses, contact lenses, or a head-mounted device (HMD).

[0115] In summary, the embodiments of the present disclosure provide a packaging structure and a manufacturing method thereof, as well as a packaging device. First, a chip is placed on a first interconnection layer, and then a filling layer is formed on the first interconnection layer, and the width of the filling layer is smaller than the width of the first interconnection layer, and then a plastic encapsulation layer is covered on the first interconnection layer, the chip and the filling layer, and at the same time, the width of the plastic encapsulation layer is larger than the width of the first interconnection layer. In the embodiments of the present disclosure, since the width of the plastic encapsulation layer is larger than the width of the first interconnection layer, the plastic encapsulation layer can cover the side edge of the first interconnection layer. At the same time, since the width of the filling layer is smaller than the width of the plastic encapsulation layer, multiple interfaces of the plastic encapsulation layer, the filling layer and the first interconnection layer will not be formed on the side wall of the packaging structure, that is, there is only one material, the plastic encapsulation layer, on the outer surface of the packaging structure, so the delamination problem caused by the different thermal expansion coefficients of the various materials can be improved.

[0116] At the same time, when cutting, since there is only plastic packaging material in the dicing area, and no PI glue and filling material, there will be no problem of PI glue being pulled, resulting in a decrease in product yield.

[0117] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A packaging structure, characterized in that: include: a first interconnect layer; A chip located on the first interconnection layer; a filling layer, located on the first interconnection layer and filled between the first interconnection layer and the chip; A plastic encapsulation layer covers the first interconnection layer, the chip and the filling layer. The width of the plastic encapsulation layer is greater than the width of the first interconnection layer, and the width of the filling layer is less than the width of the plastic encapsulation layer.

2. The packaging structure according to claim 1, characterized in that: The width of the first interconnection layer is greater than the width of the filling layer.

3. The packaging structure according to claim 1 or 2, characterized in that: The device further includes a second interconnection layer, wherein the second interconnection layer is located on the first interconnection layer, and the chip is located on the second interconnection layer, wherein the width of the first interconnection layer is greater than the width of the second interconnection layer.

4. The packaging structure according to claim 3, characterized in that: The filling layer is located on the second interconnection layer and is filled between the second interconnection layer and the chip. The width of the filling layer is smaller than the width of the second interconnection layer.

5. The packaging structure according to claim 3, characterized in that: Blocking walls are arranged on the edge of the first interconnection layer and the edge of the second interconnection layer.

6. The packaging structure according to claim 3, characterized in that: The plastic encapsulation layer covers the side edge of the first interconnection layer and the side edge of the second interconnection layer, and the bottom surface of the plastic encapsulation layer is coplanar with the bottom surface of the first interconnection layer.

7. The packaging structure according to claim 1, characterized in that: A difference between a width of the first interconnection layer and a width of the second interconnection layer is smaller than a difference between a width of the first interconnection layer and a width of the plastic encapsulation layer.

8. The packaging structure according to claim 3, characterized in that: A difference between a width of the second interconnect layer and a width of the filling layer is smaller than a difference between a width of the first interconnect layer and a width of the second interconnect layer.

9. A method for manufacturing a packaging structure, characterized in that: include: Providing a temporary substrate, the temporary substrate comprising a patch area and a scribing area, wherein the scribing area is located between the patch areas; forming a first interconnect layer on the temporary substrate, wherein the first interconnect layer is located in the patch area; placing a chip on the first interconnect layer; forming a filling layer on the first interconnect layer, wherein the filling layer is also located between the first interconnect layer and the chip; A plastic encapsulation layer is formed, the plastic encapsulation layer covers the first interconnection layer, the chip and the filling layer, the width of the plastic encapsulation layer is greater than the width of the first interconnection layer, and the width of the filling layer is less than the width of the plastic encapsulation layer.

10. The manufacturing method according to claim 9, wherein the step of forming the first interconnect layer comprises: forming a first initial layer on the temporary substrate, wherein the first initial layer covers the patch area and the scribing area; removing the first initial layer located in the scribing area; Curing the first initial layer A first interconnection line is formed on the first initial layer to form the first interconnection layer.

11. The manufacturing method according to claim 10, characterized in that: After forming the first interconnection layer, a second interconnection layer is further formed on the first interconnection layer, and the step of forming the second interconnection layer includes: forming a second initial layer on the first interconnect layer, the second initial layer also being located in the dicing region; removing the second initial layer in the scribing area, and removing a portion of the second initial layer on both sides of the scribing area, so that the width of the second initial layer is smaller than the width of the first interconnection layer; curing the second initial layer; A second interconnection line is formed in the second initial layer to form the second interconnection layer.

12. The manufacturing method according to claim 10 or 11, characterized in that: The steps of forming the plastic encapsulation layer include: Covering the temporary substrate with a plastic encapsulation material, wherein the plastic encapsulation material covers the first interconnection layer, the second interconnection layer, the chip and the filling layer; Wherein, the plastic encapsulation material also covers the dicing area.

13. The manufacturing method according to claim 12, characterized in that: Also includes: removing the temporary substrate; The molding material in the dicing area is cut so that the molding material covers the side edge of the first interconnection layer and the side edge of the second interconnection layer.

14. The manufacturing method according to claim 11, characterized in that: During the solidification of the first initial layer and the second initial layer, a barrier wall is formed on the edge of the first initial layer and the edge of the second initial layer.

15. The manufacturing method according to claim 14, characterized in that: The steps of forming the filling layer include: injecting a filling material onto the first interconnect layer, wherein the filling material also enters between the first interconnect layer and the chip; The blocking wall blocks the filling material on the first interconnection layer, so that the width of the first interconnection layer is greater than the width of the filling layer.

16. A packaged device, characterized in that: include: A substrate and a packaging structure as described in any one of claims 1 to 8, wherein the packaging structure is located on the substrate.

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