Non-singulated semiconductor package

Abstract

An unsingulated semiconductor package includes a plurality of integrated circuits disposed on a single substrate segment and encapsulated by a single cap. The unsingulated semiconductor package is mounted on a PCB of a computing component to increase the capacity and performance capabilities of the computing component without occupying additional space on the PCB.

Description

Background Art

[0001] Computing components typically include several semiconductor packages mounted on a printed circuit board (PCB). For example, a solid-state drive (SSD) typically includes several individual NAND memory packages mounted on a PCB.

[0002] The capacity of a computing component can be increased by adding additional semiconductor packages. For example, to increase the capacity of an SSD, additional NAND memory packages are mounted to a PCB. However, as additional semiconductor packages are added, the size of the computing component increases.

[0003] Therefore, it would be beneficial to increase the capabilities of a computing component without increasing the size of the computing component and without increasing the number of semiconductor packages mounted on a PCB of the computing component. Summary of the invention

[0004] The present application describes an unsingulated semiconductor package. In one example, the unsingulated semiconductor package includes a plurality of integrated circuits disposed on a single substrate segment. The unsingulated semiconductor package may be mounted on or otherwise coupled to a printed circuit board (PCB) of a computing component. When compared to current solutions in which a plurality of singulated semiconductor packages are mounted on a PCB of a computing component, the unsingulated semiconductor package described herein increases the capacity / performance capability of the computing component by at least fifty percent without occupying additional space on the PCB.

[0005] Thus, examples of the present disclosure describe a computing component that includes a PCB and an unsingulated semiconductor package electrically coupled to the PCB. In one example, the unsingulated semiconductor package includes a plurality of integrated circuits disposed on an unsingulated substrate segment. The unsingulated substrate segment may include a first substrate segment, a second substrate segment adjacent to the first substrate segment, and an unsingulated region disposed between the first substrate segment and the second substrate segment.

[0006] In another example, the present disclosure describes a method that includes assembling a plurality of semiconductor packages on a substrate. In one example, each semiconductor package includes a plurality of integrated circuits attached to a substrate segment. In addition, each substrate segment is defined by a plurality of sawing lanes and includes a first singulation region, a second singulation region, and an unsingulated region. In one example, a first integrated circuit among the plurality of integrated circuits is adjacent to the first singulation region, a second integrated circuit among the plurality of integrated circuits is adjacent to the second singulation region, and a third integrated circuit among the plurality of integrated circuits is placed on the unsingulated region between the first integrated circuit and the second integrated circuit. A semiconductor package singulation process is used to separate each of the plurality of semiconductor packages along each of the plurality of sawing lanes.

[0007] In yet another example, the present disclosure describes a memory device comprising a substrate having at least one sawing path separating the substrate into adjacent first and second sections. A plurality of memory dies are disposed on a first surface of the substrate. In one example, the plurality of memory dies include a first memory die mounted on the first section, a second memory die mounted on the second section, and a third memory die mounted in an area between the first section and the second section and across at least one sawing path. The memory device also includes: a member for electrically connecting the plurality of memory dies to the substrate; a member for encapsulating the plurality of memory dies; and an external electrical connection member attached to a second surface of the substrate opposite to the first surface of the substrate, the external electrical connection member allowing the memory device to be connected to a host device.

[0008] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Non-limiting and non-exhaustive examples are described with reference to the following figures.

[0010] Figure 1A A substrate strip with an array of semiconductor packages according to the current solution is shown.

[0011] Figure 1B A semiconductor package singulation process according to an example is shown. Figure 1A The singulated semiconductor packages are separated by substrate strips.

[0012] Figure 1C According to an example Figure 1B 1. A side view of a singulated semiconductor package.

[0013] Figure 1D A plurality of singulated semiconductor packages mounted on a PCB are shown according to an example.

[0014] Figure 2A A substrate strip having an array of semiconductor packages, each having a plurality of integrated circuits, is shown according to an example.

[0015] Figure 2B A semiconductor package singulation process according to an example is shown. Figure 2A A semiconductor package that has not been singulated by separating the substrate strips.

[0016] Figure 2C According to an example Figure 2B A side view of an unsingulated semiconductor package.

[0017] Figure 2D A schematic diagram showing a device mounted on a PCB according to an example Figure 2C Unsingulated semiconductor packages.

[0018] Figure 3 A method for manufacturing an unsingulated semiconductor package according to an example is shown. DETAILED DESCRIPTION

[0019] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and in which specific embodiments or examples are shown as illustrations. These aspects may be combined, other aspects may be utilized, and structural changes may be made without departing from the present disclosure. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0020] Computing components often include several semiconductor packages that are surface mounted or otherwise coupled to a printed circuit board (PCB). Typically, each semiconductor package includes a single integrated circuit. The number and type of semiconductor packages included in a particular computing component may vary depending on the intended use and / or desired performance capabilities of the computing component.

[0021] For example, a memory device such as a solid state drive (SSD) may include up to sixteen (or more) separate NAND memory packages mounted on a PCB. In addition, each NAND memory package may include a single memory die (or a stack of memory dies).

[0022] During the semiconductor package assembly process, an integrated circuit (e.g., a memory die) is attached to a designated area on a substrate panel or substrate strip. Bonding wires may be used to electrically couple the integrated circuit to the substrate and / or to interconnects associated with the semiconductor package. A mold compound and / or capping typically encapsulates the bonding wires and the integrated circuit. One or more solder balls may also be coupled to the bottom side of the substrate.

[0023] Once the semiconductor packages have been assembled, the semiconductor packages undergo a semiconductor package singulation process. During the semiconductor package singulation process, a saw (or other cutting tool, such as a laser) is used to separate each semiconductor package from other semiconductor packages assembled on a substrate panel or substrate strip.

[0024] For example, the substrate panel or substrate strip includes various saw lines or saw streets arranged in a grid pattern. During the semiconductor package singulation process, the saw cuts along each of the saw streets to produce a singulated semiconductor package. Subsequently, each singulated semiconductor package can be tested and / or individually mounted to a PCB.

[0025] This process helps ensure a high yield of usable semiconductor packages and increases the efficiency and cost-effectiveness of semiconductor package production. However, the sawing streets occupy a large area on the substrate strip. In some examples, each sawing street has a width between 0.25 millimeters (mm) and 1.3 mm. Thus, a large amount of space on the substrate strip is wasted.

[0026] To address the above issues, the present application describes an unsingulated semiconductor package that includes multiple independent integrated circuits (e.g., semiconductor dies, NAND memory dies, NAND memory die stacks, dynamic random access memory (DRAM) dies, application specific integrated circuits (ASICs)) on a single substrate segment. In one example, at least one integrated circuit of the unsingulated semiconductor package is attached to or placed on an area of ​​the substrate segment that would normally be reserved, otherwise identified as a singulation area and / or include saw streets (e.g., during a die attach phase of a semiconductor package assembly process).

[0027] During the semiconductor package singulation process, saw streets or areas of the substrate segment on which the integrated circuits are placed are skipped. Thus, an unsingulated semiconductor package having a plurality of integrated circuits is produced. Once the unsingulated semiconductor packages have been separated from other unsingulated semiconductor packages, each unsingulated semiconductor package can be tested and electrically and / or communicatively coupled to a PCB. In some examples, the performance capabilities (e.g., storage capacity) of the unsingulated semiconductor packages can be fifty percent higher when compared to currently singulated semiconductor packages while occupying the same amount of space on the PCB.

[0028] Thus, a number of technical benefits may be achieved, including, but not limited to, increasing the capacity of computing components while maintaining space requirements, and enabling semiconductor packages to be more densely arranged when compared to current solutions, which may reduce command response times and power requirements. Additionally, the present disclosure avoids unnecessary material waste by reducing the number of times substrate strips are cut, while also simplifying the semiconductor package testing process (by enabling integrated circuits of unsingulated semiconductor packages to be tested simultaneously), and by simplifying the computing component assembly process (by enabling multiple integrated circuits of unsingulated semiconductor packages to be mounted on a PCB during a single step).

[0029] About Figure 1A-Figure 3 These and other examples are shown and described in further detail.

[0030] Figure 1AA substrate strip 100 having an array of semiconductor packages 110 according to the present solution is shown. In the example shown, the substrate strip 100 includes eight semiconductor packages 110. Each semiconductor package 110 includes an integrated circuit 120. Although eight semiconductor packages 110 are shown, the substrate strip 100 may include any number of semiconductor packages 110.

[0031] Each semiconductor package 110 is assembled using any suitable semiconductor package assembly process. For example, once the integrated circuits 120 are fabricated, each integrated circuit 120 is attached to a designated area on the substrate strip 100. Figure 1A In the example shown in , a first integrated circuit is attached to a first area on the substrate strip 100 , a second integrated circuit is attached to a second area on the substrate strip 100 , and so on.

[0032] Each region on the substrate strip 100 is defined by one or more saw streets. For example, the substrate strip 100 includes a horizontal saw street 130 and a plurality of vertical saw streets 140. As shown, the saw streets are arranged in a grid pattern and are used to designate various regions or substrate segments 150 of the substrate strip 100. In an example, each saw street includes, defines, or is otherwise associated with a width "W." The width of each saw street is typically between 0.25 millimeters (mm) and 1.3 mm.

[0033] Once the integrated circuits 120 have been attached to the various regions of the substrate strip 100, a wire bonding process may be used to communicatively couple the integrated circuits 120 to their respective substrate segments 150. Subsequently, a mold compound may be used to encapsulate the integrated circuits 120 and the bond wires. Subsequently, solder balls may be attached to or otherwise formed on the bottom surface of each substrate segment 150.

[0034] Once the semiconductor package assembly process is completed, the semiconductor package singulation process separates each of the semiconductor packages 110 into singulated semiconductor packages. For example, a saw forms cuts along each of the horizontal sawing streets 130 and the vertical sawing streets 140 to separate each semiconductor package 110 from other semiconductor packages 110.

[0035] Figure 1B A semiconductor package singulation process according to an example is shown. Figure 1A The singulated semiconductor packages 115 are separated from the substrate strip 100. Figure 1B As shown in FIG. 1 , singulated semiconductor package 115 includes a single integrated circuit 120 on substrate segment 150. In one example, singulated semiconductor package 115 has a width “A” and a length “B.” Thus, semiconductor package 110 has an area of ​​A*B.

[0036] Figure 1C According to an example Figure 1B 1 is a side view of a singulated semiconductor package 115. As previously discussed, the singulated semiconductor package 115 includes an integrated circuit 120 mounted on a substrate segment 150. Bond wires 160 electrically and / or communicatively couple the integrated circuit 120 to the substrate segment 150 and / or to various solder balls 180 disposed on the bottom surface of the substrate segment 150. A mold compound or cover 170 may encapsulate the integrated circuit 120 and the bond wires 160.

[0037] Figure 1D A plurality of singulated semiconductor packages 115 are shown mounted on a PCB 190 according to an example. As shown, each singulated semiconductor package 115 is separately mounted to the PCB 190. In an example, the singulated semiconductor packages 115 occupy an area on the PCB 190 equivalent to (2A+Space)*B, where "Space" (denoted by reference numeral 195) is the amount of space between each singulated semiconductor package 115 on the PCB 190.

[0038] Figure 2A A substrate strip 200 is shown having an array of semiconductor packages 210 according to an example, wherein each semiconductor package 210 has a plurality of integrated circuits 220. In the example shown, the substrate strip 200 includes four semiconductor packages 210. Although four semiconductor packages 210 are shown, the substrate strip 200 may include any number of semiconductor packages 210.

[0039] About Figure 1A In contrast to the semiconductor package 110 shown and described as including a single integrated circuit 120, each semiconductor package 210 includes a plurality of integrated circuits 220. For example, each semiconductor package 210 includes three different / separate integrated circuits 220. Although three integrated circuits 220 are shown, the semiconductor package 210 may have less than three (e.g., two) integrated circuits 220 or more than three integrated circuits 220.

[0040] In one example, the substrate strip 200 includes various regions or substrate segments. For example, the substrate strip 200 may include a first substrate segment 250A and a second substrate segment 250B. In addition, each region or substrate segment may be defined by various saw streets. For example, the substrate strip 200 includes a horizontal saw street 230 and a plurality of vertical saw streets (e.g., a first vertical saw street 240, a second vertical saw street 245, and a third vertical saw street 255). Although a specific number of saw streets are shown, the substrate strip 200 may include any number of horizontal and vertical saw streets.

[0041] Each saw street has a width "W". In one example, the width of each saw street is between 0.25 mm and 1.3 mm, but other widths may be used. For purposes of explanation, each saw street may be identified or otherwise referred to as a singulation region. As used herein, a singulation region is an area or portion of the substrate strip 200 that contains a saw street, or is identified as an area that would typically contain a saw street (e.g., if one integrated circuit 220 is placed on each substrate segment, e.g., Figure 1A , then the region includes or will include a saw street). In one example and as will be described in more detail below, the singulation region or saw street may be cut during the semiconductor package singulation process, or the singulation region or saw street may be skipped during the semiconductor package singulation process.

[0042] In one example, each semiconductor package 210 is assembled using any suitable semiconductor package assembly process. For example, once the integrated circuits 220 are fabricated, the integrated circuits 220 are placed and / or arranged on the semiconductor strip 200. In one example, the first integrated circuit 220 is placed adjacent to a first singulation area or saw street, the second integrated circuit 220 is placed adjacent to a second singulation area or saw street, and the third integrated circuit 220 is placed on an unsingulated area disposed between the first integrated circuit 220 and the second integrated circuit 220.

[0043] In one example, the unsingulated area is an area on the substrate strip 200 that contains a saw street (e.g., the first vertical saw street 240 or the third vertical saw street 255) or is otherwise identified as a singulated area (e.g., a saw street may or may not exist on the singulated area, but will be skipped or otherwise not cut during the semiconductor package singulation process). In one example, two or more adjacent substrate segments may be combined or otherwise remain unsingulated after the semiconductor package singulation process has occurred. For example, the first substrate segment 250A and the second substrate segment 250B may remain combined or otherwise remain unseparated (e.g., unsingulated) during the semiconductor package singulation process.

[0044] Once the integrated circuits 220 have been attached to the various regions of the substrate strip 200, a wire bonding process may be used to communicatively couple each integrated circuit 220 of the semiconductor package 210 to its respective substrate segment. Subsequently, a mold compound may be used to encapsulate the integrated circuits 220 and the bonding wires. Subsequently, solder balls may be attached to or otherwise formed on the bottom surface of the substrate strip 200.

[0045] Once the semiconductor package assembly process is complete, the semiconductor package singulation process separates each of the semiconductor packages 220 into separate “un-singulated” semiconductor packages. For example, the semiconductor package singulation process causes a saw (or other cutting mechanism) to form cuts along the horizontal saw street 230 and the second vertical saw street 245. The semiconductor package singulation process bypasses or skips cutting along the first vertical saw street 240 and the third vertical saw street 255.

[0046] Figure 2B FIG. 2 shows an unsingulated semiconductor package 215 according to an example. Figure 2A The substrate strip 200 is shown and described as performing a semiconductor package singulation process to produce un-singulated semiconductor packages 215 .

[0047] In one example, the unsingulated semiconductor package 215 includes a plurality of separate / independent integrated circuits 220 on an unsingulated substrate segment 275. For example, the unsingulated substrate segment 275 includes two adjacent substrate segments (e.g., substrate segment 250A and substrate segment 250B) and at least one saw street (e.g., first vertical saw street 240 ( Figure 2A ) part).

[0048] For example, the unsingulated semiconductor package 215 includes a first integrated circuit 220A, a second integrated circuit 220B, and a third integrated circuit 220C. In one example, each of the integrated circuits 220 is a NAND memory die or a stack of NAND memory dies. In another example, the integrated circuit is any type of semiconductor die or chip, such as a DRAM die, an ASIC, etc.

[0049] In one example, the first integrated circuit 220A is adjacent to the first singulation region 260 (e.g., a region including saw streets or otherwise sawed through during a semiconductor package singulation process), and the second integrated circuit 220B is adjacent to the second singulation region 265. In addition, the third integrated circuit 220C is disposed on the unsingulated region 270.

[0050] In one example, the unsingulated areas 270 may include saw streets (e.g., at least portions of the first vertical saw streets 240) that are skipped or otherwise not sawed through during the semiconductor package singulation process. In one example, the saw streets that include portions of the unsingulated areas 270 may be visible or otherwise present on the substrate strip 200. In another example, the saw streets themselves may not be visible or present, but may be visible or present if the integrated circuits 220 are formed in a manner similar to those of FIG. Figure 1A, then the unsingulated region 270 can be identified as the region where the saw streets (or singulation regions) would typically be present. In another example, the unsingulated region 270 can include the region between two adjacent semiconductor segments (e.g., semiconductor segment 250A and semiconductor segment 250B).

[0051] In one example, the unsingulated semiconductor package 215 has a width of "2A+W", where "A" is the width of the first semiconductor segment 250A and the width of the second semiconductor segment 250B, and where "W" is the width of the saw street (e.g., the first vertical saw street 240) that is skipped or passed over from the semiconductor package singulation process. The unsingulated semiconductor package 215 also has a length "B". Thus, the unsingulated semiconductor package 215 has an area of ​​(2A+W)*B.

[0052] Figure 2C According to an example Figure 2B 2 is a side view of an unsingulated semiconductor package 215. In one example, the unsingulated semiconductor package 215 includes a plurality of integrated circuits on unsingulated semiconductor segments. For example, a first integrated circuit 220A is attached to or mounted on a first substrate segment 250A, a second integrated circuit 220B is attached to or mounted on a second substrate segment 250B, and a third integrated circuit 220C is attached to or mounted on an unsingulated region 270 between the first integrated circuit 220A and the second integrated circuit 220B.

[0053] In one example, the un-singulated area 270 includes at least a portion of the first substrate segment 250A, at least a portion of the second substrate segment 250B, and saw streets (or other areas identified as singulation areas) that will be skipped or otherwise not cut during the semiconductor package singulation process.

[0054] Figure 2C Each integrated circuit is also shown to include bond wires 280 that electrically and / or communicatively couple the integrated circuit to the substrate and / or to various solder balls 290 disposed on the bottom surface of the substrate. A mold compound, cap, or cover 285 may encapsulate the integrated circuits and bond wires 280.

[0055] Figure 2D FIG. 2 shows an unsingulated semiconductor package 215 mounted on a PCB 295 according to an example. Figure 1D When compared to the semiconductor package 110 shown in , the unsingulated semiconductor package 215 increases the capacity by at least fifty percent while occupying the same or substantially the same area on the PCB 295 .

[0056] For example and as previously described, the unsingulated semiconductor package 215 may occupy an area of ​​(2A+W)*B, while the two singulated semiconductor packages 115 may occupy an area of ​​(2A+Space)*B. Depending on the comparison of "Space" to "W," the unsingulated semiconductor package 215 may occupy the same or similar area on the PCB 295 as the two singulated semiconductor packages 115, but with at least fifty percent increased capacity (e.g., due to the additional integrated circuits).

[0057] Figure 3 A method 300 for manufacturing a semiconductor package that has not been singulated is shown according to an example. In one example, the method 300 can be used to manufacture a semiconductor package that has not been singulated. Figure 2B-2C Unsingulated semiconductor package 215 is shown and described. In another example, method 300 can be used to fabricate a computing component that utilizes one or more unsingulated semiconductor packages.

[0058] The method 300 begins when an integrated circuit is manufactured (310). In one example, the integrated circuit is manufactured using one or more manufacturing techniques / processes. Once the integrated circuit has been manufactured, the integrated circuit is attached (320) to one or more substrate segments of a substrate strip. In one example, the substrate strip includes a number of saw streets or segmentation regions. The saw streets or segmentation regions may be arranged in a grid or other pattern and may define one or more of the substrate segments.

[0059] During placement of the integrated circuits, a first integrated circuit may be placed on the substrate strip (or substrate segment) adjacent to the first singulation region. Likewise, a second integrated circuit may be placed on the substrate strip (or substrate segment) adjacent to the second singulation region. Furthermore, a third integrated circuit may be placed on the substrate strip (or substrate segment) at an area identified as a non-singulated area.

[0060] In one example, the unsingulated area may be between the first integrated circuit and the second integrated circuit. The unsingulated area may (or may not) include saw streets, or may be otherwise identified as potential singulation areas. However, as will be described below, even if the unsingulated area includes saw streets (or is otherwise identified as a singulation area), the saw streets will not be cut during a subsequent semiconductor package singulation process (e.g., the saw streets will be skipped). In addition to the placement / attachment of the integrated circuits on the substrate strip, operation 320 may also include a wire bonding process, an encapsulation process, and / or a solder ball attach process.

[0061] When the semiconductor package has been assembled, saw lanes to be used in the semiconductor package singulation process are identified (330). In one example, the saw lanes identified for cutting are saw lanes on which integrated circuits have not yet been placed. In another example and as part of the semiconductor package singulation process, one or more saw lanes may be selected for cutting / sawing, while other saw lanes may be skipped or otherwise not selected for cutting / sawing. In yet another example, saw lanes on which integrated circuits were placed during operation 320 may be identified as saw lanes to be skipped during the semiconductor singulation process.

[0062] Subsequently, a semiconductor package singulation process may be performed (340). It should be appreciated that the semiconductor package singulation process of the present disclosure requires fewer cuts to produce a higher density semiconductor package when compared to current solutions. For example, because the integrated circuits may be placed on or otherwise associated with some sawing streets, those sawing streets are skipped during the semiconductor package singulation process. Thus, a higher density semiconductor package is produced with fewer cutting steps / processes.

[0063] Once the semiconductor packages have been separated, the unsingulated semiconductor packages are tested (350). In one example, because the unsingulated semiconductor packages contain multiple integrated circuits, the testing process can be simplified when compared to current solutions. For example, a single testing process can test two (or more) integrated circuits at a time when compared to current solutions in which a single integrated circuit in a semiconductor package is tested.

[0064] After passing the testing process, the unsingulated semiconductor package can be mounted (360) on the PCB. Like the singulation and testing process, the mounting process is also an improvement over current solutions. For example, a single mounting process using an unsingulated semiconductor package enables two (or more) integrated circuits to be attached to a PCB, as compared to the single integrated circuit typically included in current semiconductor packages.

[0065] Based on the above, an example of the present disclosure describes a computing component, which includes: a printed circuit board (PCB); and an unsingulated semiconductor package electrically coupled to the PCB, the unsingulated semiconductor package including: a plurality of integrated circuits disposed on an unsingulated substrate segment, the unsingulated substrate segment including: a first substrate segment; a second substrate segment adjacent to the first substrate segment; and an unsingulated region disposed between the first substrate segment and the second substrate segment. In one example, the unsingulated substrate segment is associated with a plurality of sawing streets. In one example, each of the plurality of sawing streets has a width between 0.25 millimeters (mm) and 1.3 mm. In one example, a first integrated circuit of the plurality of integrated circuits is disposed on the first substrate segment; a second integrated circuit of the plurality of integrated circuits is disposed on the second substrate segment; and a third integrated circuit of the plurality of integrated circuits is disposed on the unsingulated region. In one example, the unsingulated region is associated with a sawing street that is skipped during a semiconductor package singulation process. In one example, each of the plurality of integrated circuits includes one or more semiconductor dies. In one example, the plurality of integrated circuits are encapsulated by a single cover. In one example, an unsingulated semiconductor package is separated from a plurality of other unsingulated semiconductor packages during a semiconductor package singulation process.

[0066] The example also describes a method, which includes: assembling a plurality of semiconductor packages on a substrate, wherein: each semiconductor package includes a plurality of integrated circuits attached to a substrate segment; and each substrate segment is defined by a plurality of sawing streets and includes a first singulation area, a second singulation area, and an unsingulated area, wherein a first integrated circuit of the plurality of integrated circuits is adjacent to the first singulation area, a second integrated circuit of the plurality of integrated circuits is adjacent to the second singulation area, and a third integrated circuit of the plurality of integrated circuits is placed on the unsingulated area between the first integrated circuit and the second integrated circuit; and performing a semiconductor package singulation process to separate each of the plurality of semiconductor packages along each of the plurality of sawing streets. In one example, the method further includes mounting at least one semiconductor package of the plurality of semiconductor packages on a printed circuit board (PCB). In one example, the unsingulated area is associated with a sawing street that is skipped during the semiconductor package singulation process. In one example, the sawing street has a width between 0.25 millimeters (mm) and 1.3 mm. In one example, each of the plurality of integrated circuits includes one or more semiconductor dies.

[0067] The example also describes a memory device, comprising: a substrate having at least one sawing road separating the substrate into adjacent first and second sections; a plurality of memory dies disposed on a first surface of the substrate, wherein the plurality of memory dies include a first memory die mounted on the first section, a second memory die mounted on the second section, and a third memory die mounted in an area between the first section and the second section and across at least one sawing road; a member for electrically connecting the plurality of memory dies to the substrate; a member for encapsulating the plurality of memory dies; and an external electrical connection member attached to a second surface of the substrate opposite to the first surface of the substrate, the external electrical connection member allowing the memory device to be connected to a host device. In one example, the electrical connection member comprises a bonding wire. In one example, at least one sawing road has a width between 0.25 millimeters (mm) and 1.3 mm. In one example, the memory die comprises a NAND die. In one example, at least one sawing road is a sawing road that is skipped during a semiconductor package singulation process. In one example, the encapsulation member comprises a molding compound. In one example, the external electrical connection members include solder balls.

[0068] The description and illustration of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of this disclosure in any way. The aspects, examples and details provided in this disclosure are considered sufficient to convey ownership and enable others to make and use the best mode of the claimed disclosure.

[0069] The disclosure required should not be construed as being limited to any aspect, example or detail provided in the present disclosure. Whether combined or separately displayed and described, various features (structures and methods) are intended to be selectively rearranged, included or omitted to produce an embodiment with a specific feature set. After the description and illustration of the present application have been provided, those skilled in the art may envision changes, modifications and alternative aspects within the spirit of the broader aspects of the general inventive concept embodied in the present application, which changes, modifications and alternative aspects do not depart from the broader scope of the disclosure required.

[0070] Aspects of the present disclosure have been described above with reference to schematic flow charts and / or schematic block diagrams of methods, devices, systems, and computer program products according to embodiments of the present disclosure. It should be understood that each frame of the schematic flow chart and / or schematic block diagram and the combination of frames in the schematic flow chart and / or schematic block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor or other programmable data processing device of a computer to produce a machine, so that instructions executed via a processor or other programmable data processing device produce components for implementing the functions and / or actions specified in the frames of one or more schematic flow charts and / or schematic block diagrams. In addition, it is expected that aspects of the flow chart and / or flow chart can be combined and / or executed in any order.

[0071] References to elements using identifiers such as "first," "second," etc. herein generally do not limit the number or order of those elements. In fact, these identifiers can be used as a method of distinguishing two or more elements or examples of elements. Thus, reference to a first element and a second element does not mean that only two elements can be used, or that the first element is before the second element. Furthermore, unless otherwise stated, a collection of elements may include one or more elements.

[0072] A term of the form "at least one of A, B, or C" or "A, B, C, or any combination thereof" used in the description or claims means "A or B or C, or any combination of these elements." For example, this term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, or 2A and B, etc. As an additional example, "at least one of: A, B, or C" is intended to cover A, B, C, AB, AC, BC, and ABC, and multiples of the same member. Similarly, "at least one of: A, B, and C" is intended to cover A, B, C, AB, AC, BC, and ABC, and multiples of the same member.

[0073] Similarly, as used herein, a phrase referring to a list of items associated with "and / or" refers to any combination of the items. As an example, "A and / or B" is intended to cover A alone, B alone, or A and B together. As another example, "A, B, and / or C" is intended to cover A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

Claims

1. A computing component comprising: Printed circuit board (PCB); as well as an unsingulated semiconductor package electrically coupled to the PCB, the unsingulated semiconductor package comprising: A plurality of integrated circuits disposed on an unsingulated substrate segment, the unsingulated substrate segment comprising: a first substrate segment; a second substrate segment adjacent to the first substrate segment; and An unsingulated region is disposed between the first substrate segment and the second substrate segment. 2 . The computing component of claim 1 , wherein the unsingulated substrate segments are associated with a plurality of saw streets. 3 . The computing component of claim 2 , wherein each of the plurality of saw streets has a width between 0.25 millimeters (mm) and 1.3 mm.

4. The computing component of claim 1, wherein: A first integrated circuit of the plurality of integrated circuits is disposed on the first substrate segment; A second integrated circuit of the plurality of integrated circuits is disposed on the second substrate segment; and A third integrated circuit of the plurality of integrated circuits is disposed on the unsingulated region. 5 . The computing component of claim 1 , wherein the unsingulated areas are associated with saw streets that were skipped during a semiconductor package singulation process.

6. The computing component of claim 1, wherein each of the plurality of integrated circuits comprises one or more semiconductor dies.

7. The computing component of claim 1, wherein the plurality of integrated circuits are enclosed by a single cover.

8. The computing component of claim 1, wherein the unsingulated semiconductor package is separated from a plurality of other unsingulated semiconductor packages during a semiconductor package singulation process.

9. A method comprising: A plurality of semiconductor packages are assembled on a substrate, wherein: Each semiconductor package includes a plurality of integrated circuits attached to a substrate segment; and each substrate segment is defined by a plurality of saw streets and includes a first singulation region, a second singulation region, and an unsingulated region, wherein a first integrated circuit of the plurality of integrated circuits is adjacent to the first singulation region, a second integrated circuit of the plurality of integrated circuits is adjacent to the second singulation region, and a third integrated circuit of the plurality of integrated circuits is placed on the unsingulated region between the first integrated circuit and the second integrated circuit; and A semiconductor package singulation process is performed to separate each of the plurality of semiconductor packages along each of the plurality of saw streets. 10 . The method of claim 9 , further comprising mounting at least one semiconductor package of the plurality of semiconductor packages on a printed circuit board (PCB). 11 . The method of claim 9 , wherein the unsingulated areas are associated with saw streets that were skipped during the semiconductor package singulation process. 12 . The method of claim 11 , wherein the saw streets have a width between 0.25 millimeters (mm) and 1.3 mm.

13. The method of claim 9, wherein each of the plurality of integrated circuits comprises one or more semiconductor dies.

14. A memory device comprising: a substrate having at least one saw street separating the substrate into adjacent first and second sections; a plurality of memory dies disposed on a first surface of the substrate, wherein the plurality of memory dies include a first memory die mounted on the first section, a second memory die mounted on the second section, and a third memory die mounted in an area between the first section and the second section and across the at least one saw street; means for electrically connecting the plurality of memory dies to the substrate; means for encapsulating the plurality of memory dies; as well as External electrical connection means are attached to a second surface of the substrate opposite the first surface of the substrate, the external electrical connection means allowing the memory device to be connected to a host device. The memory device of claim 14 , wherein the electrical connection means comprises a bonding wire.

16. The memory device of claim 14, wherein the at least one saw street has a width between 0.25 millimeters (mm) and 1.3 mm.

17. The memory device of claim 14, wherein the memory die comprises a NAND die.

18. The memory device of claim 14, wherein the at least one saw street is a saw street that is skipped during a semiconductor package singulation process.

19. The memory device of claim 14, wherein the encapsulation member comprises a molding compound.

20. The memory device of claim 14, wherein the external electrical connection members include solder balls.

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