Wiring substrate, semiconductor package having wiring substrate, and method of manufacturing same

Abstract

Provided are: a wiring substrate in which a thick wiring layer to which a large current can be applied and a thin wiring layer to which precision processing can be performed coexist in the same layer; and a method for manufacturing the wiring substrate. The present invention provides a wiring substrate comprising: an insulating film which is positioned on a first wiring and has a through hole; and a second wiring on the insulating film. The second wiring has a laminated structure including a first layer and a second layer on the first layer and in contact with the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping the first layer is different from a thickness of the second layer within the via.

Description

[0001] This application is a divisional application of a patent application with an application date of November 22, 2016, a priority date of December 11, 2015, an application number of 201611048337.5, and an invention name of “Wiring substrate, semiconductor package with wiring substrate and manufacturing method thereof”. Technical Field

[0002] The present invention relates to a wiring substrate, a semiconductor package or a stacked semiconductor package having the wiring substrate, and methods for manufacturing the same. For example, the present invention relates to a wiring substrate for a power device driven by a large current, a semiconductor package or a stacked semiconductor package having the wiring substrate, and methods for manufacturing the same. Background Art

[0003] Power devices are semiconductor devices whose basic functions are the conversion and control of electric power. The above-mentioned power devices are not only used in inverters or small motors used in home appliances or OA (office automation) machines, but also play an important role in the conversion or control of electric power in the power system of power plants, motor drive systems of electric cars or cars, etc. Unlike semiconductor devices such as thin film transistors used in displays, etc., power devices are driven by high voltage and large currents are applied. Therefore, countermeasures for heating of wiring caused by large currents have been studied (see Japanese Patent Publication No. 2013-219267, Japanese Patent Publication No. 2005-79462, and Japanese Patent Publication No. 2015-162516). Summary of the invention

[0004] In one embodiment of the present invention, a wiring substrate comprises: an insulating film located on a first wiring and having a via; and a second wiring on the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is directly connected to the first wiring at the via. The thickness of the second layer in the region overlapping the first layer is different from the thickness of the second layer in the via.

[0005] In the above-mentioned embodiment, the film thickness of the second layer in the through hole may be greater than the film thickness of the second layer in the region overlapping with the first layer. The film thickness of the first layer may be greater than the film thickness of the second layer in the region overlapping with the first layer. The first layer and the second layer may contain copper. The electrical conductivity of the first layer and the second layer may be different from each other. The upper surface of the insulating film may have a recess between the through hole and the first layer.

[0006] In one embodiment of the present invention, a wiring substrate comprises: an insulating film located on a first wiring and having a through hole; and a second wiring on the insulating film. The second wiring has a stacked structure, the stacked structure comprising: a second layer directly connected to the first wiring in the through hole; and a first layer located on the second layer and electrically connected to the second layer. The thickness of the second layer in the region overlapping the insulating film is different from the thickness of the first layer in the through hole.

[0007] In the above embodiment, the film thickness of the second layer in the through hole may be greater than the film thickness of the second layer in the region overlapping with the insulating film. The film thickness of the first layer may be greater than the film thickness of the second layer in the region overlapping with the insulating film. The first layer and the second layer may contain copper. The electrical conductivity of the first layer and the second layer may be different from each other.

[0008] In one embodiment of the present invention, a semiconductor package has: a semiconductor device having a terminal; an insulating film located on the terminal and having a through hole; and wiring on the insulating film. The wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is directly connected to the terminal in the through hole, and the thickness of the second layer in the region overlapping the first layer is different from the thickness of the second layer in the through hole.

[0009] In the above-mentioned embodiment, the film thickness of the second layer in the through hole may be greater than the film thickness of the second layer in the region overlapping with the first layer. The film thickness of the first layer may be greater than the film thickness of the second layer in the region overlapping with the first layer. The first layer and the second layer may contain copper. The electrical conductivity of the first layer and the second layer may be different from each other. The upper surface of the insulating film may have a recess between the through hole and the first layer.

[0010] In one embodiment of the present invention, a semiconductor package comprises: a semiconductor device located on a first wiring and having a first terminal and a second terminal; an insulating film located on the second terminal and having a through hole; and a second wiring on the insulating film. The second wiring has a stacked structure, the stacked structure comprising: a second layer directly connected to the second terminal in the through hole; and a first layer located on the second layer and electrically connected to the second layer. The thickness of the second layer in the region overlapping the insulating film is different from the thickness of the second layer in the through hole.

[0011] In the above embodiment, the film thickness of the second layer in the through hole may be greater than the film thickness of the second layer in the region overlapping with the insulating film. The film thickness of the first layer may be greater than the film thickness of the second layer in the region overlapping with the insulating film. The first layer and the second layer may contain copper. The electrical conductivity of the first layer and the second layer may be different from each other.

[0012] One embodiment of the present invention provides a method for manufacturing a wiring substrate. The above-mentioned method for manufacturing a wiring substrate includes the following steps: forming an insulating film on a first wiring; and forming a second wiring layer having a first layer and a second layer on the above-mentioned insulating film. The formation of the second wiring includes the following steps: forming the above-mentioned second layer by bonding a metal plate to the above-mentioned insulating film; forming an opening in the above-mentioned second layer to expose the above-mentioned insulating film; forming a through hole in the above-mentioned insulating film to expose the above-mentioned first wiring; and forming the above-mentioned first layer by electrolytic plating in a manner that it is located on the above-mentioned first wiring and the above-mentioned second layer and is directly connected to the above-mentioned first wiring and the above-mentioned second layer.

[0013] In the above embodiment, the film thickness of the second layer in the through hole may be greater than the film thickness of the second layer in the region overlapping with the first layer. The film thickness of the first layer may be greater than the film thickness of the second layer in the region overlapping with the first layer. The first layer and the second layer may contain copper. The electrical conductivity of the first layer and the second layer may be different from each other.

[0014] One embodiment of the present invention provides a method for manufacturing a wiring substrate. The above-mentioned method for manufacturing a wiring substrate includes the following steps: forming an insulating film on a first wiring; forming a through hole in the above-mentioned insulating film to expose the above-mentioned first wiring; and forming a second wiring having a first layer and a second layer on the above-mentioned insulating film. The formation of the second wiring includes the following steps: forming the above-mentioned second layer by electrolytic plating in a manner that is located on the above-mentioned first wiring and the above-mentioned insulating film and is in contact with the above-mentioned first wiring and the above-mentioned insulating film; and forming the above-mentioned first layer in a manner that is electrically connected to the above-mentioned second layer by providing a metal plate on the above-mentioned second layer.

[0015] In the above embodiment, the film thickness of the second layer in the through hole may be greater than the film thickness of the second layer in the region overlapping with the insulating film. The film thickness of the first layer may be greater than the film thickness of the second layer in the region overlapping with the insulating film. The first layer and the second layer may contain copper. The electrical conductivity of the first layer and the second layer may be different from each other.

[0016] One embodiment of the present invention provides a method for manufacturing a semiconductor package. The method for manufacturing the semiconductor package includes the following steps: providing a semiconductor device having a first terminal and a second terminal on a first wiring; forming an insulating film on the second terminal; and forming a second wiring having a first layer and a second layer on the insulating film. The formation of the second wiring includes the following steps: forming the second layer by bonding a metal plate to the insulating film; forming an opening in the second layer to expose the insulating film; forming a through hole in the insulating film to expose the first wiring; and forming the first layer by electrolytic plating in a manner that it is located on the first wiring and the second layer and is directly connected to the first wiring and the second layer.

[0017] In the above-mentioned embodiment, the film thickness of the second layer in the through hole may be greater than the film thickness of the second layer in the region overlapping with the first layer. The film thickness of the first layer may be greater than the film thickness of the second layer in the region overlapping with the first layer. The first layer and the second layer may contain copper. The electrical conductivity of the first layer and the second layer may be different from each other. The upper surface of the insulating film may have a recess between the through hole and the first layer.

[0018] One embodiment of the present invention provides a method for manufacturing a semiconductor package. The method for manufacturing the semiconductor package includes the following steps: forming a semiconductor device having a first terminal and a second terminal on a first wiring; forming an insulating film on the second terminal; and forming a second wiring having a first layer and a second layer on the insulating film. The formation of the second wiring includes the following steps: forming the second layer by electrolytic plating in a manner that is located on the first wiring and the insulating film and is in contact with the first wiring and the insulating film; and forming the first layer in a manner that is electrically connected to the second layer by providing a metal plate on the second layer.

[0019] In the above embodiment, the film thickness of the second layer in the through hole may be greater than the film thickness of the second layer in the region overlapping with the insulating film. The film thickness of the first layer may be greater than the film thickness of the second layer in the region overlapping with the insulating film. The first layer and the second layer may contain copper. The electrical conductivity of the first layer and the second layer may be different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figures 1A to 1E A diagram showing a wiring substrate and a method for manufacturing the same according to an embodiment of the present invention.

[0021] FIG. 2A to FIG. 2D A diagram showing a wiring substrate and a method for manufacturing the same according to an embodiment of the present invention.

[0022] FIG. 3A to FIG. 3D A diagram showing a wiring substrate and a method for manufacturing the same according to an embodiment of the present invention.

[0023] Figure 4A , Figure 4B A diagram showing a wiring substrate and a method for manufacturing the same according to an embodiment of the present invention.

[0024] FIG. 5A to FIG. 5C It is a diagram showing a semiconductor package and a method for manufacturing the same according to an embodiment of the present invention.

[0025] FIG. 6A to FIG. 6C It is a diagram showing a semiconductor package and a method for manufacturing the same according to an embodiment of the present invention.

[0026] FIG. 7A to FIG. 7C It is a diagram showing a semiconductor package and a method for manufacturing the same according to an embodiment of the present invention.

[0027] FIG. 8A to FIG. 8C It is a diagram showing a semiconductor package and a method for manufacturing the same according to one embodiment of the present invention.

[0028] Fig.9A , Fig. 9B It is a diagram showing a semiconductor package and a method for manufacturing the same according to an embodiment of the present invention.

[0029] Fig. 10A , Fig. 10B It is a diagram showing a semiconductor package and a method for manufacturing the same according to one embodiment of the present invention.

[0030] Fig.11 This is a circuit diagram of a semiconductor package according to one embodiment of the present invention.

[0031] Fig.12 FIG. 1 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0032] Fig.13 FIG. 1 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0033] (Explanation of Reference Numerals)

[0034] 100: first wiring; 110: insulating film; 115: through hole; 120: metal plate; 125: first layer;

[0035] 130: second layer; 140: second wiring; 200: first wiring; 210: insulating film; 215: through hole;

[0036] 220: second layer; 225: metal bonding layer; 230: first layer; 240: second wiring; 300: first wiring;

[0037] 310: insulating film; 312: recess; 315: through hole; 320: metal plate; 330: second layer;

[0038] 340: second wiring; 400: first wiring; 410: adhesive layer; 420: semiconductor device;

[0039] 422: first terminal; 424: second terminal; 430: insulating film; 432: through hole; 434: through hole;

[0040] 440: metal plate; 445: first layer; 450: second layer; 460: second wiring; 470: third layer;

[0041] 480: fourth layer; 490: third wiring; 500: first wiring; 510: adhesive layer; 520: semiconductor device;

[0042] 522: first terminal; 524: second terminal; 530: insulating film; 532: through hole; 534: through hole;

[0043] 540: second layer; 550: metal bonding layer; 560: first layer; 570: second wiring; 580: third layer;

[0044] 585: fourth layer; 590: third wiring; 600: control IC; 602: terminal; 610: power device;

[0045] 612: first terminal; 614: second terminal; 620: power device; 622: first terminal;

[0046] 624: second terminal; 630: first wiring; 640: adhesive layer; 650: metal adhesive layer; 660: insulating film;

[0047] 665: insulating film; 670: first layer; 680: second layer; 690: second wiring; 695: upper wiring;

[0048] 700: second layer; 710: metal bonding layer; 720: first layer; 730: second wiring; 740: insulating film;

[0049] 750: Upper wiring DETAILED DESCRIPTION

[0050] Hereinafter, various embodiments of the present invention will be described with reference to the drawings, etc. However, the present invention can be implemented in various embodiments without departing from the gist thereof, and therefore the present invention should not be interpreted as being limited to the description of the embodiments illustrated below.

[0051] In addition, in order to make the description clearer, the drawings schematically show the width, thickness and shape of each part compared with the actual implementation. In the final analysis, the drawings are only examples and are not used to limit the interpretation of the present invention. In addition, in the specification and each drawing of the present invention, the same figure number is given to the elements having the same function as the elements described for the existing drawings, and repeated description is omitted.

[0052] Even if there are other effects different from the effects brought about by the modes of each embodiment described below, effects that are clearly known according to the description of the specification of the present invention or effects that are easily predicted by ordinary technicians in the field to which the present invention belongs should be understood as effects brought about by the present invention.

[0053] (First Embodiment)

[0054] In the embodiment of the present invention, a wiring structure and a manufacturing method thereof used in a wiring substrate of one embodiment of the present invention will be described with reference to FIG. Figure 1E As shown in FIG. 1 , the wiring structure includes a wiring (second wiring 140) formed by stacking a thick layer (first layer 125) through which a large current can flow and a thin layer (second layer 130) through which precision machining can be performed and electrically connected to each other. In addition, the thin second layer 130 is also formed in the through hole. Such a wiring structure can be used to electrically connect a plurality of stacked wiring layers or wiring substrates.

[0055] Specifically, Figure 1A As shown, an insulating film 110 is formed on the first wiring 100. The first wiring 100 may be a wiring formed on an insulating substrate such as a glass or plastic substrate, or may be a lead or pad provided on an integrated circuit (IC) chip or a power device. The first wiring 100 may include metals such as gold, copper, titanium, molybdenum, and aluminum. As the insulating film 110, an organic material such as acrylic resin, polyimide resin, or polyester resin may be used, and the insulating film 110 may be formed by a wet film forming method such as a spin coating method, an inkjet method, and a printing method. Alternatively, the insulating film 110 may be formed by providing a film of the above-mentioned resin on the first wiring 100 and performing crimping (lamination processing).

[0056] Next, the metal plate 120 is bonded to the insulating film 110 ( Figure 1A , Figure 1B ). The metal plate 120 may be made of, for example, copper or gold. The thickness of the metal plate 120 only needs to be selected to allow sufficient current to flow through the wiring substrate. For example, the thickness of the metal plate 120 can be selected from a range of 1 μm to 10 mm, and preferably, the thickness of the metal plate 120 is in a range of 100 μm to 300 μm. The metal plate 120 can be bonded by applying pressure from the upper portion of the insulating film 110 while being heated. Figure 1A In the embodiment, the metal plate 120 has a recessed portion formed by half etching, etc. By forming the recessed portion, the opening described later can be easily formed, but the embodiments of the present invention are not limited to these embodiments, and a metal plate 120 having no recessed portion and having a flat surface can also be used.

[0057] Next, if Figure 1C As shown, an opening is formed on the metal plate 120 by etching or the like, the insulating film 110 is exposed, and the first layer 125 is formed at the same time. In the case where the metal plate 120 has a concave portion, since etching is started from the region overlapping the concave portion (the opposite side of the concave portion), the opening can be easily opened at the position corresponding to the concave portion. Etching can be any method of dry etching or wet etching.

[0058] Next, if Figure 1DAs shown, the insulating film 110 exposed by forming an opening in the metal plate 120 is laser processed or etched to form the through hole 115. Thus, the surface of the first wiring 100 is exposed.

[0059] Afterwards, if Figure 1E As shown, the second layer 130 is formed by electrolytic plating or the like. For example, electrolytic copper plating or electrolytic gold plating can be used for the electrolytic plating, thereby forming the second layer 130 with copper or gold. The wiring having the stacked structure of the first layer 125 and the second layer 130 is the second wiring 140.

[0060] At this time, the second layer 130 is formed to cover the first layer 125 and bury the through hole 115. In other words, the film thickness of the second layer 130 in the region overlapping with the first layer 125 is different from the film thickness of the second layer 130 in the through hole 115, and the film thickness of the latter is larger. In addition, in the case where the film thickness of the second layer 130 formed in the through hole 115 is small, for example, the through hole 115 can be buried with a conductive paste or the like after or before the formation of the second layer 130. As the conductive paste, a gold paste, a silver paste, or the like can be used. Afterwards, the second layer 130 can be processed by etching or the like to form the desired circuit wiring.

[0061] The thickness of the second layer 130 may be smaller than the thickness of the first layer 125. Specifically, the thickness of the second layer 130 in the region overlapping with the first layer 125 may be smaller than the thickness of the first layer 125. Thus, the time for forming the second layer 130 can be shortened, and the process can be shortened. The thickness of the second layer 130 may be 1 μm to 50 μm, preferably 10 μm to 30 μm.

[0062] The resistivity of the first layer 125 and the second layer 130 may be different. Alternatively, the concentration of impurities in the first layer 125 and the second layer 130 may be different. Alternatively, the density of the first layer 125 and the second layer 130 may be different.

[0063] In addition, the second layer 130 may be formed by, for example, sputtering other than the electrolytic plating method.

[0064] Generally, when packaging power devices, wire bonding or clip electrodes are used to connect the power devices to external electrodes. Unlike semiconductor devices such as thin film transistors used in displays, power devices can be driven by high voltages and large currents can be applied. Since it is difficult to thicken the wiring using connection methods such as wire bonding, heat generation caused by wiring resistance becomes a major problem when such a large current is applied.

[0065] In addition, in recent years, in response to the requirements of high integration, low cost and miniaturization of devices, a stacked package has been proposed, which has a structure in which the entire chip is buried in an insulating resin and a wiring layer and an insulating layer are stacked in layers. In such a stacked package, through-hole wiring is used to achieve electrical connection between different layers, and the through-hole is buried and the wiring layer is formed simultaneously by electrolytic plating. However, the electrolytic plating method is not suitable for forming wiring with a large film thickness, and it takes a long time to form a thick wiring layer, so the production efficiency is reduced, resulting in an increase in production costs.

[0066] Furthermore, as mentioned above, since a large current is applied to the power device, a thick wiring layer is required to suppress the heating of the wiring. Therefore, in the case of using a through-hole wiring with a relatively small film thickness formed by electrolytic plating, the heating caused by the wiring resistance becomes a very big problem. On the other hand, if a wiring with a large film thickness is formed by using a metal plate, the heating can be suppressed, but the through hole cannot be buried using this method. In addition, it is difficult to perform micro-processing on the wiring with a large film thickness, so it is impossible to form a wiring structure with a high degree of integration. For example, in a module package where power devices and control ICs are mixed, the minimum design rule for forming thick metal wiring for power devices is larger than the electrode spacing of the control IC. The wiring for the control IC needs to be configured with a higher degree of integration, so the power device and the control IC cannot be patterned using the same wiring.

[0067] However, in the wiring structure of the embodiment of the present invention, a metal layer with a large film thickness formed by a metal plate (the first layer 125 in the embodiment of the present invention) and a metal layer with a small film thickness formed by electrolytic plating or the like (the second layer 130 in the embodiment of the present invention) coexist. Therefore, the conductive path mainly composed of the first layer 125 can flow a large current and can drive the power device. On the other hand, for areas where high-integration wiring is not required to flow a large current, the second layer 130 formed based on electrolytic plating or the like can be used. For this reason, wiring patterning for control ICs can also be achieved. As a result, devices with different required design rules, such as power devices and control ICs, can be configured in the same layer and connected using the same wiring process.

[0068] (Second Embodiment)

[0069] In the embodiment of the present invention, a wiring structure of a wiring board different from that of the first embodiment will be described using Fig. 2. In addition, description of the same structure as that of the first embodiment of the present invention will be omitted.

[0070] like Figure 2DAs shown, the wiring structure used in the wiring substrate of one embodiment of the present invention has a wiring (second wiring 240) in which a thick layer (first layer 230) through which a large current can flow and a thin layer (second layer 220) that can be precisely processed are stacked and electrically connected to each other. In addition, the thin second layer 220 is also formed in the through hole. As in the first embodiment, such a wiring structure can be used to electrically connect a plurality of stacked wiring layers or wiring substrates.

[0071] First, an insulating film 210 is formed on the first wiring 200, and the insulating film 210 is processed to form a through hole 215 ( Figure 2A , Figure 2B ) Regarding the material that can be used for the insulating film 210 or the film forming method thereof, the materials described in the first embodiment can be adopted.

[0072] Thereafter, the second layer 220 is formed on the insulating film 210 by electrolytic plating or sputtering. Figure 2C ). The electrolytic plating method can adopt the method described in the first embodiment. At this time, the second layer 220 is formed in a manner of burying the through hole 215. In other words, the film thickness of the second layer 220 in the area overlapping with the insulating film 210 is different from the film thickness of the second layer 220 in the through hole 215, and the latter has a larger film thickness. Furthermore, similarly to the first embodiment, when the film thickness of the second layer 220 formed in the through hole 215 is small, for example, the through hole 215 can be buried using a conductive paste or the like after or before the formation of the second layer 220. The specific film thickness of the second layer 220 is the same as that of the first embodiment.

[0073] Next, if Figure 2D As shown, the first layer 230 is formed by joining the metal plate to the second layer 220 via the metal adhesive layer 225. The metal plate can be made of, for example, copper or gold. As in the first embodiment, the thickness of the metal plate only needs to be selected to be a film thickness that can sufficiently allow the required current to flow through the wiring substrate, and can be selected from the film thickness described in the first embodiment. The metal plate can be joined by applying pressure from the upper part of the metal adhesive layer 225 while being heated. The metal adhesive layer 225 can be made of a metal with a relatively low melting point, such as zinc or tin, or its alloy, and can also contain several percentage points (for example, 3% to 10%, or 5% to 8%) of phosphorus. Thereafter, the first layer 230 can be processed into a desired shape by etching or the like. The wiring having a stacked structure of the first layer 230 and the second layer 220 is the second wiring 240.

[0074] The thickness of the second layer 220 may be smaller than that of the first layer 230. Specifically, the thickness of the second layer 220 in the region overlapping the insulating film 210 is smaller than that of the first layer 230. Therefore, the time required to form the second layer 220 can be shortened, thereby shortening the process.

[0075] The resistivity of the second layer 220 may be different from that of the first layer 230. Alternatively, the concentration of impurities in the second layer 220 may be different from that of the first layer 230. Alternatively, the density of the second layer 220 may be different from that of the first layer 230.

[0076] As described in the first embodiment, in the wiring structure of the present embodiment, a metal layer with a large film thickness formed by a metal plate (the first layer 230 in the embodiment) and a metal layer with a small film thickness formed by electrolytic plating or the like (the second layer 220 in the embodiment) are mixed. Therefore, the conductive path mainly composed of the first layer 230 can flow a large current and can drive power devices. On the other hand, the second layer 220 formed by electrolytic plating or the like can be used in areas where wiring with a high degree of integration is required that does not require a large current to flow. For this purpose, wiring patterning for a control IC can be implemented. Thus, devices with different required design rules, such as power devices and control ICs, can be formed in the same layer and connected using the same wiring process.

[0077] (Third Embodiment)

[0078] In this embodiment, a wiring structure of a wiring substrate different from that of the first embodiment and the second embodiment is described using Fig. 3 and Fig. 4. In addition, description of the same structure as that of the first embodiment and the second embodiment is omitted.

[0079] like Figure 4B As shown, the wiring structure of the wiring substrate of this embodiment is different from the wiring structure of the wiring substrate of the first embodiment in that the insulating film 310 formed on the first wiring 300 has a recessed portion.

[0080] First, if Figure 3A As shown in FIG. 1 , an insulating film 310 is formed on the first wiring 300. The material and formation method of the first wiring 300 and the insulating film 310 may be the same as those used in the first embodiment.

[0081] Next, the metal plate 320 is bonded to the insulating film 310 ( Figure 3A , Figure 3B ). The material or thickness of the metal plate 320 can be selected from the range described in the first embodiment. In addition, the method for joining the metal plate 320 can also be the method described in the first embodiment. Figure 3AIn the embodiment, the metal plate 320 has a plurality of recesses formed by half etching, etc. By forming the recesses, the openings described later can be easily formed on the metal plate 320, but the present embodiment is not limited to these embodiments, and a metal plate 320 having no recesses and having a flat surface can also be used.

[0082] Next, if Figure 3C As shown, an opening is formed on the metal plate 320 by etching or the like to expose the insulating film 310, and at the same time, the first layer 325 is formed. In the case where the metal plate 320 has a recessed portion, the opening can be easily opened at a position corresponding to the recessed portion by etching from a region overlapping the recessed portion (the opposite side of the recessed portion).

[0083] Next, if Figure 3C As shown by the arrows, for the exposed insulating film 310, a recessed portion 312 ( Figure 3D ). The recessed portion 312 may also be formed by laser irradiation. By forming such a recessed portion 312, a through hole can be easily formed in the insulating film 310 later.

[0084] Next, if Figure 4A As shown, a through hole 315 is formed by etching or laser irradiation in the insulating film 310 having the recessed portion 312. Thus, the surface of the first wiring 300 is exposed.

[0085] Next, if Figure 4B As shown, the second layer 330 is formed by electrolytic plating or the like. The electrolytic plating method can be the method described in Embodiment 1. The wiring having a structure in which the first layer 325 and the second layer 330 are stacked is the second wiring 340.

[0086] At this time, the second layer 330 is formed to cover the first layer 325 and bury the through hole 315. In other words, the film thickness of the second layer 330 in the region overlapping with the first layer 325 is different from the film thickness of the second layer 330 in the through hole 315, and the film thickness of the latter is larger. In addition, in the case where the film thickness of the second layer 330 formed in the through hole 315 is small, for example, the through hole 315 can be buried with a conductive paste or the like after or before the formation of the second layer 330. Thereafter, the second layer 330 can be processed by etching or the like to form the desired circuit wiring.

[0087] The film thickness of the second layer 330 may be smaller than the film thickness of the first layer 325. Specifically, the film thickness of the second layer 330 in the region overlapping with the first layer 325 may be smaller than the film thickness of the first layer 325. Therefore, the formation time of the second layer 330 can be shortened, and the process can be shortened. The specific film thicknesses of the first layer 325 and the second layer 330 can be selected from the film thicknesses described in the first embodiment.

[0088] The resistivity of the first layer 325 and the second layer 330 may be different. Alternatively, the concentration of impurities in the first layer 325 and the second layer 330 may be different. Alternatively, the density of the first layer 325 and the second layer 330 may be different.

[0089] In addition, the second layer 330 may be formed by, for example, sputtering instead of electrolytic plating.

[0090] As described in the first embodiment, in the wiring structure of the present embodiment, a metal layer with a large film thickness formed by a metal plate (the first layer 325 in the present embodiment) and a metal layer with a small film thickness formed by electrolytic plating or the like (the second layer 330 in the embodiment of the present invention) are mixed. Therefore, the conductive path mainly composed of the first layer 325 can flow a large current and can drive the power device. On the other hand, for areas where high-integration wiring that does not require a large current to flow is required, the second layer 330 formed based on electrolytic plating or the like can be used. Therefore, wiring patterning for control ICs can be performed. As a result, devices with different required design rules, such as power devices and control ICs, can be configured in the same layer and connected through the same wiring process.

[0091] (Fourth Embodiment)

[0092] In this embodiment, an example in which the wiring substrate having the wiring structure described in the first embodiment is applied to a semiconductor package is described using Figures 5 to 7. In addition, description of the same structure as that of the first embodiment is omitted.

[0093] like Figure 6C or Figure 7C As shown, in the embodiment, the wiring substrate has wiring at least above or below the semiconductor device such as the power device. In addition, the wiring has a structure in which a layer with a large film thickness and a layer with a small film thickness are mixed. The layer with a large film thickness can be used as a path for a large current to flow, and the layer with a small film thickness can be used to form a wiring with a high degree of integration.

[0094] FIGS. 5 to 7 show a method for manufacturing a semiconductor package of the present embodiment. First, a semiconductor device 420 such as a power device is bonded to a first wiring 400 via an adhesive layer 410. A first terminal 422 and a second terminal 424 are provided above and below the semiconductor device 420 as lead-out wirings. The first wiring 400 may be a wiring provided on an insulating substrate, or may be a wiring formed in a layered state, or may be a wiring for connecting wiring formed in a layered state. In addition, the first wiring 400 may be a lead-out wiring or a pad provided on an IC chip or a power device. The adhesive layer 410 may use an organic adhesive material such as an acrylic resin adhesive. Alternatively, the adhesive layer 410 may be a metal adhesive layer containing a metal with a relatively low melting point such as zinc or tin, or an alloy thereof.

[0095] Next, an insulating film 430 is formed to cover the first wiring 400 and the semiconductor device 420. The insulating film 430 may be made of the material or produced by the method described in the first embodiment. The insulating film 430 protects the semiconductor device 420 and prevents the intrusion of impurities such as water or ions from the outside.

[0096] Next, if Figure 5C As shown, the metal plate 440 is bonded to the insulating film 430. The material or bonding method of the metal plate 440 can also be the material or bonding method shown in the first embodiment of the present invention. The metal plate 440 can be half-etched in advance to form a recessed portion on the surface in contact with the insulating film 430.

[0097] Next, the metal plate 440 is processed by etching or the like to form a first layer 445 ( Fig. 6A Here, a plurality of openings are formed in the metal plate 440 to expose the insulating film 430 .

[0098] Next, if Figure 6B As shown, the insulating film 430 on the second terminal 422 of the semiconductor device 420 is etched or laser irradiated to remove the area exposed in the opening to expose the second terminal 422. Thus, a plurality of through holes 432 are formed on the second terminal 422. In addition, before processing the insulating film 430, a physical force may be applied to its surface or laser irradiation may be performed to form a recess.

[0099] Afterwards, if Figure 6C As shown, the second layer 450 is formed by electrolytic plating or the like to cover the first layer 445 and bury the through hole 432. The electrolytic plating method can be the method shown in the first embodiment. The wiring having a structure in which the first layer 445 and the second layer 450 are stacked is the second wiring 460. The characteristics of the film thickness of the first layer 445 and the second layer 450 are the same as those of the first embodiment.

[0100] Through the above steps, wiring (first layer 445, second layer 450) having a stacked structure can be formed on semiconductor device 420. A large current for driving semiconductor device 420 can be mainly received through first layer 445, and highly integrated wiring can be formed using second layer 450.

[0101] FIG. 7 shows a method of forming wiring having a stacked structure on the lower side of the semiconductor device 420. Fig. 7A 4 shows the steps of forming a stacked wiring (second wiring 460) on the upper side of the semiconductor device 420. First, a through hole 434 is formed in the first wiring 400 and the adhesive layer 410 by etching or the like, exposing the first terminal 422 ( Figure 7B ). Here, a plurality of through holes 434 are formed. Thus, the third layer 470 can be formed. The first wiring 400 and the adhesive layer 410 can be processed at the same time, and the through holes 434 can be formed in one step. Alternatively, an opening can be first formed on the first wiring 400 by etching or the like, and in the next step, the adhesive layer 410 can be processed by, for example, different conditions or techniques to form the through holes 434.

[0102] Thereafter, the fourth layer 480 is formed by electrolytic plating or the like so as to cover the third layer 470 and bury the through hole 434. The wiring having the stacked structure of the third layer 470 and the fourth layer 480 is the third wiring 490. The features related to the film thickness of the first wiring 400 and the fourth layer 480 are the same as those of the first embodiment.

[0103] Through the above steps, wiring (third layer 470, fourth layer 480) having a stacked structure can be formed under the semiconductor device 420. The large current for driving the semiconductor device 420 can be mainly received by the third layer 470, and the wiring with high integration can be formed by the fourth layer 480. By using the manufacturing method of this embodiment, a semiconductor package can be manufactured in which wiring for large current and wiring for small current coexist on the same layer.

[0104] (Fifth Embodiment)

[0105] In this embodiment, an example of applying a wiring substrate having the wiring structure described in the first embodiment and the second embodiment of the present invention to a semiconductor package is described using Figures 8 to 10. The description of the same structure as the first embodiment and the second embodiment is omitted.

[0106] like Fig. 9B or Fig. 10BAs shown, the wiring substrate of this embodiment has wiring at least above or below a semiconductor device such as a power device. In addition, the wiring has a structure in which a thick layer and a thin layer are mixed. The thick layer can be used as a path for a large current to flow, and the thin layer can be used to form a wiring with a high degree of integration.

[0107] 8 to 10 show a method for manufacturing a semiconductor package according to the present embodiment. First, a semiconductor device 520 such as a power device is bonded to a first wiring 500 via an adhesive layer 510 ( Fig. 8A ). A first terminal 522 and a second terminal 524 are provided above and below the semiconductor device 520 as lead-out wiring. The first wiring 500 may be a wiring provided on an insulating substrate, or may be a wiring formed in a layer, or may be a wiring for connecting wiring formed in a layer. In addition, the first wiring 500 may be a lead-out wiring or a pad provided on an IC chip or a power device. The adhesive layer 510 may use an organic adhesive material such as an acrylic resin adhesive. Alternatively, the adhesive layer 510 may be a metal adhesive layer containing a metal with a relatively low melting point, such as zinc or tin, or an alloy thereof.

[0108] Next, an insulating film 530 ( Figure 8B The insulating film 530 may be made of the material or produced by the method described in the first embodiment. The insulating film 530 can protect the semiconductor device 520, thereby preventing the intrusion of impurities such as water or ions from the outside.

[0109] Next, if Figure 8C As shown, a through hole 532 is formed in the insulating film 530 to expose the second terminal 524. Here, a plurality of through holes 532 are formed. The through holes 532 can be formed by etching or laser irradiation.

[0110] Thereafter, the second layer 540 ( ) is formed on the insulating film 530 by the electrolytic plating method or the sputtering method as described in the first embodiment so as to bury the through hole 532. Fig.9A ).

[0111] Next, if Fig. 9B As shown, the metal plate is bonded to the second layer 540 via the metal bonding layer 550 to form the first layer 560. For the metal plate or the metal bonding layer 550, the same material as that shown in the second embodiment can be used and bonded by the same method. The characteristics related to the film thickness of the first layer 560 and the second layer 540 are the same as those of the second embodiment. Afterwards, the first layer 560 can be processed into a desired shape by etching or the like. The wiring having the stacked structure of the first layer 560 and the second layer 540 is the second wiring 570.

[0112] Through the above steps, wiring with a stacked structure (first layer 560, second layer 540) can be formed on semiconductor device 520. The large current for driving semiconductor device 520 can be mainly received by first layer 560, and highly integrated wiring can be formed by second layer 540.

[0113] FIG. 10 shows a method of further forming the wiring having the stacked structure shown in the first embodiment on the lower side of the semiconductor device 520. First, a through hole 534 is formed on the first wiring 500 and the adhesive layer 510 by etching or the like to expose the first terminal 522 ( Fig. 10A ). Here, a plurality of through holes 534 are formed. Thus, the third layer 580 is formed. The first wiring 500 and the adhesive layer 510 may be processed at the same time, and the through holes 534 may be formed in one step. Alternatively, the first wiring 500 may be firstly formed with an opening by etching or the like, and in the next step, the adhesive layer 510 may be processed by, for example, different conditions or techniques to form the through holes 534.

[0114] Thereafter, the fourth layer 585 is formed by electrolytic plating or the like so as to cover the third layer 580 and bury the through hole 534. The wiring having the structure in which the third layer 580 and the fourth layer 585 are stacked is the third wiring 590. The features related to the film thickness of the third layer 580 and the fourth layer 585 are the same as those of the first embodiment. Thereafter, by appropriately processing the fourth layer 585, for example, a circuit wiring with a high degree of integration can be formed.

[0115] Through the above steps, wiring (third layer 580, fourth layer 585) having a stacked structure can be formed under the semiconductor device 520. The large current for driving the semiconductor device 520 can be mainly received by the third layer 580, and the wiring with high integration can be formed by the fourth layer 585. By using the manufacturing method of this embodiment, a semiconductor package can be manufactured in which wiring for large current and wiring for small current coexist on the same layer.

[0116] (Sixth Embodiment)

[0117] In this embodiment, using Fig.11 , Fig.12 A semiconductor package is described in which wiring for large current and wiring for small current coexist on the same layer, and a semiconductor device driven by small power and a power device to which a large current is applied coexist on the same layer.

[0118] Fig.11600 is a circuit diagram of a semiconductor package shown in this embodiment. Reference numeral 600 is a control IC for controlling two power devices 610 and 620. The power devices 610 and 620 have a transistor structure, and their drains are electrically connected to each other. The control IC 600 is a device driven by a relatively small current, while the power devices 610 and 620 are devices driven by a large current. Therefore, it is preferred that the wiring connected to the control IC 600 is a wiring with a small thickness, while the power devices 610 and 620 are connected to a wiring with a large thickness.

[0119] Fig.12 For Fig.11 An example of a cross-sectional structure of a wiring substrate is shown in . The wiring substrate of this embodiment has first wirings 630, 632, and 634. The control IC 600 is fixed to the first wiring 630 via an adhesive layer 640. As the adhesive layer 640, the same material as that shown in the fourth embodiment can be used.

[0120] The power device 610 has a first terminal 612 and a second terminal 614, and similarly, the power device 620 has a first terminal 622 and a second terminal 624. The power device 610 is fixed to the first wiring 632 by, for example, a metal adhesive layer 650, and is electrically connected to the first wiring 632. Similarly, the power device 620 is fixed to the first wiring 634 by, for example, a metal adhesive layer 650, and is electrically connected to the first wiring 634.

[0121] The insulating film 660 is provided to bury the control IC 600 and the power devices 610 and 620 and to cover the terminal 602 of the control IC 600 and the second terminals 614 and 624 of the power devices 610 and 620. The insulating film 660 may have the same structure as the insulating film 110 of the first embodiment.

[0122] A first layer 670 having a large film thickness is provided on the power devices 610 and 620 via an insulating film 660. The first layer 670 may have the same structure as the first layer 125 of the first embodiment and may be formed by the same method as the first layer 125 of the first embodiment. The first layer 670 may be used as a main wiring path for supplying a large current to the power devices 610 and 620.

[0123] Through holes are provided on the first layer 670 and the insulating film 660 to expose the terminal 602 of the control IC 600, the second terminals 614 and 624 of the power devices 610 and 620, and the first wirings 632 and 634, and a second layer 680 is formed on the first layer 670 by burying the through holes using an electrolytic plating method or the like. The second layer 680 may have the same structure as the second layer 130 of the first embodiment and may be formed by the same method as the second layer 130 of the first embodiment. Fig.12 In the embodiment, the second layer 680 may be further patterned and used to supply signals from, for example, a control IC. The wiring formed by stacking the first layer 670 and the second layer 680 is the second wiring 690 .

[0124] An upper wiring 695 is further stacked on the second layer 680 via the insulating film 665. The upper wiring 695 can be formed by the same method as that of the second layer 680.

[0125] As described above, the semiconductor package of this embodiment has a structure in which wiring for large current (first layer 670) and wiring for small current (second layer 680) coexist on the same layer, and devices with different required design rules such as power devices and control ICs can be arranged on the same layer and connected through the same wiring process.

[0126] (Seventh Embodiment)

[0127] In this embodiment, using Fig.11 , Fig.13 A semiconductor package is described in which wiring for large current and wiring for small current coexist on the same layer, and a semiconductor device driven by small power and a power device to which a large current is applied coexist on the same layer. In addition, this embodiment is different from the sixth embodiment in terms of the second wiring structure. The structure different from the sixth embodiment is mainly described, and the description of the same structure is omitted.

[0128] Fig.11 This is a circuit diagram of a semiconductor package shown in this embodiment, which is the same as that of the sixth embodiment. Fig.13 For Fig.11 An example of a cross-sectional structure of a wiring substrate is shown in FIG. Through holes are provided on the insulating film 660 to reach the terminal 602 of the control IC, the second terminal 614 of the power device 610, the second terminal 624 of the power device 620, and the first wirings 632 and 634, and a second layer 700 is formed to fill these through holes. The second layer 700 can be formed using the same material and method as the second layer 220 of the second embodiment.

[0129] A first layer 720 having a large film thickness is provided on the region of the second layer 700 that overlaps with the power devices 610 and 620 via the metal adhesive layer 710. The first layer 720 may have the same structure as the first layer 125 of the first embodiment, and may be formed by the same method as the first layer 125 of the first embodiment. The structure in which the first layer 720 and the second layer 700 are stacked is a second wiring 730, which corresponds to the second wiring 240 of the second embodiment. The first layer 720 may be used as a wiring path for supplying a large current to the power devices 610 and 620, and the second layer 700 may be used to form a wiring with a high degree of integration, for example, may be used to supply a signal from a control IC.

[0130] An upper wiring 750 is further stacked on the first layer 720 via the insulating film 740. The upper wiring 750 can be formed by the same method as that of the second layer 700.

[0131] As described above, the wiring substrate of this embodiment has a structure in which wiring for large current (first layer 720) and wiring for small current (second layer 700) coexist on the same layer, and devices such as power devices and control ICs with different required design rules can be arranged on the same layer and connected through the same wiring process.

Claims

1. A semiconductor package, characterized in that: have: A first power device having a first surface, a second surface opposite to the first surface, and a first terminal adjacent to the first surface of the first power device; A second power device having a first surface, a second surface opposite to the first surface, and a second terminal adjacent to the first surface of the second power device; A control device having a first surface, a second surface opposite to the first surface, and a control device terminal adjacent to the first surface of the control device; a first lower wiring, adjacent to the second surface of the first power device; a second lower wiring, adjacent to the second surface of the second power device; a third lower wiring line, adjacent to the second surface of the control device; A first insulating layer covering the first power device, the second power device, the control device, the first lower wiring, the second lower wiring and the third lower wiring, wherein the first insulating layer includes a first opening extending from a first surface of the first insulating layer to the first terminal, the second terminal and the control device terminal; A first conductive layer, located above the first terminal and the second terminal but not located above the control device terminal; The second conductive layer is located above the first terminal, the second terminal and the control device terminal, wherein: The second conductive layer is located in the first opening; The second conductive layer is interposed between the first terminal and the first conductive layer and between the second terminal and the first conductive layer; and The first portion of the first conductive layer and the first portion of the second conductive layer are coupled to the first terminal and the second lower wiring through one of the first openings in the first insulating layer; as well as The second insulating layer covers the first conductive layer and the second conductive layer.

2. The semiconductor package according to claim 1, wherein: The first power device further includes a first control terminal; The second power device further includes a second control terminal; and The first control terminal and the second control terminal are not covered by the first conductive layer.

3. The semiconductor package according to claim 2, wherein: The second conductive layer couples one of the control device terminals to one or more of the first control terminal or the second control terminal.

4. A semiconductor package, characterized in that: have: A first power device having a first surface, a second surface opposite to the first surface, a first terminal adjacent to the first surface of the first power device, and a first control terminal; a first lower wiring, adjacent to the second surface of the first power device; A first insulating layer covers the first power device and the first lower wiring, wherein: The first insulating layer comprises a first opening extending from a first surface of the first insulating layer to the first terminal; A first conductive layer, located above the first terminal but not above the first control terminal; a second conductive layer, located above the first terminal and the first control terminal; and a second insulating layer; in: The second conductive layer is located in the first opening; The second conductive layer is between the first terminal and the first conductive layer; The second conductive layer and the first conductive layer are located in the second insulating layer; The first conductive layer comprises a first conductive layer top side away from the second conductive layer; and The second insulating layer overlaps with and covers the top side of the first conductive layer.

5. The semiconductor package according to claim 4, wherein: Further including: A second power device having a first surface, a second surface opposite to the first surface, a second terminal adjacent to the first surface of the second power device, and a second control terminal; as well as The second lower wiring is adjacent to the second surface of the second power device; wherein: The first opening extends from the first surface of the first insulating layer to the second terminal; The first conductive layer is located above the second terminal but not above the second control terminal; The second conductive layer is located above the second terminal and the second control terminal; and The second conductive layer is located between the first conductive layer and the second terminal.

6. The semiconductor package according to claim 5, wherein: A first portion of the first conductive layer and a first portion of the second conductive layer are connected to the first terminal and the second lower wiring through one of the first openings in the first insulating layer.

7. The semiconductor package according to claim 6, wherein: The second insulating layer comprises a second opening, and the second opening extends from the first surface of the second insulating layer to a second portion of the first conductive layer located above the second power device; and The semiconductor package further includes an upper wiring located in the second opening and coupled to the second portion of the first conductive layer.

8. The semiconductor package according to claim 7, wherein: The second insulating layer does not have a second opening located above the first portion of the first conductive layer.

9. The semiconductor package according to claim 4, wherein: Further including: A control device having a first surface, a second surface opposite to the first surface, and a control device terminal adjacent to the first surface of the control device; as well as A second lower wiring is adjacent to the second surface of the control device, wherein: The first opening extends from the first surface of the first insulating layer to the control device terminal; The control device terminal is not covered by the first conductive layer; and The second conductive layer is located above the control device terminal.

10. The semiconductor package according to claim 9, wherein: The second conductive layer couples one of the control device terminals to the first control terminal.

11. The semiconductor package according to claim 9, wherein: The second insulating layer includes a second opening extending from the first surface of the second insulating layer to the control device terminal; and The semiconductor package further includes an upper wiring located in the second opening and coupled to the control device terminal.

12. The semiconductor package according to claim 4, wherein: Further including: The metal bonding layer is between the first conductive layer and the second conductive layer, wherein: The first control terminal is adjacent to the first surface of the first power device; and The first control terminal does not have the metal adhesive layer.

13. The semiconductor package according to claim 4, wherein: The first conductive layer is coupled to a second lower wiring through one of the first openings in the first insulating layer.

14. The semiconductor package according to claim 4, wherein: The first conductive layer comprises a first conductive layer bottom side opposite to the first conductive layer top side; The second conductive layer includes a second conductive layer top side; The bottom side of the first conductive layer is adjacent to the top side of the second conductive layer; No portion of the second insulating layer is between the bottom side of the first conductive layer and the top side of the second conductive layer; and No portion of the first insulating layer is between the bottom side of the first conductive layer and the top side of the second conductive layer.

15. A method for manufacturing a semiconductor package, characterized in that: include: providing a semiconductor device including a first terminal and a second terminal; providing a first conductive layer above the second terminal; providing a first insulating layer above the first terminal and the second terminal; providing a second insulating layer above the first terminal; Providing a first through hole, wherein the first through hole extends through the first insulating layer and the second insulating layer to expose at least a portion of the first terminal; Providing a second through hole, wherein the second through hole extends through the first conductive layer and the first insulating layer to expose at least a portion of the second terminal; as well as A second conductive layer is provided, wherein the second conductive layer has a first portion located in the first through hole and a second portion located above the first conductive layer and in the second through hole, wherein: The first insulating layer is between the first conductive layer and the second terminal and between the second insulating layer and the first terminal; The first portion of the second conductive layer is a portion of a first wiring path; The second portion of the second conductive layer and the first conductive layer are part of a second wiring path; and The first wiring path does not have the first conductive layer.

16. The method according to claim 15, characterized in that: The second insulating layer is not above the second terminal.

17. The method according to claim 15, characterized in that: The second portion of the second conductive layer overlaps with the upper surface of the first conductive layer; The second portion of the second conductive layer has a first thickness overlapping the upper surface of the first conductive layer and a second thickness in the second through hole; and The first thickness is smaller than the second thickness.

18. The method according to claim 17, characterized in that: The first conductive layer has a third thickness; and The first thickness is smaller than the third thickness.

19. The method according to claim 15, characterized in that: The first conductive layer includes a patterned metal plate.

20. The method according to claim 15, characterized in that: The first conductive layer and the second conductive layer have different conductivity from each other.

Images