Embedded chip package, semiconductor package, and method of forming embedded chip package

Abstract

An embedded chip package is provided. The embedded chip package includes a chip, an electrically insulating material at least partially encapsulating the chip, at least one metal layer configured to provide at least one electrically conductive connection structure to the chip, and an information section including encoded information about the embedded chip package, where in the information section, the electrically insulating material at least partially encapsulates the chip. The information is encoded as a pattern of conductive portions and electrically insulating portions.

Description

Technical Field

[0001] Various embodiments generally relate to an embedded chip package, a semiconductor package, a method of forming an embedded chip package, a method of forming a semiconductor package, and to a method of analyzing an embedded chip package or a semiconductor package. Background Art

[0002] Semiconductor devices, such as D2pak, TO220, PQFN, are often marked with information that can identify the device using, for example, a laser for marking a molding material of the semiconductor device.

[0003] The information may for example include device type, manufacturing date, batch details etc. The information may for example be written using alphanumeric characters or as a data matrix code (DMC). After the devices have been assembled on the circuit board, the user can still easily read the information if necessary. This therefore allows full traceability of every component assembled on the circuit board.

[0004] Typically, these devices are configured as plastic encapsulated packages and typically include a metal lead frame with an attached and wire-connected bare die (also called a chip). The lead frame with the mounted chip is then typically overmolded with a plastic molding compound. After the molding process, the semiconductor device is singulated and tested. The molding compound is then laser-marked with device markings, date codes, and manufacturer logos. Other process flows that are loosely connected to the mentioned process flows may be used in addition or alternatively.

[0005] This type of semiconductor package may have disadvantages such as high parasitic effects, high losses, and / or large size.

[0006] To create applications with very small footprints that have high power density, embedded circuits can be created within printed circuit boards.

[0007] Semiconductor (eg, silicon) chips may be embedded in a laminated package in a so-called embedded chip package, which may form an inlay that may then be laminated into a final printed circuit board (PCB).

[0008] The technology may enable integration of multiple devices into a PCB in a 3D configuration.

[0009] Embedded chip packages may provide significantly lower parasitics, better efficiency and / or a small form factor.

[0010] A major challenge with inlay technology can be identifying and tracking the device embedded in the PCB. Depending on the size of the pre-packaged inlay, the device marking can be added using the laser marking process described above. However, once the pre-packaged inlay is embedded in the PCB, the device marking is not visible because the PCB material is not optically transparent.

[0011] The PCB can be disassembled (e.g., by chemically etching away the layer covering the marking) to expose the marking, but this is a destructive process that can result in damage to the circuit.

[0012] This means that using traditional marking methods, it is no longer possible to identify an embedded chip package embedded in a PCB while the PCB is operating or at least remains in a functional state. Summary of the invention

[0013] An embedded chip package is provided. The embedded chip package comprises a chip, an electrically insulating material at least partially encapsulating the chip, at least one metal layer configured to provide at least one electrically conductive connection structure to the chip, and an information section comprising encoded information about the embedded chip package, wherein in the information section, the information is encoded as a pattern of conductive parts and electrically insulating parts. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In the accompanying drawings, the same reference numerals generally refer to the same parts in different views. The drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

[0015] Figure 1A shows a schematic top view of an embedded chip package according to various embodiments;

[0016] Figure 1B Shows Figure 1A A schematic cross-sectional view of an embedded chip package;

[0017] Figure 2A shows a schematic top view of an embedded chip package according to various embodiments;

[0018] Figure 2B Shows Figure 2A A schematic cross-sectional view of an embedded chip package;

[0019] Figure 3A shows a schematic top view of an embedded chip package according to various embodiments;

[0020] Figure 3B Shows Figure 3A A schematic cross-sectional view of an embedded chip package;

[0021] Figure 3C Shows Figure 3A and Figure 3B A schematic cross-sectional view of a core of an embedded chip package;

[0022] Figure 4A shows a schematic top view of an embedded chip package according to various embodiments;

[0023] Figure 4B Shows Figure 4A A schematic cross-sectional view of an embedded chip package;

[0024] Figure 4C Shows Figure 4A and Figure 4B A schematic cross-sectional view of a core of an embedded chip package;

[0025] Figure 5 shows schematic cross-sectional views of semiconductor packages according to various embodiments; and

[0026] Figure 6 A flow chart of a method of forming an embedded chip package according to various embodiments is shown. DETAILED DESCRIPTION

[0027] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0028] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0029] Various aspects of the present disclosure are provided for devices, and various aspects of the present disclosure are provided for methods. It should be understood that the basic properties of the device also apply to the method, and vice versa. Therefore, for the sake of brevity, repeated descriptions of these properties may have been omitted.

[0030] In various embodiments, an embedded chip package for embedding into a PCB is provided.

[0031] The term "embedded chip package" should be understood to describe a structure, such as a package, that includes an embedded chip (as opposed to a chip package having embedded properties).

[0032] The term "semiconductor package" should be understood to refer to packages including embedded chip packages.

[0033] In various embodiments, a marking system is provided that is integrated into an embedded chip package (also referred to as an inlay or pre-packaged device) so that a specific device can be identified and traced later in the operational phase.

[0034] In various embodiments, individual (e.g., traceability) information for each device can be engraved on the inner layer of the package during manufacturing. The information can be obtained using non-visual imaging techniques (e.g., x-ray and / or ultrasound imaging of the device) or using sectioning during failure analysis.

[0035] In various embodiments, the (e.g., traceability) information may be provided (e.g., engraved and / or etched) in or on the embedded chip package in one or more of a variety of ways. For example, the encoded information may be provided by varying the diameter of laser / mechanical vias that fall on the chip and / or on the exterior of the embedded chip package and forming a data matrix code (DMC), and / or by arranging the shape of recognizable characters. Alternative or additional ways include dummy / half-drilled laser / mechanical vias on the metal layer structure and engraving characters and / or dot codes on internal and / or external unused metal layers.

[0036] In other words, information (e.g., coded information) can be arranged inside or outside the embedded chip package by modifying the functional metal structure of the embedded chip package and / or by arranging additional non-functional metal structures inside or outside the embedded chip package. In this article, functionality / non-functionality refers to the operation of the embedded chip package. The functional metal structure may, for example, include or be composed of a redistribution layer, a metal thermal interface layer, a metal shielding layer and / or a vertical interconnect structure (e.g., a via), while the non-functional metal structure may, for example, include or be composed of a dummy via, a metal layer (e.g., a floating metal layer) and / or other metal structures arranged on the inside or outside surface of the embedded chip package that do not have an electrical function for the embedded chip package.

[0037] Although structures carrying information within or on an embedded chip package are described herein as metallic structures because metals are known to have sufficiently high atomic numbers Z and / or densities to make them distinguishable from low-Z (e.g., carbon-rich) environments in non-visual imaging techniques, it should be understood that, as an alternative, non-metallic materials that are distinguishable in non-visual imaging (e.g., X-ray imaging and / or ultrasound imaging), for example due to differences in atomic number and / or density compared to the surrounding medium, may also be used, at least in non-functional structures.

[0038] Figure 1A shows a schematic top view of an embedded chip package 100 according to various embodiments, Figure 1B Shows Figure 1A The embedded chip package 100 is Figure 1A Schematic cross-sectional view of the horizontal line in .

[0039] The embedded chip package 100 includes a chip 102 , for example a semiconductor chip that may include or consist of an electronic device or an integrated circuit.

[0040] The embedded chip package 100 further comprises an electrically insulating material 104 at least partially encapsulating the chip 102. The electrically insulating material 104 may, for example, comprise or consist of a molding material, which may be configured substantially as known in the art, optionally as a laminated layer. The molding material is typically a carbon-based material, such as a polymer, such that their atomic number may be approximately Z=6 (atomic number of carbon) and a density of approximately 0.9 g / cm 3 To about 1.5g / cm 3 within the range.

[0041] The embedded chip package 100 further includes at least one metal layer 106 , 116 configured to provide at least one electrically conductive connection structure to the chip 102 .

[0042] The at least one metal layer 106 may, for example, be at least partially exposed on an outer surface of the embedded chip package 100, or connected to a structure exposed on an outer surface of the embedded chip package 100. In various embodiments, the at least one metal layer 106, 116 may not be exposed on an outer surface of the embedded chip package 100, but once the embedded chip package 100 is in its final functional configuration (e.g. embedded in a PCB), the at least one metal layer 106, 116 may be contacted, for example, by an interconnect structure, such as a vertical interconnect structure (which may extend between the main surfaces of the embedded chip package 100, e.g. orthogonal to a plane parallel to one or both main surfaces of the embedded chip package 100).

[0043] At least one metal layer 106, 116 may, for example, be configured as a redistribution layer (RDL). At least one metal layer 106, 116 may, for example, include or consist of copper, silver, gold, aluminum, alloys, and / or other combinations thereof (e.g., layer stacks), and may generally be configured substantially as known in the art, except for the differences that may be outlined herein.

[0044] The embedded chip package 100 further includes an information section I including encoded information about the embedded chip package 100 , wherein in the information section I, the information is encoded as a pattern of conductive portions and electrically insulating portions.

[0045] As mentioned above, in a more general sense, the pattern may not necessarily need to be formed of electrically conductive parts and electrically insulating parts, but it may be sufficient to use two (or more) materials that are distinguishable in non-visual imaging techniques such as X-rays or ultrasound. For example, non-metallic materials based on aluminum (Z = 13) and / or silicon (Z = 14), such as aluminum oxide and / or silicon oxide, can be sufficiently distinguished from the surrounding carbon (Z = 6) based materials and are therefore suitable for creating a coded pattern of information segments.

[0046] However, for practical reasons, conductive materials such as copper (Z=29), silver (Z=47), gold (Z=79), etc. may be used, which can be easily distinguished from any non-metallic materials in the embedded chip package 100; and / or for example aluminum (Z=13), which may be indistinguishable from silicon (Z=14) in X-ray and / or ultrasound imaging, but can be easily distinguished from carbon-based materials such as polymers.

[0047] In various embodiments, the pattern of electrically conductive portions and electrically insulating portions may include a plurality of vertically elongated conductive portions, wherein at least two of the vertically elongated conductive portions differ in diameter and / or length.

[0048] Figure 1A and Figure 1B An exemplary embodiment of such a configuration is shown in .

[0049] In the described embodiment, the conductive portion used to encode the information in the information segment I is a vertical interconnect structure (via) 112, which conductively connects one of the metal layers 106, 116 (i.e., metal layer 106) to the first contact pad 108 of the chip 102 (wherein, the first contact pad 108 can be arranged on the first side of the chip 102), and / or conductively connects the other of the metal layers 106, 116 (i.e., metal layer 116) to the second contact pad 118 and / or the third contact pad 120 of the chip 102 (wherein, the second contact pad 118 and the third contact pad 120 can be arranged on the second side of the chip 102 opposite to the first side).

[0050] The vertical interconnect structure 112 may be formed substantially as is known in the art, for example using laser drilling and / or an etching process with a mask.

[0051] like Figure 1A and Figure 1BAs shown, the vertical interconnect structures 112 can be provided in two forms, namely with a narrower diameter (112A) and with a wider diameter (112B), or with any other distinguishable shape, for example, a circle, a square, a star, etc. For easier differentiation, they are also shown in different grayscales. The difference in diameter can be obtained, for example, by having a laser beam with different diameters and / or by changing the motion pattern of the laser during the formation of the opening in the electrically insulating material 104 and / or by using the following etching process, which uses a structured mask with predefined mask openings with different diameters.

[0052] In a pattern including a vertical interconnect structure 112A having a narrower diameter and a vertical interconnect structure 112B having a wider diameter Figure 1A and Figure 1B In the embodiment of the present invention, the encoded information in the information section I provided as a pattern of conductive and electrically insulating portions is located in an annular region extending from a narrower diameter to a wider diameter. The annular region is either filled with the metal of the (wider) vertical interconnect structure 112B or filled with the insulating material 104 through which the vertical interconnect structure 112A extends. Thus, a two-bit or two-dimensional encoding can be provided.

[0053] In cases where the number of vertical interconnect structures may not need to be maximized (in other words, where one or more vertical interconnect structures may be omitted without compromising the performance of the embedded chip package), three-bit encoding (i.e., increasing one bit) may be achieved by optionally omitting vertical interconnect structures 112 located at one or more predefined positions (e.g., at predefined positions in a two-dimensional matrix).

[0054] Further bits (not shown) may be added by alternatively or additionally varying the length of the vertical interconnect structures 112 (which may downgrade a "vertical interconnect structure" to a "vertical dummy interconnect structure", since shortening of (some) interconnect structures 112 may mean that they no longer reach the respective contact pads 108, 118, 120). The variable length of the vertical interconnect structures 112 may be achieved, for example, by forming an opening in the electrically insulating material 104 extending from the outer surface of the embedded chip package 100 towards the chip 102 either completely or only partially, and then filling the opening with an electrically conductive material.

[0055] Figure 2A shows a schematic top view of an embedded chip package 100 according to various embodiments, Figure 2B Shows Figure 2A The embedded chip package 100 is Figure 2A Schematic cross-sectional view of the horizontal line in .

[0056] exist Figure 2A and Figure 2BIn the embodiment of FIG. 1 , another type of vertically elongated conductive portion 220 is provided in the information section I. Figure 2A In the top view of FIG. 1 , the positions of the two-dimensional matrix are shown as positions where vertically elongated conductive portions 220 may be optionally formed. At several of these positions, the vertically elongated conductive portions 220 may be arranged with at least one end that is not electrically connected. Thus, Figure 2A and Figure 2B The vertically elongated conductive portion 220 shown in FIG. 2 may also be referred to as a dummy via 220 .

[0057] The dummy via 220 may be electrically and physically connected to the metal layer 106 or 116 , respectively, and may extend vertically from one or both outer main surfaces of the electrically insulating material 104 toward a center plane of the embedded chip package 100 .

[0058] As a result, they can additionally serve as anchors for metal layers 106 , 116 .

[0059] The anchoring function of the dummy via 220 may have positive effects that may be independent of the encoding function.

[0060] Therefore, in Figure 2A and Figure 2B In FIG. 2 , an exemplary embodiment of an embedded chip package is additionally identified as embedded chip package 200 .

[0061] The embedded chip package 200 of various embodiments may include: a chip 102; an electrically insulating material 104 that at least partially encapsulates the chip 102; at least one metal layer 106, 116 configured to provide at least one electrically conductive connection structure to the chip 102; and at least one vertically elongated conductive portion 220 including a first end connected to the at least one metal layer 106, 116 and a second end arranged in the electrically insulating material 104; wherein the second end is not electrically connected.

[0062] Except for the differences described in the context of embedded chip package 200, embedded chip package 200 may be similar to or the same as embedded chip package 100. Embedded chip package 200 may have all positions provided with dummy vias 220, or may have positions provided with dummy vias 220 defined solely based on the anchoring function provided thereby, rather than encoding information and thereby combining positions provided with dummy vias 220 with positions not provided with dummy vias 220 in a two-dimensional pattern.

[0063] In various embodiments, the patterns formed by the dummy vias 220 on the first side of the embedded chip package 200 may mirror each other, or may be independent of each other.

[0064] Returning to the coding information in the embedded chip package 100, in various embodiments, the embedded chip package 100 may include a coding pattern of dummy vias 220 located on a first main side of the embedded chip package 200, and may have a mirrored coding pattern for dummy vias 220 located on an opposite second side of the embedded chip package 200. In other words, under each formed dummy via 220, another formed dummy via 220 may be arranged, and in the two-dimensional pattern, a position where no dummy via 220 is arranged on the first side is also not arranged under the second side.

[0065] Therefore, the encoded information included in the information section I on the first side of the embedded chip package 100 may be the same as the encoded information included in the information section I on the second side of the embedded chip package 100 , thereby providing the encoded information in a redundant manner.

[0066] The redundantly provided information may be advantageous, for example, in the case where a portion of the embedded chip package 100 is covered by a metal portion, which, even in a 3D tomography scan, would prevent, for example, X-rays from penetrating toward the information segment on one of the sides of the embedded chip package 100. In this case, the information segment I on the other side of the embedded chip package 100 may be accessed by, for example, X-rays.

[0067] In various embodiments, the pattern of the dummy vias 220 in the information section I on the first side may be different from the pattern of the dummy vias 220 on the second side. Therefore, the amount of information that can be encoded in the embedded chip package 100 may be greater.

[0068] The information section I may be embedded in the embedded chip package 100, for example Figure 1B and Figure 2B As shown, the information section I may be exposed at the outer surface of the embedded chip package 100 . To implement such an embodiment, the metal layer 106 and / or the metal layer 116 may be at least partially removed above the dummy via 220 .

[0069] In various embodiments, the pattern of electrically conductive portions and electrically insulating portions may be formed as a structured metal layer.

[0070] A corresponding exemplary embodiment is described in FIG. 3A to FIG. 3C and FIG. 4A to FIG. 4C Shown in.

[0071] Figure 3A shows a schematic top view of an embedded chip package 100 according to various embodiments, Figure 3B Shows Figure 3A The embedded chip package 100 is Figure 3A A schematic cross-sectional view of the line shown in, Figure 3C Shows Figure 3A and Figure 3B FIG. 1 is a schematic cross-sectional view of a core of an embedded chip package 100 .

[0072] Figure 4A shows a schematic top view of an embedded chip package 100 according to various embodiments, Figure 4B Shows Figure 4A The embedded chip package 100 is Figure 4A A schematic cross-sectional view of the line shown in, Figure 4C Shows Figure 4A and Figure 4B FIG. 1 is a schematic cross-sectional view of a core of an embedded chip package 100 .

[0073] The embedded chip package 100 may include a core 330. The core 330 may include an opening in which the chip 102 may be arranged. Although the opening is shown as a through hole, which contacts the chip 102 from both sides, this may not necessarily be the case. The opening may be formed as a cavity open to only one main side of the core, or as a partial through hole, which may, for example, form a frame on which the chip 102 may rest, but which may have a further opening providing access to the side of the chip resting on the frame.

[0074] In various embodiments, the core 330 may include or consist of an electrically insulating material or, for example, an electrically conductive low-Z material such as carbon. This may allow the information section I to be provided on one or both major surfaces of the core 330 or inside the core 330 (not shown) in a manner that can be read by, for example, X-ray and / or ultrasound diagnosis.

[0075] exist Figure 3A In the embodiment, one or more metal layers 332, 342 are arranged on a first (main) side of the core 330 and / or on an opposite second (main) side of the core 330. The metal layers 332, 342 may, for example, include or consist of typical metal structure / RDL materials such as copper, but may also include or consist of silver, gold, titanium, etc. In the case of a low-Z core, the metal layers 332, 342 may also be aluminum, for example.

[0076] The information encoding as a pattern of conductive and electrically insulating portions can be provided by selectively removing the metal layers 332, 342 in predefined locations, thereby forming insulating portions 334 (which can be filled with electrically insulating material 104 at a later stage, for example during an encapsulation process), and by leaving the metal layers 332, 342 in place at other predefined locations. Figure 3A The exemplary embodiment of FIG. 1 can again show a two-bit encoding possibility for information segment I.

[0077] FIG. 4A to FIG. 4C shows a similar FIG. 3A to FIG. 3C Here, letters and / or numbers may be provided in the information section I (in addition, but letters and / or numbers may also be provided instead of the two-dimensional array of the removed portion / retained portion).

[0078] In various embodiments, the pattern of electrically conductive and electrically insulating portions may be provided by selectively forming the metal layer 332 , 342 in predefined locations, eg by structured deposition.

[0079] For information provided on the first and second sides of the core 330, similar reasoning regarding redundant and non-redundant information applies as provided above in the context of the dummy via 220. In principle, any two sub-portions of all information sections I included in the embedded chip package 100 (e.g., respectively, Figure 3A or Figure 4A The two “arms” of the “U” in FIG. 1 , etc.) can often be considered for redundant or independent information encoding.

[0080] Although the information segment I formed as part of the metal layers 332, 334 is shown to provide an illustrative example of an information segment buried within the embedded chip package 100, any metal layer of the embedded chip package 100, in particular any part of the redistribution layer of the embedded chip package 100, may be used as the information segment I. For example, the metal layers 106, 116 may be used, such as portions of the metal layers 106, 116 that may not be directly electrically contacted when the embedded chip package 100 is integrated into a PCB (in areas that are to be directly electrically contacted, electrically insulating portions of the coding pattern may be filled with interconnection materials such as solder or conductive glue, which may make it difficult to identify these portions in diagnostic images).

[0081] The encoded information about the embedded chip package 100 may, for example, include properties of the embedded chip package 100, such as the horizontal position of the chip 102 within the embedded chip package 100, the vertical position of the chip 102 within the embedded chip package 100, a batch ID, an ID of the embedded chip package 100 and / or additional traceability data.

[0082] In various embodiments, the plurality of chips 102 may be included in the embedded chip package 100 .

[0083] In various embodiments, various information sections I may be included in a single embedded chip package 100. For example, the diameter / length of the vertical interconnect structure 112 may be used in combination with the dummy via 220 and / or with the structured metal layers 332, 342 and / or the structured metal layers 106, 116, etc.

[0084] Figure 5 A schematic cross-sectional view of a semiconductor package 500 according to various embodiments is shown.

[0085] The semiconductor package 500 includes at least one embedded chip package 100 as described above, for example, Figures 1A to 4C Alternatively, the semiconductor package 500 may include two or more than two embedded chip packages 100 .

[0086] The semiconductor package 500 may further include an encapsulation material 558 at least partially encapsulating the embedded chip package 100 .

[0087] The semiconductor package 500 may, for example, form a printed circuit board (PCB) having the embedded chip package 100 embedded as an inlay.

[0088] The semiconductor package 500 may further include conductive contact areas 550, 554 on its main surface, which may be used to electrically contact the chip 102, for example in combination with vias 552, 556 that conductively connect the contact areas 550, 554 to the metal layers 108, 118 and 120, respectively, and / or may be used to mount circuit components (not shown) that may be connected to the chip 102, such as capacitors, resistors, etc.

[0089] In various embodiments, the semiconductor package 500 may further include a package core 560 , which may provide structural support and may be electrically insulating or conductive as desired. The package core 560 may include an opening in which the embedded chip package 100 may be arranged.

[0090] In various embodiments, the volume region vertically above and / or below the information segment I can be kept substantially free of metal to allow X-ray imaging and / or ultrasonic analysis of the information segment I.

[0091] Typically, in order to retrieve the embedded coded information from the embedded chip package 100 in a non-destructive manner, in some cases, X-ray imaging and / or ultrasonic analysis from a single direction may be sufficient. In other cases, when "looking" from a single direction, (e.g., functional) metal features such as connecting wires may obscure at least a portion of the information segment I, an X-ray tomography scan may be obtained, which may be used as a basis for a three-dimensional reconstruction of structures with different atomic numbers identified in the embedded chip package 100, and / or ultrasonic analysis may be performed from different directions.

[0092] Figure 6 A flow chart 600 of a method of forming an embedded chip package 100 according to various embodiments is shown.

[0093] The method includes: at least partially encapsulating the chip with an electrically insulating material (610); arranging at least one metal layer as at least one conductive connection structure to the chip (620); and forming a pattern of conductive portions and electrically insulating portions in the embedded chip package to form an information segment including encoded information about the embedded chip package (630).

[0094] The method can be used to form the above combination Figures 1A to 4C And the embedded chip package 100 described in other embodiments.

[0095] Various examples are described below:

[0096] Example 1 is an embedded chip package. The embedded chip package includes a chip, an electrically insulating material at least partially encapsulating the chip, at least one metal layer configured to provide at least one conductive connection structure to the chip, and an information segment including encoded information about the embedded chip package, wherein in the information segment, the information is encoded as a pattern of conductive parts and electrically insulating parts.

[0097] In Example 2, the subject matter of Example 1 can optionally include that the pattern of electrically conductive portions and electrically insulating portions includes a plurality of vertically elongated conductive portions, wherein at least two of the vertically elongated conductive portions have different diameters and / or lengths.

[0098] In Example 3, the subject matter of Example 2 can optionally include that at least one of the vertically elongated conductive portions forms a conductive connection structure between the chip and the at least one metal layer.

[0099] In Example 4, the subject matter of Example 2 or 3 can optionally include that at least one of the vertically elongated conductive portions has at least one end that is not electrically connected.

[0100] In Example 5, the subject matter of any one of Examples 1-4 can optionally include that the information section comprises a row or matrix of predefined pattern locations, and the pattern of electrically conductive portions and electrically insulating portions is distributed over the predefined pattern locations.

[0101] In Example 6, the subject matter of any one of Examples 1-5 may optionally include: the information section being exposed at an outer surface of the embedded chip package.

[0102] In Example 7, the subject matter of any one of Examples 1-5 may optionally include: the information section being buried inside the embedded chip package.

[0103] In Example 8, the subject matter of any one of Examples 1-7 may optionally include that the encoded information is configured to be determinable via at least X-ray imaging, and optionally also via ultrasound analysis (eg, ultrasound imaging).

[0104] In Example 9, the subject matter of any of Examples 1-8 can optionally include that the pattern of the electrically conductive portions and the electrically insulating portions is formed as a structured metal layer.

[0105] In Example 10, the subject matter of Example 9 can optionally include that the structured metal layer is formed from a continuous metal layer by selectively removing the structured metal layer in the electrically insulating portion.

[0106] In Example 11, the subject matter of Example 9 can optionally include that the structured metal layer is formed by selectively arranging the structured metal layer in the conductive portion.

[0107] In Example 12, the subject matter of any of Examples 1, 5, 7, or 8 may optionally include a carrier having an opening, wherein the chip is arranged in the opening, wherein the pattern of electrically conductive portions and electrically insulating portions is arranged over the carrier.

[0108] In Example 13, the subject matter of any of Examples 1-12 can optionally include that the electrically insulating material includes at least one laminate layer.

[0109] In Example 14, the subject matter of any of Examples 1-13 can optionally include that the pattern of the electrically conductive portions and the electrically insulating portions is a two-dimensional or three-dimensional pattern.

[0110] In Example 15, the subject matter of any one of Examples 1-14 may optionally include: the encoded information about the embedded chip package includes at least one of a set of attributes of the embedded chip package, the set of attributes including or consisting of the following attributes: the horizontal position of the chip in the embedded chip package, the vertical position of the chip in the embedded chip package, the batch ID, the ID of the embedded chip package, and additional traceability data.

[0111] Example 16 is a semiconductor package that includes the embedded chip package of any one of Examples 1-15 and a packaging material that at least partially encapsulates the embedded chip package.

[0112] In Example 17, the subject matter of Example 16 can form a printed circuit board (PCB) having an embedded chip package embedded as an inlay.

[0113] In Example 18, the subject matter of Example 16 or 17 can optionally include that a volume region vertically above and / or below the information segment remains substantially free of metal to allow X-ray imaging of the information segment.

[0114] Example 19 is a method of forming an embedded chip package. The method includes: at least partially encapsulating a chip with an electrically insulating material; arranging at least one metal layer as at least one conductive connection structure to the chip; and forming a pattern of conductive portions and electrically insulating portions in the embedded chip package to form an information segment including encoded information about the embedded chip package.

[0115] In Example 20, the subject matter of Example 19 can optionally include that forming the pattern includes forming a plurality of vertically elongated conductive portions such that at least two of the vertically elongated conductive portions have different diameters and / or lengths.

[0116] In Example 21, the subject matter of Example 20 can optionally include: at least one of the vertically elongated conductive portions forming a conductive connection structure between the chip and the at least one metal layer.

[0117] In Example 22, the subject matter of Example 20 or 21 can optionally include at least one of the vertically elongated conductive portions having at least one end that is not electrically connected.

[0118] In Example 23, the subject matter of any one of Examples 19-22 can optionally include that the information section comprises a row or matrix of predefined pattern locations, and the pattern of electrically conductive portions and electrically insulating portions is distributed on the predefined pattern locations.

[0119] In Example 24, the subject matter of any one of Examples 19-23 may optionally include: the information section being exposed at an outer surface of the embedded chip package.

[0120] In Example 25, the subject matter of any one of Examples 19-24 may optionally include: the information section being buried inside the embedded chip package.

[0121] In Example 26, the subject matter of any one of Examples 19-25 may optionally include: the encoded information is configured to be determinable via at least X-ray imaging.

[0122] In Example 27, the subject matter of any of Examples 19-26 can optionally include that the pattern of the electrically conductive portions and the electrically insulating portions is formed as a structured metal layer.

[0123] In Example 28, the subject matter of Example 27 can optionally include that the structured metal layer is formed from a continuous metal layer by selectively removing the structured metal layer in the electrically insulating portion.

[0124] In Example 29, the subject matter of Example 27 can optionally include that the structured metal layer is formed by selectively arranging the structured metal layer in the conductive portion.

[0125] In Example 30, the subject matter of any of Examples 19, 23, 25, or 26 may optionally include a carrier having an opening, wherein the chip is arranged in the opening, wherein the pattern of electrically conductive portions and electrically insulating portions is arranged over the carrier.

[0126] In Example 31, the subject matter of any of Examples 19-30 can optionally include that the electrically insulating material includes at least one laminate layer.

[0127] In Example 32, the subject matter of any of Examples 19-31 can optionally include that the pattern of the electrically conductive portions and the electrically insulating portions is a two-dimensional or three-dimensional pattern.

[0128] In Example 33, the subject matter of any one of Examples 19-32 may optionally include: the encoded information about the embedded chip package includes at least one of a set of attributes of the embedded chip package, the set of attributes including or consisting of the following attributes: the horizontal position of the chip in the embedded chip package, the vertical position of the chip in the embedded chip package, the batch ID, the ID of the embedded chip package, and additional traceability data.

[0129] In Example 34, the subject matter of Example 19 or 20 can optionally include that forming the pattern includes forming the structured metal layer by selectively removing a pre-arranged metal layer or by selectively depositing a metal layer.

[0130] Example 35 is a method of forming a semiconductor package, the method comprising at least partially encapsulating the embedded chip package of any of Examples 1-15 with an encapsulation material.

[0131] In Example 36, the method of Example 35 may further include, before at least partially encapsulating the embedded chip package, checking the information section to obtain encoded information about the embedded chip package.

[0132] Example 37 is a method of analyzing an embedded chip package or a semiconductor package, the method comprising performing X-ray imaging on the embedded chip package of any one of Examples 1-15 or the semiconductor package of any one of Examples 16-18 to obtain coded information about the embedded chip package.

[0133] Example 38 is an embedded chip package. The embedded chip package includes a chip, an electrically insulating material at least partially encapsulating the chip, at least one metal layer configured to provide at least one electrically conductive connection structure to the chip, and at least one vertically elongated conductive portion including a first end connected to the at least one metal layer and a second end arranged in the electrically insulating material, wherein the second end is not electrically connected.

[0134] Although the present invention has been particularly shown and described with reference to specific embodiments, it will be appreciated by those skilled in the art that various changes may be made to the present invention in form and detail without departing from the spirit and scope of the present invention as defined by the appended claims. Therefore, the scope of the present invention is indicated by the appended claims, and therefore it is intended to cover all changes within the meaning and scope of the equivalents of the claims.

Claims

1. An embedded chip package, comprising: chip; an electrically insulating material at least partially encapsulating the chip; at least one metal layer configured to provide at least one electrically conductive connection structure to the chip; as well as an information section including coded information about the embedded chip package; Wherein, in the information section, information is encoded as a pattern of conductive parts and electrically insulating parts.

2. The embedded chip package according to claim 1, in, The pattern of electrically conductive and insulating portions comprises a plurality of vertically elongated conductive portions, at least two of which have different diameters and / or lengths.

3. The embedded chip package according to claim 2, in, At least one of the vertically elongated conductive portions forms a conductive connection structure between the chip and the at least one metal layer.

4. The embedded chip package according to claim 2 or 3, in, At least one of the vertically elongated conductive portions has at least one end that is not electrically connected.

5. The embedded chip package according to any one of claims 1 to 4, in, The information section comprises a row or a matrix of predefined pattern locations, on which a pattern of electrically conductive parts and electrically insulating parts is distributed.

6. The embedded chip package according to any one of claims 1 to 5, in, The information section is exposed at an outer surface of the embedded chip package.

7. The embedded chip package according to any one of claims 1 to 5, in, The information section is buried inside the embedded chip package.

8. The embedded chip package according to any one of claims 1 to 7, in, The encoded information is configured to be determinable via at least X-ray imaging.

9. The embedded chip package according to any one of claims 1 to 8, in, The pattern of electrically conductive portions and electrically insulating portions is formed as a structured metal layer.

10. The embedded chip package according to claim 9, in, The structured metal layer is formed from a continuous metal layer by selectively removing the structured metal layer in the electrically insulating portion.

11. The embedded chip package according to claim 9, in, The structured metal layer is formed by selectively arranging the structured metal layer in the conductive portion.

12. The embedded chip package according to any one of claims 1-5, 7-8, wherein: The embedded chip package further comprises: a carrier having an opening, wherein the chip is arranged in the opening; Therein, a pattern of conductive parts and electrically insulating parts is arranged above the carrier.

13. The embedded chip package according to any one of claims 1 to 12, in, The electrically insulating material comprises at least one laminate layer.

14. The embedded chip package according to any one of claims 1 to 13, in, The pattern of electrically conductive portions and electrically insulating portions is a two-dimensional or three-dimensional pattern.

15. The embedded chip package according to any one of claims 1 to 14, in, The encoded information about the embedded chip package includes at least one of a set of attributes of the embedded chip package, the set of attributes including or consisting of the following attributes: The horizontal position of the chip within the embedded chip package; the vertical position of the chip within the embedded chip package; Batch ID; The ID of the embedded chip package; and Additional traceability data.

16. A semiconductor package, comprising: The embedded chip package according to any one of claims 1 to 15; as well as A packaging material at least partially encapsulates the embedded chip package.

17. The semiconductor package according to claim 16, wherein: The semiconductor package forms a printed circuit board (PCB) having the embedded chip package embedded as an inlay.

18. The semiconductor package according to claim 16 or 17, in, A volume region vertically above and / or below the information section remains substantially free of metal to allow X-ray imaging of the information section.

19. A method for forming an embedded chip package, the method comprising: at least partially encapsulating the chip with an electrically insulating material; arranging at least one metal layer as at least one electrically conductive connection structure to the chip; as well as A pattern of electrically conductive portions and electrically insulating portions is formed in the embedded chip package, thereby forming an information section including encoded information about the embedded chip package.

20. The method according to claim 19, in, Forming the pattern includes forming a plurality of vertically elongated conductive portions such that at least two of the vertically elongated conductive portions have different diameters and / or lengths.

21. The method according to claim 19 or 20, in, Forming the pattern includes forming a structured metal layer by selectively removing a pre-arranged metal layer or by selectively depositing a metal layer.

22. A method of forming a semiconductor package, the method comprising: The embedded chip package according to any one of claims 1 to 15 is at least partially encapsulated with an encapsulation material.

23. The method according to claim 22, wherein: The method further comprises: Before at least partially encapsulating the embedded chip package, the information section is checked to obtain encoded information about the embedded chip package.

24. A method for analyzing an embedded chip package or a semiconductor package, the method comprising: X-ray imaging is performed on the embedded chip package according to any one of claims 1 to 15 or the semiconductor package according to any one of claims 16 to 18 to obtain coded information about the embedded chip package.

25. An embedded chip package, comprising: chip; an electrically insulating material at least partially encapsulating the chip; at least one metal layer configured to provide at least one electrically conductive connection structure to the chip; as well as at least one vertically elongated electrically conductive portion comprising a first end connected to said at least one metal layer and a second end arranged in said electrically insulating material, Wherein, the second end is not electrically connected.

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