Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The multiple electrode layers are sequentially stacked from bottom to top and located on the substrate, and in every two adjacent electrode layers, the side wall, covered by the upper electrode layer, of the lower electrode layer is in a step shape; and the dielectric layer is located between the two adjacent electrode layers. According to the invention, the problem that the reliability of the semiconductor structure is influenced by an overlarge electric field caused by the sharp corner of the lower electrode layer is solved, and the probability that the resistance is increased due to the fact that the thickness of the upper electrode layer formed on the vertical side wall is too thin is reduced; therefore, the material covering the step-shaped side wall is easier to remove, side wall residues can be reduced, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in materials and design in the IC industry have produced successive generations of integrated circuits. Each generation has smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and similar advances in IC processing and manufacturing are required to achieve these advances. Over the course of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component that can be made using a manufacturing process) has decreased.

[0003] One type of capacitor is a Metal Insulator Metal (MIM) capacitor, which is commonly used in mixed-signal devices and logic devices (such as embedded memory and RF devices). MIM capacitors are commonly used to store charge in various semiconductor devices. In order to meet the performance requirements of the device, the capacitance density of MIM capacitors is also gradually increasing. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a plurality of electrode layers stacked in sequence from bottom to top, located on the substrate, and in two adjacent electrode layers, the side wall of the lower electrode layer covered by the upper electrode layer is step-shaped; and a dielectric layer is located between the two adjacent electrode layers.

[0006] Optionally, the number of steps of the stepped electrode layer sidewall is greater than or equal to 3.

[0007] Optionally, in two adjacent electrode layers, the upper electrode layer covers a side wall of the lower electrode layer.

[0008] Optionally, in the multi-layer electrode layers, two adjacent electrode layers partially overlap, and the non-overlapping portions serve as extensions, and the extensions of the electrode layers from bottom to top extend alternately to both sides of the electrode layers in sequence.

[0009] Optionally, in the multi-layer electrode layers, the extension portions of the electrode layers of the odd-numbered layers are stacked sequentially from bottom to top, and the extension portions of the electrode layers of the even-numbered layers are stacked sequentially from bottom to top.

[0010] Optionally, the semiconductor structure further includes: a first electrical connection structure, which penetrates through the extension portion of the even-numbered electrode layers and is electrically connected thereto; and a second electrical connection structure, which penetrates through the extension portion of the odd-numbered electrode layers and is electrically connected thereto.

[0011] Optionally, when the number of the multi-layer electrode layers is an odd number, the semiconductor structure further includes: a dummy electrode layer located on an extension of the topmost even-numbered electrode layer; and the first electrical connection structure also penetrates the dummy electrode layer.

[0012] Optionally, the dummy electrode layer and the topmost odd-numbered electrode layer are in the same layer structure.

[0013] Optionally, the material of the dielectric layer includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; the material of the electrode layer includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0014] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of electrode layers stacked in sequence from bottom to top on the substrate, and a dielectric layer located between two adjacent electrode layers, wherein the side wall of the lower electrode layer covered by the upper electrode layer is step-shaped in the two adjacent electrode layers.

[0015] Optionally, the steps of forming a plurality of electrode layers stacked in sequence from bottom to top on a substrate, and a dielectric layer located between two adjacent electrode layers include: performing multiple patterning processes and a dielectric layer forming process between two adjacent patterning processes until the number of electrode layers reaches a preset number; the patterning process includes: forming an electrode material layer on the substrate; performing multiple sub-patterning processes on the electrode material layer until the sub-patterning process is completed on the electrode material layer of the entire thickness to form an electrode layer with a stepped side wall; the sub-patterning process includes: patterning the electrode material layer of a partial width from the side wall to the middle position of the electrode material layer, and removing a partial thickness of the electrode material layer; wherein the processing width of the multiple sub-patterning processes increases successively, and the processing surface of each sub-patterning process includes the surface processed by all previous sub-patterning processes; the dielectric layer forming process includes: forming a dielectric layer covering the electrode layer.

[0016] Optionally, the step of patterning the electrode material layer with a partial width from the side wall to the middle position of the electrode material layer and removing a portion of the thickness of the electrode material layer includes: forming a mask layer covering a portion of the top surface of the electrode material layer, and the mask layer exposes a portion of the top surface of at least one side of the electrode material layer; patterning the electrode material layer exposed by the mask layer, and removing a portion of the thickness of the electrode material layer; wherein, in multiple sub-patterning processes, the coverage range of the mask layer of the latter sub-patterning process is smaller than the coverage range of the mask layer of the previous sub-patterning process, and exposes a portion of the top surface of the electrode material layer covered by the previous sub-patterning process; after the patterning process, the mask layer is removed.

[0017] Optionally, in the subsequent sub-patterning process, the step of forming a mask layer covering a portion of the top surface of the electrode material layer includes: patterning the mask layer formed after the previous sub-patterning process, removing a portion of the width of the mask layer, and exposing a portion of the top surface of the electrode material layer.

[0018] Optionally, in the step of performing multiple sub-patterning processes on the electrode material layer, the number of sub-patterning processes is greater than or equal to 3 times.

[0019] Optionally, a dry etching process is used to pattern the electrode material layer exposed by the mask layer to remove a portion of the thickness of the electrode material layer.

[0020] Optionally, in the step of forming a plurality of electrode layers stacked sequentially from bottom to top on the substrate, in two adjacent electrode layers, the upper electrode layer covers a side wall of the lower electrode layer.

[0021] Optionally, in the step of forming a plurality of electrode layers stacked from bottom to top on a substrate, two adjacent electrode layers in the plurality of electrode layers partially overlap, and the non-overlapping portions serve as extensions, and the extensions of the electrode layers from bottom to top extend alternately to both sides of the electrode layers.

[0022] Optionally, in the step of forming a plurality of electrode layers stacked sequentially from bottom to top on a substrate, in the plurality of electrode layers, extension portions of the electrode layers of odd-numbered layers are stacked sequentially from bottom to top, and extension portions of the electrode layers of even-numbered layers are stacked sequentially from bottom to top.

[0023] Optionally, after forming multiple electrode layers stacked in sequence from bottom to top on the substrate, the formation method also includes: forming an extension portion that penetrates the even-numbered electrode layers and is electrically connected to a first electrical connection structure; forming an extension portion that penetrates the odd-numbered electrode layers and is electrically connected to a second electrical connection structure.

[0024] Optionally, when the number of multi-layer electrode layers is an odd number, the formation method also includes: forming a dummy electrode layer on the extension portion of the topmost even-numbered electrode layer; in the step of forming a first electrical connection structure that passes through the extension portion of the even-numbered electrode layer and is electrically connected thereto, the first electrical connection structure also passes through the dummy electrode layer.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the semiconductor structure provided by the embodiment of the present invention, a plurality of electrode layers stacked in sequence from bottom to top are located on a substrate, and in two adjacent electrode layers, the side wall of the lower electrode layer covered by the upper electrode layer is in a step-like shape; in the embodiment of the present invention, the side wall of the lower electrode layer covered by the upper electrode layer is in a step-like shape. Compared with the solution in which the side wall of the lower electrode layer covered by the upper electrode layer is in a right-angle shape, it is beneficial to alleviate the problem of excessive electric field at the location affected by the sharp corners of the lower electrode layer, which affects the reliability of the semiconductor structure, and is also beneficial to reduce the probability of increased resistance caused by the upper electrode layer being too thin on the vertical side wall. At the same time, the stepped side wall reduces the verticality of the side wall, making it easier to cover the electrode layer with the stepped side wall, and in the semiconductor process, when the upper electrode layer is graphically formed, it is easier to remove the material covering the stepped side wall, which is beneficial to reduce side wall residues, thereby improving the performance of the semiconductor structure.

[0027] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a plurality of electrode layers stacked in sequence from bottom to top and a dielectric layer located between two adjacent electrode layers are formed on a substrate, and in the two adjacent electrode layers, the side wall of the lower electrode layer covered by the upper electrode layer is in a step-like shape; in the embodiment of the present invention, the side wall of the lower electrode layer covered by the upper electrode layer is in a step-like shape. Compared with the solution in which the side wall of the lower electrode layer covered by the upper electrode layer is in a right-angle shape, it is beneficial to alleviate the problem that the electric field at the location is too large due to the sharp corners of the lower electrode layer, which affects the reliability of the semiconductor structure, and it is also beneficial to reduce the probability that the thickness of the upper electrode layer formed on the vertical side wall is too thin, resulting in an increase in resistance. At the same time, the stepped side wall reduces the verticality of the side wall, making it easier to cover the electrode layer on the stepped side wall, and in the semiconductor process, when the upper electrode layer is graphically formed, it is easier to remove the material covering the stepped side wall, which is beneficial to reduce the side wall residue, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of a conductor structure;

[0029] Figures 2 to 3 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0030] Figures 4 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0031] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a semiconductor structure.

[0032] Figure 1 It is a structural diagram of a conductor structure.

[0033] refer to Figure 1 The semiconductor structure includes: a substrate 30; a plurality of electrode layers 11 stacked in sequence from bottom to top, located on the substrate 30; and a dielectric layer 12 located between two adjacent electrode layers 11.

[0034] The multilayer electrode layer 11 and the dielectric layer 12 constitute a Metal Insulator Metal (MIM) capacitor, wherein the side wall of the lower electrode layer 11 covered by the upper electrode layer 11 is in a right angle shape, and the electric field is large at the sharp corner, which can easily affect the reliability of the semiconductor structure. Moreover, the electrode layer 11 formed on the vertical side wall is thinner, which can easily lead to the problem of increased resistance of the upper electrode layer 11. At the same time, it is difficult to cover the electrode layer 11 on the right-angled side wall. In the semiconductor process, when the upper electrode layer 11 is graphically formed, it is difficult to remove the material covering the right-angled side wall, which can easily lead to the generation of side wall residues, thereby affecting the performance of the semiconductor structure.

[0035] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a plurality of electrode layers stacked in sequence from bottom to top, located on the substrate, and in two adjacent electrode layers, the side wall of the lower electrode layer covered by the upper electrode layer is step-shaped; and a dielectric layer is located between the two adjacent electrode layers.

[0036] In the embodiment of the present invention, the side wall of the lower electrode layer covered by the upper electrode layer is in a step shape. Compared with the scheme in which the side wall of the lower electrode layer covered by the upper electrode layer is in a right angle shape, it is helpful to alleviate the problem of excessive electric field at the location affected by the sharp corners of the lower electrode layer, which affects the reliability of the semiconductor structure. It is also helpful to reduce the probability of increased resistance caused by the upper electrode layer being too thin on the vertical side wall. At the same time, the stepped side wall reduces the verticality of the side wall, making it easier to cover the electrode layer on the stepped side wall. In the semiconductor process, when the upper electrode layer is patterned, it is easier to remove the material covering the stepped side wall, which is helpful to reduce the side wall residue, thereby improving the performance of the semiconductor structure.

[0037] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 2 and Figure 3 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0038] Combined with reference Figure 2 and Figure 3 , Figure 3 for Figure 2 The enlarged view of the part at the dotted circle in the middle shows that the semiconductor structure includes: a substrate 300; a plurality of electrode layers 110 stacked in sequence from bottom to top, located on the substrate 300, and in two adjacent electrode layers 110, the side wall of the lower electrode layer 110 covered by the upper electrode layer 110 is in a step shape; and a dielectric layer 120, located between two adjacent electrode layers 110.

[0039] The substrate 300 is used to provide a process platform for the subsequent formation of the MIM capacitor. In this embodiment, the substrate 300 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

[0040] Multiple electrode layers 110 are alternately stacked from bottom to top to serve as electrode plates of the MIM capacitor structure.

[0041] In the present embodiment, the side wall of the lower electrode layer 110 covered by the upper electrode layer 110 is in a step shape. Compared with the solution in which the side wall of the lower electrode layer covered by the upper electrode layer is in a right angle shape, this is conducive to alleviating the problem of excessive electric field at the location affected by the sharp corners of the lower electrode layer 110, which affects the reliability of the semiconductor structure. It is also conducive to reducing the probability of increased resistance caused by the upper electrode layer 110 being too thin on the vertical side wall. At the same time, the stepped side wall reduces the verticality of the side wall, making it easier to cover the electrode layer 110 with the stepped side wall. In the semiconductor process, when the upper electrode layer 110 is patterned, it is easier to remove the material covering the stepped side wall, which is conducive to reducing side wall residues, thereby improving the performance of the semiconductor structure.

[0042] It should be noted that, in this embodiment, the number of steps on the side wall of the stepped electrode layer 110 should not be too small. If the number of steps on the side wall of the stepped electrode layer 110 is too small, it is easy to lead to poor relief effect on the verticality of the side wall of the electrode layer 110, and it is difficult to improve the problem that the electric field at the lower electrode layer 110 is too large due to the sharp corners, which affects the reliability of the semiconductor structure, and it is difficult to reduce the probability that the thickness of the upper electrode layer 110 formed on the vertical side wall is too thin, resulting in increased resistance. In addition, in the semiconductor manufacturing process, when the upper electrode layer 110 is graphically formed, it is easy to cause residues on the side wall of the electrode layer 110, which makes it difficult to improve the performance of the semiconductor structure. For this reason, in this embodiment, the number of steps on the side wall of the stepped electrode layer 110 is greater than or equal to 3.

[0043] In this embodiment, in two adjacent electrode layers 110 , the upper electrode layer 110 covers one side wall of the lower electrode layer 110 , and a step-shaped side wall is formed on the covered side wall of the lower electrode layer 110 .

[0044] In other embodiments, stepped sidewalls may be formed on both sidewalls of the lower electrode layer.

[0045] In this embodiment, in the multi-layer electrode layer 110 , two adjacent electrode layers 110 partially overlap, and the non-overlapping portion serves as an extension portion 300y . The extension portions 300y of the electrode layer 110 from bottom to top extend alternately to both sides of the electrode layer 110 .

[0046] Two adjacent electrode layers 110 are partially overlapped, and the electrode layers 110 of the overlapping parts are opposite to each other to form a capacitor structure. The non-overlapping parts serve as extension parts 300y, and the extension parts 300y are used to electrically connect to the outside, so as to load electrical signals for each electrode layer 110. The extension parts 300y of the electrode layers 110 from bottom to top extend alternately to both sides of the electrode layer 110 in turn, which is conducive to making full use of the space and making the multi-layer electrode layers 110 evenly arranged. Accordingly, in two adjacent electrode layers 110, the upper electrode layer 110 covers a side wall of the lower electrode layer 110.

[0047] In this embodiment, in the multi-layer electrode layer 110 , the extension portions 300 y of the electrode layers 110 of the odd-numbered layers are stacked sequentially from bottom to top, and the extension portions 300 y of the electrode layers 110 of the even-numbered layers are stacked sequentially from bottom to top.

[0048] The extension portions 300y of the electrode layers 110 of the odd-numbered layers are stacked in sequence from bottom to top, and the extension portions 300y of the electrode layers 110 of the even-numbered layers are stacked in sequence from bottom to top. This allows the odd-numbered layers 110 to be loaded with electrical signals through the extension portions 300y of the electrode layers 110 of the odd-numbered layers, and also allows the even-numbered layers 110 to be loaded with electrical signals through the extension portions 300y of the electrode layers 110 of the even-numbered layers. This is beneficial to simplifying the structure, simplifying the process flow, and improving the integration of the semiconductor structure.

[0049] In this embodiment, the material of the electrode layer 110 is a conductive material. As an example, the material of the electrode layer 110 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0050] It should be noted that in this embodiment, the thickness of the electrode layer 110 should not be too large or too small. If the thickness of the electrode layer 110 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the electrode layer 110 is too small, it is easy to cause the resistance of the electrode layer 110 to be too large, affecting the performance of the capacitor structure. For this reason, in this embodiment, the thickness of the electrode layer 110 is to

[0051] The dielectric layer 120 is used as an insulating layer in the MIM capacitor.

[0052] In this embodiment, the material of the dielectric layer 120 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material is conducive to increasing the capacitance value of the MIM capacitor and correspondingly increasing the capacitance density.

[0053] Specifically, the dielectric layer 120 is a high-k dielectric layer formed by stacking, that is, the dielectric layer 120 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the dielectric layer 120 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0054] In this embodiment, the dielectric layer 120 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer stacked together. In other embodiments, according to process requirements, the material of the first dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0055] In this embodiment, when the number of the multi-layer electrode layer 110 is an odd number, the semiconductor structure further includes: a dummy electrode layer 130 located on the extension portion 300 y of the topmost even-numbered electrode layer 110 .

[0056] In this embodiment, two adjacent electrode layers 110 are partially overlapped, and the non-overlapped portion is used as an extension portion 300y. The extension portions 300y of the adjacent electrode layers 110 are stacked from bottom to top in sequence, so that the electrical signal can be simultaneously loaded to the adjacent electrode layers 110 through the extension portions 300y of the adjacent electrode layers 110. When the number of electrode layers 110 is an odd number, the number of stacked layers of the extension portions 300y of the electrode layers 110 of the odd number is one more than the number of stacked layers of the extension portions 300y of the electrode layers 110 of the even number. Therefore, in this embodiment, a pseudo electrode layer 130 is formed on the extension portion 300y of the topmost even number electrode layer 110, so that the electrode layers 110 of the odd number are stacked. The number of metal film layers at the extension portion 300y position of 10 is equal to the number of metal film layers at the extension portion 300y position of the electrode layer 110 of the even-numbered layer, so that when the second electrical connection structure in which the electrode layer 110 of the odd-numbered layer is loaded with an electrical signal and the first electrical connection structure in which the electrode layer 110 of the even-numbered layer is loaded with an electrical signal, the number of etched metal film layers is consistent, and the thickness of the etched metal film layers tends to be consistent accordingly, so that the etching process when forming the first electrical connection structure and the etching process when forming the second electrical connection structure can be performed with the same etching process parameters, that is, the first electrical connection structure and the second electrical connection structure can be formed in the same step, thereby improving the process efficiency.

[0057] In the present embodiment, in order to make the thickness of the etched metal film layer tend to be consistent when the second electrical connection structure for loading electrical signals on the electrode layer 110 formed as an odd-numbered layer and the first electrical connection structure for loading electrical signals on the electrode layer 110 formed as an even-numbered layer are formed, the top-layer odd-numbered electrode layer 110 and the dummy electrode layer 130 are patterned through the same electrode material layer, so that the top-layer odd-numbered electrode layer 110 and the dummy electrode layer 130 have the same thickness, which is beneficial to simplify the process flow and improve the process efficiency. Therefore, in the present embodiment, the dummy electrode layer 130 and the top-layer odd-numbered electrode layer 110 are the same layer structure.

[0058] In this embodiment, the semiconductor structure further includes: a first electrical connection structure 410 that penetrates through the extension portion 300y of the even-numbered electrode layer 110 and is electrically connected thereto.

[0059] The first electrical connection structure 410 is used to electrically connect the even-numbered electrode layers 110 , so as to load electrical signals to the even-numbered electrode layers 110 .

[0060] Specifically, in the present embodiment, in the step of forming the first electrical connection structure 410, a positioning structure corresponding to the first electrical connection structure 410 is used as a formation position to form a first electrical connection structure 410 that penetrates the even-numbered electrode layer 110. The first electrical connection structure 410 penetrates the even-numbered electrode layer 110 and is in full contact with the even-numbered electrode layer 110, thereby being able to achieve better electrical connection performance.

[0061] In this embodiment, the material of the first electrical connection structure 410 is a conductive material. As an example, the material of the first electrical connection structure 410 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0062] Accordingly, in the present embodiment, when the number of the multi-layer electrode layer 110 is an odd number, the first electrical connection structure 410 also penetrates the pseudo electrode layer 130, so that when the second electrical connection structure for loading electrical signals on the electrode layer 110 formed as an odd number of layers and the first electrical connection structure for loading electrical signals on the electrode layer 110 formed as an even number of layers are formed, the number of etched metal film layers is consistent, and accordingly the thickness of the etched metal film layers tends to be consistent, so that the etching process for forming the first electrical connection structure and the etching process for forming the second electrical connection structure can be performed using the same etching process parameters, that is, the first electrical connection structure and the second electrical connection structure can be formed in the same step, thereby improving the process efficiency.

[0063] In this embodiment, the semiconductor structure further includes: a second electrical connection structure 420 that penetrates through the extension portion 300y of the odd-numbered electrode layer 110 and is electrically connected thereto.

[0064] The second electrical connection structure 420 is used to electrically connect the odd-numbered electrode layers 110 , so as to load electrical signals to the odd-numbered electrode layers 110 .

[0065] Specifically, in the present embodiment, in the step of forming the second electrical connection structure 420, a positioning structure corresponding to the second electrical connection structure 420 is used as a formation position to form a second electrical connection structure 420 that penetrates the odd-numbered electrode layer 110. The second electrical connection structure 420 penetrates the odd-numbered electrode layer 110 and is in full contact with the odd-numbered electrode layer 110, thereby being able to achieve better electrical connection performance.

[0066] In this embodiment, the material of the second electrical connection structure 420 is a conductive material. As an example, the material of the second electrical connection structure 420 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0067] In this embodiment, the semiconductor structure further includes: a lower metal layer 310 located in the substrate 300 at the bottom of the first through-hole interconnect structure 410 and electrically connected thereto, and located in the substrate 300 at the bottom of the second through-hole interconnect structure 420 and electrically connected thereto.

[0068] The lower metal layer 310 is used to realize electrical connection between the first through-hole interconnect structure 410 and the second through-hole interconnect structure 420 and the outside, and is also used to provide positioning for the formation of the first through-hole interconnect structure 410 and the second through-hole interconnect structure 420 .

[0069] In this embodiment, the material of the lower metal layer 310 is a conductive material. As an example, the material of the lower metal layer 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0070] In this embodiment, the semiconductor structure further includes: an upper metal layer 320 located on top of the first through-hole interconnect structure 410 and electrically connected thereto, and located on top of the second through-hole interconnect structure 420 and electrically connected thereto.

[0071] The upper metal layer 320 is used to realize electrical connection between the first through-hole interconnect structure 410 and the second through-hole interconnect structure 420 and the outside.

[0072] In this embodiment, the material of the upper metal layer 320 is a conductive material. As an example, the material of the upper metal layer 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0073] It should be noted that, in this embodiment, according to actual process requirements, the first through-hole interconnection structure 410 and the second through-hole interconnection structure 420 can realize electrical connection with the outside from the upper metal layer 320, and can also realize electrical connection with the outside from the lower metal layer 310, so that the electrical connection route of the first through-hole interconnection structure 410 and the second through-hole interconnection structure 420 is more flexible, which is conducive to improving the flexible application of the semiconductor structure.

[0074] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 4 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0075] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.

[0076] refer to Figure 4 , providing a substrate 300.

[0077] The substrate 300 is used to provide a process platform for the subsequent formation of a MIM capacitor.

[0078] In this embodiment, the base 300 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

[0079] In this embodiment, the semiconductor structure further includes: a lower metal layer 310 located in the substrate 300 .

[0080] Specifically, in this embodiment, the lower metal layer 310 is located in the substrate 300 at the bottom of the first through-hole interconnection structure formed subsequently and is electrically connected thereto, and is located in the substrate 300 at the bottom of the second through-hole interconnection structure formed subsequently and is electrically connected thereto.

[0081] The lower metal layer 310 is used to realize electrical connection between the first through-hole interconnect structure and the second through-hole interconnect structure formed subsequently and the outside, and is also used to provide positioning for the formation of the first through-hole interconnect structure and the second through-hole interconnect structure formed subsequently.

[0082] In this embodiment, the material of the lower metal layer 310 is a conductive material. As an example, the material of the lower metal layer 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0083] Combined with reference Figures 5 to 13 ,in, Fig.13 for Fig.12 The local enlarged view of the dotted circle in the middle shows that a plurality of electrode layers 110 are stacked in sequence from bottom to top on the substrate 300, and a dielectric layer 120 is located between two adjacent electrode layers 110. In the two adjacent electrode layers 110, the side wall of the lower electrode layer 110 covered by the upper electrode layer 110 is in a step shape.

[0084] Multiple electrode layers 110 are alternately stacked from bottom to top to serve as electrode plates of the MIM capacitor structure.

[0085] In the present embodiment, the side wall of the lower electrode layer 110 covered by the upper electrode layer 110 is in a step shape. Compared with the solution in which the side wall of the lower electrode layer covered by the upper electrode layer is in a right angle shape, this is conducive to alleviating the problem of excessive electric field at the location affected by the sharp corners of the lower electrode layer 110, which affects the reliability of the semiconductor structure. It is also conducive to reducing the probability of increased resistance caused by the upper electrode layer 110 being too thin on the vertical side wall. At the same time, the stepped side wall reduces the verticality of the side wall, making it easier to cover the electrode layer 110 with the stepped side wall. In the semiconductor process, when the upper electrode layer 110 is patterned, it is easier to remove the material covering the stepped side wall, which is conducive to reducing side wall residues, thereby improving the performance of the semiconductor structure.

[0086] It should be noted that, in this embodiment, the number of steps on the side wall of the stepped electrode layer 110 should not be too small. If the number of steps on the side wall of the stepped electrode layer 110 is too small, it is easy to lead to poor relief effect on the verticality of the side wall of the electrode layer 110, and it is difficult to improve the problem that the electric field at the lower electrode layer 110 is too large due to the sharp corners, which affects the reliability of the semiconductor structure, and it is difficult to reduce the probability that the thickness of the upper electrode layer 110 formed on the vertical side wall is too thin, resulting in increased resistance. In addition, in the semiconductor manufacturing process, when the upper electrode layer 110 is graphically formed, it is easy to cause residues on the side wall of the electrode layer 110, which makes it difficult to improve the performance of the semiconductor structure. For this reason, in this embodiment, the number of steps on the side wall of the stepped electrode layer 110 is greater than or equal to 3.

[0087] In this embodiment, in the step of forming a plurality of electrode layers 110 stacked from bottom to top on the substrate 300, in two adjacent electrode layers 110, the upper electrode layer 110 covers a side wall of the lower electrode layer 110, and a step-shaped side wall is formed on the covered side wall of the lower electrode layer 110.

[0088] In other embodiments, in the step of forming a plurality of electrode layers stacked sequentially from bottom to top on the substrate, step-shaped side walls may be formed on both side walls of the lower electrode layer.

[0089] In this embodiment, in the step of forming a multilayer electrode layer 110 stacked from bottom to top on a substrate 300, two adjacent electrode layers 110 in the multilayer electrode layer 110 partially overlap, and the non-overlapping portion serves as an extension portion 300y, and the extension portion 300y of the electrode layer 110 from bottom to top extends alternately to both sides of the electrode layer 110 in sequence.

[0090] Two adjacent electrode layers 110 are partially overlapped, and the electrode layers 110 of the overlapping parts are opposite to each other to form a capacitor structure. The non-overlapping parts serve as extension parts 300y, and the extension parts 300y are used to electrically connect to the outside, so as to load electrical signals for each electrode layer 110. The extension parts 300y of the electrode layers 110 from bottom to top extend alternately to both sides of the electrode layer 110 in turn, which is conducive to making full use of the space and making the multi-layer electrode layers 110 evenly arranged. Accordingly, in two adjacent electrode layers 110, the upper electrode layer 110 covers a side wall of the lower electrode layer 110.

[0091] In this embodiment, in the step of forming a multilayer electrode layer 110 stacked from bottom to top on the substrate 300, in the multilayer electrode layer 110, the extension portions 300y of the electrode layers 110 of the odd-numbered layers are stacked from bottom to top, and the extension portions 300y of the electrode layers 110 of the even-numbered layers are stacked from bottom to top.

[0092] The extension portions 300y of the electrode layers 110 of the odd-numbered layers are stacked in sequence from bottom to top, and the extension portions 300y of the electrode layers 110 of the even-numbered layers are stacked in sequence from bottom to top. This allows the odd-numbered layers 110 to be loaded with electrical signals through the extension portions 300y of the electrode layers 110 of the odd-numbered layers, and also allows the even-numbered layers 110 to be loaded with electrical signals through the extension portions 300y of the electrode layers 110 of the even-numbered layers. This is beneficial to simplifying the structure, simplifying the process flow, and improving the integration of the semiconductor structure.

[0093] In this embodiment, in the step of forming a plurality of electrode layers 110 stacked sequentially from bottom to top on the substrate 300, the material of the electrode layer 110 is a conductive material. As an example, the material of the electrode layer 110 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0094] It should be noted that in this embodiment, the thickness of the electrode layer 110 should not be too large or too small. If the thickness of the electrode layer 110 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the electrode layer 110 is too small, it is easy to cause the resistance of the electrode layer 110 to be too large, affecting the performance of the capacitor structure. For this reason, in this embodiment, the thickness of the electrode layer 110 is to

[0095] The dielectric layer 120 is used as an insulating layer in the MIM capacitor.

[0096] In this embodiment, the material of the dielectric layer 120 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material is conducive to increasing the capacitance value of the MIM capacitor and correspondingly increasing the capacitance density.

[0097] Specifically, the dielectric layer 120 is a high-k dielectric layer formed by stacking, that is, the dielectric layer 120 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the dielectric layer 120 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0098] In this embodiment, the dielectric layer 120 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer stacked together. In other embodiments, according to process requirements, the material of the first dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0099] Specifically, in this embodiment, the steps of forming a plurality of electrode layers 110 stacked in sequence from bottom to top on the substrate 300, and a dielectric layer 120 located between two adjacent electrode layers 110 include: performing multiple patterning processes, and forming the dielectric layer 120 between two adjacent patterning processes until the number of electrode layers 110 reaches a preset number of layers.

[0100] In this embodiment, the patterning process includes: forming an electrode material layer 100 on a substrate 300; performing multiple sub-patterning processes on the electrode material layer 100 until the sub-patterning process is completed on the entire thickness of the electrode material layer 100 to form an electrode layer 110 with stepped sidewalls.

[0101] Among them, the electrode material layer 100 is subjected to multiple sub-patterning treatments until the sub-patterning treatment is completed for the electrode material layer 100 of the entire thickness, which means that each sub-patterning treatment removes a portion of the thickness of the electrode material layer 100 until the entire electrode material layer 100 of a partial width is removed through multiple sub-patterning treatments to complete the patterning treatment.

[0102] In this embodiment, it can be seen from the above that the number of steps of the stepped sidewall of the electrode layer 110 is greater than or equal to 3. Accordingly, in the step of performing multiple sub-patterning processes on the electrode material layer 100, the number of sub-patterning processes is greater than or equal to 3 times.

[0103] The following combination Figures 5 to 10 , describes in detail the process of multiple sub-graphic processing, where, for the sake of clarity, Figures 5 to 10 Only one electrode material layer 100 is shown as a schematic diagram of forming an electrode layer 110. Specifically, Figure 5 and Figure 6 For the first sub-graphics processing, Figure 7 and Figure 8 . This is the second sub-graphics processing. Fig. 9 and Fig.10 This is the third sub-graphics processing.

[0104] In this embodiment, the sub-patterning process includes: patterning a portion of the width of the electrode material layer 100 from the side wall to the middle position of the electrode material layer 100 , and removing a portion of the thickness of the electrode material layer 100 .

[0105] In this embodiment, the processing widths of the multiple sub-patterning processes are increased sequentially, and the processing surface of each sub-patterning process includes the surface processed by all previous sub-patterning processes.

[0106] refer to Figure 5 and Figure 6 , the processing width of the first sub-patterning process is 100a, refer to Figure 7 and Figure 8 The processing width of the second sub-patterning process is 100a, refer to Fig. 9 and Fig.10 , the processing width of the third sub-patterning process is 100a. It can be seen that the processing width 100a of each sub-patterning process increases successively, and the processing surface of the subsequent sub-patterning process covers the processing surface of the previous sub-patterning process.

[0107] Specifically, refer to Figure 5 and Figure 6 In the first sub-patterning process, the electrode material layer 100 having a width and a thickness of partly from the side wall to the middle position is removed; Figure 7 and Figure 8 , the surface of the electrode material layer 100 exposed by the first sub-patterning treatment and the partial surface not exposed by the first sub-patterning treatment are treated together, and a portion of the thickness of the electrode material layer 100 is removed along the treated surface at the same time. Since the surface of the electrode material layer 100 exposed by the first sub-patterning treatment and the partial surface not exposed by the first sub-patterning treatment have different heights, after the partial thickness of the electrode material layer 100 is removed along the treated surface at the same time, the treated surface still presents a morphology with different heights; refer to Fig. 9 and Fig.10 Similarly, after the entire electrode material layer 100 is processed, a step-shaped sidewall morphology is obtained.

[0108] In this embodiment, the steps of patterning the electrode material layer 100 from the sidewall to the middle of the electrode material layer 100 and removing the electrode material layer 100 from the thickness thereof include: Figure 5 , forming a mask layer 200 covering a portion of the top surface of the electrode material layer 100, and the mask layer 200 exposes a portion of the top surface of at least one side of the electrode material layer 100; Figure 6 , the electrode material layer 100 exposed by the patterned mask layer 200 is removed, and a portion of the thickness of the electrode material layer 100 is removed.

[0109] In this embodiment, in multiple sub-patterning processes, the coverage of the mask layer 200 in the latter sub-patterning process is smaller than the coverage of the mask layer 200 in the previous sub-patterning process, and a portion of the top surface of the electrode material layer 100 covered by the previous sub-patterning process is exposed.

[0110] That is to say, Figure 7 The coverage of the mask layer 200 is smaller than Figure 5 The coverage of the mask layer 200 is formed. Fig. 9 The coverage of the mask layer 200 is smaller than Figure 7 The coverage of the formed mask layer 200 is shown in FIG.

[0111] Specifically, refer to Figure 5 and Figure 6 In the first sub-patterning process, the mask layer 200 covers part of the top surface of the electrode material layer 100, exposing the top surface of the electrode material layer 100 from the side wall to the middle part, and removing part of the thickness of the electrode material layer 100 along the exposed surface of the electrode material layer 100; Figure 7 and Figure 8 The mask layer 200 formed has a smaller coverage than the previous sub-patterning treatment, exposing the surface of the electrode material layer 100 exposed by the first sub-patterning treatment and a portion of the surface adjacent to the surface processed by the first sub-patterning treatment. The exposed surface presents steps of different heights. The exposed surfaces are processed together, and a portion of the thickness of the electrode material layer 100 is removed simultaneously along the processed surfaces at different heights. After a portion of the thickness of the electrode material layer 100 is removed simultaneously along the processed surfaces, the processed surface still presents morphologies of different heights. Fig. 9 and Fig.10 Similarly, after the entire electrode material layer 100 is processed, a step-shaped sidewall morphology is obtained.

[0112] In this embodiment, in the subsequent sub-patterning process, the step of forming a mask layer 200 covering a portion of the top surface of the electrode material layer 100 includes: patterning the mask layer 200 formed after the previous sub-patterning process, removing a partial width of the mask layer 200, and exposing a portion of the top surface of the electrode material layer 100.

[0113] Specifically, refer to Figure 6 and Figure 7 , patterning the mask layer 200 formed after the previous sub-patterning process, performing lateral etching on the mask layer 200 obtained after the previous sub-patterning process, removing the mask layer 200 covering a portion of the top surface of the electrode material layer 100, exposing a portion of the top surface that was not processed by the previous sub-patterning process, and forming a mask layer 200 for a subsequent sub-patterning process; referring to Figure 8 and Fig. 9 , the same as above.

[0114] It should be noted that, in this embodiment, in the step of performing transverse etching on the mask layer 200 obtained after the previous sub-patterning process to remove the mask layer 200 covering part of the top surface of the electrode material layer 100, the width of the removed mask layer 200 should not be too large or too small. If the width of the removed mask layer 200 is too large, the electrode material layer 100 that has been patterned is exposed too much, which may easily lead to the width of the step surface being too large, resulting in the area of ​​the electrode layer 110 occupied by multiple steps being too large, affecting the effective film thickness of the electrode layer 110, and thus affecting the performance of the semiconductor structure; if the width of the removed mask layer 200 is too small, the electrode material layer 100 that has been patterned is exposed too little, which may easily lead to the width of the step surface being too small, resulting in the verticality of the side wall of the electrode layer 110 composed of multiple steps still being too large, making it difficult to alleviate the problem of the reliability of the semiconductor structure being affected by the excessive electric field at that location due to the sharp corners of the lower electrode layer 110, simplifying the process of covering the electrode layer 110 on the stepped sidewalls, reducing the sidewall residues, and thus improving the performance of the semiconductor structure. To this end, in this embodiment, the mask layer 200 obtained after the previous sub-patterning process is laterally etched to remove the mask layer 200 covering a portion of the top surface of the electrode material layer 100, and the width of the removed mask layer 200 is 5nm to 50nm.

[0115] In this embodiment, a dry etching process is used to pattern the electrode material layer 100 exposed by the mask layer 200, and a portion of the thickness of the electrode material layer 100 is removed.

[0116] The dry etching process has the characteristics of anisotropic etching, and the etching is more directional. It can advance downward simultaneously along the processing surfaces of different heights exposed by the mask layer 200, and remove part of the electrode material layer 100 with similar thickness on the processing surface at each height, so as to obtain a stepped side wall, and it is also beneficial to obtain an electrode layer 110 with higher side wall quality.

[0117] refer to Fig.11 In this embodiment, after the patterning process is performed, the mask layer 200 is removed.

[0118] The mask layer 200 is removed to prepare for the dielectric layer 120 formation process.

[0119] In this embodiment, the process of forming the dielectric layer 120 includes: forming the dielectric layer 120 covering the electrode layer 110 .

[0120] refer to Fig.12 In this embodiment, in the step of forming a plurality of electrode layers 110 stacked sequentially from bottom to top on a substrate 300, when the number of the plurality of electrode layers 110 is an odd number, the formation method further includes: forming a dummy electrode layer 130 on an extension portion 300y of the topmost even-numbered electrode layer 110.

[0121] In this embodiment, two adjacent electrode layers 110 are partially overlapped, and the non-overlapped portion is used as an extension portion 300y. The extension portions 300y of the adjacent electrode layers 110 are stacked from bottom to top in sequence, so that the electrical signal can be simultaneously loaded to the adjacent electrode layers 110 through the extension portions 300y of the adjacent electrode layers 110. When the number of electrode layers 110 is an odd number, the number of stacked layers of the extension portions 300y of the electrode layers 110 of the odd number is one more than the number of stacked layers of the extension portions 300y of the electrode layers 110 of the even number. Therefore, in this embodiment, a pseudo electrode layer 130 is formed on the extension portion 300y of the topmost even number electrode layer 110, so that the electrode layers 110 of the odd number are stacked. The number of metal film layers at the extension portion 300y position of 10 is equal to the number of metal film layers at the extension portion 300y position of the electrode layer 110 of the even-numbered layer, so that when the second electrical connection structure in which the electrode layer 110 of the odd-numbered layer is loaded with an electrical signal and the first electrical connection structure in which the electrode layer 110 of the even-numbered layer is loaded with an electrical signal, the number of etched metal film layers is consistent, and the thickness of the etched metal film layers tends to be consistent accordingly, so that the etching process when forming the first electrical connection structure and the etching process when forming the second electrical connection structure can be performed with the same etching process parameters, that is, the first electrical connection structure and the second electrical connection structure can be formed in the same step, thereby improving the process efficiency.

[0122] In the present embodiment, in order to make the thickness of the etched metal film layer tend to be consistent when the second electrical connection structure for loading electrical signals on the electrode layer 110 formed as an odd-numbered layer and the first electrical connection structure for loading electrical signals on the electrode layer 110 formed as an even-numbered layer are formed, the top-layer odd-numbered electrode layer 110 and the dummy electrode layer 130 are patterned through the same electrode material layer, so that the top-layer odd-numbered electrode layer 110 and the dummy electrode layer 130 have the same thickness, which is beneficial to simplify the process flow and improve the process efficiency. Therefore, in the present embodiment, the dummy electrode layer 130 and the top-layer odd-numbered electrode layer 110 are the same layer structure.

[0123] Specifically, in this embodiment, when the number of electrode layers 110 is an odd number, in the step of forming the topmost electrode layer 110 , the electrode material layer 100 is patterned to obtain the electrode layer 110 and the dummy electrode layer 130 at the same time.

[0124] Continue to refer Fig.12 After forming a plurality of electrode layers 110 stacked sequentially from bottom to top on the substrate 300, the forming method further includes: forming an extension portion 300y penetrating the even-numbered electrode layers 110 and electrically connecting the first electrical connection structure 410 thereto.

[0125] The first electrical connection structure 410 is used to electrically connect the even-numbered electrode layers 110 , so as to load electrical signals to the even-numbered electrode layers 110 .

[0126] Specifically, in the present embodiment, in the step of forming the first electrical connection structure 410, a positioning structure corresponding to the first electrical connection structure 410 is used as a formation position to form a first electrical connection structure 410 that penetrates the even-numbered electrode layer 110. The first electrical connection structure 410 penetrates the even-numbered electrode layer 110 and is in full contact with the even-numbered electrode layer 110, thereby being able to achieve better electrical connection performance.

[0127] In this embodiment, the material of the first electrical connection structure 410 is a conductive material. As an example, the material of the first electrical connection structure 410 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0128] Accordingly, in the present embodiment, when the number of the multi-layer electrode layer 110 is an odd number, in the step of forming the first electrical connection structure 410 which penetrates the extension portion 300y of the even-numbered electrode layer 110 and is electrically connected thereto, the first electrical connection structure 410 also penetrates the dummy electrode layer 130, so that when the second electrical connection structure for loading electrical signals on the electrode layer 110 formed as an odd number of layers and the first electrical connection structure for loading electrical signals on the electrode layer 110 formed as an even number of layers are formed, the number of etched metal film layers is consistent, and accordingly the thickness of the etched metal film layers tends to be consistent, so that the etching process for forming the first electrical connection structure and the etching process for forming the second electrical connection structure can be performed using the same etching process parameters, that is, the first electrical connection structure and the second electrical connection structure can be formed in the same step, thereby improving the process efficiency.

[0129] In this embodiment, after forming multiple electrode layers 110 stacked sequentially from bottom to top on the substrate 300 , the forming method further includes: forming an extension portion 300y penetrating the odd-numbered electrode layers 110 and a second electrical connection structure 420 electrically connected thereto.

[0130] The second electrical connection structure 420 is used to electrically connect the odd-numbered electrode layers 110 , so as to load electrical signals to the odd-numbered electrode layers 110 .

[0131] Specifically, in the present embodiment, in the step of forming the second electrical connection structure 420, a positioning structure corresponding to the second electrical connection structure 420 is used as a formation position to form a second electrical connection structure 420 that penetrates the odd-numbered electrode layer 110. The second electrical connection structure 420 penetrates the odd-numbered electrode layer 110 and is in full contact with the odd-numbered electrode layer 110, thereby being able to achieve better electrical connection performance.

[0132] In this embodiment, the material of the second electrical connection structure 420 is a conductive material. As an example, the material of the second electrical connection structure 420 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0133] In this embodiment, the semiconductor structure further includes: a lower metal layer 310 located in the substrate 300 at the bottom of the first through-hole interconnect structure 410 and electrically connected thereto, and located in the substrate 300 at the bottom of the second through-hole interconnect structure 420 and electrically connected thereto.

[0134] The lower metal layer 310 is used to realize electrical connection between the first through-hole interconnect structure 410 and the second through-hole interconnect structure 420 and the outside, and is also used to provide positioning for the formation of the first through-hole interconnect structure 410 and the second through-hole interconnect structure 420 .

[0135] In this embodiment, the material of the lower metal layer 310 is a conductive material. As an example, the material of the lower metal layer 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0136] In this embodiment, the semiconductor structure further includes: an upper metal layer 320 located on top of the first through-hole interconnect structure 410 and electrically connected thereto, and located on top of the second through-hole interconnect structure 420 and electrically connected thereto.

[0137] The upper metal layer 320 is used to realize electrical connection between the first through-hole interconnect structure 410 and the second through-hole interconnect structure 420 and the outside.

[0138] In this embodiment, the material of the upper metal layer 320 is a conductive material. As an example, the material of the upper metal layer 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0139] It should be noted that, in this embodiment, according to actual process requirements, the first through-hole interconnection structure 410 and the second through-hole interconnection structure 420 can realize electrical connection with the outside from the upper metal layer 320, and can also realize electrical connection with the outside from the lower metal layer 310, so that the electrical connection route of the first through-hole interconnection structure 410 and the second through-hole interconnection structure 420 is more flexible, which is conducive to improving the flexible application of the semiconductor structure.

[0140] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; Multiple electrode layers are stacked in sequence from bottom to top, located on the substrate, and in two adjacent electrode layers, the side wall of the lower electrode layer covered by the upper electrode layer is in a step shape; The dielectric layer is located between two adjacent electrode layers.

2. The semiconductor structure according to claim 1, wherein: The number of steps of the stepped sidewall of the electrode layer is greater than or equal to 3.

3. The semiconductor structure according to claim 1, wherein: In two adjacent electrode layers, the upper electrode layer covers a side wall of the lower electrode layer.

4. The semiconductor structure according to claim 1 or 3, characterized in that: In the plurality of electrode layers, two adjacent electrode layers partially overlap, and the non-overlapping portions serve as extensions, and the extensions of the electrode layers from bottom to top extend alternately to both sides of the electrode layers in sequence.

5. The semiconductor structure according to claim 4, characterized in that In the plurality of electrode layers, the extension parts of the electrode layers of the odd-numbered layers are stacked sequentially from bottom to top, and the extension parts of the electrode layers of the even-numbered layers are stacked sequentially from bottom to top.

6. The semiconductor structure according to claim 5, characterized in that The semiconductor structure further includes: a first electrical connection structure, penetrating through the extension portion of the electrode layer of the even-numbered layers and electrically connected thereto; The second electrical connection structure penetrates through the extension portions of the odd-numbered electrode layers and is electrically connected thereto.

7. The semiconductor structure according to claim 6, wherein: When the number of the electrode layers is an odd number, the semiconductor structure further comprises: a dummy electrode layer located on an extension of the electrode layer of the topmost even number layer; The first electrical connection structure also penetrates the dummy electrode layer.

8. The semiconductor structure according to claim 7, wherein: The dummy electrode layer and the topmost odd-numbered electrode layer are in the same layer structure.

9. The semiconductor structure according to claim 1, wherein: The material of the dielectric layer includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; The material of the electrode layer includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A plurality of electrode layers stacked in sequence from bottom to top and a dielectric layer located between two adjacent electrode layers are formed on the substrate, wherein the side wall of the lower electrode layer covered by the upper electrode layer is in a step shape.

11. The method for forming a semiconductor structure according to claim 10, wherein: The step of forming a plurality of electrode layers stacked sequentially from bottom to top on the substrate, and a dielectric layer located between two adjacent electrode layers, comprises: performing multiple patterning processes and performing a dielectric layer forming process between two adjacent patterning processes until the number of electrode layers reaches a preset number; The patterning process includes: forming an electrode material layer on the substrate; performing multiple sub-patterning processes on the electrode material layer until the sub-patterning process is completed on the entire thickness of the electrode material layer to form an electrode layer with a stepped sidewall; The sub-patterning process includes: patterning the electrode material layer from the side wall to the middle of the electrode material layer, and removing a portion of the thickness of the electrode material layer; Wherein, the processing width of the multiple sub-patterning processes increases successively, and the processing surface of each sub-patterning process includes the surface processed by all the previous sub-patterning processes; The dielectric layer forming process includes: forming a dielectric layer covering the electrode layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The step of patterning the electrode material layer having a width from the side wall to the middle position of the electrode material layer and removing a portion of the thickness of the electrode material layer comprises: forming a mask layer covering a portion of the top surface of the electrode material layer, wherein the mask layer exposes a portion of the top surface of at least one side of the electrode material layer; patterning the electrode material layer exposed by the mask layer and removing a portion of the thickness of the electrode material layer; Among the multiple sub-patterning processes, the coverage of the mask layer of the subsequent sub-patterning process is smaller than the coverage of the mask layer of the previous sub-patterning process, and a portion of the top surface of the electrode material layer covered by the previous sub-patterning process is exposed; After the patterning process is performed, the mask layer is removed.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the subsequent sub-patterning process, the step of forming a mask layer covering part of the top surface of the electrode material layer includes: patterning the mask layer formed after the previous sub-patterning process, removing part of the width of the mask layer, and exposing part of the top surface of the electrode material layer.

14. The method for forming a semiconductor structure according to claim 12, wherein: In the step of performing multiple sub-patterning processes on the electrode material layer, the number of sub-patterning processes is greater than or equal to 3 times.

15. The method for forming a semiconductor structure according to claim 12, wherein: The electrode material layer exposed by the mask layer is patterned by a dry etching process to remove a portion of the electrode material layer.

16. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming a plurality of electrode layers stacked sequentially from bottom to top on the substrate, in two adjacent electrode layers, the upper electrode layer covers a side wall of the lower electrode layer.

17. The semiconductor structure according to claim 10 or 16, characterized in that: In the step of forming a plurality of electrode layers stacked from bottom to top on the substrate, two adjacent electrode layers partially overlap, and the non-overlapping parts serve as extensions, and the extensions of the electrode layers from bottom to top extend alternately to both sides of the electrode layers.

18. The method for forming a semiconductor structure according to claim 17, wherein: In the step of forming a plurality of electrode layers stacked sequentially from bottom to top on the substrate, among the plurality of electrode layers, extensions of the electrode layers of odd-numbered layers are stacked sequentially from bottom to top, and extensions of the electrode layers of even-numbered layers are stacked sequentially from bottom to top.

19. The method for forming a semiconductor structure according to claim 18, wherein: After forming multiple electrode layers stacked sequentially from bottom to top on the substrate, the forming method further comprises: forming a first electrical connection structure that penetrates through the extension portions of the even-numbered electrode layers and is electrically connected thereto; A second electrical connection structure is formed which penetrates through the extension portions of the odd-numbered electrode layers and is electrically connected thereto.

20. The method for forming a semiconductor structure according to claim 19, wherein: When the number of the electrode layers is an odd number, the forming method further comprises: forming a dummy electrode layer on an extension of the electrode layer of the topmost even number layer; In the step of forming a first electrical connection structure that penetrates through the extension portions of the even-numbered electrode layers and is electrically connected thereto, the first electrical connection structure also penetrates through the dummy electrode layer.

Images