Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a first chip and an encapsulation assembly. The substrate is provided with a first surface and a second surface; the first surface is provided with a circuit, and a chip welding area, a plurality of inner pin welding areas and a plurality of electrode welding areas which are connected with the circuit; the first chip is provided with a front surface and a back surface, the front surface of the first chip is provided with a first electrode and a second electrode, the back surface of the first chip is provided with a third electrode, the back surface of the first chip faces the substrate, and the third electrode is welded on the chip welding area; the at least two sheet-shaped electric connecting pieces are used for respectively connecting the first electrode and the second electrode on the front surface of the first chip to different electrode welding areas on the substrate; the packaging assembly comprises a second chip, a plurality of inner pins connected with the second chip, and a packaging body. The packaging body is provided with a third surface and a fourth surface, and the inner pins are partially exposed and extend out of the third surface; the third surface of the packaging body faces the substrate, the inner pins are welded to the inner pin welding areas respectively, and the first chip is located between the packaging body and the substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In the traditional IMS (aluminum substrate) module packaging structure, the field effect tube and the control chip are generally packaged together. The field effect tube and the control chip are arranged on the IMS in the same layer spacing. The field effect tube has three poles, namely the gate, source, and drain. The drain is connected to the IMS (aluminum substrate) through an adhesive, and the gate and source are connected to the corresponding pins of the IMS (aluminum substrate) by metal wires; the control chip is connected to the gate, and the signal end is connected to the IMS (aluminum substrate) by wire bonding, so as to achieve line conduction.

[0003] This type of packaging structure has a fixed product size. Therefore, high-current and high-voltage power chips and devices cannot be arranged within the limited packaging structure size (high-current and high-voltage power chips have a large area), which affects the power and functional output of the product. Summary of the invention

[0004] An embodiment of the present application provides a semiconductor structure, which includes:

[0005] A substrate having a first surface and a second surface facing away from each other, wherein the first surface is provided with a circuit and a chip welding area connected to the circuit, a plurality of inner pin welding areas and a plurality of electrode welding areas;

[0006] A first chip has a front side and a back side, wherein a first electrode and a second electrode are arranged on the front side of the first chip, a third electrode is arranged on the back side of the first chip, the back side of the first chip faces the substrate, and the third electrode is welded on a chip welding area;

[0007] At least two sheet-shaped electrical connectors, used to respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate;

[0008] An encapsulation component comprises a second chip, a plurality of inner pins connected to the second chip, and an encapsulation body, wherein the encapsulation body covers the second chip and the inner pins; the encapsulation body has a third surface and a fourth surface which are opposite to each other, and the inner pins are partially exposed and extend beyond the side where the third surface is located; the encapsulation component is arranged on the substrate, the third surface of the encapsulation body faces the substrate, the plurality of inner pins are respectively welded to the plurality of inner pin welding areas, and the first chip is located between the encapsulation body and the substrate.

[0009] In some embodiments, the encapsulation assembly further includes a third chip; the encapsulation body further covers the third chip;

[0010] The third chip is arranged on the same layer as the second chip.

[0011] In some embodiments, the encapsulation assembly further includes a lead frame base island located within the encapsulation body;

[0012] The second chip has a front side and a back side, the front side of the second chip is provided with a plurality of electrodes, and the back side of the second chip faces the lead frame base island and is provided on the lead frame base island;

[0013] The third chip has a front side and a back side. The front side of the third chip is provided with a plurality of electrodes. The back side of the third chip faces the lead frame base island and is provided on the lead frame base island.

[0014] In some embodiments, the encapsulation assembly further includes a plurality of leads, a portion of the leads being used to connect the electrodes on the front side of the second chip with the corresponding inner pins, and another portion of the leads being used to connect the electrodes on the front side of the third chip with the corresponding inner pins.

[0015] In some embodiments, the first surface is provided with a plurality of external pin welding areas located at least on one side of the chip welding area, and the plurality of external pin welding areas are connected to the circuit; the semiconductor structure further comprises a plurality of external pins; the plurality of external pins are respectively welded to the plurality of external pin welding areas;

[0016] Conductive solder is provided on the chip welding area, multiple electrode welding areas, multiple inner pin welding areas, multiple outer pin welding areas, and the first pole and the second pole of the first chip. The first chip is soldered to the chip welding area through the conductive solder, the multiple inner pins are respectively soldered to the multiple inner pin welding areas through the conductive solder, the multiple outer pins are respectively soldered to the multiple outer pin welding areas through the conductive solder, at least one sheet-like electrical connector is soldered to the first pole and the corresponding electrode welding area through the conductive solder, and at least one sheet-like electrical connector is soldered to the second pole and the corresponding electrode welding area through the conductive solder.

[0017] In some embodiments, the semiconductor structure includes a plastic package, the plastic package covers the first chip disposed on one side of the first surface of the substrate, the encapsulation component, the at least two sheet-like electrical connectors and the exposed portion of the first surface of the substrate; and / or

[0018] The first chip is a MOS chip, the second chip is an IC chip, and the third chip is an MCU chip.

[0019] The present application also provides a method for preparing a semiconductor structure, which includes:

[0020] The first chip is arranged on the substrate; the substrate has a first surface and a second surface which are opposite to each other, the first surface is provided with a circuit and a chip welding area connected to the circuit, a plurality of inner pin welding areas and a plurality of electrode welding areas; the first chip has a front side and a back side, the front side of the first chip is provided with a first pole and a second pole, the back side of the first chip is provided with a third pole, the back side of the first chip faces the substrate, and the third pole is welded on the chip welding area;

[0021] At least two sheet-shaped electrical connectors are provided; the at least two sheet-shaped electrical connectors respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate;

[0022] An encapsulation component is provided; the encapsulation component includes a second chip, a plurality of inner pins connected to the second chip, and an encapsulation body; the encapsulation body covers the second chip and the inner pins; the encapsulation body has a third surface and a fourth surface which are opposite to each other, and the inner pins are partially exposed and extend beyond the side where the third surface is located; the encapsulation component is provided on the substrate, the third surface of the encapsulation body faces the substrate, the plurality of inner pins are respectively welded to the plurality of inner pin welding areas, and the first chip is located between the encapsulation body and the substrate.

[0023] In some embodiments, the encapsulation assembly further includes a third chip, and the encapsulation body further covers the third chip;

[0024] The third chip is arranged on the same layer as the second chip.

[0025] In some embodiments, before providing the encapsulation component, the method includes:

[0026] Assembling the second chip and the lead frame; the lead frame comprises a lead frame base island and a plurality of inner pins located on at least one side of the lead frame base island; the second chip has a front side and a back side, a plurality of electrodes are arranged on the front side of the second chip, the back side of the second chip faces the lead frame base island and is arranged on the lead frame base island, and the plurality of electrodes of the second chip are respectively connected to the plurality of inner pins;

[0027] An encapsulation body is provided to form an encapsulation assembly.

[0028] In some embodiments, the encapsulation assembly includes a third chip, and before providing the encapsulation body, the method further includes:

[0029] A third chip is provided; the third chip has a front side and a back side, a plurality of electrodes are provided on the front side of the third chip, and the back side of the third chip faces the lead frame base island and is provided on the lead frame base island;

[0030] After providing the third chip and before providing the encapsulation body, the method includes:

[0031] A plurality of leads are provided, a portion of the leads are used to connect the electrodes on the front side of the second chip with the corresponding inner pins, and another portion of the leads are used to connect the electrodes on the front side of the third chip with the corresponding inner pins.

[0032] In some embodiments, after providing the encapsulation assembly, the method includes:

[0033] A plurality of external pins are provided; the first surface is provided with a plurality of external pin welding areas located at least on one side of the chip welding area, and the plurality of external pin welding areas are connected to the circuit; the plurality of external pins are respectively welded to the plurality of external pin welding areas;

[0034] Before placing the first chip on the substrate, the method includes: placing conductive solder on the chip welding area, multiple electrode welding areas, multiple inner pin welding areas, and multiple outer pin welding areas;

[0035] After setting a plurality of outgoing pins, the method includes:

[0036] The conductive solder is reflow-cured.

[0037] In some embodiments, after setting the plurality of egress pins, the method includes:

[0038] A plastic package is formed; the plastic package covers the first chip, the encapsulation component, the at least two sheet-like electrical connectors and the exposed portion of the first surface of the substrate.

[0039] The main technical effects achieved by the embodiments of the present application are:

[0040] The semiconductor structure and manufacturing method provided in the embodiment of the present application, by arranging a package including a second chip on the first chip, so that the second chip and the first chip are stacked, a larger chip size can be arranged within a limited packaging space, thereby achieving effective packaging of high-current and high-voltage power chips; at the same time, due to the optimization of the packaging structure, it is convenient to encapsulate more chips and devices within the limited packaging space, thereby achieving more functional outputs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0042] Figure 2 is a cross-sectional view of another semiconductor structure provided by an exemplary embodiment of the present application;

[0043] Figure 3 is a flow chart of a method for preparing a semiconductor structure provided by an exemplary embodiment of the present application;

[0044] Figures 4 to 11 It is a preparation process diagram of a method for preparing a semiconductor structure provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0047] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0048] The present application provides a semiconductor structure and a method for preparing the same. The semiconductor structure includes a substrate, a first chip, at least two sheet-like electrical connectors and an encapsulation component. The substrate has a first surface and a second surface that are opposite to each other, and the first surface is provided with a circuit and a chip welding area connected to the circuit, a plurality of inner pin welding areas and a plurality of electrode welding areas. The first chip has a front side and a back side, and the front side of the first chip is provided with a first pole and a second pole, and the back side of the first chip is provided with a third pole, and the back side of the first chip faces the substrate, and the third pole is welded on the chip welding area. At least two sheet-like electrical connectors are used to respectively connect the first pole and the second pole on the front side of the first chip to different electrode welding areas on the substrate. The encapsulation assembly includes a second chip, a plurality of inner pins connected to the second chip, and an encapsulation body, wherein the encapsulation body covers the second chip and the inner pins; the encapsulation body has a third surface and a fourth surface that are opposite to each other, and the inner pins are partially exposed and extend beyond the side where the third surface is located; the encapsulation assembly is arranged on the substrate, the third surface of the encapsulation body faces the substrate, the plurality of inner pins are respectively welded to the plurality of inner pin welding areas, and the first chip is located between the encapsulation body and the substrate. The above semiconductor structure, by arranging the encapsulation body including the second chip on the first chip, makes the second chip and the first chip stacked, and can arrange a larger chip size in a limited packaging space, thereby realizing effective packaging of high-current and high-voltage power chips; at the same time, due to the optimization of the packaging structure, it is convenient to enclose more chips and devices in a limited packaging space, thereby realizing more functional outputs.

[0049] The following is combined with Figures 1 to 11 , some embodiments of the present application are described in detail. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0050] Please refer to Figure 1 , and when necessary, combine Figure 2 As shown, the semiconductor structure 1000 includes a substrate 10 , a first chip 30 , at least two sheet-shaped electrical connectors 40 and a second chip 61 .

[0051] The substrate 10 has a first surface 101 and a second surface 102 which are opposite to each other. The first surface 101 is provided with a circuit and a chip welding area 103 connected to the circuit, a plurality of inner lead welding areas 106 and a plurality of electrode welding areas 104 .

[0052] The first chip 30 has a front side 301 and a back side facing away from each other. The front side 301 of the first chip 30 is provided with a first pole and a second pole, the back side of the first chip 30 is provided with a third pole, the back side of the first chip 30 faces the substrate 10, and the third pole is welded on the chip welding area 103.

[0053] At least two sheet-shaped electrical connectors 40 are used to respectively connect the first electrode and the second electrode on the front side of the first chip 30 to different electrode welding areas 104 on the substrate 10 .

[0054] The encapsulation component 60 includes a second chip 61, a plurality of inner pins 632 connected to the second chip 61, and an encapsulation body 65, wherein the encapsulation body 65 covers the second chip 61 and the inner pins 632. The encapsulation body 65 has a third surface 601 and a fourth surface 602 which are opposite to each other. The inner pins 632 are partially exposed and extend outside the side where the third surface 601 is located, that is, Figure 1 The encapsulation assembly 60 is arranged on the substrate 10, the third surface 601 of the encapsulation body 65 faces the substrate 10, the plurality of inner pins 632 are respectively welded to the plurality of inner pin welding areas 106, and the first chip 30 is located between the encapsulation body 65 and the substrate 10.

[0055] The substrate mentioned here may be a metal plate (IMS, Insulated Metal Substrate), such as an aluminum substrate.

[0056] The first chip 30 mentioned here can be a MOS chip, that is, a driving MOS transistor, and the second chip 61 can be an IC chip, that is, a driving chip. It can be understood that the size of the second chip 61 here is smaller than that of the first chip 30.

[0057] The first electrode mentioned here is a gate electrode, the second electrode mentioned here can be a source electrode, and the third electrode is a drain electrode, or vice versa.

[0058] It is understandable that passive components such as resistors, capacitors, inductors, etc. may also be disposed on the substrate 10 .

[0059] The sheet-like electrical connector 40 mentioned here can be a copper sheet. Figure 1 As shown, the sheet-like electrical connector 40 may include a first connecting portion 41 extending laterally and used to connect the first pole or the third pole of the first chip 30, and a second connecting portion 42 located at the side of the first chip 30 and extending longitudinally. The sheet-like electrical connector can lead the first pole and the second pole of the front side 301 of the first chip 30 to the circuit on the connection substrate 10.

[0060] Please continue to refer to Figure 1As shown, the package component 60 of the semiconductor structure 1000 further includes a third chip 62, and the package body 65 further covers the third chip 62. By integrating the second chip 61 and the third chip 62 into one package component, the arrangement of the second chip 61 and the third chip 62 is facilitated and the preparation is convenient.

[0061] The third chip 62 may be an MCU chip, i.e., a control chip. The semiconductor structure 1000 places an encapsulation body 65 encapsulating the second chip 61 on the first chip 30, so that the second chip 61 is stacked on the first chip 30, and introduces the third chip 62. Compared with the implementation in which the MCU chip is separately placed outside and the IC chip and the MOS chip are integrated in a semiconductor structure with the same layer interval, the semiconductor structure 1000 introduces other chips or devices such as the MCU, which is conducive to realizing more functions while realizing high current and high voltage power of the semiconductor structure.

[0062] It should be noted that, here, the encapsulation component 60 is adopted to encapsulate the second chip 61 or the second chip 61 and the third chip 62 and then arrange them on the substrate 10, so as to facilitate the flexible arrangement of the second chip 61 or the second chip 61 and the third chip 62, so that the arrangement of the second chip 61 or the second chip 61 and the third chip 62 can be determined according to specific needs, and does not need to be completely stacked on the first chip 30 or other similar structures.

[0063] It should also be noted that the orthographic projections of the encapsulation body 65 and the first chip 30 and its sheet-like electrical connector 40 in the encapsulation assembly 60 in the thickness direction T of the semiconductor structure 1000 mostly overlap. The outer dimensions of the encapsulation body 65 are substantially equal to or equal to the outer dimensions of the sheet-like electrical connector 40. Figure 1 The dimensions w1 and w2 in the width direction W are substantially equal. For another example, w1 can be controlled within the range of 0.9w2-1.1w2, so that the package 65 is not too small, and the inner pins 632 are not extended too much inward, so that there is sufficient support for the package 65 and the second chip 61 or the second chip 61 and the third chip 62 enclosed therein, and the package 65 is not too large, which is not conducive to the size control along the thickness direction T perpendicular to the semiconductor structure 1000.

[0064] In some embodiments, the third chip 62 and the second chip 61 are disposed in the same layer in the package, which is beneficial for achieving high current and high voltage power of the semiconductor structure while controlling the thickness of the semiconductor structure.

[0065] Please continue to refer to Figure 1As shown, in some embodiments, the encapsulation component 60 further includes a lead frame base island 631 located inside the encapsulation body 65. The lead frame base island 631 and the inner lead 632 may be different parts of the same lead frame. The lead frame base island 631 may be used to arrange the second chip 61 and the third chip 62 so that the two are arranged in the same layer.

[0066] The second chip 61 has a front side 611 and a back side facing away from each other. The front side 611 of the second chip 61 is provided with a plurality of electrodes. The back side of the second chip 61 faces the lead frame base island 631 and is provided on the lead frame base island 631 .

[0067] The third chip 62 has a front side 621 and a back side. A plurality of electrodes are disposed on the front side of the third chip 62 . The back side of the third chip 62 faces the lead frame base island 631 and is disposed on the lead frame base island 631 .

[0068] Of course, it is understandable that the encapsulation component may also include other carriers or bearings for arranging the second chip and the third chip, but not including the lead frame base island. Alternatively, the encapsulation component may not be provided with a lead frame base island or a corresponding bearing. Figure 1 As shown, the encapsulation component 60 of the semiconductor structure 1000 also includes a plurality of leads 66, a portion of the plurality of leads 66 is used to connect the electrode on the front side of the second chip 61 with the corresponding inner pin 632, and another portion of the plurality of leads 66 is used to connect the electrode on the front side of the third chip 62 with the corresponding inner pin.

[0069] Furthermore, in some embodiments, a portion of the leads 66 may be used to connect the electrodes on the front surface of the second chip 61 and the electrodes on the front surface of the third chip 62 .

[0070] The lead wire 66 can be a conductive wire such as an aluminum wire or a copper wire.

[0071] Please continue to refer to Figure 1 As shown, the first surface 101 is provided with a plurality of external pin welding areas 105 located at least on one side of the chip welding area 103, and the plurality of external pin welding areas 105 are connected to the circuit. The semiconductor structure 1000 also includes a plurality of external pins 50. The plurality of external pins 50 are respectively welded to the plurality of external pin welding areas 105.

[0072] Please continue to refer to Figure 1As shown, conductive solder 20 is provided on the chip welding area 103, multiple electrode welding areas 104, multiple inner pin welding areas 106, multiple outer pin welding areas 105, and the first pole and the second pole of the first chip 30. The first chip 30 is soldered to the chip welding area 103 through the conductive solder 20, the multiple inner pins 632 are respectively soldered to the multiple inner pin welding areas 106 through the conductive solder 20, the multiple outer pins 50 are respectively soldered to the multiple outer pin welding areas 105 through the conductive solder 20, at least one sheet electrical connector 40 is soldered to the first pole and the corresponding electrode welding area 104 through the conductive solder 20, and at least one sheet electrical connector 40 is soldered to the second pole and the corresponding electrode welding area 104 through the conductive solder 20.

[0073] The conductive solder may be solder paste, or other solders, such as silver.

[0074] Please continue to refer to Figure 1 As shown, the semiconductor structure 1000 includes a plastic package 110 , which covers the first chip 30 disposed on one side of the first surface 101 of the substrate 10 , the encapsulation component 60 , the at least two sheet-like electrical connectors 40 and the exposed portion of the first surface 101 of the substrate 10 .

[0075] It is understandable that the plastic package 110 also covers a portion of the external pin 50. The external end of the external pin 50 can be exposed from the plastic package 110 to be electrically connected to an external structure.

[0076] It should be noted that the third chip 62 is an MCU chip, the second chip 61 is an IC chip, and the first chip 30 is a MOS chip. When the semiconductor structure 1000 is working, the MCU chip will provide a control signal to the IC chip, and the IC chip will drive the MOS chip to perform corresponding work after receiving the control signal.

[0077] It should be noted that, in some other embodiments, the encapsulated component in the semiconductor structure may not include the third chip, that is, the MCU chip. Figure 2 As shown, the semiconductor structure 2000 does not include a third chip, that is, does not include an MCU chip. Accordingly, when the semiconductor structure 2000 is working, it can cooperate with the MCU structure that is separately externally placed outside the semiconductor structure 2000. That is, the second chip 61 is an IC chip, and the first chip 30 is a MOS chip. When the semiconductor structure 2000 is working, the MCU structure that is separately externally placed outside the semiconductor structure 2000 will provide a control signal to the IC chip, and the IC chip will drive the MOS chip to perform corresponding work after receiving the control signal.

[0078] It should be noted that the outgoing pins 50 of the semiconductor structure 1000 and the semiconductor structure 2000 may be further bent, for example, bent toward the lower surface side in the figure, so as to facilitate subsequent connection with other structures.

[0079] In addition, it should be noted that the semiconductor structure 1000 or 2000 can be a power device, which can be applied to a drive switch as a module structure of a drive switch. For example, it can be applied to air conditioners, washing machines or other electrical structures. Taking the application in air conditioners as an example, it can be applied to control or drive at least one of the functions of air conditioners such as cooling, heating, and frequency conversion. The difference is that the semiconductor structure 1000 is integrated with an MCU chip (that is, a control chip), while the semiconductor structure 2000 is not integrated with an MCU chip, and needs to work with a separate MCU chip or MCU structure.

[0080] Please refer to Figure 3 As shown, the present application further provides a semiconductor intermediate structure, which may include a plurality of semiconductor structures 1000 or 2000 or similar semiconductor structures as described above. The plurality of semiconductor structures may be arranged in an array.

[0081] The present application further provides a method for preparing a semiconductor structure, which includes the following steps S101 to S105:

[0082] In step S101, a first chip is arranged on a substrate; the substrate has a first surface and a second surface facing away from each other, the first surface is provided with a circuit and a chip welding area connected to the circuit, a plurality of inner pin welding areas and a plurality of electrode welding areas; the first chip has a front side and a back side, the front side of the first chip is provided with a first pole and a second pole, the back side of the first chip is provided with a third pole, the back side of the first chip faces the substrate, and the third pole is welded on the chip welding area.

[0083] In step S103, at least two sheet-shaped electrical connectors are provided; the at least two sheet-shaped electrical connectors respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate.

[0084] In step S105, an encapsulation component is provided. The encapsulation component includes a second chip, a plurality of inner pins connected to the second chip, and an encapsulation body; the encapsulation body covers the second chip and the inner pins; the encapsulation body has a third surface and a fourth surface that are opposite to each other, and the inner pins are partially exposed and extend beyond the side where the third surface is located; the encapsulation component is provided on the substrate, the third surface of the encapsulation body faces the substrate, the plurality of inner pins are respectively welded to the plurality of inner pin welding areas, and the first chip is located between the encapsulation body and the substrate.

[0085] Combine the following Figures 4 to 11 As shown, taking the preparation of the semiconductor structure 1000 as an example, the preparation method of the semiconductor structure is described in detail.

[0086] Please combine Figure 6 As shown, in the method for preparing the semiconductor structure, first, a substrate 10 is provided. The substrate 10 has a first surface 101 and a second surface 102 which are separated from each other, and the first surface 101 is provided with a circuit and a chip welding area 103 connected to the circuit, a plurality of electrode welding areas 104, a plurality of inner pin welding areas 106 and an outer pin welding area 105.

[0087] The substrate 10 mentioned here may be a metal plate (IMS, Insulated Metal Substrate), such as an aluminum substrate.

[0088] Please continue to combine Figure 6 As shown, before the first chip 30 is placed on the substrate 10 in step S101, the method includes the following step S102:

[0089] In step S102 , the conductive solder 20 is provided on the chip pad 103 , the plurality of electrode pads 104 , the plurality of inner lead pads 106 , and the outer lead pad 105 .

[0090] The conductive solder 20 can be solder paste, silver, etc.

[0091] Please combine Figure 7 As shown, in step S101, a first chip 30 is disposed on a substrate 10. The first chip 30 has a front side 301 and a back side, the front side 301 of the first chip 30 is provided with a first pole and a second pole, the back side of the first chip 30 is provided with a third pole, the back side of the first chip 30 faces the substrate 10, and the third pole is welded on the chip welding area 103.

[0092] The first chip 30 mentioned here may be a MOS chip. It is understandable that passive components such as resistors, capacitors, inductors, etc. may also be arranged on the substrate 10.

[0093] The first electrode mentioned here is a gate electrode, the second electrode mentioned here can be a source electrode, and the third electrode is a drain electrode, or vice versa.

[0094] Please combine Figure 8 As shown, in step S103, at least two sheet-shaped electrical connectors 40 are provided. The at least two sheet-shaped electrical connectors 40 respectively connect the first electrode and the second electrode on the front side of the first chip 30 to different electrode welding areas 104 on the substrate 10.

[0095] The sheet-like electrical connector 40 mentioned here can be a copper sheet. Figure 1 As shown, the sheet-like electrical connector 40 may include a first connecting portion 41 extending laterally and used to connect the first pole or the third pole of the first chip 30, and a second connecting portion 42 located at the side of the first chip 30 and extending longitudinally. The sheet-like electrical connector can lead the first pole and the second pole of the front side 301 of the first chip 30 to the circuit on the connection substrate 10.

[0096] Before setting the encapsulation component 60 in step S105, the method includes the following step S104:

[0097] In step S104 , the encapsulation component 60 is formed.

[0098] Please combine Figure 4 and Figure 5 As shown, the encapsulation component 60 includes a second chip 61, a lead frame 63 connected to the second chip 61, and an encapsulation body 65. The lead frame 63 includes a lead frame base island 631 and a plurality of inner pins 632 located on at least one side of the lead frame base island 631. Specifically, the plurality of inner pins 632 are respectively connected to the second chip 61.

[0099] The encapsulation body 65 covers the second chip 61, the lead frame base island 631 and the inner pins 632. The encapsulation body 65 has a third surface 601 and a fourth surface 602 which are opposite to each other, and the inner pins 632 are partially exposed and extend beyond the side where the third surface 601 is located.

[0100] The second chip 61 mentioned here may be an IC chip.

[0101] Specifically, please combine Figure 4 and Figure 5 As shown, step S104 can be implemented through the following steps S1041 and S1043.

[0102] like Figure 4 As shown, in step S1041, the second chip 61 and the lead frame 63 are assembled. The second chip 61 has a front side 611 and a back side, the front side 611 of the second chip 61 is provided with a plurality of electrodes, the back side of the second chip 61 faces the lead frame base island 631 and is provided on the lead frame base island 631, and the plurality of electrodes of the second chip 61 are respectively connected to the plurality of inner pins 632.

[0103] In this step, the second chip 61 can be placed on the lead frame base island 631 by means of adhesive 64. The adhesive 64 is preferably an insulating adhesive, such as insulating adhesive EN-4900GCN3.

[0104] like Figure 5As shown, in step S1043 , an encapsulation body 65 is provided to form an encapsulation assembly 60 .

[0105] Please combine Fig. 9 As shown, in step S105, an encapsulation component 60 is provided. The encapsulation component 60 is provided on the substrate 10, the third surface 601 of the encapsulation body 65 faces the substrate 10, the plurality of inner pins 632 are respectively welded to the plurality of inner pin welding areas 106, and the first chip 30 is located between the encapsulation body 65 and the substrate 10. The first chip 30 and the sheet-shaped electrical connector connected thereto may be spaced apart from the encapsulation body 65.

[0106] It can be understood that, in some embodiments, the encapsulation component 60 further includes a third chip 62 , and the encapsulation body 65 further covers the third chip 62 .

[0107] The third chip 62 may be an MCU chip. In the semiconductor structure 1000, the encapsulation body 65 encapsulating the second chip 61 is arranged on the first chip 30, so that the second chip 61 is stacked on the first chip 30, and the third chip 62 is introduced. Compared with the implementation method in which the MCU chip is separately external, and the IC chip and the MOS chip are integrated in a semiconductor structure with the same layer interval, the semiconductor structure 1000 introduces other chips or devices such as the MCU, which is conducive to realizing more functions while realizing the high current and high voltage power of the semiconductor structure.

[0108] In some embodiments, the third chip 62 and the second chip 61 can be arranged in the same layer, which is beneficial to realize high current and high voltage power of the semiconductor structure while controlling the thickness size of the semiconductor structure.

[0109] Accordingly, for the third chip 62 , before providing the encapsulation body 65 in step S1043 , the method may further include the following step S1042 .

[0110] In step S1042 , a third chip 62 is provided. The third chip 62 has a front side 621 and a back side. The front side 621 of the third chip 62 is provided with a plurality of electrodes. The back side of the third chip 62 faces the lead frame base island 631 and is provided on the lead frame base island 631 .

[0111] In this step, the third chip 62 can also be placed on the lead frame base island 631 by means of adhesive 64. The adhesive 64 is preferably an insulating adhesive, such as insulating adhesive EN-4900GCN3.

[0112] It should be noted that the order of step S1042 and step S1041 is not limited.

[0113] It can be understood that after step S1041 and step S1042 and before step S1043, the method includes the following step S1044.

[0114] In step S1044, a plurality of leads 66 are provided, a portion of the leads 66 is used to connect the electrode on the front side 611 of the second chip 61 with the corresponding inner pin 632, and another portion of the leads 66 is used to connect the electrode on the front side of the third chip 62 with the corresponding inner pin 632.

[0115] It is understandable that part of the leads 66 may also be used to connect the electrodes on the front side of the second chip 61 and the electrodes on the front side of the third chip 62 .

[0116] Please combine Fig.10 As shown, after the encapsulation component 60 is provided in step S105, the method further includes the following step S106:

[0117] In step S106, multiple external pins 50 are set; the first surface 101 is provided with multiple external pin welding areas 105 located on at least one side of the chip welding area 103, and the multiple external pin welding areas 105 are connected to the circuit; the multiple external pins 50 are respectively welded to the multiple external pin welding areas 105.

[0118] The output pin 50 is provided to facilitate electrical extraction and electrical signal input within the semiconductor structure 1000 .

[0119] It should be noted that after setting a plurality of outgoing pins 50 in step S106, the method includes the following step S107:

[0120] In step S107 , the conductive solder 20 is reflow-cured.

[0121] Taking the conductive solder as solder paste as an example, the solder paste can be solidified by reflow heating to achieve a fixed connection of the corresponding structure.

[0122] Please combine Fig.11 As shown, after step S106 and step S107, the method includes the following step S108:

[0123] In step S108 , a plastic package 110 is formed; the plastic package 110 covers the first chip 30 , the encapsulation component 60 , the at least two sheet-like electrical connectors 40 and the exposed portion of the first surface 101 of the substrate 10 .

[0124] Furthermore, after the plastic package 110 is formed, a semiconductor intermediate structure may be formed, wherein the semiconductor intermediate structure includes a plurality of semiconductor structural units. The plurality of semiconductor structural units may be similar to Fig.10 In the structure shown, the substrates 10 of different semiconductor structure units can be connected into a continuous structure.

[0125] Accordingly, after forming the semiconductor intermediate structure, the method comprises the following step S109:

[0126] In step S109, the semiconductor intermediate structure is cut into pieces to form semiconductor structures.

[0127] Please refer to Fig.11 As shown, when the semiconductor intermediate structure is cut, the following Fig.11 A semiconductor structure 1000 is shown.

[0128] It should be noted that in the formation of Fig.11 After the semiconductor structure 1000 is shown, the method may further include bending the outgoing pin 50, such as bending it toward the lower surface side in the figure, so as to facilitate subsequent connection with other structures.

[0129] The semiconductor structure 2000 may be manufactured by referring to the above corresponding manufacturing method steps.

[0130] The embodiment of the method for manufacturing a semiconductor structure provided in the embodiment of the present application and the embodiment of the semiconductor structure belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0131] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0132] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0133] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a first surface and a second surface facing away from each other, wherein the first surface is provided with a circuit and a chip welding area connected to the circuit, a plurality of inner pin welding areas and a plurality of electrode welding areas; A first chip has a front side and a back side, wherein a first electrode and a second electrode are arranged on the front side of the first chip, a third electrode is arranged on the back side of the first chip, the back side of the first chip faces the substrate, and the third electrode is welded on a chip welding area; At least two sheet-shaped electrical connectors, used to respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate; An encapsulation component, comprising a second chip, a plurality of inner pins connected to the second chip, and an encapsulation body, wherein the encapsulation body covers the second chip and the inner pins; the encapsulation body has a third surface and a fourth surface which are opposite to each other, and the inner pins are partially exposed and extend beyond the side where the third surface is located; The encapsulation component is arranged on the substrate, the third surface of the encapsulation body faces the substrate, the plurality of inner pins are respectively welded to the plurality of inner pin welding areas, and the first chip is located between the encapsulation body and the substrate.

2. The semiconductor structure according to claim 1, wherein: The encapsulation component further includes a third chip; the encapsulation body further covers the third chip; The third chip is arranged on the same layer as the second chip.

3. The semiconductor structure according to claim 2, wherein: The encapsulation assembly also includes a lead frame base island located inside the encapsulation body; The second chip has a front side and a back side, the front side of the second chip is provided with a plurality of electrodes, and the back side of the second chip faces the lead frame base island and is provided on the lead frame base island; The third chip has a front side and a back side. The front side of the third chip is provided with a plurality of electrodes. The back side of the third chip faces the lead frame base island and is provided on the lead frame base island.

4. The semiconductor structure according to claim 3, characterized in that The encapsulation component also includes a plurality of leads, a portion of which is used to connect the electrodes on the front side of the second chip with the corresponding inner pins, and another portion of which is used to connect the electrodes on the front side of the third chip with the corresponding inner pins.

5. The semiconductor structure according to claim 2, wherein: The first surface is provided with a plurality of external pin welding areas located at least on one side of the chip welding area, and the plurality of external pin welding areas are connected to the circuit; the semiconductor structure also includes a plurality of external pins; the plurality of external pins are respectively welded to the plurality of external pin welding areas; Conductive solder is provided on the chip welding area, multiple electrode welding areas, multiple inner pin welding areas, multiple outer pin welding areas, and the first pole and the second pole of the first chip. The first chip is soldered to the chip welding area through the conductive solder, the multiple inner pins are respectively soldered to the multiple inner pin welding areas through the conductive solder, the multiple outer pins are respectively soldered to the multiple outer pin welding areas through the conductive solder, at least one sheet-like electrical connector is soldered to the first pole and the corresponding electrode welding area through the conductive solder, and at least one sheet-like electrical connector is soldered to the second pole and the corresponding electrode welding area through the conductive solder.

6. The semiconductor structure according to any one of claims 2 to 5, characterized in that: The semiconductor structure comprises a plastic package, wherein the plastic package covers the first chip disposed on one side of the first surface of the substrate, the encapsulation component, the at least two sheet-shaped electrical connectors and the exposed portion of the first surface of the substrate; and / or The first chip is a MOS chip, the second chip is an IC chip, and the third chip is an MCU chip.

7. A method for preparing a semiconductor structure, characterized in that: include: placing a first chip on a substrate; The substrate has a first surface and a second surface which are opposite to each other, the first surface is provided with a circuit and a chip welding area connected to the circuit, a plurality of inner pin welding areas and a plurality of electrode welding areas; the first chip has a front side and a back side, the front side of the first chip is provided with a first electrode and a second electrode, the back side of the first chip is provided with a third electrode, the back side of the first chip faces the substrate, and the third electrode is welded on the chip welding area; At least two sheet-shaped electrical connectors are provided; the at least two sheet-shaped electrical connectors respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate; An encapsulation component is provided; the encapsulation component comprises a second chip, a plurality of inner pins connected to the second chip, and an encapsulation body; the encapsulation body covers the second chip and the inner pins; the encapsulation body has a third surface and a fourth surface which are opposite to each other, and the inner pins are partially exposed and extend beyond the side where the third surface is located; The encapsulation component is arranged on the substrate, the third surface of the encapsulation body faces the substrate, the plurality of inner pins are respectively welded to the plurality of inner pin welding areas, and the first chip is located between the encapsulation body and the substrate.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The encapsulation component further includes a third chip, and the encapsulation body further covers the third chip; The third chip is arranged on the same layer as the second chip.

9. The method for preparing a semiconductor structure according to claim 7 or 8, characterized in that: Prior to providing the encapsulation component, the method comprises: Assembling the second chip and the lead frame; the lead frame comprises a lead frame base island and a plurality of inner pins located on at least one side of the lead frame base island; the second chip has a front side and a back side, a plurality of electrodes are arranged on the front side of the second chip, the back side of the second chip faces the lead frame base island and is arranged on the lead frame base island, and the plurality of electrodes of the second chip are respectively connected to the plurality of inner pins; An encapsulation body is provided to form an encapsulation assembly.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The encapsulation assembly includes a third chip, and before providing the encapsulation body, the method further includes: A third chip is provided; the third chip has a front side and a back side, a plurality of electrodes are provided on the front side of the third chip, and the back side of the third chip faces the lead frame base island and is provided on the lead frame base island; After providing the third chip and before providing the encapsulation body, the method includes: A plurality of leads are provided, a portion of the leads are used to connect the electrodes on the front side of the second chip with the corresponding inner pins, and another portion of the leads are used to connect the electrodes on the front side of the third chip with the corresponding inner pins.

11. The method for preparing a semiconductor structure according to claim 8, wherein: After providing the encapsulation assembly, the method includes: A plurality of external pins are provided; the first surface is provided with a plurality of external pin welding areas located at least on one side of the chip welding area, and the plurality of external pin welding areas are connected to the circuit; the plurality of external pins are respectively welded to the plurality of external pin welding areas; Before placing the first chip on the substrate, the method includes: placing conductive solder on the chip welding area, multiple electrode welding areas, multiple inner pin welding areas, and multiple outer pin welding areas; After setting a plurality of outgoing pins, the method includes: The conductive solder is reflow-cured.

12. The method for preparing a semiconductor structure as claimed in claim 11, characterized in that: After setting a plurality of outgoing pins, the method includes: A plastic package is formed; the plastic package covers the first chip, the encapsulation component, the at least two sheet-like electrical connectors and the exposed portion of the first surface of the substrate.

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