Electronic device

Abstract

The invention discloses an electronic device. The electronic device includes an interposer, a voltage regulator, a first circuit structure, and an electronic component. The voltage regulator is attached to the interposer. The first circuit structure is supported by the interposer. The electronic component is disposed adjacent to the interposer and electrically connected to the voltage regulator via the first circuit structure and the interposer.

Description

Technical Field

[0001] The present disclosure generally relates to an electronic device. Background Art

[0002] For high performance computing (HPC) systems of electronic devices, power supply units with low power consumption and high heat dissipation are required. The power delivery path for transmitting power signals is usually provided by a system board on which several dies are mounted. The layout design may be limited by the need to minimize electromagnetic interference between power signals and non-power signals (e.g., electrical signals), which can limit the ability to miniaturize the system board.

[0003] The voltage and power requirements of the die vary, and the rapid increase in the total number and variety of dies has led to a corresponding increase in the number of power delivery paths. One approach to providing a more stable power delivery path is to provide power through an interconnect structure or power conditioning components on the interconnect die. However, this may increase the size of the electronic device and place further constraints on the level of miniaturization of the electronic device that can be achieved. Summary of the invention

[0004] In some embodiments, an electronic device includes an insert, a voltage regulator, a first circuit structure, and an electronic component. The voltage regulator is attached to the insert. The first circuit structure is supported by the insert. The electronic component is disposed adjacent to the insert and is electrically connected to the voltage regulator via the first circuit structure and the insert.

[0005] In some embodiments, an electronic device includes a first circuit structure, a second circuit structure, and a voltage regulator. The second circuit structure is disposed below the first circuit structure. The voltage regulator is configured to transfer power between the first circuit structure and the second circuit structure. The voltage regulator vertically overlaps the first circuit structure and the second circuit structure.

[0006] In some embodiments, an electronic device includes a circuit structure and an insert. The insert is vertically connected to the circuit structure. The circuit structure and the insert define a space to accommodate a voltage regulator. The insert is configured to transmit power to the circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of some embodiments of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that the various structures may not be drawn to scale, and the sizes of the various structures may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0009] Figure 2A Describe some embodiments of the present disclosure. Figure 1 An enlarged view of an insert of an electronic device is shown in FIG.

[0010] Figure 2B A cross-sectional view of an insert from another perspective is illustrated according to some embodiments of the present disclosure.

[0011] Figure 2C Describe some embodiments of the present disclosure. Figure 1 An enlarged view of a circuit structure in an electronic device shown in FIG.

[0012] Figure 3 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0013] Figure 4 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0014] Figure 5 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0015] Figure 6 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0016] Figure 7 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0017] Figure 8 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0018] Fig. 9 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0019] Fig.10 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0020] Fig.11 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0021] Fig.12 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0022] Fig.13 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0023] Fig.14A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0024] Fig.15 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] Common reference numbers are used throughout the drawings and detailed description to indicate the same or similar components.The arrangement of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0026] The following disclosure provides many different arrangements or examples of different features of the provided themes. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. Of course, these components and arrangements are examples only and are not intended to be restrictive. For example, in the following description, a first feature is formed above or on a second feature, and an arrangement in which the first feature and the second feature are directly contacted or arranged may be included, and an arrangement in which an additional feature may be formed or arranged between the first feature and the second feature so that the first feature and the second feature may not be directly contacted may also be included. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various arrangements and / or configurations discussed.

[0027] Figure 1 A cross-sectional view illustrating an electronic device 1a according to some embodiments of the present disclosure. In some embodiments, the electronic device 1a may include a circuit structure 10, an electronic component 20, an electronic component 30, a bridge circuit 40, an interposer 50, a circuit structure 60, a power management integrated circuit 72, and a voltage regulator 74.

[0028] The circuit structure 10 (or carrier or bottom circuit structure) may include a system board, a mainboard, a main printed circuit board (PCB) or other suitable carrier. The circuit structure 10 may include an interconnection structure, such as a redistribution layer (RDL), a circuit layer, a conductive trace, a conductive via, or other suitable elements. The interconnection structure may provide a signal path for other components electrically connected to the circuit structure 10. For example, the circuit structure 10 may facilitate and allow communication between components mounted thereon. In some embodiments, the circuit structure 10 may receive and / or transmit non-power signals (non-power signals) (e.g., I / O (input / output) signals) from the electronic component 20 and / or the electronic component 30. In some embodiments, the circuit structure 10 may receive and / or transmit power signals (powersignal) toward the insert 50. The circuit structure 10 may have a surface 10s1 (or a lower surface) and a surface 10s2 (or an upper surface) opposite to the surface 10s1. The circuit structure 10 may include a solder resist (not shown) on the surface 10s1 and / or the surface 10s2 of the circuit structure 10 to completely expose the conductive pad for electrical connection or expose at least a portion thereof.

[0029] The electronic device 1a may include electrical connectors 11, 12, and 13. The electrical connector 11 may be disposed below or on a surface 10s1 of the circuit structure 10. The electrical connector 11 may be configured to electrically connect the electronic device 1a with an external device (not shown). The electrical connector 12 may be disposed on or above a surface 10s2 of the circuit structure 10. The electrical connector 12 may be configured to electrically connect the circuit structure 10 with an electronic component 20. The electrical connector 13 may be disposed on or above a surface 10s2 of the circuit structure 10. The electrical connector 13 may be configured to electrically connect the circuit structure 10 with an electronic component 30. The electrical connectors 11, 12, and 13 may include solder balls, such as controlled collapse chip connection (C4) bumps, ball grid arrays (BGA), land grid arrays (LGA), and the like. The electrical connectors 11 , 12 , and 13 may include a solder material, which may include an alloy of gold and tin solder or an alloy of silver and tin solder or other suitable materials.

[0030] The electronic component 20 may be disposed on or above the surface 10s2 of the circuit structure 10. The electronic component 20 may be electrically connected to the circuit structure 10 via the electrical connector 12. The electronic component 20 may include a chip. In some embodiments, the electronic component 20 may include an active component that relies on an external power source to control, output, or modify an electrical signal. For example, the electronic component 20 may include a processor, a controller, a memory, or an input / output (I / O) buffer, etc. The electronic component 20 may include a logic die (e.g., an application-specific IC (ASIC), an application processor (AP), a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing die) DSP) die, front-end die (e.g., analog front-end (AFE) die), or other active components. The electronic component 20 may include a surface 20s1 (or a lower surface or a front surface) and a surface 20s2 (or an upper surface or a backside surface or a passive surface). The surface 20s1 may face the circuit structure 10. The surface 20s2 may be opposite to the surface 20s1. In some embodiments, the surface 20s1 may be configured to transmit an input / output (I / O) signal, which may include an alternating current (AC) or be composed of an alternating current (AC). In some embodiments, the surface 20s2 may be configured to receive power, which may include a direct current (DC) or be composed of a direct current (DC).

[0031] The electronic component 20 may include a logic circuit 21, a front redistribution structure 22, and a backside redistribution structure 23. The logic circuit 21 may be positioned adjacent to or formed on a surface 20s1 of the electronic component 20. The logic circuit 21 may include one or more ICs configured to generate non-power signals, such as one or more I / O signals for communicating with other electronic components.

[0032] The front side redistribution structure 22 may be disposed adjacent to the surface 20s1 of the electronic component 20. The front side redistribution structure 22 may also be referred to as a fan-in structure. The front side redistribution structure 22 may include conductive traces (not shown) and conductive vias (not shown) disposed on or within a dielectric layer. The front side redistribution structure 22 may be configured to transmit non-power signals, such as I / O signals or other signals or signals for communication with other electronic components.

[0033] A backside redistribution structure 23 may extend between the surface 20s2 and the logic circuit 21. The backside redistribution structure 23 may serve as a power delivery circuit. The backside redistribution structure 23 may include conductive traces (not shown) and conductive vias (not shown) configured to transfer power (or power signals) from the surface 20s2 to the logic circuit 21.

[0034] The electronic device 1a may include a conductive structure 24. The conductive structure 24 may be configured to electrically connect the electronic component 20 to the bridge circuit 40. The conductive structure 24 may include a plurality of conductive elements, such as conductive pads, solder elements, and / or other suitable elements. The conductive pads may include conductive materials, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. The solder element may include an alloy of gold and tin solder or an alloy of silver and tin solder, or other suitable materials.

[0035] The electronic device 1a may include a conductive structure 25. The conductive structure 25 may be configured to electrically connect the electronic component 20 and the circuit structure 10. The conductive structure 25 may include a plurality of conductive elements, such as conductive pillars and / or other suitable elements. The conductive pillars may include conductive materials, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. The length of the conductive structure 25 may be greater than the length of the conductive structure 24.

[0036] The electronic device 1a may include an encapsulant 26. The encapsulant 26 may be disposed on or below the surface 20s1 of the electronic component 20. In some embodiments, the encapsulant 26 may cover the bridge circuit 40. The encapsulant 26 may encapsulate the conductive structures 24 and 25. The encapsulant 26 may include an insulating material or a dielectric material. In some embodiments, the encapsulant 26 may be made of a molding compound, which may include, for example, a novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. A suitable filler may also be included, such as powdered SiO2.

[0037] The electronic component 30 may be disposed on or above the surface 10s2 of the circuit structure 10. The electronic component 30 may be electrically connected to the circuit structure 10 via the electrical connector 13. The electronic component 30 may include a chip. The electronic component 30 may include a processor, a controller, a memory, or an input / output (I / O) buffer, etc. The electronic component 30 may include a logic die (e.g., an application specific IC (ASIC), an application processor (AP), a system on a chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory die (e.g., a high bandwidth memory (HBM), a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electromechanical system (MEMS) die, etc. The electronic component 30 may include a surface 30s1 and a surface 30s2 opposite to the surface 30s1. The surface 30s1 may face the circuit structure 10. The surface 30s2 may be opposite to the surface 30s1. The surface 30s1 may be referred to as an active surface. The surface 30s2 may be referred to as a passive surface. Although not shown, the electronic component 30 may include an IC layer or an IC region adjacent to the surface 30s1.

[0038] The electronic device 1a may include a conductive structure 31. The conductive structure 31 may be configured to electrically connect the electronic component 30 and the bridge circuit 40. The conductive structure 31 may include a plurality of conductive elements, such as conductive pads, solder elements, and / or other suitable elements.

[0039] The electronic device 1a may include a conductive structure 32. The conductive structure 32 may be configured to electrically connect the electronic component 30 and the circuit structure 10. The conductive structure 32 may include a plurality of conductive elements, such as conductive pillars and / or other suitable elements.

[0040] The electronic device 1a may include an encapsulant 33. The encapsulant 33 may be disposed on or below the surface 30s1 of the electronic component 30. In some embodiments, the encapsulant 33 may cover the side (not labeled) of the electronic component 30. In some embodiments, the encapsulant 33 may cover the bridge circuit 40. The encapsulant 33 may encapsulate the conductive structures 31 and 32. The encapsulant 33 may include an insulating material or a dielectric material. In some embodiments, the encapsulant 33 may be made of a molding material, which may include, for example, a novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. A suitable filler may also be included, such as powdered SiO2.

[0041] The bridge circuit 40 may be disposed on or above the surface 10s2 of the circuit structure 10. The bridge circuit 40 may be configured to transmit signals (e.g., non-power signals) between the electronic components 20 and 30. In some embodiments, the bridge circuit 40 may be a bridge die. The bridge circuit 40 may include an integrated circuit. In some embodiments, the bridge circuit 40 may include a high-level data link control (HDLC) chip. The bridge circuit 40 may include a surface 40s1 (or a lower surface) and a surface 40s2 (or an upper surface) opposite to the surface 40s1. In some embodiments, the bridge circuit 40 may include a redistribution structure (not shown) adjacent to the surface 40s2 for electrically connecting the electronic components 20 and 30. In some embodiments, the surface 40s2 of the bridge circuit 40 may be covered by the encapsulant 26. In some embodiments, the surface 40s2 of the bridge circuit 40 may be covered by the encapsulant 33. In some embodiments, the side (not labeled) of the bridge circuit 40 may be covered by the encapsulant 26. In some embodiments, the sides of the bridge circuit 40 may be covered by the encapsulant 33 .

[0042] The electronic device 1a may include a heat transfer structure 42. The heat transfer structure 42 may be disposed on or below the surface 40s1 of the bridge circuit 40. In some embodiments, the heat transfer structure 42 may be configured to provide a heat transfer path for dissipating heat from the bridge circuit 40. The heat transfer structure 42 may be configured to attach the bridge circuit 40 to the circuit structure 10. In some embodiments, the heat transfer structure 42 may include glue, thermal interface material (TIM), or other suitable materials. In some embodiments, the heat transfer structure 42 may include a heat plate made of metal or other suitable materials.

[0043] In some embodiments, the insert 50 may be disposed on or above the surface 10s2 of the circuit structure 10. In some embodiments, the insert 50 may be disposed between the circuit structures 10 and 60. In some embodiments, the insert 50 may overlap or align laterally with the bridge circuit 40 along the X direction. In some embodiments, the insert 50 may overlap or align laterally with the electronic component 20 along the X direction. The insert 50 may be disposed adjacent to the surface 20s3 (or side) of the electronic component 20. In some embodiments, the insert 50 may be configured to receive and / or transmit power (or power signal) and / or regulated power (or regulated power signal). In some embodiments, the electronic component 20 may be disposed between the insert 50 and the electronic component 30.

[0044] In some embodiments, the circuit structure 60 may be disposed on or above the surface 20s2 of the electronic component 20. The circuit structure 60 may be disposed on or above the insert 50. In some embodiments, the circuit structure 60 may connect the electronic component 20 and the insert 50. In some embodiments, the electronic component 30 may not overlap with the circuit structure 60. In some embodiments, the circuit structure 60 may be supported by the insert 50. The circuit structure 60 may be configured to electrically connect the electronic component 20 and the insert 50. In some embodiments, the circuit structure 60 may overlap or align vertically with the insert 50 along the Z direction. The circuit structure 60 may cover the insert 50. In some embodiments, the circuit structure 60 may overlap or align vertically with the electronic component 20 along the Z direction. The circuit structure 60 may cover the electronic component 20. In some embodiments, a portion of the surface 20s2 of the electronic component 20 may be exposed by the circuit structure 60. In some embodiments, the circuit structure 60 may be configured to receive power (or power signal) and / or regulated power (or regulated power signal) from the insert 50 and / or transmit it to the electronic component 20. In some embodiments, the circuit structure 60 may be configured to receive and / or transmit a ground signal to the electronic component 20 .

[0045] See also Figure 2A , the insert 50 may extend vertically between the circuit structures 10 and 60. In some embodiments, the insert 50 may overlap or align vertically with the circuit structure 10 along the Z direction. In some embodiments, the insert 50 may overlap or align vertically with the circuit structure 60 along the Z direction. The insert 50 may include a surface 50s1 (or a lower surface) and a surface 50s2 (or an upper surface) opposite to the surface 50s1. The surface 50s1 may face the circuit structure 10. The surface 50s2 may face the circuit structure 60. The insert 50 may include a surface 50s3 (or a side or side surface) and a surface 50s4 (or a side or side surface) opposite to the surface 50s3. The surface 50s4 may face the electronic component 20, as shown in FIG. Figure 1 Surface 50s3 may face away from electronic component 20, such as Figure 1 . The insert 50 may include a substrate 51 and power delivery traces 52a and 52b. The insert 50 may include one or more conductive pads (not shown) proximate to, adjacent to, embedded in, and / or exposed by the surface 50s1 and / or surface 50s2 of the insert 50. The surface 50s4 may be substantially parallel to the substrate 51 and power delivery traces 52a and 52b. Figure 1 Surface 20s3 shown in FIG.

[0046] In some embodiments, the substrate 51 may have a relatively large hardness so that the substrate 51 can support the circuit structure 60. The substrate 51 may include a benzocyclobutene (BCB) based polymer or a polyimide (PI). The substrate 51 may include additional additives and / or fillers to enhance hardness.

[0047] Power delivery traces 52a (represented by solid lines) and power delivery traces 52b (represented by dashed lines) may be embedded within substrate 51. Power delivery traces 52a (or 52b) may be configured to transmit power (or power signals) and / or regulated power (or regulated power signals). Power delivery traces 52a and 52b may be configured to electrically connect circuit structure 10, power management integrated circuit 72, voltage regulator 74, and circuit structure 60.

[0048] In some embodiments, the insert 50 may be inserted into a recess 10r defined by the circuit structure 10 or partially located within the recess. The recess 10r may be recessed from the surface 10s2. In some embodiments, the insert 50 may be electrically connected to the circuit structure 10 via an electrical connector 53. The electrical connector 53 may be configured to electrically connect the circuit structure 10 with the insert 50. The electrical connector 53 may at least partially fill the recess 10r of the circuit structure 10. The electrical connector 53 may be disposed on or above the surface 10s2 of the circuit structure 10. The electrical connector 53 may include a soldering material, which may include an alloy of gold and tin solder or an alloy of silver and tin solder or other suitable materials. In some embodiments, the insert 50 may be inserted into the electrical connector 53 or partially located within the electrical connector, thereby increasing the contact area between the insert 50 and the electrical connector 53.

[0049] In some embodiments, the insert 50 may be inserted into a recess 60r defined by the circuit structure 60 or partially located in the recess. The recess 60r may be recessed from the surface 60s1 (or lower surface). In some embodiments, the insert 50 may be electrically connected to the circuit structure 60 through an electrical connector 54. The electrical connector 54 may be configured to electrically connect the circuit structure 60 with the insert 50. The electrical connector 54 may at least partially fill the recess 60r of the circuit structure 60. The electrical connector 54 may be disposed on or below the surface 60s1 of the circuit structure 60. The electrical connector 54 may include a soldering material, which may include an alloy of gold and tin solder or an alloy of silver and tin solder or other suitable materials. In some embodiments, the insert 50 may be inserted into the electrical connector 54 or partially located in the electrical connector, thereby increasing the contact area between the insert 50 and the electrical connector 54.

[0050] like Figure 2B As shown in , each of the electrical connectors 53 may be configured to electrically connect a corresponding terminal (eg, conductive pad) of the circuit structure 10 . Each of the electrical connectors 54 may be configured to electrically connect a corresponding terminal (eg, conductive pad) of the circuit structure 60 .

[0051] Return to reference Figure 2A, the power management integrated circuit 72 may be disposed on the surface 50s4 of the insert 50. The power management integrated circuit 72 may be electrically connected to the insert 50 by, for example, a soldering material 72e. The power management integrated circuit 72 may be disposed between the circuit structures 10 and 60 along the Z direction. The power management integrated circuit 72 may be electrically connected to the insert 50 using flip chip technology. The power management integrated circuit 72 may have a size (e.g., volume or surface area) that is smaller than a size (e.g., volume or surface area) of the electronic component 20. In some embodiments, the power management integrated circuit 72 may overlap or align vertically with the circuit structure 10 along the Z direction. In some embodiments, the power management integrated circuit 72 may overlap or align vertically with the circuit structure 60 along the Z direction. In some embodiments, the power management integrated circuit 72 may include an alternating current (AC) to direct current (DC) (AC / DC) converter and a DC to DC (DC / DC) converter. The power management integrated circuit 72 may be configured to manage multiple input powers (or power signals) from the circuit structure 10. For example, the power management integrated circuit 72 may be configured to tune or stabilize a plurality of input power (or power signals) and transmit (or distribute) the tuned or stabilized power to the circuit structure 60. The power management integrated circuit 72 may have a surface 72s1 (or a front surface or an active surface) and a surface 72s2 (or a backside surface or a passive surface) opposite to the surface 72s1. The integrated circuit of the power management integrated circuit 72 may be disposed adjacent to the surface 72s1. In some embodiments, the surface 72s2 of the power management integrated circuit 72 may face the electronic component 20, such as Figure 1 As shown in .

[0052] In some embodiments, the voltage regulator 74 may be disposed on the surface 50s4 of the interposer 50. The voltage regulator 74 may be electrically connected to the interposer 50 by, for example, a solder material 74e. The voltage regulator 74 may be disposed between the circuit structures 10 and 60 along the Z direction. The voltage regulator 74 may be electrically connected to the interposer 50 using flip chip technology. The voltage regulator 74 may have a size (e.g., volume or surface area) that is smaller than the size (e.g., volume or surface area) of the electronic component 20. In some embodiments, the voltage regulator 74 may overlap or align vertically with the circuit structure 10 along the Z direction. In some embodiments, the voltage regulator 74 may overlap or align vertically with the circuit structure 60 along the Z direction. In some embodiments, the voltage regulator 74 may overlap or align vertically with the power management integrated circuit 72 along the Z direction. The voltage regulator 74 may be configured to provide power (or a power signal) and / or regulated power (or a regulated power signal) to the electronic component 20. The voltage regulator 74 may include a linear regulator (which is configured to maintain a constant output voltage) or a switching regulator (which is configured to generate an output voltage that is higher or lower than the input voltage). In some embodiments, the voltage regulator 74 may include a step-down (buck) converter, a step-up (boost) converter, an analog / digital converter, a digital / analog converter, an AC / DC converter, a DC / DC converter, other types of converters, or a combination thereof. The voltage regulator 74 may have a surface 74s1 (or a front surface or active surface) and a surface 74s2 (or a backside surface or passive surface) opposite to the surface 74s1. The integrated circuit of the voltage regulator 74 may be arranged adjacent to the surface 74s1. In some embodiments, the surface 74s2 of the voltage regulator 74 may face the electronic component 20, such as Figure 1 As shown in .

[0053] See also Figure 2C The circuit structure 60 may have a surface 60s2 (or an upper surface) opposite to the surface 60s1. The circuit structure 60 may include a substrate 61, a ground layer 62, a ground circuit 63, and a power delivery circuit 64. The substrate 61 may include one or more dielectric layers formed of polyimide, a phenolic compound, or other suitable materials.

[0054] The ground layer 62 may be disposed adjacent to the surface 60s2 of the circuit structure 60. In some embodiments, the ground layer 62 may be exposed by the surface 60s2. The ground layer 62 may be electrically connected to ground. In some embodiments, the ground layer 62 may also serve as a heat sink.

[0055] A ground circuit 63 (represented by a solid line) may be electrically connected to the ground layer 62. The ground circuit 63 may include one or more conductive traces and conductive vias embedded within the substrate 61.

[0056] The power delivery circuit 64 (indicated by the dashed lines) may be electrically connected to the insert 50, such as Figure 1 . The power delivery circuit 64 may include one or more conductive traces and conductive vias embedded within the substrate 61. In some embodiments, the power delivery circuit 64 may be configured to receive power (or a power signal) and / or regulated power (or a regulated power signal) from the interposer 50 and / or transmit it to the electronic component 20.

[0057] The electronic device 1a may include a conductive structure 65. The conductive structure 65 may be disposed on or below the surface 60s1 of the circuit structure 60. The conductive structure 65 may be configured to electrically connect the circuit structure 60 and the electronic component 20. The conductive structure 65 may include a plurality of conductive elements, such as conductive pads, solder elements, and / or other suitable elements.

[0058] Return to reference Figure 1 , the electronic device 1a may include a path P1. Path P1 may be a power path. In some embodiments, path P1 describes a transmission path of power (or power signal) and / or regulated power (or regulated power signal). Path P1 may pass through the insert 50. Path P1 may pass through the power management integrated circuit 72. Path P1 may pass through the voltage regulator 74. Path P1 may pass through the circuit structure 60. Path P1 may pass through the surface 20s2 of the electronic component 20. In some embodiments, power (or power signal) and / or regulated power (or regulated power signal) may pass vertically through the insert 50.

[0059] The electronic device 1a may include a path P2. The path P2 may be a non-power path. In some embodiments, the path P2 describes a transmission path of a non-power signal such as an I / O signal. The path P2 may be transmitted from the surface 20s1 of the electronic component 20 to the circuit structure 10.

[0060] The electronic device 1a may include a path P3. The path P3 may be a non-power path. In some embodiments, the path P3 describes a transmission path for a non-power signal such as an I / O signal. The path P3 may be transmitted between the electronic components 20 and 30. The bridge circuit 40 may provide a horizontal transmission path for transmitting signals (or non-power signals). In some embodiments, the path P3 may pass through the surface 20s1 of the electronic component 20. The path P3 may pass through the surface 40s2 of the bridge circuit 40. The path P3 may pass through the surface 30s1 of the electronic component 30.

[0061] In some embodiments, the electronic device 1a may include an encapsulation (not shown) encapsulating the electronic component 20, the encapsulation 33, the bridge circuit 40, the interposer 50, the circuit structure 60, the power management integrated circuit 72, and the voltage regulator 74. The encapsulation may include a material that is the same as or similar to that of the encapsulation 26.

[0062] In this embodiment, the path of the signal and the path of the power pass through two opposite surfaces of the electronic component 20, so that the power and the signal can not interfere with each other. In the comparative example, the voltage regulator (or PMIC) is stacked on the electronic component or the circuit structure above the electronic component so as to provide power from the back surface of the electronic component. As a result, the thickness of the electronic device increases. In this embodiment, the power management integrated circuit 72 (or voltage regulator 74) with a smaller size is accommodated in the space defined by the circuit structure 10, the insert 50 and the circuit structure 60, thereby reducing the thickness of the electronic device 1a. The electronic component 20 is placed in the space and is spaced apart from the power management integrated circuit 72 (or voltage regulator 74). The power management integrated circuit 72 (or voltage regulator 74) is attached to the side of the insert 50, which provides a relatively short power transmission path. In addition, the insert 50 can be inserted into the circuit structure 10 through the electrical connector 53, thereby increasing the contact area between the circuit structure 10 and the insert 50. As a result, the resistance is reduced, resulting in an improvement in power loss.

[0063] Figure 3 A cross-sectional view illustrating an electronic device 1b according to some embodiments of the present disclosure. The electronic device 1b may be similar to the electronic device 1a, with the following differences therebetween.

[0064] In some embodiments, the electronic device 1b may include a heat sink 81. In some embodiments, the heat sink 81 may be disposed on the surface 50s3 of the insert 50. The voltage regulator 74 and the heat sink 81 may be disposed on two different sides of the insert 50 (e.g., the surfaces 50s3 and 50s4). For example, the voltage regulator 74 may be disposed on or attached to the surface 50s4, and the heat sink 81 may be disposed on or attached to the surface 50s3. In other embodiments, the heat sink 81 may be disposed on or attached to a side adjacent to the surface 50s4.

[0065] In some embodiments, the heat sink 81 may overlap or align vertically with the circuit structure 10 along the Z direction. In some embodiments, the heat sink 81 may overlap or align vertically with the circuit structure 60 along the Z direction. The heat sink 81 may include a heat sink, such as a heat sink fin as shown, which extends from the base portion along a direction substantially perpendicular to the surface 50s3 of the insert 50. In some embodiments, the heat sink 81 may include but is not limited to a solid metal block or an electrical insulator coated with a metal film. In some embodiments, the heat sink 81 may have one or more conductive layers. For example, the heat sink 81 may include copper (Cu), aluminum (Al), gold (Au), nickel (Ni) and / or other suitable layers. The heat sink 81 may also include aluminum oxide (Al2O3), aluminum nitride (AlN) or a silicon nitride (SiN) plate coated with copper. In some embodiments, the heat sink 81 may include a first layer serving as a thermally conductive layer having a larger thickness and a second layer serving as a protective layer having a smaller thickness. The heat sink 81 may be configured to facilitate dissipating heat from the power management integrated circuit 72 and / or the voltage regulator 74 .

[0066] In some embodiments, the interposer 50 may include heat transfer traces 55 and 56. The heat transfer trace 55 may be spaced apart from the power delivery trace 52a (or the power delivery trace 52b). The heat transfer trace 55 may connect the voltage regulator 74 and the heat sink 81. The heat transfer trace 56 may be spaced apart from the power delivery trace 52a (or the power delivery trace 52b). The heat transfer trace 56 may connect the power management integrated circuit 72 and the heat sink 81. The heat sink 81 may be connected to the substrate 51 via an adhesive layer (not shown). The adhesive layer may include a conductive material, a dielectric layer, and / or a thermally conductive material. The heat transfer trace 55 (or the heat transfer trace 56) may be configured to provide a heat transfer path between the heat sink 81 and the voltage regulator 74 (or the power management integrated circuit 72).

[0067] Figure 4 A cross-sectional view illustrating an electronic device 1c according to some embodiments of the present disclosure. The electronic device 1c may be similar to the electronic device 1b, with the following differences.

[0068] In some embodiments, the electronic device 1c may include a heat sink 82. In some embodiments, the heat sink 82 may be disposed on the surface 50s4 of the insert 50. In some embodiments, the heat sink 82 may be spaced apart from the insert 50. In some embodiments, the heat sink 82 may be disposed on the surface 72s2 of the power management integrated circuit 72. In some embodiments, the heat sink 82 may be disposed on the surface 74s2 of the voltage regulator 74. The heat sink 82 may be connected to the power management integrated circuit 72 (or the voltage regulator 74) via an adhesive layer (not shown). The adhesive layer may include a conductive material, an insulating material, and / or a thermally conductive material. The heat sink 82 may include a heat sink, such as a heat sink fin shown, extending from a base portion in a direction substantially perpendicular to the surface 50s4 of the insert 50. In some embodiments, the heat sink 82 may have one or more conductive layers. The heat sink 82 may be positioned across a gap (not labeled) between the power management integrated circuit 72 and the voltage regulator 74. The heat sink 82 may connect the power management integrated circuit 72 and the voltage regulator 74.

[0069] Figure 5 A cross-sectional view illustrating an electronic device 1d according to some embodiments of the present disclosure. The electronic device 1d may be similar to the electronic device 1a, with the following differences therebetween.

[0070] In some embodiments, the power management integrated circuit 72 may be disposed on the surface 50s3 of the interposer 50 , and the voltage regulator 74 may be disposed on the surface 50s4 of the interposer 50 .

[0071] The electronic device may include a heat sink 83 and a heat sink 84. The heat sink 83 may be configured to facilitate dissipation of heat from the voltage regulator 74. The heat sink 83 may be disposed on the surface 74s2 of the voltage regulator 74. The heat sink 83 may be disposed on the surface 50s4 of the insert 50. The heat sink 83 may include a heat sink. In some embodiments, the heat sink 83 may have one or more conductive layers.

[0072] The heat sink 84 may be configured to facilitate dissipation of heat from the power management integrated circuit 72. The heat sink 84 may be disposed on the surface 72s2 of the power management integrated circuit 72. The heat sink 84 may be disposed on the surface 50s3 of the interposer 50. The heat sink 84 may include a heat sink. In some embodiments, the heat sink 84 may have one or more conductive layers.

[0073] Figure 6 1 is a cross-sectional view illustrating an electronic device 1e according to some embodiments of the present disclosure. The electronic device 1e may be similar to the electronic device 1a, with the following differences. It should be noted that for the sake of simplicity, some elements of the circuit structures 10 and 60 and the interposer 50 (e.g., conductive traces, pads, or other elements) are shown in FIG. Figure 6 Or other figures are omitted.

[0074] In some embodiments, the voltage regulator 74 may be disposed on the surface 50s2 of the interposer 50. In some embodiments, the voltage regulator 74 may be disposed between the interposer 50 and the circuit structure 60. In some embodiments, the voltage regulator 74 may be disposed within or between the gap defined by the interposer 50 and the circuit structure 60. In some embodiments, the voltage regulator 74 may be disposed between the surface 50s2 (e.g., the upper surface) of the interposer 50 and the bottom surface (e.g., the bottom surface) of the circuit structure 60. Figure 2A In some embodiments, the voltage regulator 74 may be closer to the circuit structure 60 than the circuit structure 10. In some embodiments, the voltage regulator 74 may be accommodated in the space defined by the insert 50, the electrical connector 54, and the circuit structure 60. In some embodiments, the voltage regulator 74 may be disposed between the electrical connectors 54. The electrical connectors 54 may be configured to protect the voltage regulator 74 from electromagnetic interference (EMI). Although Figure 6 Although not shown, the power management integrated circuit 72 may be disposed on the surface 50s2 of the interposer 50. In this embodiment, the power management integrated circuit 72 may be closer to the circuit structure 60 than the circuit structure 10. Compared to the comparative example, the electronic device 1e may have a small thickness.

[0075] Figure 7 A cross-sectional view illustrating an electronic device 1f according to some embodiments of the present disclosure. The electronic device 1f may be similar to the electronic device 1a with the following differences.

[0076] In some embodiments, the voltage regulator 74 may be embedded within the interposer 50. The voltage regulator 74 may be embedded within the substrate 51 of the interposer 50. Although not shown, the power management integrated circuit 72 may be embedded within the interposer 50. In this embodiment, the electronic device 1f may provide a shorter transmission path, thereby reducing power loss.

[0077] Figure 8 A cross-sectional view illustrating an electronic device 1g according to some embodiments of the present disclosure. The electronic device 1g may be similar to the electronic device 1a, with the following differences therebetween.

[0078] In some embodiments, the electronic device 1g may include a socket 90. The socket 90 may be configured to electrically connect the circuit structure 10 and the insert 50. The socket 90 may include a redistribution structure (not shown) therein. The socket 90 may have a surface 90s1 (or lower surface) and a surface 90s2 (or upper surface) opposite to the surface 90s1. The socket 90 may define a recess 90r recessed from the surface 90s2. In some embodiments, the insert 50 may be inserted into or located within the recess 90r of the socket 90. In some embodiments, the surface 50s1 of the insert 50 may contact the bottom of the recess 90r.

[0079] In some embodiments, the fixing member 94 may be disposed in the recess 90r. The fixing member 94 may be configured to fix the insert 50. The fixing member 94 may surround the insert 50. In some embodiments, the insert 50 may be spaced apart from the sidewall of the recess 90r by the fixing member 94. The fixing member 94 may be configured to electrically connect the socket 90 and the insert 50. The fixing member 94 may have relatively large flexibility and deformability. When the power delivery trace 52b is placed against the fixing member 94, the fixing member 94 may provide a reaction force to the insert 50 so that the insert 50 can be fastened above the circuit structure 10. In some embodiments, the fixing member 94 may have a horizontal portion extending between the socket 90 and the insert 50, and a vertical portion contacting the terminal (e.g., conductive pad) of the insert 50. In some embodiments, the fixing member 94 may include a metal, an alloy or other suitable material. The socket 90 may provide a relatively large surface area that the insert 50 contacts. As a result, the resistance may be reduced, resulting in an improvement in power loss.

[0080] Although not shown, the electronic device 1g may include an additional socket configured to connect the insert 50 and the circuit structure 60. The additional socket may define a recess to accommodate the insert 50.

[0081] Fig. 9 A cross-sectional view illustrating an electronic device 1h according to some embodiments of the present disclosure. The electronic device 1h may be similar to the electronic device 1g, with the following differences therebetween.

[0082] In some embodiments, the socket 90 may be embedded in the recess 10r of the circuit structure 10. In some embodiments, the fixing member 94 may be embedded in the recess 10r of the circuit structure 10. In this embodiment, the thickness of the electronic device 1h may be reduced.

[0083] Fig.10 A cross-sectional view illustrating an electronic device 1i according to some embodiments of the present disclosure. The electronic device 1i may be similar to the electronic device 1a with the following differences.

[0084] In some embodiments, interposer 50 and circuit structure 60 may be a monolithic structure. For example, a trace (eg, power delivery trace 52a) may extend from interposer 50 to circuit structure 60 without borders. Substrates 51 and 61 may be made of the same material and / or process.

[0085] Fig.11 A cross-sectional view illustrating an electronic device 1j according to some embodiments of the present disclosure. The electronic device 1j may be similar to the electronic device 1a, with the following differences therebetween.

[0086] In some embodiments, the electronic device 1j may include a heat sink 85. In some embodiments, the heat sink 85 may be disposed on or above the surface 60s2 of the circuit structure 60. The heat sink 85 may be in contact with the ground layer 62. The heat sink 85 may include a heat sink, such as a heat sink fin shown, extending from a base portion in a direction substantially perpendicular to the surface 60s2 of the circuit structure 60. In some embodiments, a portion of the surface 60s2 of the circuit structure 60 may be exposed by the heat sink. The heat sink 85 may be configured to facilitate dissipation of heat from the circuit structure 60 to an external space of the electronic device 1j.

[0087] Fig.12 A cross-sectional view illustrating an electronic device 1k according to some embodiments of the present disclosure. The electronic device 1k may be similar to the electronic device 1a, with the following differences therebetween.

[0088] In some embodiments, the electronic device 1k may further include a carrier 44. The carrier 44 may be configured to support the electronic components 20 and 30. The carrier 44 may be disposed between the electronic component 20 and the bridge circuit 40. The carrier 44 may include a redistribution structure (not shown) for electrically connecting the bridge circuit 40 and the electronic components 20 and 30.

[0089] The bridge circuit 40 may include conductive structures 46 and 47. The conductive structure 46 may be disposed and electrically connected between the carrier 44 and the surface 40s2 of the bridge circuit 40. The conductive structure 46 may include, for example, a metal stud (e.g., a copper stud) or other suitable elements. The conductive structure 47 may be disposed and electrically connected between the carrier 44 and the surface 10s2 of the circuit structure 10. The conductive structure 47 may include, for example, a metal pillar (e.g., a copper pillar) or other suitable elements.

[0090] The electronic device 1k may include an encapsulant 48. The encapsulant 48 may be disposed between the surface 10s2 of the circuit structure 10 and the carrier 44. The encapsulant 48 may encapsulate the bridge circuit 40. The encapsulant 48 may encapsulate the conductive structures 46 and 47. In some embodiments, the encapsulant 48 may be made of a molding material, which may include, for example, a novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. A suitable filler, such as powdered SiO2, may also be included. In this embodiment, the path P2 may further pass through the carrier 44. In this embodiment, the path P3 may further pass through the carrier 44.

[0091] Fig.13 A cross-sectional view illustrating an electronic device 11 according to some embodiments of the present disclosure. The electronic device 11 may be similar to the electronic device 1k, with the following differences therebetween.

[0092] The electronic device 11 may further include an interconnect structure 92, an electrical connector 93, and an encapsulant 95. The interconnect structure 92 may be disposed on the circuit structure 10. The interconnect structure 92 may be configured to electrically connect the circuit structure 10 to the carrier 44. The interconnect structure 92 may include a dielectric structure 92d and a conductive element 92e embedded in the dielectric structure 92d. The dielectric structure 92d may include a benzocyclobutene-based polymer or a polyimide. The conductive element 92e may include a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. In some embodiments, the conductive structure 47 may penetrate a portion of the dielectric structure 92d and connect to the conductive element 92e.

[0093] The electrical connector 93 may be disposed between the interconnect structure 92 and the circuit structure 10. The electrical connector 93 may electrically connect the interconnect structure 92 and the circuit structure 10. The electrical connector 93 may include a solder element, which may include an alloy of gold and tin solder or an alloy of silver and tin solder or other suitable materials.

[0094] In some embodiments, the electronic device 11 may include an underfill 15. The underfill 15 may encapsulate the electrical connector 12. In some embodiments, the electronic device 11 may include an underfill 16. The underfill 16 may encapsulate the electrical connector 13.

[0095] Encapsulant 95 may be disposed on carrier 44. Encapsulant 95 may encapsulate electronic component 20. Encapsulant 95 may encapsulate electronic component 30. Encapsulant 95 may encapsulate underfill 15. Encapsulant 95 may encapsulate underfill 16. Encapsulant 95 may include an insulating material or a dielectric material. In some embodiments, encapsulant 95 may be made of a molding material, which may include, for example, a novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. A suitable filler may also be included, such as powdered SiO2.

[0096] Fig.14 A cross-sectional view illustrating an electronic device 1m according to some embodiments of the present disclosure. The electronic device 1m may be similar to the electronic device 1b, with the following differences therebetween.

[0097] In some embodiments, insert 50 may be replaced by insert 57. Insert 57 may be electrically connected to circuit structure 10 via electrical connector 53. Insert 57 may be electrically connected to circuit structure 60 via electrical connector 54. Voltage regulator 74 may be disposed on surface 57s1 (or side) of insert 57. Insert 57 may include dielectric layer 57d, seed layer 57e, conductive layer 57c, and conductive via 57v. Dielectric layer 57d may include benzocyclobutene (BCB) based polymer or polyimide (PI). Seed layer 57e may be disposed on dielectric layer 57d. Seed layer 57e may include titanium (Ti), copper (Cu), titanium nitride (TiN), or other suitable materials. Conductive layer 57c may be disposed on seed layer 57e. Conductive via 57v may extend between seed layer 57e and conductive layer 57c. Conductive via 57v may gradually narrow toward circuit structure 10. Although Fig.14 Not shown, but the power management integrated circuit 72 may be disposed on the surface 57s1 of the interposer 57.

[0098] Fig.15 A cross-sectional view illustrating an electronic device 1n according to some embodiments of the present disclosure. The electronic device 1n may be similar to the electronic device 1m, with the following differences.

[0099] The electronic device 1n may further include a core substrate 58 and an insert 59. The core substrate 58 may be disposed between the inserts 57 and 59. The core substrate 58 may include a through hole (not labeled) that penetrates the core substrate 58 and electrically connects the inserts 57 and 59. The insert 59 may be electrically connected to the circuit structure 10 through the electrical connector 53. The insert 59 may include a dielectric layer 59d, a seed layer 59e, a conductive layer 59c, and a conductive via 59v. The dielectric layer 59d may include a benzocyclobutene (BCB)-based polymer or a polyimide (PI). The seed layer 59e may be disposed on the dielectric layer 59d. The seed layer 59e may include titanium (Ti), copper (Cu), titanium nitride (TiN), or other suitable materials. The conductive layer 59c may be disposed on the seed layer 59e. The conductive via 59v may extend between the seed layer 59e and the conductive layer 59c. The conductive via 59v may gradually narrow toward the circuit structure 60. Fig.15 It is illustrated that the voltage regulator 74 is disposed on the surface 57 s 1 of the insert 57 , but the voltage regulator 74 may be disposed on the surface 59 s 1 (or the side surface) of the insert 59 .

[0100] Unless otherwise specified, spatial descriptions such as "above", "below", "up", "left", "right", "lower", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "above", "below", etc. are indicated relative to the orientation shown in the figure. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that embodiments of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not deviated by such arrangements.

[0101] As used herein, the terms "approximately," "substantially," "generally," "about," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, these terms may refer to instances where the event or circumstance occurred exactly as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation of less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value may be considered to be "substantially" the same as or equal to the second numerical value. For example, "substantially" vertical can refer to an angular variation range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0102] If the displacement between the two surfaces is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar. If the displacement between the highest point and the lowest point of a surface is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm, then the surface can be considered to be substantially flat.

[0103] As used herein, the singular forms "a," "an," and "the" may include plural or plural referents unless the context clearly indicates otherwise.

[0104] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to carry an electric current. Conductive materials are materials that present little or no resistance to the flow of electric current. One unit of measurement for conductivity is Siemens per meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m, for example at least 10 5 S / m or at least 10 6 S / m of a material. The conductivity of a material sometimes varies with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0105] In addition, amounts, ratios and other numerical values ​​are sometimes presented herein in a range format. It should be understood that such a range format is used for the sake of convenience and brevity, and should be flexibly construed to include not only the values ​​explicitly specified as the limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly specified.

[0106] Although the present disclosure has been described and illustrated with reference to the specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be replaced without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in the present disclosure and the actual equipment. There may be other embodiments that are not specifically described in the present disclosure. The description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to make specific situations, materials, material compositions, methods or processes suitable for the goals, spirit and scope of the present disclosure. All such modifications are deemed to be included within the scope of the appended claims. Although the disclosed method has been described herein with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. An electronic device, comprising: Inserts; a voltage regulator attached to the insert; a first circuit structure supported by the insert; as well as An electronic component is disposed adjacent to the interposer and is electrically connected to the voltage regulator via the first circuit structure and the interposer. 2 . The electronic device according to claim 1 , wherein the first circuit structure covers the voltage regulator and the electronic component. 3 . The electronic device of claim 2 , wherein the electronic component comprises a first surface, a second surface, and a logic circuit closer to the first surface than to the second surface, and the logic circuit is configured to receive power from the first circuit structure via the second surface. The electronic device according to claim 3 , wherein the second surface of the electronic component is a passive surface. 5 . The electronic device of claim 1 , wherein the voltage regulator has a passive surface and an active surface disposed between the interposer and the passive surface of the voltage regulator. The electronic device of claim 5 , wherein the voltage regulator is disposed between the interposer and the electronic component. 7 . The electronic device of claim 5 , wherein a side surface of the interposer is substantially parallel to a side surface of the electronic component.

8. The electronic device of claim 5, wherein the voltage regulator is disposed between the interposer and the first circuit structure. 9 . The electronic device of claim 8 , wherein the voltage regulator is disposed within a gap defined by an upper surface of the interposer and the first circuit structure.

10. The electronic device according to claim 1, further comprising: A heat sink is adjacent to the interposer and covered by the first circuit structure. 11 . The electronic device of claim 10 , wherein the voltage regulator is disposed at a first side of the interposer, and the heat sink is disposed at a second side of the interposer opposite the first side.

12. The electronic device of claim 10, wherein the voltage regulator is connected to the heat sink.

13. An electronic device comprising: A first circuit structure; a second circuit structure disposed below the first circuit structure; as well as A voltage regulator is configured to transfer power between the first circuit structure and the second circuit structure, wherein the voltage regulator vertically overlaps the first circuit structure and the second circuit structure.

14. The electronic device according to claim 13, further comprising: An electronic component is disposed between the first circuit structure and the second circuit structure, wherein the electronic component is configured to receive the power.

15. The electronic device of claim 14, wherein the voltage regulator does not vertically overlap the electronic component.

16. The electronic device of claim 14, wherein the electronic component is connected to the first circuit structure.

17. The electronic device of claim 16, wherein the electronic component is connected to the second circuit structure. 18 . The electronic device of claim 13 , wherein the first circuit structure has an upper surface and a bottom surface, and the first circuit structure includes a heat dissipation layer closer to the upper surface than to the bottom surface.

19. An electronic device comprising: Circuit structure; as well as An interposer is vertically connected to the circuit structure, wherein the circuit structure and the interposer define a space to accommodate a voltage regulator, wherein the interposer is configured to transmit power to the circuit structure. 20 . The electronic device of claim 19 , further comprising an electronic component disposed within the space and spaced apart from the voltage regulator, and the electronic component is configured to receive the power via the circuit structure.

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