Sepic power factor correction converter
By adopting bridgeless interleaving structure and ramp wave compensation technology in Sepic PFC circuit, the problems of output current distortion and low efficiency at high output power are solved, and high-efficiency power factor correction and electrical isolation are achieved, which is suitable for charging piles and intelligent power distribution systems.
Patent Information
- Application Number
- CN202411766067.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-02-28
AI Technical Summary
The output current of the traditional Sepic PFC circuit will distort at high output power, and the input voltage rectification of the rectifier bridge increases the on-state loss, making it difficult to improve the circuit efficiency.
High-efficiency bridgeless interleaved Sepic power factor correction converter is adopted, including two isolated Sepic power factor correction conversion circuits and ramp compensation circuits. The output power is increased through the staggered parallel structure and the input voltage zero-crossing distortion is reduced through ramp compensation technology.
It realizes high-efficiency power factor correction, with efficiency up to 98%, input current harmonics can be less than 3%, PF value up to 0.99 or above, and output is easy to be electrically isolated, suitable for charging piles and intelligent power distribution systems.
Smart Images
Figure CN119543634A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of converters, and in particular to a Sepic power factor correction converter. Background Art
[0002] Switching power supplies have attracted widespread attention in the industry with their advantages such as light weight, high efficiency, flexible control, high power density, and strong reliability, and have been widely used in modern power conversion devices. Some AC nonlinear loads in converter equipment or circuits represented by switching power supplies will generate a large amount of harmonic current components that distort the AC input waveform and inject them into the power grid, which has a negative impact on the power quality and transmission efficiency of the AC power grid. Therefore, controlling the harmonic pollution of converter equipment and improving the input power factor performance have become key issues to be tackled in green power electronics technology.
[0003] Traditional power factor correction circuits generally use Boost circuits, which have complex circuit control, higher output voltage than input voltage, and difficult to achieve electrical isolation between input and output. In order to achieve electrical isolation between input and output, BOOST circuits are currently usually used to shape the input current. The output voltage of the previous stage is the voltage of the energy storage capacitor. Regardless of whether the capacitor is large or small, there is a double line frequency ripple. Then, isolation and conversion are achieved through a DC-DC converter to obtain a high-precision DC output voltage. However, it uses a two-stage circuit, which is complex, costly, low overall efficiency, and large in size. Some scholars use a power factor correction circuit composed of a flyback circuit, but it must work in the intermittent state of the inductor current, has large electromagnetic interference, and is not suitable for high-power occasions.
[0004] Sepic circuit has unique advantages in power factor correction. Since its front stage is similar to Boost converter, it can ensure the continuity of input current and reduce electromagnetic interference. Its output stage is similar to flyback circuit, which is easy to achieve electrical isolation. A single Sepic circuit can naturally achieve power factor by working in the discontinuous current state. The discontinuous here refers to the discontinuous current on the diode, while the current on the input boost inductor is continuous. For this reason, Sepic-based PFC circuits are receiving more and more attention. Traditional Sepic-type PFC circuits are only suitable for low-power occasions. As the output power increases, its output current will be distorted. In addition, traditional Sepic-type PFC usually uses a rectifier bridge to rectify the input voltage, which increases the conduction loss and makes it difficult to improve the efficiency of traditional Sepic-type PFC circuits.
[0005] Therefore, it is necessary to provide a Sepic power factor correction converter with complete protection function, high circuit reliability, simple software control and low cost. Summary of the invention
[0006] The invention discloses a Sepic power factor correction converter, which relates to the technical field of power factor correction converters for power supplies, and in particular to a high-efficiency bridgeless interleaved Sepic power factor correction converter, which can effectively solve the technical problems involved in the background technology.
[0007] To achieve the above object, the technical solution of the present invention is:
[0008] A Sepic power factor correction converter includes a conversion circuit, wherein the conversion circuit includes a port L and a port N, wherein the port L is connected to one end of a capacitor C201 and one end of an inductor L21, the other end of the capacitor C201 is connected to one end of a capacitor C244, the other end of the inductor L21 is connected to the drain of a MOS tube Q15, the negative end of a diode D57 and one end of a capacitor C277, the other end of the capacitor C277 is connected to one end of the inductor L17 and a pin 1 of a transformer T4, the source of the MOS tube Q15 is connected to the source of the MOS tube Q14, the positive end of the diode D57, the positive end of the diode D58, the other end of the inductor L17, one end of the inductor L20, the pin 2 of the transformer T4 and the pin 3 of the transformer T4, and the port N is connected to the drain of a MOS tube Q15, the negative end of a diode D57 and the positive end of a diode D58, the other end of the inductor L17, the positive end of a diode D58 ... Port N is connected to the other end of the capacitor C244, the drain of the MOS tube Q14, the negative end of the diode D58 and one end of the capacitor C246, the other end of the capacitor C246 is connected to the other end of the inductor L20 and the pin 4 of the transformer T4; the pin 5 of the transformer T4 is connected to the source of the MOS tube Q17, the pin 6 of the transformer T4 is connected to the pin 7 of the transformer T4, one end of the capacitor C305 and the port GND, the pin 8 of the transformer T4 is connected to the source of the MOS tube Q16, the drain of the MOS tube Q16 is connected to the drain of the MOS tube Q17, one end of the capacitor C301 and the port VOUT+, the other end of the capacitor C301 is connected to the other end of the capacitor C305, and the converter also includes a compensation circuit.
[0009] A high-efficiency bridgeless interleaved Sepic power factor correction converter is disclosed, which is suitable for charging piles or some intelligent power distribution systems. It includes two isolated Sepic power factor correction conversion circuits and a ramp compensation circuit. The ramp compensation technology is used to solve the zero-crossing distortion problem of the low input voltage of the converter. At the same time, the converter adopts interleaved parallel connection to improve the output power of the converter and reduce the output voltage and current ripple of the converter. The high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit includes an input energy storage capacitor, an energy storage inductor, a top-to-top MOS tube, an energy storage capacitor, an energy storage inductor, and a transformer connected in sequence; a rectifier MOS tube, and the ramp compensation circuit includes an error amplifier, a comparator, and a compensation network; the high-efficiency bridgeless interleaved Sepic power factor correction converter can ensure the continuity of the input current, thereby reducing electromagnetic interference. Since this converter is only a single-stage circuit, its efficiency can be as high as 98%, its input current harmonics can be less than 3%, and the PF value is as high as 0.99 or above; the advantage of its output being easy to electrically isolate makes the entire converter safe and stable; it is suitable for charging piles or some intelligent power distribution systems, with complete protection functions, high circuit reliability, simple software control, and low cost.
[0010] As a preferred improvement of the present invention: there are multiple conversion circuits, and the ports L of the multiple conversion circuits are connected to each other, the ports N are connected to each other, the ports VOUT+ are connected to each other, and the ports GND are connected to each other.
[0011] As a preferred improvement of the present invention: the number of the conversion circuits is two, and the two conversion circuits work alternately at 180 degrees.
[0012] As a preferred improvement of the present invention: the port L and the port N are connected to the mains, and the port VOUT+ is connected to a load or a battery.
[0013] As a preferred improvement of the present invention: the gate of the MOS tube Q16 is connected to one end of the resistor R245 and one end of the resistor R242, the other end of the resistor R245 is connected to the positive end of the diode D63, the other end of the resistor R242 and the negative end of the diode D63 are connected to port DRV_4; the gate of the MOS tube Q17 is connected to one end of the resistor R236 and one end of the resistor R237, the other end of the resistor R237 is connected to the positive end of the diode D61, the other end of the resistor R236 and the negative end of the diode D61 are connected to port DRV_3; the gate of the MOS tube Q15 is connected to one end of the resistor R250, one end of the resistor R256 and one end of the resistor R257, the resistor The other end of R257 is connected to the source of the MOS tube Q15, the other end of the resistor R256 is connected to the positive end of the diode D21, the other end of the resistor R250 and the negative end of the diode D21 are connected to port DRV_1; the gate of the MOS tube Q14 is connected to one end of the resistor R258, one end of the resistor R259 and one end of the resistor R260, the other end of the resistor R260 is connected to the drain of the MOS tube Q14, the other end of the resistor R259 is connected to the positive end of the diode D24, the other end of the resistor R258 and the negative end of the diode D24 are connected to port DRV_1; the port DRV_1, the port DRV_3 and the port DRV_4 are connected to the controller.
[0014] As a preferred improvement of the present invention: the converter also includes a compensation circuit, which includes a port V_COMP, the port V_COMP is connected to pin 1 of the comparator U27, the pin 2 of the comparator U27 is connected to port CS, the pin 3 of the comparator U27 is connected to pin 1 of the amplifier U26, one end of the capacitor C252 and one end of the capacitor C247, the other end of the capacitor C252 is connected to one end of the resistor R261, the pin 2 of the amplifier U26 is connected to the other end of the resistor R261, the other end of the capacitor C247, one end of the resistor R249, one end of the resistor R248 and one end of the capacitor C250, the other end of the resistor R249 is connected to port GND, the other end of the capacitor C250 is connected to one end of the resistor R262, the other end of the resistor R248 and the other end of the resistor R262 are connected to port VOUT+, the pin 3 of the amplifier U26 is connected to one end of the capacitor C245 and port VREF, and the other end of the capacitor C245 is connected to port GND.
[0015] As a preferred improvement of the present invention: the port VREF is connected to a 1.5V power supply.
[0016] As a preferred improvement of the present invention: the port V_COMP is connected to the feedback pin of the controller, the port CS is connected to the reference pin of the controller, and the controller is connected to the gates of MOS tube Q14, MOS tube Q15, MOS tube Q16 and MOS tube Q17.
[0017] The beneficial effects of the present invention are as follows:
[0018] The invention has a simple structure and stable operation, and discloses a high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit, whose efficiency can be as high as 98%, whose input current harmonics can be less than 3%, and whose PF value is as high as above 0.99; whose output is easy to electrically isolate, making the whole converter safe and stable; and which is suitable for charging piles or some intelligent power distribution systems, and has perfect protection functions, high circuit reliability, simple software control and low cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:
[0020] Figure 1 is a schematic diagram of a conversion circuit of the present invention;
[0021] Figure 2 is a schematic diagram of a compensation circuit of the present invention;
[0022] Figure 3 It is a structural diagram of embodiment 1. DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the present invention will be described clearly and completely below in combination with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0024] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0025] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0026] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0027] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.
[0028] See also Figure 1As shown, the present invention provides a Sepic power factor correction converter, including a conversion circuit, a compensation circuit and a controller, the conversion circuit includes a port L and a port N, the port L is connected to one end of a capacitor C201 and one end of an inductor L21, the other end of the capacitor C201 is connected to one end of a capacitor C244, the other end of the inductor L21 is connected to the drain of a MOS tube Q15, the negative end of a diode D57 and one end of a capacitor C277, the other end of the capacitor C277 is connected to one end of an inductor L17 and a pin 1 of a transformer T4, the source of the MOS tube Q15 is connected to the source of the MOS tube Q14, the positive end of the diode D57, the positive end of the diode D58, the other end of the inductor L17, one end of the inductor L20, the pin 2 of the transformer T4 and the pin 3 of the transformer T4, the port N is connected to the capacitor C The other end of the inductor L20 is connected to the drain of the MOS tube Q14, the negative end of the diode D58 and one end of the capacitor C246, the other end of the capacitor C246 is connected to the other end of the inductor L20 and the pin 4 of the transformer T4; the pin 5 of the transformer T4 is connected to the source of the MOS tube Q17, the pin 6 of the transformer T4 is connected to the pin 7 of the transformer T4, one end of the capacitor C305 and the port GND, the pin 8 of the transformer T4 is connected to the source of the MOS tube Q16, the drain of the MOS tube Q16 is connected to the drain of the MOS tube Q17, one end of the capacitor C301 and the port VOUT+, the other end of the capacitor C301 is connected to the other end of the capacitor C305, the port L and the port N are connected to the mains, the port VOUT+ is connected to the load or the battery, and the compensation circuit is connected to the port VOUT+.
[0029] Disclosed is a high-efficiency bridgeless interleaved Sepic power factor correction converter, comprising a Sepic power factor correction conversion circuit and a ramp compensation circuit. The ramp compensation technology is used to solve the zero-crossing distortion problem of the low input voltage of the converter. At the same time, the converter adopts interleaved parallel connection to improve the output power of the converter and reduce the output voltage and current ripple of the converter. The high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit is connected in sequence with an input energy storage capacitor, an energy storage inductor, a top-to-top MOS tube, an energy storage capacitor, an energy storage inductor, and a transformer; a rectifier MOS tube, and the ramp compensation circuit include an error amplifier, a comparator, and a compensation network. The converter efficiency can be as high as 98%, the input current harmonics can be less than 3%, and the PF value is as high as 0.99 or above.
[0030] As an implementation manner, the gate of the MOS tube Q16 is connected to one end of a resistor R245 and one end of a resistor R242, the other end of the resistor R245 is connected to the positive end of a diode D63, the other end of the resistor R242 and the negative end of the diode D63 are connected to port DRV_4; the gate of the MOS tube Q17 is connected to one end of a resistor R236 and one end of a resistor R237, the other end of the resistor R237 is connected to the positive end of a diode D61, the other end of the resistor R236 and the negative end of the diode D61 are connected to port DRV_3; the gate of the MOS tube Q15 is connected to one end of a resistor R250, one end of a resistor R256 and one end of a resistor R257, the resistor R2 The other end of 57 is connected to the source of the MOS tube Q15, the other end of the resistor R256 is connected to the positive end of the diode D21, the other end of the resistor R250 and the negative end of the diode D21 are connected to port DRV_1; the gate of the MOS tube Q14 is connected to one end of the resistor R258, one end of the resistor R259 and one end of the resistor R260, the other end of the resistor R260 is connected to the drain of the MOS tube Q14, the other end of the resistor R259 is connected to the positive end of the diode D24, the other end of the resistor R258 and the negative end of the diode D24 are connected to port DRV_1; the port DRV_1, the port DRV_3 and the port DRV_4 are connected to the controller. It should be further explained that the use of other components to achieve the above effects should all belong to the inventive concept of the present invention and should belong to the protection scope of the present invention.
[0031] See also Figure 2As shown, the converter also includes a compensation circuit, which includes a port V_COMP, the port V_COMP is connected to pin 1 of the comparator U27, the pin 2 of the comparator U27 is connected to port CS, the pin 3 of the comparator U27 is connected to pin 1 of the amplifier U26, one end of the capacitor C252 and one end of the capacitor C247, the other end of the capacitor C252 is connected to one end of the resistor R261, the pin 2 of the amplifier U26 is connected to the other end of the resistor R261, the other end of the capacitor C247, one end of the resistor R249, one end of the resistor R248 and one end of the capacitor C250, the resistor R249 The other end is connected to port GND, the other end of the capacitor C250 is connected to one end of the resistor R262, the other end of the resistor R248 and the other end of the resistor R262 are connected to port VOUT+, the pin 3 of the amplifier U26 is connected to one end of the capacitor C245 and port VREF, the other end of the capacitor C245 is connected to port GND, the port VREF is connected to a 1.5V power supply, the port V_COMP is connected to the feedback pin of the controller, the port CS is connected to the reference pin of the controller, and the controller is connected to the gate of the MOS tube Q14, the gate of the MOS tube Q15, the gate of the MOS tube Q16, and the gate of the MOS tube Q17. It should be further explained that the use of other components to achieve the above effects should all belong to the inventive concept of the present invention and should belong to the protection scope of the present invention.
[0032] As an implementation manner, the number of the conversion circuits is multiple, and the ports L of the multiple conversion circuits are connected to each other, the ports N are connected to each other, the ports VOUT+ are connected to each other, and the ports GND are connected to each other. Preferably, the number of the conversion circuits is two, and the two conversion circuits work 180 degrees staggered.
[0033] Embodiment 1
[0034] See also Figure 3 As shown, a high-efficiency bridgeless interleaved Sepic power factor correction converter includes two isolated Sepic power factor correction conversion circuits and a ramp compensation circuit. The ramp compensation technology is used to solve the zero-crossing distortion problem of the low input voltage of the converter. At the same time, this converter adopts interleaved parallel connection to improve the output power of the converter and reduce the output voltage and current ripple of the converter. The converter efficiency can be as high as 98%, the input current harmonics can be less than 3%, and the PF value is as high as 0.99 or above.
[0035] The first path of the bridgeless interleaved Sepic power factor correction conversion circuit described above includes a first energy storage inductor L21, a first MOS tube Q15, a second MOS tube Q14, a first diode D57, a second diode D58, a first energy storage capacitor C277, a second energy storage capacitor C246, a second energy storage inductor L17, a third energy storage inductor L20, and a primary side of a first transformer T4. The energy storage inductor L21 is connected to the input live wire and the drain of the first MOS tube Q15 and the cathode of the first diode D57 and the first energy storage capacitor C277. The source of the first MOS tube Q15 and the first diode D57 are connected to the cathode of the first diode D57. The anode of the second MOS tube Q14 is connected to the source of the second MOS tube Q14 and the anode of the second diode D58, the drain of the second MOS tube Q14 is connected to the input neutral line and the cathode of the second diode D58 is connected to the second energy storage capacitor C246 and the first energy storage capacitor C277, the second energy storage capacitor C246 is respectively connected to the second energy storage inductor L17, the third energy storage inductor L20 and the primary side of the first transformer; the center tap of the primary side of the first transformer is connected to the second energy storage inductor L17, the midpoint of the third energy storage inductor L20 and the source of the first MOS tube Q15, the gates of the first MOS tube Q15 and the second MOS tube Q14 are all connected to the drive circuit.
[0036] The first path of the high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit described above includes a first transformer secondary side, a third MOS tube Q16, and a fourth MOS tube Q17. The first transformer secondary side is connected to the source of the third MOS tube Q16 and the fourth MOS tube Q17. The center tap of the first transformer secondary side is connected to the output ground. The drains of the third MOS tube Q16 and the fifth MOS tube Q17 are connected and connected to the output positive terminal.
[0037] The second path of the high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit described above includes a fourth energy storage inductor L18, a fifth MOS tube Q8, a sixth MOS tube Q9, a third diode D35, a fourth diode D36, a third energy storage capacitor C203, a fourth energy storage capacitor C208, a fifth energy storage inductor L22, a sixth energy storage inductor L23, and the primary side of the second transformer T1. The energy storage inductor L18 is connected to the input live wire and the drain of the fifth MOS tube Q18 and the cathode of the third diode D35 and the third energy storage capacitor C203. The source of the fifth MOS tube Q18 and the third diode D The anode of 35 is connected to the source of the sixth MOS tube Q9 and the anode of the fourth diode D36, the drain of the sixth MOS tube Q9 is connected to the input neutral line and the cathode of the fourth diode D36 is connected to the fourth energy storage capacitor C208 and the third energy storage capacitor C203, the second energy storage capacitor C208 is respectively connected to the fifth energy storage inductor L22, the sixth energy storage inductor L23 is connected to the primary side of the second transformer, the primary side of the second transformer, the center tap is connected to the fifth energy storage inductor L22, the midpoint of the sixth energy storage inductor L23 and the source of the fifth MOS tube Q8, the fifth MOS tube Q15 and the sixth MOS tube Q9 are all connected to the drive circuit.
[0038] The second path of the high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit described above includes a second transformer secondary side, a seventh MOS transistor Q10, and an eighth MOS transistor Q11. The second transformer secondary side is connected to the source of the seventh MOS transistor Q10 and the eighth MOS transistor Q11. The center tap of the second transformer secondary side is connected to the output ground. The drains of the seventh MOS transistor Q10 and the eighth MOS transistor Q11 are connected and connected to the output positive terminal.
[0039] The above-mentioned high-efficiency bridgeless interleaved Sepic power factor correction converter ramp compensation circuit includes an error amplifier U26, a comparator U27 and its compensation network C252, R261, C247, a sampling voltage divider resistor R248 connected to the output positive and feedforward R262, C250 composed of a differential circuit and the error amplifier U26 pin 2, R249 is grounded, and the error amplifier U26 pin 3 is connected to a given reference, the error amplifier U26 output pin 1 is connected to the comparator U27 pin 3, and the comparator U27 pin 2 is connected to the sawtooth wave generator CS (generated by the chip), and the output of the comparator U27 controls the driving duty cycle of the MOS tube.
[0040] Working principle:
[0041] See also Figure 1 When the input AC is in the positive half cycle, the first MOS tube of this converter drives DRV_1 to a high position, Q15 and Q14 are turned on at the same time, the L-L21-Q15-Q14-N circuit and the C277-Q15-L17 circuit are turned on at the same time, and L21 and L17 store energy. When the MOS tube drives DRV_1 to a low position, the L-L21-C277-T4A-Q14(D58)-N circuit and the L17-T4-A circuit are turned on at the same time. At this time, the input and L21 supply power to the load and charge C277 at the same time. The energy stored in C277 is transferred to L17 when driving DRV_1 to a high position. At this time, the secondary transformer T4 discharges to the load through Q16. At this time, turning on the Q16 drive realizes the synchronous rectification function, which can improve the efficiency of the converter.
[0042] When the input AC negative half cycle occurs, the MOS tube drives DRV_1 to a high position, Q15 and Q14 are turned on at the same time, the N-Q14-Q15-L21-L circuit and the C246-Q14-L20 circuit are turned on at the same time, and L21 and L20 store energy. When the MOS tube drives DRV_1 to a low position, the N-C246-T4A-Q15(D57)-L21-L circuit and the L20-T4-A circuit are turned on at the same time. At this time, the input and L21 supply power to the load and charge C246 at the same time. The energy stored in C246 is transferred to L20 when driving DRV_1 to a high position. At this time, the secondary transformer T4 discharges to the load through Q17. At this time, turning on the Q17 drive realizes the synchronous rectification function, which can improve the efficiency of the converter.
[0043] See also Figure 2 The voltage compensator shown in the figure is a high-efficiency bridgeless interleaved Sepic power factor correction converter. The output voltage is processed by the voltage-dividing resistors R248, R249 and the feedforward R262, C250, and then connected to the inverting end of the error amplifier to be compared with the given reference. The error signal is generated after passing through the compensation network of C247, C252, and R261, and is compared with the sawtooth wave CS to output the MOS tube duty cycle driving pulse.
[0044] When the second path of this converter is running, it only works 180 degrees staggered with the first path. The principle is exactly the same and will not be repeated here.
[0045] The above-mentioned high-efficiency bridgeless interleaved Sepic power factor correction converter can ensure the continuity of input current, thereby reducing electromagnetic interference. Since this converter is only a single-stage circuit, its efficiency can be as high as 98%, its input current harmonics can be less than 3%, and the PF value is as high as 0.99 or above. The advantage of its easy electrical isolation of the output makes the entire converter safe and stable, suitable for charging piles or some intelligent power distribution systems, and has perfect protection functions, high circuit reliability, simple software control, low cost and other advantages.
[0046] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the embodiments. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.
Claims
1. A Sepic power factor correction converter, characterized in that: The invention comprises a conversion circuit, wherein the conversion circuit comprises a port L and a port N, wherein the port L is connected to one end of a capacitor C201 and one end of an inductor L21, the other end of the capacitor C201 is connected to one end of a capacitor C244, the other end of the inductor L21 is connected to the drain of a MOS transistor Q15, the negative end of a diode D57 and one end of a capacitor C277, the other end of the capacitor C277 is connected to one end of the inductor L17 and a pin 1 of a transformer T4, the source of the MOS transistor Q15 is connected to the source of a MOS transistor Q14, the positive end of the diode D57, the positive end of a diode D58, the other end of the inductor L17, one end of the inductor L20, a pin 2 of the transformer T4 and a pin 3 of the transformer T4, the port N is connected to the other end of the capacitor C244, the drain of the MOS transistor Q14, the negative end of the diode D58 and one end of a capacitor C246, the other end of the capacitor C246 is connected to the other end of the inductor L20 and a pin 4 of the transformer T4; Pin 5 of the transformer T4 is connected to the source of the MOS tube Q17, pin 6 of the transformer T4 is connected to pin 7 of the transformer T4, one end of the capacitor C305 and port GND, pin 8 of the transformer T4 is connected to the source of the MOS tube Q16, the drain of the MOS tube Q16 is connected to the drain of the MOS tube Q17, one end of the capacitor C301 and port VOUT+, and the other end of the capacitor C301 is connected to the other end of the capacitor C305.
2. A Sepic power factor correction converter according to claim 1, characterized in that: There are multiple conversion circuits, and the ports L of the multiple conversion circuits are connected to each other, the ports N are connected to each other, the ports VOUT+ are connected to each other, and the ports GND are connected to each other.
3. A Sepic power factor correction converter according to claim 2, characterized in that: There are two conversion circuits, and the two conversion circuits work alternately at 180 degrees.
4. A Sepic power factor correction converter according to claim 1, characterized in that: The port L and the port N are connected to the mains, and the port VOUT+ is connected to a load or a battery.
5. The Sepic power factor correction converter according to claim 1, characterized in that: The gate of the MOS transistor Q16 is connected to one end of a resistor R245 and one end of a resistor R242, the other end of the resistor R245 is connected to the positive end of a diode D63, and the other end of the resistor R242 and the negative end of the diode D63 are connected to a port DRV_4; The gate of the MOS transistor Q17 is connected to one end of a resistor R236 and one end of a resistor R237, the other end of the resistor R237 is connected to the positive end of a diode D61, and the other end of the resistor R236 and the negative end of the diode D61 are connected to a port DRV_3; The gate of the MOS transistor Q15 is connected to one end of the resistor R250, one end of the resistor R256 and one end of the resistor R257, the other end of the resistor R257 is connected to the source of the MOS transistor Q15, the other end of the resistor R256 is connected to the positive end of the diode D21, and the other end of the resistor R250 and the negative end of the diode D21 are connected to the port DRV_1; The gate of the MOS transistor Q14 is connected to one end of a resistor R258, one end of a resistor R259 and one end of a resistor R260, the other end of the resistor R260 is connected to the drain of the MOS transistor Q14, the other end of the resistor R259 is connected to the positive end of a diode D24, and the other end of the resistor R258 and the negative end of the diode D24 are connected to a port DRV_1; The port DRV_1 , the port DRV_3 , and the port DRV_4 are connected to a controller.
6. A Sepic power factor correction converter according to claim 1, characterized in that: The converter also includes a compensation circuit, which includes a port V_COMP, wherein the port V_COMP is connected to pin 1 of the comparator U27, the pin 2 of the comparator U27 is connected to port CS, the pin 3 of the comparator U27 is connected to pin 1 of the amplifier U26, one end of the capacitor C252 and one end of the capacitor C247, the other end of the capacitor C252 is connected to one end of the resistor R261, the pin 2 of the amplifier U26 is connected to the other end of the resistor R261, the other end of the capacitor C247, one end of the resistor R249, one end of the resistor R248 and one end of the capacitor C250, the other end of the resistor R249 is connected to port GND, the other end of the capacitor C250 is connected to one end of the resistor R262, the other end of the resistor R248 and the other end of the resistor R262 are connected to port VOUT+, the pin 3 of the amplifier U26 is connected to one end of the capacitor C245 and port VREF, and the other end of the capacitor C245 is connected to port GND.
7. A Sepic power factor correction converter according to claim 6, characterized in that: The port VREF is connected to a 1.5V power supply.
8. The Sepic power factor correction converter according to claim 6, characterized in that: The port V_COMP is connected to the feedback pin of the controller, the port CS is connected to the reference pin of the controller, and the controller is connected to the gates of the MOS transistors Q14, Q15, Q16 and Q17.