DC-DC converter and display device including the same

Abstract

The invention provides a DC-DC converter and a display device including the same. A DC-DC converter according to an embodiment includes: a voltage generation unit configured to generate an output voltage by changing an input voltage; a first mode driving unit that generates a first switching signal in order to drive the voltage generating unit in a first mode; a second mode driving unit that generates a second switching signal in order to drive the voltage generating unit in a second mode; a third mode driving unit that generates a third switching signal in order to drive the voltage generating unit in a third mode; and a mode control unit for determining an output load of the voltage generation unit using the first switching signal, the second switching signal, and the third switching signal, the first switching signal, the second switching signal, and the third switching signal are supplied to the voltage generation unit in accordance with the output load.

Description

Technical Field

[0001] The present invention relates to a DC-DC converter and a display device including the same. Background Art

[0002] The display device includes a DC-DC converter that converts an input voltage supplied from the outside to generate a high potential power supply and a low potential power supply required for driving pixels.

[0003] The DC-DC converter can be driven in various driving modes (for example, PWM mode and PFM mode) according to the output load (or load current). In order to sense the output load of the DC-DC converter, a sensing circuit including a resistor may be added, which may increase power consumption and mounting area. Summary of the invention

[0004] An object of the present invention is to provide a DC-DC converter and a display device including the same, which can use multiple switching signals corresponding to the driving mode of the DC-DC converter to determine the output load (or load current) and control the driving mode of the DC-DC converter corresponding to the determined output load.

[0005] A DC-DC converter according to an embodiment of the present invention comprises: a voltage generating unit for generating an output voltage by changing an input voltage; a first mode driving unit for generating a first switching signal in order to drive the voltage generating unit in a first mode; a second mode driving unit for generating a second switching signal in order to drive the voltage generating unit in a second mode; a third mode driving unit for generating a third switching signal in order to drive the voltage generating unit in a third mode; and a mode control unit for determining an output load of the voltage generating unit by using the first switching signal, the second switching signal and the third switching signal, and supplying any one of the first switching signal, the second switching signal and the third switching signal to the voltage generating unit in accordance with the output load.

[0006] According to an embodiment, the first mode is a PWM mode, the second mode is a PFM mode, and the third mode is a ULP mode generating the third switching signal having a lower frequency than the second switching signal.

[0007] According to an embodiment, the DC-DC converter further comprises: a first switch connected between the first mode driving unit and the voltage generating unit, and turned on when a first control signal of selection is supplied from the mode control unit; a second switch connected between the second mode driving unit and the voltage generating unit, and turned on when a second control signal of selection is supplied from the mode control unit; and a third switch connected between the third mode driving unit and the voltage generating unit, and turned on when a third control signal of selection is supplied from the mode control unit.

[0008] According to an embodiment, the voltage generating unit comprises: the voltage generating unit comprises: an inductor connected between an input terminal for supplying the input voltage and an output terminal for outputting the output voltage; a first transistor connected between the input terminal and the inductor, turned on during the on time of the first switching signal, the second switching signal or the third switching signal and turned off during the off time of the first switching signal, the second switching signal or the third switching signal; a second transistor connected between a common node between the first transistor and the inductor and a base potential; a driving unit receiving any one of the first switching signal, the second switching signal and the third switching signal, controlling the on and off of the first transistor and the second transistor; and a plurality of resistors connected in series between the output terminal and the base potential, outputting a feedback voltage from a node between the plurality of resistors.

[0009] According to an embodiment, the mode control unit includes: an on-time check unit, which checks the on-time interval of the first switch signal to generate an on-time control signal; an off-time check unit, which checks the off-time interval of the second switch signal to generate an off-time control signal; a first counter, which counts the second switch signal to generate a first counting signal when the feedback voltage is set to a voltage lower than a reference voltage in the second mode driving unit; and a second counter, which counts the third switch signal to generate a second counting signal when the feedback voltage is set to a voltage lower than the reference voltage in the third mode driving unit.

[0010] According to an embodiment, the on-time check unit is driven when the voltage generating unit is driven in the first mode, and when the on-time interval of the first switching signal is longer than a predetermined time, an enabling on-time control signal is generated, and when the on-time interval of the first switching signal is shorter than the predetermined time, a disabling on-time control signal is generated.

[0011] According to an embodiment, when the on-time check unit generates the enabled on-time control signal, the voltage generating unit maintains the first mode of driving, and when the on-time check unit generates the disabled on-time control signal, the voltage generating unit is driven in the second mode.

[0012] According to an embodiment, the on-time check unit includes: a current supply unit, which generates multiple currents; a current control unit, which includes multiple resistors for distributing the input voltage; a current selection unit, which controls the amount of current supplied from the current supply unit to the first node corresponding to the control of the current control unit; a reset unit, which is used to initialize the first node corresponding to the inversion of the first switching signal; and a on-time control signal generating unit, which is used to generate the on-time control signal corresponding to the voltage of the first node.

[0013] According to an embodiment, the current supply unit includes: a control transistor located between a first power supply and a current source; and a plurality of mirror transistors connected to the control transistor to form a current mirror and supplying the plurality of currents to the current selection unit.

[0014] According to an embodiment, the current control unit comprises: the plurality of resistors connected in series to distribute the input voltage, distributing the input voltage to generate a plurality of distributed voltages; and a plurality of comparators, comparing any one of the plurality of distributed voltages with a comparison voltage, and outputting control voltages corresponding to the comparison results respectively.

[0015] According to an embodiment, the current selection unit includes: a plurality of current transistors connected between the first node and any one of the plurality of mirror transistors, turned on and off according to the control voltage output from any one of the plurality of comparators, and any one of the plurality of currents supplied from the current selection unit is directly supplied to the first node.

[0016] According to an embodiment, the reset unit includes: a first transistor and a second transistor, which are connected in series between a first power supply and the basic potential; a third transistor, which is connected between the first node and the basic potential, and a gate electrode is connected to a common node of the first transistor and the second transistor, the first transistor is set to P type, the second transistor is set to N type, and the third transistor is set to N type, and the inverted first switching signal is supplied to the gate electrodes of the first transistor and the second transistor.

[0017] According to an embodiment, the on-time control signal generating unit includes: a first capacitor connected between the first node and the base potential; a first transmission gate connected between the first node and the second node; a second capacitor connected between the second node and the base potential; a second transmission gate connected between the second node and a third node; a third capacitor connected between the third node and the base potential; and a comparator for comparing the voltages of the first reference power supply and the third node to output the on-time control signal.

[0018] According to an embodiment, the first transmission gate electrically connects the first node and the second node corresponding to the first switching signal and the inverted first switching signal, and the second transmission gate electrically connects the second node and the third node while alternately turning on and off the first transmission gate corresponding to the inverted first switching signal and the first switching signal.

[0019] According to an embodiment, the disconnection time check unit is driven when the voltage generating unit is driven in the second mode, and when the disconnection time interval of the second switch signal is less than a predetermined time, an enabled disconnection time control signal is generated, and when the disconnection time interval of the second switch signal is greater than the predetermined time, a disabled disconnection time control signal is generated.

[0020] According to an embodiment, when the disconnection time checking unit generates the enabled disconnection time control signal, the voltage generating unit maintains the driving of the second mode, and when the disconnection time checking unit generates the disabled disconnection time control signal, the voltage generating unit is driven in the third mode.

[0021] According to an embodiment, the disconnection time check unit includes: a current supply unit, which supplies a predetermined current to a first node; a reset unit, which initializes the first node corresponding to a first switching signal; a control unit, which controls the voltage of the second node corresponding to the voltage of the first node; and a first output unit, which is used to generate the disconnection time control signal corresponding to the voltage of the second node.

[0022] According to an embodiment, the current supply unit includes: a control transistor connected between a first power supply and a current source; and a mirror transistor connected to the control transistor to form a current mirror to supply the predetermined current to the first node.

[0023] According to an embodiment, the control unit comprises: a fourth transistor connected between the second node and the basic potential, and a gate electrode connected to the first node; a fifth transistor connected between the first power supply and the second node, and a gate electrode connected to the gate electrode of the control transistor; and a first capacitor connected between the first node and the basic potential.

[0024] According to an embodiment, the reset unit includes: a first transistor and a second transistor, which are connected in series between a first power supply and the basic potential; and a third transistor, which is connected between the first node and the basic potential, and the gate electrode is connected to a common node of the first transistor and the second transistor, the first transistor is set to P type, the second transistor is set to N type, and the third transistor is set to N type, and the second switching signal is supplied to the gate electrodes of the first transistor and the second transistor.

[0025] According to an embodiment, the first output unit includes: a sixth transistor and a seventh transistor, which are connected in series between the first power supply and the basic potential, and the gate electrode is connected to the second node; and a D flip-flop, the clock input unit is connected to the common node between the sixth transistor and the seventh transistor, the QB terminal of the D flip-flop is connected to the D terminal, the signal output from the Q terminal of the D flip-flop is the disconnection time control signal, the sixth transistor is P type, and the seventh transistor is N type.

[0026] According to an embodiment, the off-time checking unit further includes: a second output unit for generating an on-time changing signal in accordance with a voltage of the first node in order to control the on-time of the second switching signal.

[0027] According to an embodiment, the second output unit includes: a first transmission gate connected between the first node and a fourth node; a second capacitor connected between the fourth node and the base potential; a second transmission gate connected between the fourth node and a second output terminal outputting the on-time change signal; and a third capacitor connected between the second output terminal and the base potential.

[0028] According to an embodiment, the first counter is driven when the voltage generating unit is driven in the second mode, and a disabled first count signal is generated when the feedback voltage is set to a voltage higher than the reference voltage in the second mode driving unit, and an enabled first count signal is generated when the second switching signal is repeatedly supplied more than a predetermined number of times while the feedback voltage is set to a voltage lower than the reference voltage in the second mode driving unit.

[0029] According to an embodiment, when the disabled first count signal is generated, the voltage generating section maintains the driving in the second mode, and when the enabled first count signal is generated, the voltage generating section is driven in the first mode.

[0030] According to an embodiment, the first counter comprises: a k-bit (k is a natural number) counter; an output unit, which generates the first count signal of the selection when a count signal is input from the k-bit counter; a first logic gate, which inputs a power signal set to a high voltage and the second control signal when the output voltage of the DC-DC converter is set to be above the target voltage; a second logic gate, which is used to invert the output of the first logic gate; and a third logic gate, which performs a logic operation on the output of the second logic gate and the second switch signal to supply them to the k-bit counter.

[0031] According to an embodiment, the first logic gate is a NAND gate, the second logic gate is a NOT gate, the third logic gate is an AND gate, and the output of the first logic gate is input as a reset signal of the k-bit counter.

[0032] According to an embodiment, the output section is configured as a D flip-flop, and the output section is initialized when a reset signal is supplied from the mode control section.

[0033] According to an embodiment, the second counter is driven when the voltage generating unit is driven in the third mode, generates a disabled second counting signal when the feedback voltage is set to a voltage higher than the reference voltage in the third mode driving unit, and generates an enabled second counting signal when the third switching signal is repeatedly supplied more than a predetermined number of times while the feedback voltage is set to a voltage lower than the reference voltage in the third mode driving unit.

[0034] According to an embodiment, when the disabled second count signal is generated, the voltage generating section maintains the driving in the third mode, and when the enabled second count signal is generated, the voltage generating section is driven in the second mode.

[0035] According to an embodiment, the second counter comprises: a p-bit (p is a natural number) counter; an output unit, which generates the selected second counting signal when a counting signal is input from the p-bit counter; a first logic gate, which inputs a power signal set to a high voltage and the third control signal when the output voltage of the DC-DC converter is set to be above a target voltage; a second logic gate, which is used to invert the output of the first logic gate; and a third logic gate, which performs a logic operation on the output of the second logic gate and the third switch signal to supply them to the p-bit counter.

[0036] According to an embodiment, the first logic gate is a NAND gate, the second logic gate is a NOT gate, the third logic gate is an AND gate, and the output of the first logic gate is input as a reset signal of the p-bit counter.

[0037] According to an embodiment, the output section is configured as a D flip-flop, and the output section is initialized when a reset signal is supplied from the mode control section.

[0038] According to an embodiment, the mode control unit further includes: a first logic gate, which performs a logic operation on the on-time control signal and the first counting signal; a second logic gate, which performs a logic operation on a signal that inverts a power signal set to a high voltage when the output voltage of the DC-DC converter is set to be above a target voltage, and the output of the first logic gate; a third logic gate, which performs a logic operation on the output of the second logic gate and the off-time control signal; a fourth logic gate, which performs a logic operation on the output of the third logic gate and the second counting signal; a fifth logic gate, which performs a logic operation on the inverted off-time control signal and the output of the second logic gate; and a sixth logic gate, which inverts the off-time control signal to generate an inverted off-time control signal.

[0039] According to an embodiment, the first logic gate, the second logic gate, and the fourth logic gate are set as OR gates, the third logic gate and the fifth logic gate are set as NOR gates, and the sixth logic gate is set as a NOT gate.

[0040] According to an embodiment, the output of the second logic gate is the first control signal, the output of the fourth logic gate is the second control signal, and the output of the fifth logic gate is the third control signal.

[0041] A display device according to an embodiment of the present invention comprises: a plurality of pixels connected to a plurality of scanning lines and a plurality of data lines; and a power supply unit, which includes a DC-DC converter for supplying required driving power to the plurality of pixels, and the DC-DC converter includes: a voltage generating unit for generating an output voltage by changing an input voltage; a first mode driving unit for generating a first switching signal for driving the voltage generating unit in a first mode; a second mode driving unit for generating a second switching signal for driving the voltage generating unit in a second mode; a third mode driving unit for generating a third switching signal for driving the voltage generating unit in a third mode; and a mode control unit for determining an output load of the voltage generating unit using the first switching signal, the second switching signal and the third switching signal, and supplying any one of the first switching signal, the second switching signal and the third switching signal to the voltage generating unit corresponding to the output load.

[0042] The subject of the present invention is not limited to the subject mentioned above, and those skilled in the art should be able to understand other technical subjects not mentioned through the following description.

[0043] (Effects of the Invention)

[0044] According to the DC-DC converter and the display device including the same according to the embodiment of the present invention, the output load can be determined using the switching signal generated by the mode driving unit, and the driving mode of the DC-DC converter can be controlled corresponding to the determined output load.

[0045] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be made without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a diagram schematically showing a PWM mode of a DC-DC converter.

[0047] Figure 2 It is a diagram schematically showing the PFM mode of the DC-DC converter.

[0048] Figure 3 It is a diagram showing a DC-DC converter according to an embodiment of the present invention.

[0049] Figure 4 Yes means Figure 3 A diagram of an embodiment of a mode control unit is shown.

[0050] Figure 5 Yes means Figure 4 FIG. 1 is a diagram of an embodiment of an on-time check unit shown in FIG.

[0051] Figure 6 Yes means Figure 5 1 is a waveform diagram of an embodiment of a driving method of an on-time check unit.

[0052] Figure 7 Yes means Figure 4 FIG. 1 is a diagram of an embodiment of a disconnection time check unit shown in FIG.

[0053] Figure 8 Yes means Figure 7 The waveform diagram of the embodiment of the driving method of the off-time check unit is shown.

[0054] Fig. 9 Yes means Figure 4 A diagram of an embodiment of a first counter is shown.

[0055] Fig.10 Yes means Figure 4 A diagram of an embodiment of a second counter is shown.

[0056] Fig.11 Detailed description of the invention The following is a flowchart showing the operation process of the DC-DC converter according to the embodiment of the present invention.

[0057] Fig.12 Yes means Figure 3 FIG. 1 is a diagram of an embodiment of a first mode driving unit shown in FIG.

[0058] Fig.13 Yes means Figure 3 FIG. 1 is a diagram of an embodiment of a second mode driving unit shown in FIG.

[0059] Fig.14 Yes means Figure 3 FIG. 1 is a diagram of an embodiment of a third mode driving unit shown in FIG.

[0060] Fig.15 Yes means Figure 4 FIG. 5 is a graph showing a simulation of the power consumption of the on-time check section.

[0061] Fig.16 Yes means Figure 4 A graph showing a simulation of the power consumption of the off-time check section is shown.

[0062] Fig.17 This is a simulation waveform diagram showing a process in which the DC-DC converter changes from the first mode to the second mode.

[0063] Fig.18 It is a simulation waveform diagram showing a process in which the DC-DC converter changes from the second mode to the first mode.

[0064] Fig.19 It is a simulation waveform diagram showing a process in which the DC-DC converter changes from the second mode to the third mode.

[0065] Fig. 20 : is a simulation waveform diagram showing a process in which the DC-DC converter changes from the third mode to the second mode.

[0066] Fig.21 It is a diagram showing a display device according to an embodiment of the present invention.

[0067] Fig. 22 This is a diagram for explaining a pixel according to an embodiment of the present invention.

[0068] Fig.23 It is used to illustrate Fig. 22 A diagram of an exemplary driving method for a pixel is shown.

[0069] Fig.24 It is a diagram showing an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0070] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in various different ways and is not limited to the embodiments described herein.

[0071] In order to clearly explain the present invention, parts not related to the explanation are omitted, and the same or similar components are given the same symbols throughout the specification. Therefore, the symbols explained above can be used in other drawings.

[0072] In addition, the size and thickness of each structure shown in the figure are arbitrarily shown for the convenience of explanation, and therefore the present invention is not necessarily limited to the case shown in the figure. In the drawings, the thickness is exaggerated to clearly show each layer and region.

[0073] Furthermore, the expression "same" in the description may mean "substantially the same". That is, it may mean the sameness to a degree that can be recognized by a person skilled in the art. Other expressions may be expressions in which "substantially" is omitted.

[0074] Some embodiments are described in the accompanying drawings associated with functional blocks, units and / or modules. Those skilled in the art should be able to understand that such blocks, units and / or modules can be physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, wiring connections and other electronic circuits. It can be formed using semiconductor-based manufacturing technology or other manufacturing technology. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, software can be used to program or control, so as to perform various functions discussed in the present invention, and optionally, it can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by dedicated hardware, or it can be implemented by a combination of dedicated hardware that performs some functions and processors that perform other functions (for example, more than one programmed microprocessor and related circuits). In addition, in some embodiments, blocks, units and / or modules can also be physically separated into more than two separate blocks, units and / or modules that interact with each other without exceeding the scope of the concept of the present invention. In addition, in some embodiments, blocks, units and / or modules can also be physically combined into more complex blocks, units and / or modules without exceeding the scope of the concept of the present invention.

[0075] The term "connection" between two components may refer to both electrical connection and physical connection, but is not necessarily limited to this. For example, the term "connection" used with reference to a circuit diagram may refer to electrical connection, and the term "connection" used with reference to a cross-sectional view or a plan view may refer to physical connection.

[0076] Although the terms "first" and "second" are used to describe various components, these components are certainly not limited to these terms. These terms are used only to distinguish one component from other components. Therefore, the first component mentioned below can also be the second component within the technical concept of the present invention.

[0077] On the other hand, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms. In addition, each embodiment disclosed below can be implemented alone, or can be combined with at least one other embodiment to implement in combination.

[0078] Figure 1 FIG. 1 is a diagram schematically showing a PWM mode of a DC-DC converter. Figure 1 In the example, ILOAD may represent an output load (or a load current). For example, when the DC-DC converter is included in a display device, different output loads (or load currents) ILOAD may be set corresponding to an image displayed on the display device.

[0079] exist Figure 1 In the example, IL may represent an inductor included in the DC-DC converter (as an example, Figure 3 The current of L). Figure 1 In , VPWM may represent a switching signal for controlling the current supplied to the inductor. Figure 1 In the figure, it is assumed that current is supplied to the inductor in high level intervals Ton1 and Ton2 of the switching signal VPWM (ie, on-time intervals), and that current is not supplied to the inductor in low level intervals Toff1 and Toff2 (ie, off-time intervals).

[0080] Reference Figure 1 The PWM mode may include a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM).

[0081] In the PWM mode, the switching signal VPWM may operate at a fixed switching frequency, but the duty ratio of the switching signal VPWM may be adjusted in accordance with the CCM mode and the DCM mode.

[0082] When the current IL of the inductor exceeds "0" (or the base potential GND), the DC-DC converter can be driven in CCM mode. In the CCM mode, the switching signal VPWM can be repeatedly turned on and off at a certain cycle. Thus, the output voltage of the DC-DC can be generated while the current IL of the inductor increases and decreases at a certain cycle. In the CCM mode as described above, the current IL of the inductor can change continuously at a certain cycle. The CCM mode can minimize output ripples and thus can have high output stability.

[0083] When the current IL of the inductor includes "0" (or the base potential GND), the DC-DC converter can be driven in the DCM mode. In the DCM mode, a plurality of transistors (for example, Figure 3 The peak value of the inductor current IL in the DCM mode can be smaller than the peak value of the inductor current IL in the CCM mode. Compared with the CCM mode, the duty cycle (i.e., the on-time interval) of the switching signal VPWM in the DCM mode can be smaller. Compared with the CCM mode, the DCM mode can have low power consumption.

[0084] When the DC-DC converter is driven in PWM mode, it is driven in CCM when the output load ILOAD is high, and it is driven in DCM when the output load ILOAD is small.

[0085] On the other hand, as described above, when driving in DCM mode, the on-time interval of the switching signal VPWM is reduced, so that the output load (or load current) ILOAD can be determined by using the on-time interval of the switching signal VPWM.

[0086] Figure 2 Schematically shows the PFM mode of a DC-DC converter. Figure 2 In , ILOAD can represent the output load. Figure 2 In the example, VFB can represent the distributed output voltage Vout (refer to Figure 3 ) to generate the feedback voltage. Figure 2 In FIG. 1 , it is assumed that a current is supplied to the inductor in a high-level interval Ton3 of the switching signal VPFM, and that a current is not supplied to the inductor in low-level intervals Toff3 and Toff4 .

[0087] Reference Figure 2In the PFM mode, the frequency of the switching signal VPFM can be changed in accordance with the output load ILOAD. As an example, when the output load ILOAD is relatively low, the frequency of the switching signal VPFM can be reduced to reduce the number of transistors (as an example, Figure 3 When the frequency of the switching signal VPFM is changed in accordance with the output load ILOAD, power consumption can be reduced.

[0088] In the PFM mode, the off intervals Toff3 and Toff4 during which no current is supplied to the inductor are set differently according to the output load ILOAD. Therefore, in the PFM mode, the output load (or load current level) ILOAD can be determined by using the off intervals Toff3 and Toff4 (ie, the off time intervals).

[0089] Figure 3 It is a diagram showing a DC-DC converter according to an embodiment of the present invention.

[0090] Reference Figure 3 The DC-DC converter 300 according to an embodiment of the present invention may include a voltage generating unit 310 , a first mode driving unit 320 , a second mode driving unit 330 , a third mode driving unit 340 and a mode control unit 350 .

[0091] The voltage generating unit 310 can generate the output voltage Vout using the input voltage Vin. As an example, the voltage generating unit 310 can generate the output voltage Vout in response to any one of the first switching signal VPWM supplied from the first mode driving unit 320, the second switching signal VPFM supplied from the second mode driving unit 330, and the third switching signal VULP supplied from the third mode driving unit 340 (any one of VPWM, VPFM, and VULP).

[0092] The voltage generating unit 310 may be a step-down converter and may include transistors Mp and Mn, a driving unit 312 , an inductor L, a capacitor Cout, an output resistor RL, distribution resistors R1 and R2 , and a zero current sensing unit ZCD.

[0093] The first transistor Mp may be connected between the input terminal 311 and the first node N1. Here, the meaning of connection may include the meaning of electrical connection. The first transistor Mp may be turned on in the gating interval of the switch signal supplied from the driving unit 312. The first transistor Mp may be formed by a P-type transistor, whereby the gating interval of the switch signal may be a low voltage supply interval. If the first transistor Mp is turned on, current may be supplied to the inductor L.

[0094] The second transistor Mn may be connected between the first node N1 and the base potential GND. The second transistor Mn may be turned on in a prohibited interval of the switch signal supplied from the driving unit 312. The second transistor Mn may be formed by an N-type transistor, whereby the prohibited interval of the switch signal may be a high voltage supply interval. If the second transistor Mn is turned on, no current is supplied to the inductor L.

[0095] The driving unit 312 can drive the first transistor Mp and the second transistor Mn using any one of the first switching signal VPWM, the second switching signal VPFM and the third switching signal VULP. The driving unit 312 can include a plurality of inverters, etc. to stably turn on and off the first transistor Mp and the second transistor Mn.

[0096] The inductor L is connected between the first node N1 and the second node N2. The inductor L stores energy corresponding to the current supplied from the input voltage Vin when the first transistor Mp is turned on. The inductor L can supply current to the output terminal 314 based on the stored energy when the second transistor Mn is turned on. At this time, since the current is not supplied to the inductor L from the input voltage Vin, the current supplied from the inductor L to the output terminal 314 can gradually decrease. That is, the voltage (or current) supplied to the output terminal 314 by the inductor L can be controlled by the frequency and / or duty cycle of the switching signal supplied from the driving unit 312 to the transistors Mp and Mn.

[0097] The capacitor Cout may be connected between the second node N2 (ie, the output terminal 314) and the base potential GND. The capacitor Cout may store the voltage of the second node N2.

[0098] The output resistor RL may be connected between the second node N2 (ie, the output terminal 314) and the base potential GND. The output resistor RL may equivalently represent the output load ILOAD.

[0099] The distribution resistors R1 and R2 may be connected in series between the second node N2 (i.e., the output terminal 314) and the base potential GND. The distribution resistors R1 and R2 may distribute the output voltage Vout to generate the feedback voltage VFB. As an example, the feedback voltage VFB may be output from a common node between the distribution resistors R1 and R2. The feedback voltage VFB may be supplied to the mode driving units 320, 330, and 340.

[0100] The zero current sensing unit ZCD can sense the moment when the current of the inductor L is 0. The zero current sensing unit ZCD can sense the moment when the current of the inductor L is 0, thereby supplying a zero signal to the driving unit 312. When the driving unit 312 inputs a zero signal, the second transistor Mn is turned off, thereby preventing the reverse current from flowing.

[0101] The first mode driving unit 320 receives the feedback voltage VFB and the reference voltage Vref. As described above, the first mode driving unit 320 can output a first switching signal VPWM corresponding to the PWM method. When the output load ILOAD is greater than a relatively large first load, the first switching signal VPWM can be supplied to the driving unit 312 through the mode control unit 350. The first mode driving unit 320 that generates the first switching signal VPWM can be any one of various currently known structures.

[0102] The second mode driving unit 330 receives the feedback voltage VFB and the reference voltage Vref. The second mode driving unit 330 as described above can output a second switching signal VPFM corresponding to the PFM mode. When the output load ILOAD is less than the first load and greater than the second load (the second load is a load lower than the first load), the second switching signal VPFM can be supplied to the driving unit 312 through the mode control unit 350. The second mode driving unit 330 that generates the second switching signal VPFM can be any one of various currently known structures.

[0103] The third mode driving unit 340 receives the feedback voltage VFB and the reference voltage Vref. As described above, the third mode driving unit 340 can output a third switching signal VULP corresponding to the ULP (Ultra Low Power) mode. When the output load ILOAD is lower than the second load, the third switching signal VULP can be supplied to the driving unit 312 through the mode control unit 350. The third mode driving unit 340 that generates the third switching signal VULP can be any one of various currently known structures.

[0104] The ULP method may be a method of supplying a gated third switching signal VULP to increase the output voltage Vout only when the output voltage Vout drops below a certain voltage. Here, the gated third switching signal VULP may indicate a voltage (for example, a low voltage) that turns on the first transistor Mp.

[0105] The PWM method is a method that can stably generate an output voltage Vout, and can be applied to a case with a high output load ILOAD. The PFM method is a method that can reduce power consumption compared to the PWM method, and can be applied to a case with an output load ILOAD of approximately an intermediate degree. Compared to the second switching signal VPFM, the third switching signal VULP generated in the ULP method can have a lower frequency, so the ULP method can be applied to a case with a low output load ILOAD.

[0106] The mode control unit 350 may receive the switching signals VPWM, VPFM, and VULP, and use the switching signals VPWM, VPFM, and VULP to determine the output load ILOAD. The mode control unit 350 may supply any one of the first switching signal VPWM, the second switching signal VPFM, and the third switching signal VULP to the driving unit 312 in accordance with the determined output load ILOAD.

[0107] To this end, the DC-DC converter 300 may include a first switch SW1 , a second switch SW2 , and a third switch SW3 .

[0108] The first switch SW1 may be connected between the driver 312 and the first mode driver 320. The first switch SW1 may be turned on when the first control signal CS1 (eg, a high voltage) is supplied from the mode control unit 350 to electrically connect the driver 312 and the first mode driver 320.

[0109] The second switch SW2 may be connected between the driving section 312 and the second mode driving section 330. The second switch SW2 may be turned on when the gated second control signal CS2 (eg, a high voltage) is supplied from the mode control section 350, thereby electrically connecting the driving section 312 and the second mode driving section 330.

[0110] The third switch SW3 may be connected between the driving unit 312 and the third mode driving unit 340. The third switch SW3 may be turned on when the third control signal CS3 (eg, a high voltage) is supplied from the mode control unit 350, thereby electrically connecting the driving unit 312 and the third mode driving unit 340.

[0111] Figure 4 Yes means Figure 3 A diagram of an embodiment of a mode control unit is shown.

[0112] Reference Figure 4 The mode control unit 350 according to an embodiment of the present invention may include an on-time check unit 360 , an off-time check unit 390 , a first counter 370 , a second counter 380 , and a control unit 352 .

[0113] The control unit 352 can generate the first control signal CS1, the second control signal CS2 and the third control signal CS3 using the on-time control signal ONT, the off-time control signal OFT, the first count signal PPC and the second count signal UPC. To this end, the control unit 352 can include logic gates 352a, 354, 356, 357, 358 and 359.

[0114] The first logic gate 352a may receive the on-time control signal ONT from the on-time check unit 360 and the first count signal PPC from the first counter 370. The first logic gate 352a may be set as an OR gate to perform an OR operation on the on-time control signal ONT and the first count signal PPC to output the result.

[0115] The second logic gate 354 may receive the output signal of the first logic gate 352a and the inverted power signal POK. Here, if the output voltage of the DC-DC converter 300 is set to a certain target voltage or above, the power signal POK may be set to a high voltage. That is, the power signal POK may be set to a high voltage when the DC-DC converter 300 is normally driven. The power signal POK may be inverted (i.e., logic "0") and supplied to the second logic gate 354.

[0116] The second logic gate 354 may be configured as an OR gate to perform an OR operation on the output signal of the first logic gate 352a and the inverted power signal POK and output the resultant signal. The output signal of the second logic gate 354 may be supplied to the first output terminal 351 as the first control signal CS1.

[0117] The third logic gate 356 may receive the off time control signal OFT from the off time check unit 390 and the first control signal CS1 from the second logic gate 354. The third logic gate 356 may be configured as a NOR gate to perform a NOR operation on the off time control signal OFT and the first control signal CS1 and output the result.

[0118] The fourth logic gate 358 may receive the second count signal UPC from the second counter 380 and the output signal of the third logic gate 356. The fourth logic gate 358 may be set as an OR gate to perform an OR operation on the second count signal UPC and the output signal of the third logic gate 356. The output signal of the fourth logic gate 358 may be supplied to the second output terminal 353 as the second control signal CS2.

[0119] The fifth logic gate 359 may receive the inverted disconnection time control signal and the first control signal CS1. The fifth logic gate 359 may be set as a NOR gate to perform a NOR operation on the inverted disconnection time control signal and the first control signal CS1 to output. The output signal of the fifth logic gate 359 may be supplied to the third output terminal 355 as the third control signal CS3.

[0120] The sixth logic gate 357 may invert the off-time control signal OFT to supply it to the fifth logic gate 359. The sixth logic gate 357 is set as a NOT gate.

[0121] The on-time check unit 360 may be driven when the voltage generating unit 310 operates in the first mode (PWM mode). The on-time check unit 360 may determine the gating interval (or on-time interval) of the first switching signal VPWM. The on-time check unit 360 as described above may use the on-time interval to determine the load of the output load ILOAD. As an example, the on-time check unit 360 may use the on-time interval to determine whether the output load ILOAD is lower than the first load.

[0122] In the case of PWM driving, when the output load ILOAD decreases, the on-time interval can be reduced. The on-time check unit 360 can determine that the output load ILOAD is lower than the first load when the on-time interval decreases. As an example, the on-time check unit 360 can generate an enabling on-time control signal ONT when the on-time interval of the first switching signal VPWM is longer than a predetermined time, and generate a disabling on-time control signal ONT when the on-time interval of the first switching signal VPWM is shorter than a predetermined time.

[0123] The on-time check unit 360 may output an enabled on-time control signal ONT (for example, a high voltage) (or corresponding to a logic "1") when it is determined that the output load ILOAD is greater than the first load, and may output a disabled on-time control signal ONT (for example, a low voltage) (or corresponding to a logic "0") when it is determined that the output load ILOAD is less than the first load.

[0124] The disconnection time check unit 390 may be driven when the voltage generating unit 310 operates in the second mode (PFM mode). The disconnection time check unit 390 may determine the prohibited interval (or disconnection time interval) of the second switching signal VPFM. The disconnection time check unit 390 as described above may use the disconnection time interval to determine the load of the output load ILOAD. As an example, the disconnection time check unit 390 may use the disconnection time interval to determine whether the output load ILOAD is lower than the second load.

[0125] The disconnection time check unit 390 may generate an enabled disconnection time control signal OFT when the disconnection time interval of the second switch signal VPFM is less than a predetermined time, and may generate a disabled disconnection time control signal OFT when the disconnection time interval of the second switch signal VPFM is longer than a predetermined time.

[0126] In the case of driving in the PFM mode, when the output load ILOAD decreases, the off-time interval may increase. The off-time check unit 390 may determine that the output load ILOAD is lower than the second load when the off-time interval increases.

[0127] The disconnection time check unit 390 can output an enabled disconnection time control signal OFT (as an example, a low voltage) (or corresponding to a logic "0") when it is judged that the output load ILOAD is greater than the second load, and output a disabled disconnection time control signal OFT (as an example, a high voltage) (or corresponding to a logic "1") when it is judged that the output load ILOAD is less than the second load.

[0128] The first counter 370 may be driven when the voltage generating unit 310 operates in the second mode (PFM mode). The first counter 370 may count the second switching signal VPFM when the feedback voltage VFB is lower than the reference voltage Vref in the second mode driving unit 330. Here, the situation where the feedback voltage VFB is lower than the reference voltage Vref may indicate a situation where the output voltage Vout should be increased. The first counter 370 may include a k-bit counter (k is a natural number) and outputs a gated first count signal PPC (or a high voltage) when the second switching signal VPFM is repeated k times or more (as an example, k+1 times). Here, the gated first count signal PPC may correspond to a logic "1". The first counter 370 may output a disabled first count signal PPC (or a low voltage) (as an example, corresponding to a logic "0") during a period when the gated first count signal PPC is not output.

[0129] The second counter 380 may be driven when the voltage generating unit 310 operates in the third mode (ULP mode). The second counter 380 may count the third switch signal VULP when the feedback voltage VFB is lower than the reference voltage Vref in the third mode driving unit 340. Here, the situation where the feedback voltage VFB is lower than the reference voltage Vref may indicate a situation where the output voltage Vout should be increased. The second counter 380 may include a p-bit counter (p is a natural number less than k) and outputs a gated second count signal UPC (or a high voltage) when the third switch signal VULP is repeated p times or more (as an example, p+1 times). Here, the gated second count signal UPC may correspond to a logic "1". The second counter 380 may output a disabled second count signal UPC (or a low voltage) (as an example, corresponding to a logic "0") during a period when the gated second count signal UPC is not output.

[0130] Figure 5 Yes means Figure 4 FIG. 1 is a diagram of an embodiment of an on-time check unit shown in FIG.

[0131] Reference Figure 5, the on-time check unit 360 can use the on-time interval of the first switching signal VPWM to determine the output load ILOAD. When the on-time interval of the first switching signal VPWM becomes shorter, the on-time check unit 360 can determine that the output load ILOAD decreases, and output a prohibited on-time control signal ONT corresponding to the change in the driving method. When the prohibited on-time control signal ONT is output, the driving method of the DC-DC converter 300 can be changed from PWM to PFM.

[0132] The on-time check section 360 may include a current supply section 362 , a current control section 363 , a current selection section 364 , a reset section 365 , and an on-time control signal generation section 361 .

[0133] The current supply unit 362 can supply a plurality of currents I1, I2, ..., I6, I7, and I8 to the current selection unit 364. To this end, the current supply unit 362 can include a control transistor Mco located between the first power supply VDD and the current source Iref, and mirror transistors MM1, MM2, ..., MM6, MM7, and MM8 connected to the control transistor Mco to form a current mirror.

[0134] The control transistor Mco may be connected as a diode to supply a current corresponding to the current source Iref. The gate electrodes of the mirror transistors MM1 to MM8 may be electrically connected to the gate electrode of the control transistor Mco. The mirror transistors MM1 to MM8 may respectively supply currents I1 to I8 corresponding to the amount of current flowing out of the control transistor Mco to the current selection unit 364.

[0135] The current control unit 363 may include a voltage distribution unit 367 for distributing an input voltage Vin and comparators Com1, Com2, ..., Com6, Com7 for controlling the current selection unit 364 in accordance with a comparison result between the output voltages V1, V2, ..., V6, V7 of the voltage distribution unit 367 and the comparison voltage VC.

[0136] The voltage distribution unit 367 may include a plurality of resistors, and distribute the input voltage Vin to generate output voltages V1 to V7. The comparators Com1 to Com7 compare the output voltage (any one of V1 to V7) supplied to themselves with the comparison voltage VC, and output a control voltage corresponding to the comparison result, thereby controlling the conduction and cutoff of the current transistors MC1, MC2, ..., MC6, and MC7 included in the current selection unit 364. The current control unit 363 may control the amount of current supplied to the first node N11 corresponding to the magnitude of the input voltage Vin.

[0137] The current selection unit 364 may include current transistors MC1 to MC7 connected between each of the mirror transistors MM1 to MM7 and the first node N11. The gate electrodes of each of the current transistors MC1 to MC7 may be connected to any one of the comparators Com1 to Com7. The current transistors MC1 to MC7 may be turned on and off in accordance with the voltage supplied from the comparators Com1 to Com7. Furthermore, the current I8 supplied from the eighth mirror transistor MM8 may be directly supplied to the first node N11 without passing through the current transistor.

[0138] The reset unit 365 can be connected to the inverted first switching signal / VPWM (shown as ) correspondingly initializes the first node N11. To this end, the reset unit 365 may include a first transistor M11, a second transistor M12, and a third transistor M13.

[0139] The first transistor M11 and the second transistor M12 are connected in series between the first power supply VDD and the base potential GND. The inverted first switching signal / VPWM can be supplied to the gate electrodes of the first transistor M11 and the second transistor M12. The first transistor M11 and the second transistor M12 can be alternately turned on corresponding to the inverted first switching signal / VPWM. To this end, the first transistor M11 can be set to a P type, and the second transistor M12 can be set to an N type.

[0140] The third transistor M13 may be connected between the first node N11 and the base potential GND. In addition, the gate electrode of the third transistor M13 may be connected to a common node of the first transistor M11 and the second transistor M12. The third transistor M13 as described above may be set to an N-type, turned on when the first transistor M11 is turned on, and turned off when the second transistor M12 is turned on.

[0141] The on-time control signal generating section 361 may include transmission gates 366 and 368 , an output section 369 , a first capacitor C1 , a second capacitor C2 , and a third capacitor C3 .

[0142] The first capacitor C1 may be connected between the first node N11 and the base potential GND. The first capacitor C1 as described above may store the voltage of the first node N11.

[0143] The second capacitor C2 may be connected between the second node N12 and the base potential GND. The second capacitor C2 as described above may store the voltage of the second node N12.

[0144] The third capacitor C3 may be connected between the third node N13 and the base potential GND. The third capacitor C3 as described above may store the voltage of the third node N13.

[0145] The first transmission gate 366 may be connected between the first node N11 and the second node N12. The first transmission gate 366 as described above controls the electrical connection between the first node N11 and the second node N12 in response to the first switching signal VPWM and the inverted first switching signal / VPWM. To this end, the first transmission gate 366 may include a fourth transistor M14 and a fifth transistor M15.

[0146] The fourth transistor M14 may be connected between the first node N11 and the second node N12 and turned on and off in response to the first switching signal VPWM. The fifth transistor M15 may be connected between the first node N11 and the second node N12 and turned on and off in response to the inverted first switching signal / VPWM.

[0147] The second transmission gate 368 may be connected between the second node N12 and the third node N13. The second transmission gate 368 as described above controls the electrical connection between the second node N12 and the third node N13 corresponding to the inverted first switching signal / VPWM and the first switching signal VPWM. To this end, the second transmission gate 368 may include a sixth transistor M16 and a seventh transistor M17.

[0148] The sixth transistor M16 may be connected between the second node N12 and the third node N13, and may be turned on and off corresponding to the inverted first switching signal / VPWM. The seventh transistor M17 may be connected between the second node N12 and the third node N13, and may be turned on and off corresponding to the first switching signal VPWM. The second transmission gate 368 may be turned on and off alternately with the first transmission gate 366.

[0149] The output unit 369 may compare the voltage of the third node N13 with the first reference voltage Vref1 and generate an on-time control signal according to the comparison result. The output unit 369 may be composed of a comparator.

[0150] Figure 6 Yes means Figure 5 1 is a waveform diagram of an embodiment of a driving method of an on-time check unit.

[0151] Reference Figure 6 In the high level interval of the inverted first switch signal / VPWM, the first transistor M11 is turned off and the second transistor M12 is turned on. If the second transistor M12 is turned on, the third transistor M13 is turned off.

[0152] Therefore, in the high level interval of the inverted first switching signal / VPWM, the voltage of the first node N11 rises in accordance with the current supplied from the current supply unit 362 via the current selection unit 364. In addition, in the high level interval of the inverted first switching signal / VPWM, the first transmission gate 366 is turned on (M14 and M15 are turned on), so that the voltage of the first node N11 is supplied to the second node N12.

[0153] In the low level interval of the inverted first switch signal / VPWM, the first transistor M11 is turned on and the second transistor M12 is turned off. If the first transistor M11 is turned on, the third transistor M13 is turned on. If the third transistor M13 is turned on, the voltage VN11 of the first node N11 is initialized to the basic potential GND.

[0154] In the low level interval of the inverted first switching signal / VPWM, the second transmission gate 368 may be turned on (M16 and M17 are turned on), so that the voltage VN12 of the second node N12 may be supplied to the third node N13.

[0155] The inverted first switching signal / VPWM may be supplied in a pulse form, whereby the voltage VN13 of the third node N13 may rise to a peak voltage higher than the first reference voltage Vref1. Here, when the voltage VN13 of the third node N13 is set to be higher than the first reference voltage Vref1, it is determined that a high output load ILOAD is applied, whereby the output unit 369 may output a gated on-time control signal ONT (i.e., a high voltage or logic "1").

[0156] When the gated on-time control signal ONT is output from the on-time check section 360, a signal of "1" is output from the first logic gate 352a and the second logic gate 354. At this time, the gated first control signal CS1 (or high voltage) can be output from the first output terminal 351. In addition, the disabled second control signal CS2 (or low voltage) can be output from the second output terminal 353, and the disabled third control signal CS3 (or low voltage) can be output from the third output terminal 355.

[0157] Therefore, when the gated on-time control signal ONT is output from the on-time check section 360 , the first switch SW1 is turned on, and the driving section 312 may be driven in the first mode (ie, PWM mode).

[0158] On the other hand, when the output load ILOAD is reduced, the on-time interval of the first switching signal VPWM (i.e., the high voltage interval of the inverted switching signal / VPWM) can be shortened. When the on-time interval of the first switching signal VPWM is shortened, the voltage VN12 of the second node N12 can be discharged to the first node N11, and the voltage VN13 of the third node N13 can be discharged to the second node N12.

[0159] Thus, the voltage VN13 of the third node N13 may be set lower than the first reference voltage Vref1. When the voltage VN13 of the third node N13 is set lower than the first reference voltage Vref1, the output part 369 may output the disabled on-time control signal ONT (ie, low voltage or logic '0').

[0160] When the disabled on-time control signal ONT is output from the on-time check unit 360 , a signal of logic “0” is output from the first logic gate 352 a and the second logic gate 354 . At this time, the disabled first control signal CS1 may be output from the first output terminal 351 .

[0161] On the other hand, during the period when the on-time check section 360 is driven, the off-time check section 390 is not driven, and thus a logic "0" can be output. Therefore, when the first control signal CS1 of prohibition is output from the first output terminal 351, a signal of logic "1" is output from the third logic gate 356, and a signal of logic "1" is output from the fourth logic gate 358 accordingly. At this time, the second control signal CS2 of selection can be output from the second output terminal 353. The third control signal CS3 (or low voltage) of prohibition can be output to the third output terminal 355.

[0162] If the second control signal CS2 is output, the second switch SW2 is turned on, and the driving unit 312 can be driven in the second mode (i.e., PFM mode). That is, in the embodiment of the present invention, when driving in PWM mode, when the output load ILOAD decreases, the driving mode can be changed from PWM to PFM.

[0163] Figure 7 Yes means Figure 4 FIG. 1 is a diagram of an embodiment of a disconnection time check unit shown in FIG.

[0164] Reference Figure 7, the disconnection time check unit 390 can use the disconnection time interval of the second switch signal VPFM to determine the output load ILOAD. When the disconnection time interval of the second switch signal VPFM becomes longer, the disconnection time check unit 390 can determine that the output load ILOAD is reduced, and can output a prohibited disconnection time control signal OFT corresponding to the change of the driving method. When the prohibited disconnection time control signal OFT is output, the driving method of the DC-DC converter 300 can be changed from PFM to ULP.

[0165] The OFF time check unit 390 may include a current supply unit 392 , a reset unit 394 , a control unit 396 , a first output unit 398 , and a second output unit 399 .

[0166] The current supply unit 392 may supply the current I to the control unit 396. To this end, the current supply unit 392 may include a control transistor Mcoa located between the first power source VDD and the current source Iref and a mirror transistor MM1a connected to the control transistor Mcoa to form a current mirror.

[0167] The control transistor Mcoa is connected as a diode and can supply a current corresponding to the current source Iref. The gate electrode of the mirror transistor MM1a can be electrically connected to the gate electrode of the control transistor Mcoa. The mirror transistor MM1a can supply a current I corresponding to the amount of current flowing out of the control transistor Mcoa to the control unit 396.

[0168] The control unit 396 controls the voltage of the second node N22 in accordance with the amount of current supplied from the current supply unit 392 (ie, in accordance with the voltage of the first node N21). To this end, the control unit 396 may include a fourth transistor M24, a fifth transistor M25, and a first capacitor C11.

[0169] The fourth transistor M24 is connected between the second node N22 and the base potential GND. In addition, the gate electrode of the fourth transistor M24 is connected to the first node N21. The fourth transistor M24 can be turned on and off corresponding to the voltage of the first node N21 while controlling the voltage of the second node N22.

[0170] The fifth transistor M25 is connected between the first power supply VDD and the second node N22. In addition, the gate electrode of the fifth transistor M25 is connected to the gate electrode of the control transistor Mcoa. That is, the fifth transistor M25 can be connected to the control transistor Mcoa as a current mirror to supply a predetermined current to the second node N22. Therefore, when the fourth transistor M24 is set to the off state, the second node N22 can be set to the voltage of the first power supply VDD.

[0171] The first capacitor C11 may store the voltage of the first node N21.

[0172] The reset unit 394 may initialize the first node N21 in response to the second switching signal VPFM. To this end, the reset unit 394 may include a first transistor M21, a second transistor M22, and a third transistor M23.

[0173] The first transistor M21 and the second transistor M22 are connected in series between the first power supply VDD and the base potential GND. The second switching signal VPFM can be supplied to the gate electrodes of the first transistor M21 and the second transistor M22. The first transistor M21 and the second transistor M22 can be alternately turned on corresponding to the second switching signal VPFM. To this end, the first transistor M21 can be set to a P type, and the second transistor M22 can be set to an N type.

[0174] The third transistor M23 may be connected between the first node N21 and the base potential GND. In addition, the gate electrode of the third transistor M23 may be connected to the common node of the first transistor M21 and the second transistor M22. The third transistor M23 as described above may be set to an N-type, turned on when the first transistor M21 is turned on, and turned off when the second transistor M22 is turned on.

[0175] The first output unit 398 may generate an off-time control signal OFT corresponding to the voltage of the second node N22. To this end, the first output unit 398 may include a sixth transistor M26, a seventh transistor M27, and a flip-flop DFF.

[0176] The sixth transistor M26 and the seventh transistor M27 may be connected in series between the first power supply VDD and the base potential GND. In addition, the gate electrodes of the sixth transistor M26 and the seventh transistor M27 may be connected to the second node N22. The sixth transistor M26 and the seventh transistor M27 as described above may invert the voltage of the second node N22 to transfer it to the third node N23. That is, the sixth transistor M26 and the seventh transistor M27 may constitute an inverter. To this end, the sixth transistor M26 may be formed by a P-type, and the seventh transistor M27 may be formed by an N-type.

[0177] The flip-flop DFF may output a disconnection time control signal OFT to the first output terminal 391 in correspondence with the voltage of the third node N23 which is the common node of the sixth transistor M26 and the seventh transistor M27. As an example, when the voltage of the third node N23 is set to a high voltage (i.e., logic "1"), the flip-flop DFF may output a disabled disconnection time control signal OFT, and when the voltage of the third node N23 is set to a low voltage (i.e., logic "0"), the flip-flop DFF may output an enabled disconnection time control signal OFT.

[0178] The flip-flop DFF may be composed of a D flip-flop. A clock input portion of the flip-flop DFF may be connected to the third node N23, and a Q terminal of the flip-flop DFF may be connected to the first output terminal 391. In addition, a QB terminal of the flip-flop DFF may be connected to the D terminal.

[0179] The second output unit 399 can generate an on-time change signal AOT corresponding to the voltage of the first node N21. When driving in the PFM mode, the on-time change signal AOT can be used to change the on-time of the second switching signal VPFM. In the embodiment of the present invention, the second output unit 399 can also be removed.

[0180] The second output unit 399 may include transmission gates 3991 and 3992 , a second capacitor C12 , and a third capacitor C13 .

[0181] The second capacitor C12 may be connected between the fourth node N24 and the base potential GND. The second capacitor C12 as described above may store the voltage of the fourth node N24.

[0182] The third capacitor C13 may be connected between the second output terminal 393 and the base potential GND. The third capacitor C13 as described above may store the voltage of the second output terminal 393.

[0183] The first transmission gate 3991 may be connected between the first node N21 and the fourth node N24. The first transmission gate 3991 as described above is connected to the second switching signal VPFM and the inverted second switching signal / VPFM (shown as ) correspondingly controls the electrical connection between the first node N21 and the fourth node N24. To this end, the first transmission gate 3991 may include a first transistor M31 and a second transistor M32.

[0184] The first transistor M31 may be connected between the first node N21 and the fourth node N24 and turned on and off corresponding to the inverted second switching signal / VPFM. The second transistor M32 may be connected between the first node N21 and the fourth node N24 and turned on and off corresponding to the second switching signal VPFM.

[0185] The second transmission gate 3992 may be connected between the fourth node N24 and the second output terminal 393. The second transmission gate 3992 as described above controls the electrical connection between the fourth node N24 and the second output terminal 393 in accordance with the inverted second switching signal / VPFM and the second switching signal VPFM. To this end, the second transmission gate 3992 may include a third transistor M33 and a fourth transistor M34.

[0186] The third transistor M33 may be connected between the fourth node N24 and the second output terminal 393 and turned on and off corresponding to the second switching signal VPFM. The fourth transistor M34 may be connected between the fourth node N24 and the second output terminal 393 and turned on and off corresponding to the inverted second switching signal / VPFM.

[0187] Figure 8 Yes means Figure 7 The waveform diagram of the embodiment of the driving method of the off-time check unit is shown.

[0188] Reference Figure 8 In the low level interval of the second switch signal VPFM, the first transistor M21 is turned on and the second transistor M22 is turned off. If the first transistor M21 is turned on, the voltage of the first power supply VDD is supplied to the gate electrode of the third transistor M23, thereby turning on the third transistor M23. If the third transistor M23 is turned on, the voltage VN21 of the first node N21 is initialized to the basic potential GND.

[0189] In the high level interval of the second switch signal VPFM, the first transistor M21 is turned off and the second transistor M22 is turned on. When the second transistor M22 is turned on, the voltage of the base potential GND is supplied to the gate electrode of the third transistor M23, thereby turning off the third transistor M23.

[0190] At this time, the voltage VN21 of the first node N21 may gradually rise due to the current I supplied from the current supply unit 392. Here, when the off time interval (i.e., high level interval) of the second switch signal VPFM is set to be short (i.e., when the output load ILOAD is high), the voltage VN21 of the first node N21 is set to be lower than the threshold voltage Vth_M24 of the fourth transistor M24, and thus the fourth transistor M24 maintains the off state.

[0191] If the fourth transistor M24 is turned off, the second node N22 is set to the voltage of the first power supply VDD, and thus the seventh transistor M27 is set to the on state. If the seventh transistor M27 is set to the on state, the clock signal is not supplied to the flip-flop DFF (or the voltage VN23 of the third node N23 maintains a low voltage), and thus the flip-flop DFF can output the gated off time control signal OFT (i.e., a low voltage).

[0192] If the gated off-time control signal OFT is output from the off-time check unit 390, logic "1" is output from the third logic gate 356. When logic "1" is output from the third logic gate 356, logic "1" is also output from the fourth logic gate 358. At this time, the gated second control signal CS2 can be output from the second output terminal 353. At this time, the disabled first control signal CS1 can be output from the first output terminal 351, and the disabled third control signal CS3 can be output from the third output terminal 355.

[0193] Therefore, when the gated off-time control signal OFT is output from the off-time check section 390 , the second switch SW2 is turned on, and the driving section 312 may be driven in the second mode (ie, the PFM mode).

[0194] On the other hand, when the output load ILOAD decreases, the off time interval of the second switch signal VPFM may be lengthened. When the off time interval of the second switch signal VPFM is lengthened, the voltage VN21 of the first node N21 may be set to be higher than the threshold voltage Vth_M24 of the fourth transistor M24, so that the fourth transistor M24 may be turned on.

[0195] If the fourth transistor M24 is turned on, the second node N22 is set to the voltage of the basic potential GND, thereby setting the sixth transistor M26 to the on state. If the sixth transistor M26 is set to the on state, the clock signal (i.e., the high voltage of the third node N23) is supplied to the flip-flop DFF, thereby the flip-flop DFF can output the disabled off time control signal OFT (i.e., high voltage).

[0196] If the disabled OFF time control signal OFT is output from the OFF time check unit 390, logic "0" is output from the third logic gate 356. When logic "0" is output from the third logic gate 356, logic "0" is also output from the fourth logic gate 358. At this time, the disabled second control signal CS2 can be output from the second output terminal 353.

[0197] In addition, if the disabled off-time control signal OFT is output from the off-time check unit 390, a logic "1" is output from the fifth logic gate 359. At this time, the gated third control signal CS3 can be output from the third output terminal 355. If the gated third control signal CS3 is output, the third switch SW3 is turned on, and the driving unit 312 can be driven in the third mode (i.e., ULP mode). That is, in the embodiment of the present invention, when driving in the PFM mode, when the output load ILOAD decreases, the driving mode can be changed from PFM to ULP.

[0198] On the other hand, after the disabled off-time control signal OFT is supplied from the flip-flop DFF, the reset signal RSTO may be supplied after a predetermined time has passed. If the reset signal RSTO is supplied, the flip-flop DFF may output a low voltage.

[0199] Fig. 9 Yes means Figure 4 A diagram of an embodiment of a first counter is shown.

[0200] Reference Fig. 9 The first counter 370 may be driven only during driving in the second mode (ie, PFM mode). The first counter 370 may count the second switching signal VPFM when the feedback voltage VFB is lower than the reference voltage Vref in the second mode driving unit 330 .

[0201] When the feedback voltage VFB is set to be higher than the reference voltage Vref, it can be indicated that the output voltage Vout is stably generated in the second mode. Therefore, when the feedback voltage VFB is set to be higher than the reference voltage Vref, the first counter 370 is not driven. For example, when the feedback voltage VFB is set to be higher than the reference voltage Vref, the reset signal RST1 can be supplied from the mode control unit 350.

[0202] The first counter 370 may include a k-bit counter 372 , an output unit 374 , a first logic gate 375 , a second logic gate 376 , and a third logic gate 378 .

[0203] The first logic gate 375 receives the power signal POK and the second control signal CS2. Here, the power signal POK maintains a high voltage (i.e., logic "1") during normal driving. Therefore, the output of the first logic gate 375 can be determined according to the second control signal CS2. When the first logic gate 375 is set as a NAND gate and the second control signal CS2 is logic "1", a logic "0" can be output. In addition, when the second control signal CS2 is logic "0", the first logic gate 375 can output a logic "1".

[0204] Outputting logic "1" from the first logic gate 375 indicates that the reset signal RST1 is not supplied, and thus the k-bit counter 372 is not driven. That is, when the disabled second control signal CS2 is supplied (that is, when the DC-DC converter 300 is not driven in the PFM mode), the first counter 370 is not driven.

[0205] The second logic gate 376 can invert the signal of the first logic gate 375 to supply it to the third logic gate 378. The second logic gate 376 can supply a logic "1" signal to the third logic gate 378 when the DC-DC converter 300 is driven in the second mode (i.e., PFM mode) while the feedback voltage VFB is lower than the reference voltage Vref. The second logic gate 376 can be set as a NOT gate.

[0206] The third logic gate 378 may receive the output of the second logic gate 376 and the second switch signal VPFM. The third logic gate 378 may transfer the second switch signal VPFM to the k-bit counter 372 when the output of the second logic gate 376 is logic “1”. The third logic gate 378 may be configured as an AND gate.

[0207] The k-bit counter 372 may be a k-bit counter. Fig. 9 For the sake of convenience, it is assumed that k is 3. The k-bit counter 372 may include D flip-flops DFF1, DFF2, and DFF3, and may count the second switch signal VPFM.

[0208] The k-bit counter 372 may be reset when the feedback voltage VFB is set higher than the reference voltage Vref or the DC-DC converter 300 is driven in a mode other than the second mode (ie, the PFM mode) during counting of the second switching signal VPFM.

[0209] The k-bit counter 372 may count the second switch signal VPFM, thereby supplying a count signal to the output unit 374. The output unit 374 may output a gated first count signal PPC (high voltage or logic "1") when a count signal is input from the k-bit counter 372. The output unit 374 (or DFFO1) may be reset by a reset signal RSTP after a predetermined time has passed after the gated first count signal PPC is output. The output unit 374 may be set as a D flip-flop.

[0210] In the case where the gated first count signal PPC is output from the first counter 370, logic "1" is output from the first logic gate 352a and the second logic gate 354. In this case, the gated first control signal CS1 (or a high voltage) may be output from the first output terminal 351. In addition, the disabled second control signal CS2 (or a low voltage) may be output from the second output terminal 353, and the disabled third control signal CS3 (or a low voltage) may be output from the third output terminal 355.

[0211] That is, in the case where the gated first counting signal PPC is output from the first counter 370 , the first switch SW1 may be turned on, and the driving part 312 may be driven in the first mode (ie, PWM mode).

[0212] In more detail, when driving in the PFM mode, when the output load ILOAD increases, the off time of the second switching signal VPFM can be shortened. Here, the first count signal PPC generated by the first counter 370 can indicate that the output voltage Vout is set to a voltage lower than the desired voltage even if the second switching signal VPFM is supplied several times. In this case, it is determined that the output load ILOAD is high, and the DC-DC converter 300 can be driven in the first mode (i.e., PWM mode).

[0213] Fig.10 Yes means Figure 4 A diagram of an embodiment of a second counter is shown.

[0214] Reference Fig.10 The second counter 380 may be driven only during driving in the third mode (ie, ULP mode). The second counter 380 may count the third switching signal VULP when the feedback voltage VFB is lower than the reference voltage Vref in the third mode driving unit 340 .

[0215] The feedback voltage VFB is set to be higher than the reference voltage Vref, which means that the output voltage Vout is stably generated in the third mode (i.e., the ULP mode). Therefore, when the feedback voltage VFB is set to be higher than the reference voltage Vref, the second counter 380 is not driven. For example, when the feedback voltage VFB is set to be higher than the reference voltage Vref, the reset signal RST2 may be supplied from the mode control unit 350.

[0216] The second counter 380 may include a p-bit counter 382 , an output unit 384 , a first logic gate 385 , a second logic gate 386 , and a third logic gate 388 .

[0217] The first logic gate 385 receives the power signal POK and the third control signal CS3. Here, the power signal POK maintains a high voltage (i.e., logic "1") during normal driving. Therefore, the output of the first logic gate 385 can be determined according to the third control signal CS3. When the first logic gate 385 is set as a NAND gate and the third control signal CS3 is logic "1", a logic "0" can be output. In addition, the first logic gate 385 can output a logic "1" when the third control signal CS3 is logic "0".

[0218] Outputting a logic "1" from the first logic gate 385 indicates that the reset signal RST2 is supplied, and thus the p-bit counter 382 is not driven. That is, when the disabled third control signal CS3 is supplied (that is, when the DC-DC converter 300 is not driven in the ULP mode), the second counter 380 is not driven.

[0219] The second logic gate 386 can invert the signal of the first logic gate 385 to supply it to the third logic gate 388. The second logic gate 386 can supply a logic "1" signal to the third logic gate 388 when the DC-DC converter 300 is driven in the third mode (i.e., ULP mode) while the feedback voltage VFB is lower than the reference voltage Vref. The second logic gate 386 can be set as a NOT gate.

[0220] The third logic gate 388 receives the output of the second logic gate 386 and the third switch signal VULP. The third logic gate 388 may transmit the third switch signal VULP to the p-bit counter 382 when the output of the second logic gate 386 is logic “1”. The third logic gate 388 may be configured as an AND gate.

[0221] The p-bit counter 382 may be a p-bit counter. The p-bit counter 382 included in the second counter 380 may be a counter of lower bits than the k-bit counter 372 included in the first counter 370. Since the frequency of the third switching signal VULP is set to be lower than the frequency of the second switching signal VPFM, the second counter 380 may include a p-bit counter 382 of lower bits than the first counter 370.

[0222] exist Fig.10 For the sake of convenience, it is assumed that p is 2. The p-bit counter 382 may include D flip-flops DFF11 and DFF12 to count the third switch signal VULP.

[0223] The p-bit counter 382 may be reset when the feedback voltage VFB is set higher than the reference voltage Vref or the DC-DC converter 300 is driven in a mode other than the third mode (ie, ULP mode) during counting of the third switching signal VULP.

[0224] The p-bit counter 382 can count the third switch signal VULP to supply a count signal to the output unit 384. The output unit 384 can output a gated second count signal UPC (high voltage or logic "1") when the count signal is input from the p-bit counter 382. The output unit 374 (or DFFO2) can be reset according to the reset signal RSTU after a predetermined time has passed after the gated second count signal UPC is output. The output unit 384 can be set as a D flip-flop.

[0225] In the case where the gated second counting signal UPC is output from the second counter 380 , logic “1” is output from the fourth logic gate 358 . In this case, the gated second control signal CS2 may be output from the second output terminal 353 .

[0226] Further, in the case where the gated second count signal UPC is output from the second counter 380 , the reset signal RSTO may be supplied so that the gated off-time control signal OFT (or a low voltage) is generated by the off-time check section 390 .

[0227] In the case where the gated second counting signal UPC is output from the second counter 380 , the second switch SW2 may be turned on and the driving part 312 may be driven in the second mode (ie, the PFM mode).

[0228] In more detail, when driving in the ULP mode, when the output load ILOAD increases, the output voltage Vout can be set to a voltage lower than the desired voltage even if the third switching signal VULP is supplied several times. In this case, it is determined that the output load ILOAD is high, and the DC-DC converter 300 can be driven in the second mode (i.e., PFM mode).

[0229] Fig.11 Detailed description of the invention The following is a flowchart showing the operation process of the DC-DC converter according to the embodiment of the present invention.

[0230] Reference Fig.11 First, power is input to the DC-DC converter 300. After power is input to the DC-DC converter 300, it can be determined whether the DC-DC converter 300 is driven in the first mode PWM while the power signal POK is set to a high voltage (S110, S112).

[0231] In step S112, when the power signal POK is not set to a high voltage (S112: No), steps S110 and S112 may be repeated. In step S112, when the power signal POK is set to a high voltage (S112: Yes), the DC-DC converter 300 may be driven in the first mode PWM (S114).

[0232] In step S114, the on-time check unit 360 may be driven, and the off-time check unit 390, the first counter 370, and the second counter 380 may not be driven. Next, the mode control unit 350 may determine whether a prohibited on-time control signal ONT (i.e., a high voltage) is generated in the on-time check unit 360 (S116). In the case where the prohibited on-time control signal ONT is not generated in step S116 (S116: Yes), the DC-DC converter 300 is driven in the first mode PWM (S114, S116).

[0233] When the disabled on-time control signal ONT is generated in step S116 ( S116 : No), the DC-DC converter 300 may be driven in the second mode PFM ( S116 , S118 ).

[0234] In step S118, the off-time check section 390 and the first counter 370 may be driven, and the on-time check section 360 and the second counter 380 may not be driven. Next, the mode control section 350 may determine whether the disabled off-time control signal OFT (i.e., high voltage) or the enabled first count signal PPC is generated (S120, S122).

[0235] When the gated first count signal PPC is generated in step S120 (S120: Yes), the DC-DC converter 300 can be driven in the first mode PWM (S120, S114). When the gated first count signal PPC is not generated in step S120 (S120: No), the DC-DC converter 300 can maintain the second mode PFM drive (S120, S118).

[0236] In the case where the disabled off-time control signal OFT is not generated in step S122 (S122: No), the DC-DC converter 300 can maintain the driving in the second mode PFM (S122, S118). In the case where the disabled off-time control signal OFT is generated in step S122 (S122: Yes), the DC-DC converter 300 can be driven in the third mode ULP (S122, S124).

[0237] In step S124, the second counter 380 may be driven, and the on-time check section 360, the off-time check section 390, and the first counter 370 may not be driven. Next, the mode control section 350 may determine whether the gated second count signal UPC is generated in the second counter 380 (S126).

[0238] If the gated second count signal UPC is not generated in step S126 (S126: No), steps S124 and S126 may be repeated. If the gated second count signal UPC is generated in step S126 (S126: Yes), the DC-DC converter 300 may be driven in the second mode PFM (S126, S118).

[0239] That is, in the embodiment of the present invention, the mode control unit 350 can use the switching signals VPWM, VPFM, and VULP to determine the output load ILOAD, and drive the DC-DC converter 300 in the first mode PWM, the second mode PFM, or the third mode ULP corresponding to the output load ILOAD.

[0240] Fig.12 Yes means Figure 3 FIG. 1 is a diagram of an embodiment of a first mode driving unit shown in FIG.

[0241] Reference Fig.12 The first mode driving unit 320 according to an embodiment of the present invention may include an error amplifier 322 , a triangle wave generating unit 324 , and a comparator 326 .

[0242] The error amplifier 322 can compare the feedback voltage VFB with the reference voltage Vref, amplify a voltage corresponding to the difference voltage, and output it.

[0243] The triangular wave generation unit 324 may generate a triangular wave to supply it to the comparator 326 .

[0244] The comparator 326 may compare the output voltage of the error amplifier 322 with the triangle wave and generate the first switching signal VPWM corresponding to the comparison result.

[0245] Fig.13 Yes means Figure 3 FIG. 1 is a diagram of an embodiment of a second mode driving unit shown in FIG.

[0246] Reference Fig.13 The second mode driving unit 330 according to an embodiment of the present invention may include a comparator 332 , a sensor 334 , an on-time generating unit 336 , and a delay unit 338 .

[0247] The comparator 332 can compare the feedback voltage VFB with the reference voltage Vref and output a high voltage or a low voltage according to the comparison result. For example, the comparator 332 can output a high voltage when the feedback voltage VFB is higher than the reference voltage Vref, and output a low voltage in other cases.

[0248] When the output of the comparator 332 is set to a high voltage, it means that the output voltage Vout is set to a sufficiently high voltage. In this case, the on-time generating unit 336 and the like are not driven.

[0249] When the output of the comparator 332 is set to a low voltage, it means that the output voltage Vout is set to a voltage lower than a desired voltage. In this case, the on-time generator 336 can be driven.

[0250] The sensor 334 may sense whether the output of the comparator 332 is a high voltage or a low voltage to supply the result to the on-time generating section 336 .

[0251] When the output of the comparator 332 is set to a low voltage, the on-time generating unit 336 may generate the second switching signal VPFM so that the output voltage Vout may increase. Here, the on-time generating unit 336 may control the on-time of the second switching signal VPFM using the on-time changing signal AOT.

[0252] As an example, the on-time generating unit 336 may set the on-time of the second switch signal VPFM to be relatively long when it is determined that the output load ILOAD is high, and may set the on-time of the second switch signal VPFM to be relatively short when it is determined that the output load ILOAD is low.

[0253] The delay part 338 may delay the second switching signal VPFM to supply it to the sensor 334 .

[0254] Fig.14 Yes means Figure 3 FIG. 1 is a diagram of an embodiment of a third mode driving unit shown in FIG.

[0255] Reference Fig.14 The third mode driving unit 340 according to an embodiment of the present invention may include a comparator 342 , a frequency divider 344 , an on-time generating unit 346 , and a logic gate 348 .

[0256] The comparator 342 can compare the feedback voltage VFB with the reference voltage Vref and output a high voltage or a low voltage according to the comparison result. For example, the comparator 342 can output a high voltage when the feedback voltage VFB is higher than the reference voltage Vref, and output a low voltage in other cases.

[0257] When the output of the comparator 332 is set to a high voltage, it means that the output voltage Vout is set to a sufficiently high voltage. When a high voltage is output from the comparator 332, the logic gate 348 outputs a high voltage.

[0258] In this case, when the third switching signal VULP is supplied to the driving unit 312 , the first transistor Mp is set to an off state. That is, no current is supplied to the inductor L.

[0259] When the output of the comparator 332 is set to a low voltage, it means that the output voltage Vout is set to a voltage lower than a desired voltage. In this case, the output of the logic gate 348 can be controlled by the output of the on-time generator 346 .

[0260] The frequency divider 344 may divide the clock signal CLK to reduce the frequency of the clock signal CLK. In this case, the third mode driving unit 340 may be driven according to the low-frequency clock signal.

[0261] The on-time generator 346 may generate a pulse signal at a certain frequency. The pulse signal of a certain frequency generated by the on-time generator 346 may be supplied to the driver 312 as the third switching signal VULP. Here, the frequency of the third switching signal VULP may be lower than the frequency of the second switching signal VPFM.

[0262] That is, the third mode driving part 340 can supply the third switching signal VULP at a low frequency when the output load ILOAD is very low, thereby reducing power consumption.

[0263] Fig.15 Yes means Figure 4 A graph showing a simulation of the power consumption of the on-time check section is shown. Fig.15 In FIG. 1 , the X axis represents the load current (Load current; mA), and the Y axis represents the power consumption (Power consumption; μW). In addition, the input voltage Vin supplied to the on-time inspection unit 360 is set to 2.2V, 3.3V, and 5.0V, respectively.

[0264] Reference Fig.15 , the power consumption of the on-time check unit 360 can be set to be the highest at 5.0V and the lowest at 2.2V. In addition, at the same input voltage, even if the load current increases, the power consumption remains almost constant. Corresponding to the input voltage of 5.0V, the power consumption of the on-time check unit 360 is approximately 20μW. That is, the on-time check unit 360 involved in the embodiment of the present invention can consume low power while using the first switching signal VPWM to sense the output load ILOAD.

[0265] Fig.16 Yes means Figure 4 A diagram showing a simulation of the power consumption of the off-time check section is shown. Fig.16In FIG. 1 , the X-axis represents the off-time period (μs) of the second switch signal VPFM, and the Y-axis represents the power consumption (nW).

[0266] Reference Fig.16 , the power consumption of the disconnection time check unit 390 can be set to be different corresponding to the disconnection time interval. As an example, when the disconnection time interval is set to 30μs or more, the power consumption can be increased. The power consumption range of the disconnection time check unit 390 can be set to approximately 225nW to 240nW, thereby confirming that the power consumption is low. Further, when the disconnection time interval is set to 50μs or more, the driving mode of the DC-DC converter 300 can be changed to the third mode ULP.

[0267] Fig.17 It is a simulation waveform diagram showing the process of the DC-DC converter changing from the first mode to the second mode. Fig.17 In FIG. 1 , Aa shows the A portion in an enlarged manner.

[0268] Reference Fig.17 When the load current IL (or the output load ILOAD) changes from 90 mA to 3.6 mA, the DC-DC converter 300 can change from the first mode (PWM mode) to the second mode (PFM mode).

[0269] As an example, when the load current IL decreases, the on-time interval is reduced from 295ns to 188ns. When the on-time interval is shortened, the on-time control signal ONT is changed from a high voltage to a low voltage. Thus, the DC-DC converter 300 can be changed from the first mode (PWM mode) to the second mode (PFM mode).

[0270] Fig.18 It is a simulation waveform diagram showing the process of the DC-DC converter changing from the second mode to the first mode. Fig.18 In the figure, Ba shows the B part in an enlarged manner.

[0271] Reference Fig.18 When the load current IL (or the output load ILOAD) changes from 1.6 mA to 55 mA, the DC-DC converter 300 can change from the second mode (PFM mode) to the first mode (PWM mode).

[0272] When the load current IL is set to 1.6 mA, the DC-DC converter 300 is driven in the second mode (PFM mode), and the first count signal PPC is maintained at a low voltage (disabled). In addition, when the load current IL changes from 1.6 mA to 55 mA, the reference voltage Vref is set higher than the feedback voltage VFB (i.e., from Fig.13 The comparator 332 outputs a low voltage), and the second switching signal VPFM can be repeatedly generated three or more times. In this case, the first counter 370 can output the gated first counting signal PPC (i.e., a high voltage), and the DC-DC converter 300 can be changed from the second mode (PFM mode) to the first mode (PWM mode).

[0273] Next, when the on-time check unit 360 receives the first switching signal VFWM and the on-time control signal ONT is set to a high voltage, the first counter 370 may be initialized according to the reset signal RSTP.

[0274] Fig.19 This is a simulation waveform diagram showing the process of the DC-DC converter changing from the second mode to the third mode. Fig.19 In the figure, Ca is an enlarged representation of part C, and Da is an enlarged representation of part D.

[0275] Reference Fig.19 When the load current IL (or the output load ILOAD) changes from 3.8 mA to 0.2 mA, the DC-DC converter 300 can change from the second mode (PFM mode) to the third mode (ULP mode).

[0276] When the load current IL is set to 3.8 mA, the DC-DC converter 300 is driven in the second mode (PFM mode). At this time, the off time interval of the second switching signal VPFM is set to less than 50 μs, and the off time control signal OFT maintains the gated (ie, low voltage) state.

[0277] When the load current IL decreases from 3.8 mA to 0.2 mA, the off-time interval of the second switch signal VPFM increases to more than 50 μs, and the off-time control signal OFT is maintained in a disabled (i.e., high voltage) state. That is, when the load current IL decreases from 3.8 mA to 0.2 mA, the disabled off-time control signal OFT can be output from the off-time check unit 390, and thus the DC-DC converter 300 can be driven into the third mode (ULP mode).

[0278] In the third mode (ULP mode), the on-time interval T2 of the third switching signal VULP may be set to be shorter than the on-time interval T1 of the second switching signal VPFM. In addition, the third switching signal VULP may have a lower frequency than the second switching signal VPFM. Therefore, when the DC-DC converter 300 is driven in the third mode (ULP mode), it can be driven with low power consumption.

[0279] Fig. 20 : is a simulation waveform diagram showing a process in which the DC-DC converter changes from the third mode to the second mode.

[0280] Reference Fig. 20 When the load current IL (or the output load ILOAD) changes from 0.2 mA to 3.8 mA, the DC-DC converter 300 can change from the third mode (ULP mode) to the second mode (PFM mode).

[0281] When the load current IL is set to 0.2 mA, the DC-DC converter 300 is driven in the third mode (ULP mode), so that the second count signal UPC maintains a low voltage (disabled). In addition, when the load current IL changes from 0.2 mA to 3.8 mA, the reference voltage Vref can be set higher than the feedback voltage VFB (i.e., from Fig.14 The comparator 342 outputs a low voltage), and the third switching signal VULP is repeatedly input to the second counter 380 more than twice.

[0282] In this case, the second counter 380 may output the enabled second counting signal UPC (ie, a high voltage), and the DC-DC converter 300 may be changed from the third mode (ULP mode) to the second mode (PFM mode).

[0283] Fig.21 It is a diagram showing a display device according to an embodiment of the present invention.

[0284] Reference Fig.21 The display device according to an embodiment of the present invention may include a display driver 210, a display unit 110, and a power supply unit 16. The display driver 210 may include a timing control unit 11 and a data driver 12, and the display unit 110 may include a scan driver 13 and a light emitting driver 15. Here, the functional units may be integrated into one IC or multiple ICs or mounted on a display substrate in various ways according to the specifications of the display device.

[0285] The timing control unit 11 may receive data corresponding to a frame period and a timing signal from the application processor 30. Data may be supplied in units of horizontal lines in each horizontal period. A horizontal line may represent a pixel row in which a plurality of pixels connected to the same scan line are arranged.

[0286] The timing control section 11 may render data to correspond to the specification of the display device (or the pixel section 14). In addition, the timing control section 11 may supply a data control signal to the data driving section 12. In addition, the timing control section 11 may supply a scan control signal to the scan driving section 13.

[0287] The data driving part 12 may generate data signals to be provided to the data lines DL1 , DL2 , DL3 , DL4 , . . . , DLn (eg, n is a natural number) using the data and the data control signal received from the timing control part 11 .

[0288] The scanning drive unit 13 can generate scanning signals provided to the scanning lines SL0, SL1, SL2, ..., SLm (for example, m is a natural number) by using the clock signal, scanning start signal, etc. received from the timing control unit 11. The scanning drive unit 13 can sequentially supply scanning signals with pulses of a conduction level to the scanning lines SL0 to SLm. For example, the scanning drive unit 13 can sequentially supply scanning signals of a conduction level to the scanning lines SL0 to SLm in a period corresponding to the period of the horizontal synchronization signal (Hsync) during the active period of supplying data. The scanning drive unit 13 may include a scanning drive stage composed of a shift register. The scanning drive unit 13 can generate a scanning signal in a manner that sequentially transmits a scanning start signal in the form of a pulse of a conduction level to the next scanning drive stage according to the control of the clock signal.

[0289] The light-emitting driving section 15 can generate a light-emitting control signal provided to the light-emitting control lines EL1, EL2, EL3, ..., ELo (for example, o is a natural number) by using the clock signal and the light-emitting start signal received from the timing control section 11. The light-emitting driving section 15 can sequentially supply light-emitting control signals having pulses of a cut-off level to the light-emitting control lines EL1 to ELo. The light-emitting driving section 15 can include a light-emitting driving stage formed in the form of a shift register. The light-emitting driving section 15 can generate a light-emitting control signal in a manner that sequentially transmits a light-emitting start signal in the form of a pulse of a cut-off level to the next light-emitting driving stage according to the control of the clock signal.

[0290] The pixel unit 14 includes a plurality of pixels PX. Each pixel PX may be connected to a corresponding data line and a scan line. Fig. 22) can be connected to the i-th scan line SLi and the j-th data line DLj (hereinafter also referred to as data line DLj). The pixel PX can be selected to receive the data signal when the scan line connected to itself is supplied with a scan signal. The pixel PX can generate light of a predetermined brightness corresponding to the data signal.

[0291] The power supply unit 16 can generate various power supplies required for driving the display device. As an example, the power supply unit 16 can generate a first driving power supply EVDD, a second driving power supply EVSS, and an initialization power supply Vint. To this end, the power supply unit 16 can include Figure 3 The DC-DC converter 300 shown in FIG. 3 may be included in the power supply unit 16 and generates at least one power source among the first driving power source EVDD, the second driving power source EVSS and the initialization power source Vint.

[0292] The first driving power source EVDD may be a power source for supplying driving current to the pixel PX. The second driving power source EVSS may be a power source for receiving driving current from the pixel PX. During the period when the pixel PX is set to the light-emitting state, the first driving power source EVDD may be set to a voltage higher than the second driving power source EVSS. The initialization power source Vint is a power source for initializing the gate electrode of the driving transistor and the light-emitting element LD (refer to Fig. 22 ) power supply.

[0293] The first driving power EVDD generated by the power supply unit 16 may be supplied to the first power line PL1, the second driving power EVSS generated by the power supply unit 16 may be supplied to the second power line PL2, and the initialization power Vint generated by the power supply unit 16 may be supplied to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 may be commonly connected to the pixel PX, but the embodiment of the present invention is not limited thereto.

[0294] In an embodiment, the first power line PL1 is composed of a plurality of power lines, and the plurality of power lines can be connected to different pixels PX. In an embodiment, the second power line PL2 can be composed of a plurality of power lines, and the plurality of power lines can be connected to different pixels PX. In an embodiment, the third power line PL3 can be composed of a plurality of power lines, and the plurality of power lines can be connected to different pixels PX. That is, in an embodiment of the present invention, the pixel PX can be connected to any one of the plurality of first power lines PL1, any one of the plurality of second power lines PL2, and any one of the plurality of third power lines PL3.

[0295] Fig. 22 This is a diagram for explaining a pixel according to an embodiment of the present invention.

[0296] Reference Fig. 22 A pixel PXij according to an embodiment of the present invention includes transistors M41, M42, M43, M44, M45, M46, M47, a storage capacitor Cst, and a light emitting element LD.

[0297] In the following, a circuit composed of P-type transistors is used as an example for explanation. However, a person skilled in the art should be able to design a circuit composed of N-type transistors by making the polarity of the voltage applied to the gate terminal different. Similarly, a person skilled in the art should be able to design a circuit composed of a combination of P-type transistors and N-type transistors. Transistors M41, M42, M43, M44, M45, M46, and M47 can be composed of various forms such as TFT (thin film transistor), FET (field effect transistor), and BJT (bipolar junction transistor).

[0298] In the first transistor M41, a gate electrode may be connected to the first node N41, a first electrode may be connected to the second node N42, and a second electrode may be connected to the third node N43. The first transistor M41 may be named a driving transistor.

[0299] In the second transistor M42, a gate electrode may be connected to the scan line SLi1, a first electrode may be connected to the data line DLj, and a second electrode may be connected to the second node N42. The second transistor M42 may be named a scan transistor.

[0300] In the third transistor M43, a gate electrode may be connected to the scan line SLi2, a first electrode may be connected to the third node N43, and a second electrode may be connected to the first node N41. The third transistor M43 may be named a diode-connected transistor.

[0301] In the fourth transistor M44, a gate electrode may be connected to the scan line SLi3, a first electrode may be connected to the first node N41, and a second electrode may be connected to the third power line PL3. The fourth transistor M44 may be named a gate initialization transistor.

[0302] In the fifth transistor M45, a gate electrode may be connected to the i-th light emitting control line ELi, a first electrode may be connected to the first power line PL1, and a second electrode may be connected to the second node N42. The fifth transistor M45 may be named a light emitting transistor.

[0303] In the sixth transistor M46, the gate electrode may be connected to the i-th light emitting control line ELi, the first electrode may be connected to the third node N43, and the second electrode may be connected to the anode of the light emitting element LD. The sixth transistor M46 may be named as a light emitting transistor. In other embodiments, the gate electrode of the sixth transistor M46 may be connected to a light emitting control line different from the light emitting control line connected to the gate electrode of the fifth transistor M45.

[0304] In the seventh transistor M47, a gate electrode may be connected to the scan line SLi4, a second electrode may be connected to the third power line PL3, and a first electrode may be connected to the anode of the light emitting element LD. The seventh transistor M47 may be named a light emitting element initialization transistor.

[0305] In the storage capacitor Cst, a first electrode may be connected to the first power line PL1 , and a second electrode may be connected to the first node N41 .

[0306] In the light emitting element LD, the anode may be connected to the second electrode of the sixth transistor M46, and the cathode may be connected to the second power line PL2. The light emitting element LD may be a light emitting diode. The light emitting element LD may be composed of an organic light emitting diode, an inorganic light emitting diode, a quantum dot / quantum well light emitting diode, etc. In addition, in the present embodiment, each pixel PX has only one light emitting element LD, but in other embodiments, each pixel PX may also have multiple light emitting elements LD. At this time, multiple light emitting elements LD may be connected in series, in parallel, in series and in parallel, etc.

[0307] Fig.23 It is used to illustrate Fig. 22 A diagram of an exemplary driving method for a pixel is shown.

[0308] exist Fig. 22 and Fig.23 In the figure, for the sake of convenience, it is assumed that the scan lines SLi1, SLi2, and SLi4 are the i-th scan line SLi and the scan line SLi3 is the i-1th scan line SL(i-1). However, the connection relationship between the scan lines SLi1, SLi2, SLi3, and SLi4 may be different according to the embodiment. For example, the scan line SLi4 may be the i-1th scan line SL(i-1) or the i+1th scan line.

[0309] First, a light emitting control signal of a cut-off level (logic high level) is applied to the light emitting control line ELi, a data signal DATA(i-1)j for the i-1th pixel is applied to the data line DLj, and a scanning signal of a conduction level (logic low level) is applied to the scanning line SLi3. The high / low of the logic level may be different depending on whether the transistor is a P-type or an N-type.

[0310] At this time, since the scan signals of the off level are applied to the scan lines SLi1 and SLi2, the second transistor M42 is in the off state, preventing the data signal DATA(i-1)j for the i-1th pixel from being introduced into the pixel PXij.

[0311] At this time, the fourth transistor M44 is in the on state, so the first node N41 is connected to the third power line PL3, thereby initializing the voltage of the first node N41. Since the light emitting control signal of the off level is applied to the light emitting control line ELi, the transistors M45 and M46 are in the off state, preventing unnecessary light emission of the light emitting element LD caused by the application process of the initialization voltage.

[0312] Next, a data signal DATAij for the pixel PXij is applied to the data line DLj, and a scanning signal of a conduction level is applied to the scanning lines SLi1 and SLi2. As a result, the transistors M42, M41, and M43 are in a conducting state, and the data line DLj is electrically connected to the first node N41. Therefore, a compensation voltage obtained by subtracting the threshold voltage of the first transistor M41 from the data signal DATAij is applied to the second electrode of the energy storage capacitor Cst (i.e., the first node N41), and the energy storage capacitor Cst maintains a voltage equivalent to the difference between the first driving power supply EVDD and the compensation voltage. This period can be named a threshold voltage compensation period or a data writing period.

[0313] In addition, when the scan line SLi4 is the i-th scan line SLi, the seventh transistor M47 is in the on state, thereby the anode of the light emitting element LD is connected to the third power line PL3, and the light emitting element LD is initialized by the charge amount equivalent to the voltage difference between the initialization power supply Vint and the second driving power supply EVSS.

[0314] Then, as the emission control signal of the on level is applied to the emission control line ELi, the transistors M45 and M46 may be turned on, thereby forming a current path connecting the first power line PL1, the fifth transistor M45, the first transistor M41, the sixth transistor M46, the light emitting element LD and the second power line PL2.

[0315] According to the voltage stored in the energy storage capacitor Cst, the amount of driving current flowing to the first electrode and the second electrode of the first transistor M41 is adjusted. The light emitting element LD emits light at a brightness corresponding to the amount of driving current. The light emitting element LD emits light until a light emitting control signal of a cutoff level is applied to the light emitting control line ELi.

[0316] When the light emitting control signal is at the on level, the pixel PX receiving the corresponding light emitting control signal may be in a display state. Therefore, the period during which the light emitting control signal is at the on level may be named as a light emitting period EP (or a light emitting period allowed). In addition, when the light emitting control signal is at the off level, the pixel PX receiving the corresponding light emitting control signal may be in a non-display state. Therefore, the period during which the light emitting control signal is at the off level may be named as a non-light emitting period (or a light emitting period not allowed) NEP.

[0317] exist Fig.23 The non-light emitting period NEP described in is used to prevent the pixel PXij from emitting light with an undesired brightness during the period between the initialization period and the data writing period.

[0318] During the period of maintaining the data signal written into the pixel PXij (for example, one frame period), one or more non-luminous periods NEP may be provided to reduce the luminous period EP of the pixel PXij to effectively express low grayscale or to perform soft blur processing on the motion of the image.

[0319] Fig.24 It is a diagram showing an electronic device according to an embodiment of the present invention.

[0320] Reference Fig.24 The electronic device 1000 according to the embodiment of the present invention outputs various information through the display module 1140. If the processor 1110 executes an application stored in the memory 1120, the display module 1140 provides the application information to the user through the display panel 1141.

[0321] The processor 1110 obtains external input through the input module 1130 or the sensor module 1161, and executes an application corresponding to the external input. For example, when the user selects the camera icon (or camera application icon) displayed in the display panel 1141, the processor 1110 obtains the user input through the input sensor 1161-2 and activates the camera module 1171. The processor 1110 transmits image data corresponding to the captured image obtained by the camera module 1171 to the display module 1140. The display module 1140 can display an image corresponding to the captured image through the display panel 1141.

[0322] As another example, in the case of performing personal information authentication in the display module 1140, the fingerprint sensor 1161-1 obtains the input fingerprint information as input data. The processor 1110 compares the input data obtained by the fingerprint sensor 1161-1 with the authentication data stored in the memory 1120, and executes the application according to the comparison result. The display module 1140 can display information executed according to the logic of the application through the display panel 1141. The fingerprint sensor 1161-1 can be configured to be able to obtain fingerprint information in the entire area of ​​the display module 1140 (or the display panel 1141).

[0323] As another example, when the music streaming icon displayed in the display module 1140 is selected, the processor 1110 obtains the user input through the input sensor 1161-2 and activates the music streaming application stored in the memory 1120. If a music execution command is input in the music streaming application, the processor 1110 activates the sound output module 1163 to provide the user with sound information corresponding to the music execution command.

[0324] The operation of the electronic device 1000 is briefly described above. The configuration of the electronic device 1000 is described in detail below. Some of the configurations of the electronic device 1000 described below may be integrated into one configuration, or one configuration may be separated into two or more configurations.

[0325] The electronic device 1000 can communicate with the external electronic device 2000 through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device 1000 may include a processor 1110, a memory 1120, an input module 1130, a display module 1140, a power module 1150, a built-in module 1160, and an external module 1170. According to one embodiment, the electronic device 1000 may omit at least one of the above-mentioned components or add one or more other components. According to one embodiment, a part of the above-mentioned components (e.g., a sensor module 1161, an antenna module 1162, or an audio output module 1163) may be combined into another component (e.g., a display module 1140).

[0326] The processor 1110 may execute software to control at least one other component (e.g., hardware or software component) of the electronic device 1000 connected to the processor 1110, and may perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operation, the processor 1110 may store commands or data received from other components (e.g., the input module 1130, the sensor module 1161, or the communication module 1173) in the volatile memory 1121, process the commands or data stored in the volatile memory 1121, and store the result data in the non-volatile memory 1122.

[0327] The processor 1110 may include a main processor 1111 and an auxiliary processor 1112. The main processor 1111 may include one or more of a central processing unit (CPU) 1111-1 or an application processor (AP: application processor). The main processor 1111 may further include any one or more of a graphics processing unit (GPU) 1111-2, a communication processor (CP: communication processor) and an image signal processor (ISP: image signal processor). The main processor 1111 may further include a neural processing unit (neural processing unit) NPU 1111-3. The neural network processing unit NPU 1111-3 is a processor specialized for processing artificial intelligence models, which can be generated by machine learning. The artificial intelligence model may include multiple artificial neural network arrays. The artificial neural network can be a deep neural network (DNN), a CNN (convolutional neural network), an RNN (recurrent neural network), an RBM (restricted Boltzmann machine), a DBN (deep belief network), a BRDNN (bidirectional recurrent deep neural network), a deep Q-network or a combination of two or more of the above networks, and is not limited to the above examples. In addition to the hardware structure, the artificial intelligence model may additionally or alternatively include a software structure. At least two of the above-mentioned processing unit and processor can be implemented by a unified structure (for example, a single chip), and can be implemented by separate independent structures (for example, multiple chips).

[0328] The auxiliary processor 1112 may include a controller 1112-1. The controller 1112-1 may include an interface conversion circuit and a timing control circuit. As an example, the controller 1112-1 may include Fig.21The timing control unit 11 is shown. The controller 1112-1 receives the image signal from the main processor 1111, converts the data format of the image signal into an interface specification that conforms to the display module 1140, and outputs the image data. The controller 1112-1 can output various control signals required for driving the display module 1140.

[0329] The auxiliary processor 1112 may further include a data conversion circuit 1112-2, a gamma correction circuit 1112-3, a rendering circuit 1112-4, and a touch control circuit (not shown). The data conversion circuit 1112-2 may receive image data from the controller 1112-1, compensate the image data so as to display an image at a desired brightness according to the characteristics of the electronic device 1000 or the user's settings, or convert the image data in order to reduce power consumption or compensate for afterimages.

[0330] The gamma correction circuit 1112-3 may transform image data or gamma reference voltage so that an image displayed in the electronic device 1000 has a desired gamma characteristic. The rendering circuit 1112-4 may receive image data from the controller 1112-1 and render the image data in consideration of the pixel configuration of the display panel 1141 of the electronic device 1000.

[0331] The touch control circuit may supply a touch signal to the input sensor 1161 - 2 , and receive a sensing signal from the input sensor 1161 - 2 corresponding to the touch signal.

[0332] At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, the rendering circuit 1112-4, and the touch control circuit may be combined into other components (e.g., the main processor 1111 or the controller 1112-1). At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, and the rendering circuit 1112-4 may also be combined into the source driver 1143 described later.

[0333] The memory 1120 may store various data used by at least one component of the electronic device 1000 (e.g., the processor 1110 or the sensor module 1161) and input data or output data for commands related thereto. In addition, various setting data corresponding to user settings may be stored in the memory 1120. The memory 1120 may include at least one of a volatile memory 1121 and a nonvolatile memory 1122.

[0334] The input module 1130 may receive commands or data to be used in components of the electronic device 1000 (eg, the processor 1110 , the sensor module 1161 , or the audio output module 1163 ) from outside the electronic device 1000 (eg, a user or an external electronic device 2000 ).

[0335] The input module 1130 may include a first input module 1131 into which a user inputs a command or data and a second input module 1132 into which an external electronic device 2000 inputs a command or data. The first input module 1131 may include a microphone, a mouse, a keyboard, a button (e.g., a key) or a pen (e.g., a passive pen or an active pen). The second input module 1132 may support a specified protocol that can be connected to the external electronic device 2000 in a wired or wireless manner. According to one embodiment, the second input module 1132 may include an HDMI (high definition multimedia interface), a USB (universalserial bus) interface, an SD card interface, or an audio interface. The second input module 1132 may include a connector that can be physically connected to the external electronic device 2000 (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)).

[0336] The display module 1140 provides visual information to the user. The display module 1140 may include a display panel 1141, a gate driver 1142, and a source driver 1143. The display module 1140 may also include a window, a base, and a bracket for protecting the display panel 1141. The display module 1140 as described above may include Fig.21 The display device shown.

[0337] The display panel (or display) 1141 may include a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel, and the type of the display panel 1141 is not particularly limited. The display panel 1141 may be a rigid type, or may be a flexible type that is rollable or foldable. The display module 1140 may further include a support, a bracket, or a heat dissipation component that supports the display panel 1141.

[0338] The display panel 1141 may receive image data from the auxiliary processor 1112 and display an image while controlling the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the pixels PX in accordance with the image data.

[0339] The gate driver 1142 is a driving chip that can be installed in the display panel 1141. In addition, the gate driver 1142 can be integrated into the display panel 1141. For example, the gate driver 1142 may include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) built into the display panel 1141. The gate driver 1142 receives a control signal from the controller 1112-1 and outputs a scan signal to the display panel 1141 in response to the control signal. The gate driver 1142 may include Fig.21 The scanning driving unit 13 is shown.

[0340] The display module 1140 may further include a light emitting driver. The light emitting driver outputs a light emitting control signal to the display panel 1141 in response to a control signal received from the controller 1112-1. The light emitting driver may be formed separately from the gate driver 1142 or may be combined into the gate driver 1142. The light emitting driver may include Fig.21 The light emitting driving unit 15 is shown.

[0341] The source driver 1143 receives a control signal from the controller 1112-1, converts the image data into an analog voltage (eg, a data signal) in response to the control signal, and then outputs the data signal to the display panel 1141. The source driver 1143 may include Fig.21 The data driving unit 12 is shown.

[0342] The source driver 1143 may be integrated into other components (eg, the controller 1112 - 1 ). The functions of the interface conversion circuit and the timing control circuit of the controller 1112 - 1 may also be integrated into the source driver 1143 .

[0343] The display module 1140 may further include a voltage generating circuit 1144. The voltage generating circuit 1144 may output various voltages required for driving the display panel 1141. As an example, the voltage generating circuit 1144 may include Fig.21 The power supply unit 16 is shown. The voltage generating circuit 1144 may include Figure 3 The DC-DC converter 300 is shown.

[0344] In an embodiment, the display panel 1141 may include a plurality of pixel columns each including a plurality of pixels.

[0345] In an embodiment, the source driver 1143 may convert data corresponding to red (R), green (G), and blue (B) included in the image data received from the processor 1110 into red data signals (or data voltages), green data signals (or data voltages), and blue data signals (or data voltages), and provide them to a plurality of pixel columns included in the display panel 1141 within one horizontal period.

[0346] The power module 1150 supplies power to the components of the electronic device 1000. The power module 1150 may include a battery for charging the power supply voltage. The battery may include a primary battery that cannot be recharged, a secondary battery that can be recharged, or a fuel cell. The power module 1150 may include a PMIC (power management integrated circuit). The PMIC supplies optimized power to the above-mentioned modules and the modules described later, respectively. The power module 1150 may include a radio transceiver component electrically connected to the battery. The radio transceiver component may include a plurality of antenna radiators in the form of coils.

[0347] The electronic device 1000 may further include a built-in module 1160 and an external module 1170. The built-in module 1160 may include a sensor module 1161, an antenna module 1162, and an audio output module 1163. The external module 1170 may include a camera module 1171, a light module 1172, and a communication module 1173.

[0348] The sensor module 1161 can sense input caused by the user's body or input caused by the pen in the first input module 1131, and generate an electrical signal or data value corresponding to the input. The sensor module 1161 can include any one or more of a fingerprint sensor 1161-1, an input sensor 1161-2, and a digitizer 1161-3.

[0349] The fingerprint sensor 1161-1 may generate a data value corresponding to the fingerprint of the user. The fingerprint sensor 1161-1 may include an optical fingerprint sensor or a capacitive fingerprint sensor.

[0350] The input sensor 1161-2 may generate a data value corresponding to the coordinate information of the input caused by the user's body or the input caused by the pen. The input sensor 1161-2 generates the capacitance change caused by the input as a data value. The input sensor 1161-2 may sense the input caused by the passive pen or transmit and receive data with the active pen.

[0351] The input sensor 1161-2 may also measure biological signals such as blood pressure, water content, or body fat. For example, when a user places a part of the body in contact with the sensor layer or the sensing panel and does not move for a certain period of time, the input sensor 1161-2 may sense the biological signal based on the electric field change caused by the part of the body to output the information desired by the user to the display module 1140.

[0352] The digitizer 1161-3 may generate a data value corresponding to the coordinate information of the input caused by the pen. The digitizer 1161-3 generates the amount of electromagnetic change caused by the input as a data value. The digitizer 1161-3 may sense the input caused by the passive pen or transmit and receive data with the active pen.

[0353] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may also be implemented as a sensor layer formed on the display panel 1141 through a continuous process. At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be configured on the upper side of the display panel 1141, and any one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 (for example, the digitizer 1161-3) may be configured on the lower side of the display panel 1141.

[0354] Two or more of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be integrated into one sensing panel through the same process. When integrated into one sensing panel, the sensing panel may be disposed between the display panel 1141 and a window portion disposed on the upper side of the display panel 1141. According to one embodiment, the sensing panel may also be disposed on the window portion, and the position of the sensing panel is not particularly limited.

[0355] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be built in the display panel 1141. That is, at least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be simultaneously formed through the process of forming elements (e.g., light emitting elements, transistors, etc.) included in the display panel 1141.

[0356] In addition, the sensor module 1161 can generate an electrical signal or data value corresponding to the internal state or external state of the electronic device 1000. The sensor module 1161 may also include, for example, a gesture sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a grip force sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0357] The antenna module 1162 may include one or more antennas for transmitting signals or power to the outside or receiving signals or power from the outside. According to one embodiment, the communication module 1173 may transmit signals to the external electronic device 2000 or receive signals from the external electronic device 2000 through an antenna that complies with the communication method. The antenna pattern of the antenna module 1162 may also be integrated with a component of the display module 1140 (e.g., the display panel 1141) or the input sensor 1161-2, etc.

[0358] The audio output module 1163 is a device for outputting an audio signal to the outside of the electronic device 1000, and may include, for example, a speaker for general use such as multimedia playback or recording playback and a receiver for making and receiving calls. According to one embodiment, the receiver may be formed integrally with the speaker or formed separately. The audio output pattern of the audio output module 1163 may also be formed integrally with the display module 1140.

[0359] The camera module 1171 can capture still images or dynamic images. According to one embodiment, the camera module 1171 may include one or more lenses, image sensors, or image signal processors. The camera module 1171 may also include an infrared camera capable of measuring the presence of a user, the position of a user, the line of sight of a user, etc.

[0360] The light module 1172 may provide light. The light module 1172 may include a light emitting diode or a xenon lamp. The light module 1172 may operate in conjunction with the camera module 1171 or independently.

[0361] Establishment of a wireless communication channel and execution of communication based on the established communication channel. The communication module 1173 may include any or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module or a GNSS (global navigation satellite system) communication module and a wired communication module such as a LAN (local area network) communication module or a power line communication module. The communication module 1173 can communicate with the external electronic device 2000 through a short-range communication network such as Bluetooth, WiFi direct connection or IrDA (infrared data association) or a long-range communication network such as a cellular network, the Internet or a computer network (for example, LAN or WAN). The various types of communication modules 1173 mentioned above can be implemented by one chip or by separate chips.

[0362] The input module 1130 , the sensor module 1161 , the camera module 1171 , and the like can be linked with the processor 1110 and effectively utilized in controlling the operation of the display module 1140 .

[0363] The processor 1110 outputs a command or data to the display module 1140, the audio output module 1163, the camera module 1171, or the light module 1172 based on the input data received from the input module 1130. For example, the processor 1110 may generate image data corresponding to input data applied through a mouse or an active pen, etc., and output it to the display module 1140, or generate command data corresponding to the input data and output it to the camera module 1171 or the light module 1172. The processor 1110 may convert the operation mode of the electronic device 1000 to a low power mode or a sleep mode when no input data is received from the input module 1130, thereby reducing the power consumed in the electronic device 1000.

[0364] The processor 1110 outputs a command or data to the display module 1140, the audio output module 1163, the camera module 1171, or the light module 1172 based on the sensing data received from the sensor module 1161. For example, the processor 1110 may execute an application according to the comparison result after comparing the authentication data applied by the fingerprint sensor 1161-1 with the authentication data stored in the memory 1120. The processor 1110 may execute a command or output corresponding image data to the display module 1140 based on the sensing data sensed by the input sensor 1161-2 or the digitizer 1161-3. In the case where the sensor module 1161 includes a temperature sensor, the processor 1110 may receive temperature data for the temperature measured by the sensor module 1161, and further implement brightness correction for the image data based on the temperature data.

[0365] The processor 1110 may receive measurement data on the presence or absence of a user, the position of the user, the line of sight of the user, etc. from the camera module 1171. The processor 1110 may further perform brightness correction on the image data based on the measurement data. For example, the processor 1110, which has determined the presence or absence of a user through the input from the camera module 1171, may output image data whose brightness has been corrected through the data conversion circuit 1112-2 or the gamma correction circuit 1112-3 to the display module 1140.

[0366] Some of the components described can be connected to each other through a communication method between peripheral devices (for example, a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface) or UPI (Ultrapath interconnect) link), so as to exchange signals (for example, commands or data) with each other. The processor 1110 can communicate with the display module 1140 through an interface agreed upon by each other, for example, any one of the above-mentioned communication methods can be used, but it is not limited to the above-mentioned communication methods.

[0367] Although the present invention has been described above with reference to the embodiments, it should be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as described in the claims.

Claims

1. A DC-DC converter comprising: A voltage generating unit, for changing an input voltage to generate an output voltage; A first mode driving unit, which generates a first switching signal in order to drive the voltage generating unit in a first mode; a second mode driving unit, configured to generate a second switching signal in order to drive the voltage generating unit in a second mode; a third mode driving unit, configured to generate a third switching signal in order to drive the voltage generating unit in a third mode; as well as A mode control unit is used to use the first switch signal, the second switch signal and the third switch signal to determine the output load of the voltage generating unit, and supply any one of the first switch signal, the second switch signal and the third switch signal to the voltage generating unit corresponding to the output load.

2. The DC-DC converter according to claim 1, wherein: The first mode is a PWM mode, the second mode is a PFM mode, and the third mode is a ULP mode generating the third switching signal having a lower frequency than the second switching signal.

3. The DC-DC converter according to claim 1, further comprising: A first switch connected between the first mode driving unit and the voltage generating unit, and turned on when a first control signal of a gate is supplied from the mode control unit; A second switch connected between the second mode driving section and the voltage generating section, and turned on when a second control signal of a gate is supplied from the mode control section; as well as The third switch is connected between the third mode driving unit and the voltage generating unit, and is turned on when a third control signal for enabling is supplied from the mode control unit.

4. The DC-DC converter according to claim 3, wherein: The voltage generating unit comprises: an inductor connected between an input terminal for supplying the input voltage and an output terminal for outputting the output voltage; a first transistor connected between the input terminal and the inductor, turned on during an on time of the first switch signal, the second switch signal or the third switch signal and turned off during an off time of the first switch signal, the second switch signal or the third switch signal; a second transistor connected between a common node between the first transistor and the inductor and a base potential; a driving unit, receiving any one of the first switching signal, the second switching signal and the third switching signal, and controlling the on and off of the first transistor and the second transistor; and A plurality of resistors are connected in series between the output terminal and the base potential, A feedback voltage is output from a node between the plurality of resistors.

5. The DC-DC converter according to claim 4, wherein: The mode control unit comprises: an on-time checking unit, checking an on-time interval of the first switch signal to generate an on-time control signal; a disconnection time checking unit, for checking a disconnection time interval of the second switch signal to generate a disconnection time control signal; a first counter that counts the second switch signal to generate a first count signal when the feedback voltage is set to a voltage lower than a reference voltage in the second mode driving section; and The second counter counts the third switching signal to generate a second count signal when the feedback voltage is set to a voltage lower than the reference voltage in the third mode driving unit.

6. The DC-DC converter according to claim 5, wherein: The on-time inspection unit is driven when the voltage generation unit is driven in the first mode, When the on-time interval of the first switch signal is longer than a predetermined time, an enabling on-time control signal is generated, and when the on-time interval of the first switch signal is shorter than the predetermined time, a disabling on-time control signal is generated.

7. The DC-DC converter according to claim 6, wherein: When the on-time check section generates the on-time control signal of the gate, the voltage generation section maintains the driving of the first mode, When the on-time control signal for prohibition is generated by the on-time check unit, the voltage generation unit is driven in the second mode.

8. The DC-DC converter according to claim 6, wherein: The on-time checking unit comprises: a current supply unit for generating a plurality of currents; a current control unit including a plurality of resistors for distributing the input voltage; a current selection unit that controls the amount of current supplied from the current supply unit to the first node in response to control by the current control unit; a reset unit, configured to initialize the first node in response to an inverted first switch signal; as well as The on-time control signal generating unit is configured to generate the on-time control signal in accordance with the voltage of the first node.

9. The DC-DC converter according to claim 8, wherein: The current supply unit comprises: a control transistor disposed between the first power source and the current source; and A plurality of mirror transistors are connected to the control transistor to form a current mirror and supply the plurality of currents to the current selection unit.

10. The DC-DC converter according to claim 9, wherein: The current control unit comprises: The plurality of resistors are connected in series to distribute the input voltage, and distribute the input voltage to generate a plurality of distributed voltages; and The plurality of comparators compare any one of the plurality of distributed voltages with the comparison voltage, and respectively output control voltages corresponding to the comparison results.

11. The DC-DC converter according to claim 10, wherein: The current selection unit includes: a plurality of current transistors connected between the first node and any one of the plurality of mirror transistors, and turned on and off according to the control voltage output from any one of the plurality of comparators, Any one of the plurality of currents supplied from the current selection section is directly supplied to the first node.

12. The DC-DC converter according to claim 8, wherein: The reset unit comprises: A first transistor and a second transistor are connected in series between a first power supply and the base potential; a third transistor connected between the first node and the base potential, wherein a gate electrode is connected to a common node of the first transistor and the second transistor, The first transistor is set to be a P type, the second transistor is set to be an N type, and the third transistor is set to be an N type. The inverted first switching signal is supplied to gate electrodes of the first transistor and the second transistor.

13. The DC-DC converter according to claim 8, wherein: The on-time control signal generating unit comprises: A first capacitor connected between the first node and the base potential; a first transmission gate connected between the first node and the second node; a second capacitor connected between the second node and the base potential; a second transmission gate connected between the second node and a third node; a third capacitor connected between the third node and the base potential; as well as A comparator is used to compare the voltage of the first reference power source and the voltage of the third node to output the on-time control signal.

14. The DC-DC converter according to claim 13, wherein: The first transmission gate electrically connects the first node and the second node corresponding to the first switching signal and the inverted first switching signal. The second transmission gate electrically connects the second node and the third node while alternately turning on and off the first transmission gate in response to the inverted first switching signal and the first switching signal.

15. The DC-DC converter according to claim 5, wherein: The off time checking unit is driven when the voltage generating unit is driven in the second mode, When the disconnection time interval of the second switch signal is less than a predetermined time, an enabled disconnection time control signal is generated, and when the disconnection time interval of the second switch signal is greater than the predetermined time, a disabled disconnection time control signal is generated.

16. The DC-DC converter according to claim 15, wherein: When the off-time check unit generates the gated off-time control signal, the voltage generation unit maintains the second mode of driving, When the disabled OFF time control signal is generated by the OFF time checking unit, the voltage generating unit is driven in the third mode.

17. The DC-DC converter according to claim 15, wherein: The disconnection time checking unit comprises: a current supply unit for supplying a predetermined current to the first node; a reset unit, initializing the first node in response to a first switch signal; a control unit that controls a voltage of a second node corresponding to a voltage of the first node; as well as The first output unit is configured to generate the off-time control signal in accordance with the voltage of the second node.

18. The DC-DC converter according to claim 17, wherein: The current supply unit comprises: a control transistor connected between the first power source and the current source; and A mirror transistor is used to be connected with the control transistor to form a current mirror to supply the predetermined current to the first node.

19. The DC-DC converter according to claim 18, wherein: The control unit comprises: a fourth transistor connected between the second node and the base potential, with a gate electrode connected to the first node; a fifth transistor connected between the first power supply and the second node, and having a gate electrode connected to the gate electrode of the control transistor; as well as The first capacitor is connected between the first node and the base potential.

20. The DC-DC converter according to claim 17, wherein: The reset unit comprises: A first transistor and a second transistor are connected in series between a first power supply and the base potential; and a third transistor connected between the first node and the base potential, wherein a gate electrode is connected to a common node of the first transistor and the second transistor, The first transistor is set to be a P type, the second transistor is set to be an N type, and the third transistor is set to be an N type. The second switching signal is supplied to gate electrodes of the first transistor and the second transistor.

21. The DC-DC converter according to claim 17, wherein: The first output unit comprises: a sixth transistor and a seventh transistor, connected in series between the first power supply and the base potential, and having gate electrodes connected to the second node; as well as A D flip-flop, a clock input portion connected to a common node between the sixth transistor and the seventh transistor, The QB terminal of the D flip-flop is connected to the D terminal, and the signal output from the Q terminal of the D flip-flop is the off-time control signal. The sixth transistor is of P type, and the seventh transistor is of N type.

22. The DC-DC converter according to claim 17, wherein: The off-time checking unit further includes a second output unit that generates an on-time changing signal in accordance with a voltage of the first node in order to control the on-time of the second switching signal.

23. The DC-DC converter according to claim 22, wherein: The second output unit comprises: a first transmission gate connected between the first node and a fourth node; a second capacitor connected between the fourth node and the base potential; a second transmission gate connected between the fourth node and a second output terminal outputting the on-time change signal; as well as The third capacitor is connected between the second output terminal and the base potential.

24. The DC-DC converter according to claim 5, wherein: The first counter is driven when the voltage generating unit is driven in the second mode, a first disabled count signal generated when the feedback voltage is set to a voltage higher than the reference voltage in the second mode driving unit, When the second switching signal is repeatedly supplied a predetermined number of times or more while the feedback voltage is set to a voltage lower than the reference voltage in the second mode driving section, a first count signal that is gated is generated.

25. The DC-DC converter according to claim 24, wherein: When the prohibited first count signal is generated, the voltage generating unit maintains the driving of the second mode, When the gated first count signal is generated, the voltage generating section is driven in the first mode.

26. The DC-DC converter according to claim 24, wherein: The first counter comprises: k-bit counter, k is a natural number; an output section, which generates the gated first counting signal when a counting signal is input from the k-bit counter; a first logic gate, which receives as input a power signal set to a high voltage and the second control signal when the output voltage of the DC-DC converter is set to be higher than a target voltage; a second logic gate, used to invert the output of the first logic gate; as well as The third logic gate performs a logic operation on the output of the second logic gate and the second switch signal, and supplies the resultant signal to the k-bit counter.

27. The DC-DC converter according to claim 26, wherein: The first logic gate is a NAND gate, the second logic gate is a NOT gate, and the third logic gate is an AND gate. The output of the first logic gate is input as a reset signal of the k-bit counter.

28. The DC-DC converter according to claim 26, wherein: The output unit is set as a D flip-flop, and the output unit is initialized when a reset signal is supplied from the mode control unit.

29. The DC-DC converter according to claim 5, wherein: The second counter is driven when the voltage generating unit is driven in the third mode, generating a second count signal that is disabled when the feedback voltage is set to a voltage higher than the reference voltage in the third mode driving unit, The gated second count signal is generated when the third switch signal is repeatedly supplied a predetermined number of times or more while the feedback voltage is set to a voltage lower than the reference voltage in the third mode driving unit.

30. The DC-DC converter according to claim 29, wherein: When the prohibited second count signal is generated, the voltage generating unit maintains the driving in the third mode, When the gated second count signal is generated, the voltage generating section is driven in the second mode.

31. The DC-DC converter according to claim 29, wherein: The second counter comprises: p-bit counter, p is a natural number; an output section, which generates the gated second counting signal when a counting signal is input from the p-bit counter; a first logic gate that inputs a power signal set to a high voltage and the third control signal when the output voltage of the DC-DC converter is set to be higher than a target voltage; a second logic gate, used to invert the output of the first logic gate; as well as The third logic gate performs a logic operation on the output of the second logic gate and the third switch signal and supplies the resultant signal to the p-bit counter.

32. The DC-DC converter according to claim 31, wherein: The first logic gate is a NAND gate, the second logic gate is a NOT gate, and the third logic gate is an AND gate. The output of the first logic gate is input as a reset signal of the p-bit counter.

33. The DC-DC converter according to claim 31, wherein: The output unit is set as a D flip-flop, and the output unit is initialized when a reset signal is supplied from the mode control unit.

34. The DC-DC converter according to claim 5, wherein: The mode control unit further comprises: a first logic gate, performing a logic operation on the on-time control signal and the first counting signal; a second logic gate for performing a logic operation on a signal obtained by inverting a power signal set to a high voltage when the output voltage of the DC-DC converter is set to a target voltage or higher and an output of the first logic gate; a third logic gate, performing a logic operation on the output of the second logic gate and the disconnection time control signal; a fourth logic gate, performing a logic operation on the output of the third logic gate and the second counting signal; a fifth logic gate, performing a logic operation on the inverted off-time control signal and the output of the second logic gate; as well as The sixth logic gate inverts the disconnection time control signal to generate the inverted disconnection time control signal.

35. The DC-DC converter of claim 34, wherein: The first logic gate, the second logic gate, and the fourth logic gate are set as OR gates, the third logic gate and the fifth logic gate are set as NOR gates, and the sixth logic gate is set as a NOT gate.

36. The DC-DC converter of claim 34, wherein: The output of the second logic gate is the first control signal, the output of the fourth logic gate is the second control signal, and the output of the fifth logic gate is the third control signal.

37. A display device comprising: A plurality of pixels connected to a plurality of scan lines and a plurality of data lines; and The power supply unit includes a DC-DC converter to supply the required driving power to the plurality of pixels. The DC-DC converter has: A voltage generating unit, for changing an input voltage to generate an output voltage; A first mode driving unit, which generates a first switching signal in order to drive the voltage generating unit in a first mode; a second mode driving unit, configured to generate a second switching signal in order to drive the voltage generating unit in a second mode; a third mode driving unit, configured to generate a third switching signal in order to drive the voltage generating unit in a third mode; as well as A mode control unit is used to use the first switch signal, the second switch signal and the third switch signal to determine the output load of the voltage generating unit, and supply any one of the first switch signal, the second switch signal and the third switch signal to the voltage generating unit corresponding to the output load.

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