Synchronous rectification control system and power supply system

Abstract

The embodiment of the invention discloses a synchronous rectification control system and a power supply system, which are applied to the technical field of electronic information processing, and the synchronous rectification control system comprises a control module, a first side time sequence control module and a second side time sequence control module, the time sequence control module can be correspondingly used for time sequence control of a switch tube in a synchronous rectification system of a bidirectional switch power supply, and when the time sequence control module is in a synchronous rectification mode, the time sequence control module can generate a time sequence control signal according to midpoint voltage signals of two bridge arms in the synchronous rectification system so as to drive a corresponding full-bridge switch tube. Therefore, the signal conversion of the driving full-bridge switching tube is consistent with the conversion of the midpoint voltage signal, so that the condition that the phase of the input voltage and the phase of the current of the resonant inductor after passing through the resonant network are increased along with the frequency conversion of the input voltage at one side of the active working mode is avoided, and the optimal synchronous rectification turn-on time is realized; therefore, the efficiency is maximized.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic information processing, and in particular to a synchronous rectification control system and a power supply system. Background Art

[0002] Synchronous rectification is a technology that uses a dedicated power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with extremely low on-resistance to replace the rectifier diode to reduce rectification loss. It can greatly improve the efficiency of the DC / DC converter and there is no dead zone voltage caused by the Schottky barrier voltage.

[0003] Synchronous rectification technology can significantly improve the conversion efficiency of switching power supplies under high current output conditions, and is widely used in unidirectional switching power supplies, where the current in the synchronous rectification switch tube flows unidirectionally. In recent years, the rise of the energy storage industry has led to an increasing demand for bidirectional power supplies. Since the current in the switch tube flows bidirectionally, traditional synchronous rectification technology cannot meet the bidirectional demand. Summary of the invention

[0004] The embodiments of the present invention provide a synchronous rectification control system and a power supply system, which achieve an optimal synchronous rectification turn-on time.

[0005] An embodiment of the present invention provides a synchronous rectification control system for performing timing control on a synchronous rectification system, wherein the synchronous rectification system comprises: a first-side full-bridge circuit, a resonant network, an isolation transformer, and a second-side full-bridge circuit, wherein the first-side full-bridge circuit and the second-side full-bridge circuit each comprise two bridge arms, and the synchronous rectification control system comprises: A control module, configured to generate a first control signal, a first enable signal, a second control signal, and a second enable signal, wherein the first enable signal is configured to control the first-side timing control module to be in an active working mode, and the second enable signal is configured to control the second-side timing control module to be in a synchronous rectification mode; A first-side timing control module, configured to drive the first full-bridge switch tubes in the two first bridge arms according to the first control signal; The second-side timing control module is used to respectively detect the second midpoint voltage signals corresponding to the two second bridge arms in the second-side full-bridge circuit, and drive the second full-bridge switches in the two second bridge arms according to the second midpoint voltage signal and the second control signal, so that the phase shift time of the synchronous rectification of the second full-bridge switch is the first phase shift time, and the first phase shift time is the voltage conversion time of the second midpoint voltage signal.

[0006] Another aspect of the present invention provides a power supply system, including: a synchronous rectification system and a control system of the synchronous rectification, wherein: The synchronous rectification system comprises: a first-side full-bridge circuit, a resonant network, an isolation transformer, and a second-side full-bridge circuit, wherein the first-side full-bridge circuit and the second-side full-bridge circuit each comprise two bridge arms; The synchronous rectification control system is the synchronous rectification control system as described in one aspect of an embodiment of the present invention.

[0007] It can be seen that the control system of synchronous rectification in the embodiment of the present invention includes a control module, a first-side timing control module and a second-side timing control module, which can perform timing control on the switch tube in the synchronous rectification system applied to the bidirectional switching power supply, and when the timing control module on one side is in the synchronous rectification mode, it can generate a timing control signal according to the midpoint voltage signal of the two bridge arms in the synchronous rectification system to drive the corresponding full-bridge switch tube, so that the signal transformation of driving the full-bridge switch tube is consistent with the transformation of the midpoint voltage signal, so that the phase of the input voltage and the current phase of the resonant inductor after passing through the resonant network will not increase as the frequency of the input voltage on one side of the active working mode changes, thereby achieving a better synchronous rectification turn-on time, thereby maximizing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0009] Figure 1 is a structural schematic diagram of a synchronous rectification system in an embodiment of the present invention; Figure 2a It is a structural schematic diagram of a synchronous rectification control system provided by an embodiment of the present invention; Figure 2b is a structural schematic diagram of another synchronous rectification control system provided by an embodiment of the present invention; Figure 3a is a structural diagram of a first-side timing control module provided by an embodiment of the present invention; Figure 3b is a structural diagram of a second-side timing control module provided by an embodiment of the present invention; Figure 4 is a structural schematic diagram of a synchronous rectification system in a specific embodiment of the present invention; Figure 5It is a structural schematic diagram of a control module in a synchronous rectification control system in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0010] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0011] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0012] The embodiment of the present invention provides a synchronous rectification control system, which is mainly used to perform timing control on the synchronous rectification system, such as Figure 1 As shown, the synchronous rectification system may include: a first-side full-bridge circuit 10, a resonant network 11, an isolation transformer 12, and a second-side full-bridge circuit 13. Specifically: The first-side full-bridge circuit 10 includes two first bridge arms, each of which may include two first full-bridge switch tubes 110; the second-side full-bridge circuit 13 includes two second bridge arms, each of which may include two second full-bridge switch tubes 113, wherein each full-bridge switch tube may specifically be a synchronous rectifier tube, such as a MOSFET. One of the full-bridge circuits on both sides may be input with a high voltage power supply, while the other full-bridge circuit may be input with a low voltage power supply, which is a bidirectional switching current system.

[0013] The resonant network 11 may specifically include two inductors and one capacitor, and is a DC-DC resonant network that may form an LLC resonant circuit or an LC resonant circuit.

[0014] The above-mentioned resonant network 11 and isolation transformer 12 are connected between the first-side full-bridge circuit 10 and the second-side full-bridge circuit 13 .

[0015] If the first-side full-bridge circuit 10 is a high-voltage side full-bridge circuit, and the second-side full-bridge circuit 13 is a low-voltage side full-bridge circuit, the synchronous rectification system may include two operating modes, namely, a buck mode and a boost mode. Specifically: In the buck mode, the two inductors and one capacitor in the resonant network 11 form an LLC resonant circuit, which changes the switching frequency of the full-bridge switch tube in the first-side full-bridge circuit 10 to input a high-voltage power supply, and converts it into a low-voltage output through the isolation transformer 12. At this time, the full-bridge switch tube in the second-side full-bridge circuit 13 is a synchronous rectifier tube.

[0016] In the boost mode, an inductor and a capacitor in the resonant network 11 form an LC resonant circuit, and the other inductor does not participate in the resonance. The switching frequency of the full-bridge switch tube in the second-side full-bridge circuit 13 is changed to input a low-voltage power supply, and it is converted into a high-voltage output through the isolation transformer 12. At this time, the full-bridge switch tube in the first-side full-bridge circuit 10 is a synchronous rectifier tube.

[0017] The synchronous rectification control system of this embodiment includes: a control module 20, a first-side timing control module 21 and a second-side timing control module 22. Figure 2a As shown: The control module 20 is used to generate a first control signal, a first enable signal, a second control signal and a second enable signal. The first enable signal is used to control the first-side timing control module 21 to be in an active working mode, and the second enable signal controls the second-side timing control module 22 to be in a synchronous rectification mode.

[0018] The first-side timing control module 21 is used to drive the first full-bridge switch tubes 110 in the two first bridge arms according to the first control signal.

[0019] The second side timing control module 22 is used to respectively detect the second midpoint voltage signals corresponding to the two second bridge arms in the second side full-bridge circuit 13, and drive the second full-bridge switch tubes 113 in the two second bridge arms according to the second midpoint voltage signal and the second control signal, so that the phase shift time of the synchronous rectification of the second full-bridge switch tube is the first phase shift time, and the first phase shift time is the voltage conversion time of the second midpoint voltage signal. Here, the second midpoint voltage signal is the voltage signal between the two second full-bridge switch tubes 113 in any second bridge arm, and the voltage conversion of the second midpoint voltage signal is in place, which means that one of the two second midpoint voltage signals is a low level, and the other second midpoint voltage signal is a high level.

[0020] Specifically, the second side timing control module 22 will combine the two second midpoint voltage signals to obtain a second comparison signal, then the control module 20 will determine the first phase shift time according to the second comparison signal, and generate the above-mentioned second control signal according to the first phase shift time and output it to the second side timing control module 22, then the second side timing control module 22 will drive the second full-bridge switch tube 113 to follow the above-mentioned second control signal. The first phase shift time can be determined as the time difference between the second comparison signal from the starting moment to the rising edge moment, so that the transformation of the generated second control signal can be consistent with the transformation of the second midpoint voltage signal. In this way, after the first full-bridge switch tube 110 and the second full-bridge switch tube 113 are driven respectively by the first control signal and the second control signal, the phase shift time between the second full-bridge switch tube 113 and the first full-bridge switch tube 110 can be the first phase shift time.

[0021] Here, the second comparison signal can be a signal indicating the difference between the two second midpoint voltage signals. For example, the second comparison signal can be a signal obtained by XORing the two second midpoint voltage signals. When the two second midpoint voltage signals are both high or low, the obtained second comparison signal is a low level, otherwise the obtained second comparison signal is a high level.

[0022] In practical applications, in order to ensure that the transformation of the second control signal generated above is consistent with the transformation of the second midpoint voltage signal, the second control signal can be corrected. Specifically, when the second side timing control module 22 drives the second full-bridge switch tube 113, it can correct the second control signal according to the second midpoint voltage signal to obtain a second corrected signal, so that the transformation of the second corrected signal is consistent with the transformation of the second midpoint voltage signal, and then drive the second full-bridge switch tube 113 to follow the second corrected signal.

[0023] It can be understood that if the first-side full-bridge circuit 10 is input with a high voltage power supply and the second-side full-bridge circuit 13 is input with a low voltage power supply, the first-side timing control module 21 and the second-side timing control module 22 are mainly used to perform timing control when the synchronous rectification system is in the buck mode. In other embodiments, the first-side timing control module 21 and the second-side timing control module 22 can also perform timing control when the synchronous rectification system is in the boost mode, as shown in FIG. Figure 2b As shown: The first enable signal generated by the control module 20 is also used to control the first-side timing control module 21 to be in the synchronous rectification mode, and the second enable signal is also used to control the second-side timing control module 22 to be in the active working mode.

[0024] The first-side timing control module 21 is also used to respectively detect the first midpoint voltage signals corresponding to the two first bridge arms in the first-side full-bridge circuit 10, and drive the first full-bridge switch tubes 110 in the two first bridge arms according to the first midpoint voltage signal and the first control signal, so that the phase shift time of the synchronous rectification of the first full-bridge switch tube 110 is the second phase shift time, and the second phase shift time is the voltage conversion time of the first midpoint voltage signal. The voltage conversion of the first midpoint voltage signal means that one of the two first midpoint voltage signals is a low level, and the other first midpoint voltage signal is a high level.

[0025] Specifically, the first side timing control module 21 will combine the two first midpoint voltage signals to obtain a first comparison signal, then the control module 20 will determine the second phase shift time according to the first comparison signal, and generate the above-mentioned first control signal according to the second phase shift time and output it to the first side timing control module 21, then the first side timing control module 21 will drive the first full-bridge switch tube 110 to follow the above-mentioned first control signal. The second phase shift time can be determined as the time difference between the first comparison signal from the starting moment to the rising edge moment, so that the transformation of the generated first control signal can be consistent with the transformation of the first midpoint voltage signal. In this way, after the first full-bridge switch tube 110 and the second full-bridge switch tube 113 are driven respectively by the first control signal and the second control signal, the phase shift time between the first full-bridge switch tube 110 and the second full-bridge switch tube 113 can be the second phase shift time.

[0026] Here, the first comparison signal may be a signal indicating the difference between the two first midpoint voltage signals. For example, the first comparison signal may be a signal obtained by XORing the two first midpoint voltage signals. When the two first midpoint voltage signals are both at a high level or a low level, the obtained first comparison signal is a low level, otherwise the obtained first comparison signal is a high level.

[0027] In practical applications, in order to ensure that the transformation of the first control signal generated above is consistent with the transformation of the first midpoint voltage signal, the first control signal can be corrected. Specifically, when the first-side timing control module 21 drives the first full-bridge switch tube 110, it can correct the first control signal according to the first midpoint voltage signal to obtain a first corrected signal, so that the transformation of the first corrected signal is consistent with the transformation of the first midpoint voltage signal, and then drive the first full-bridge switch tube 110 to follow the first corrected signal.

[0028] The second-side timing control module 22 is further configured to drive the second full-bridge switch tubes 113 in the two second bridge arms according to the second control signal.

[0029] In a specific embodiment, the structures of the first-side timing control module 21 and the second-side timing control module 22 in the synchronous rectification control system can be the same, wherein the first-side timing control module 21 can be as follows: Figure 3a As shown, it includes: a driving generation circuit 211 composed of an XOR gate U1, two first AND gates U2 and U2', two OR gates U3 and U3' and two second AND gates U4 and U4', and may also include a first midpoint sampling conversion circuit 221 and a first output driving circuit 231. Specifically: The first midpoint voltage signals HV_VS1 and HV_VS2 are connected to the input of the XOR gate U1, and are respectively connected to the input of each first AND gate U2 and U2', the output of the XOR gate U1 is respectively connected to the input of each first AND gate U2 and U2'; the outputs of the two first AND gates U2 and U2' are respectively connected to the inputs of the two OR gates U3 and U3', the first enable signal HV_SYN_EN is respectively connected to each OR gate U3 and U3'; the outputs of the two OR gates U3 and U3' are respectively connected to the two second AND gates U4 and U4', the two first control sub-signals PWM1 and PWM2 in the first control signal are respectively connected to the two second AND gates U4 and U4', and the outputs of the two second AND gates U4 and U4' are respectively connected to the driving end of the first full-bridge switch tube 110. Among them, the output of the XOR gate U1 will be connected to the control module 20.

[0030] In a specific implementation process, when the first midpoint voltage signal is connected to the drive generating circuit 211, a first midpoint sampling conversion circuit 221 can be used. The first midpoint sampling conversion circuit 221 is used to convert the first midpoint voltage signals HV_VS1 and HV_VS2, and connect the converted first midpoint voltage signals VS1 and VS2 to the input of the XOR gate U1.

[0031] When driving the first full-bridge switch tube 110, a driving signal can be directly output to the first full-bridge switch tube 110 through the first output driving circuit 231 (denoted as U5 and U5'). The first output driving circuit 231 is used to convert the output signals of the two second AND gates U4 and U4' into driving signals HV_G1A, HV_G2B, HV_G2A and HV_G1B, and connect the driving signals to the driving end of the first full-bridge switch tube 110.

[0032] Specifically, through the XOR gate U1, the first midpoint voltage signals HV_VS1 and HV_VS2 can be level-converted to obtain the signals VS1 and VS2 to perform XOR calculation, and obtain the first comparison signal In0, which can ensure that when the potentials of the two converted first midpoint voltage signals VS1 and VS2 are changed to the right level, it can be reflected through the first comparison signal In0. For example, when the converted first midpoint voltage signals VS1 and VS2 are both high or low, the first comparison signal In0 is low, and when the converted first midpoint voltage signals VS1 and VS2 are at different levels, the first comparison signal In0 is high.

[0033] Further, the two first AND gates U2 and U2' are combined with the first comparison signal In0 to output synchronous rectification signals In1 and In1', respectively, which respectively reflect the transformation of the converted first midpoint voltage signals VS1 and VS2, and can also reflect the transformation of the first midpoint voltage signals HV_VS1 and HV_VS2. Then, the two OR gates U3 and U3' are respectively combined with the first enable signal, and the first enable signal can make the synchronous rectification process signal ignored when the first side timing control module 21 is in the active working mode, and when the first side timing control module 21 is in the synchronous rectification mode, the synchronous rectification process signals In2 ​​and In2' are output respectively. Finally, in the synchronous rectification mode, the two second AND gates U4 and U4' can respectively correct the two first control sub-signals PWM1 and PWM2, that is, respectively correct them through the synchronous rectification process signals In2 ​​and In2', and the correction time is the first phase shift time, so that the transformation of the obtained first corrected signal is consistent with the transformation of the first midpoint voltage signal.

[0034] Further, the second-side timing control module 22 can be as follows Figure 3b As shown, it includes: a driving generation circuit 212 composed of an XOR gate U6, two first AND gates U7 and U7', two OR gates U8 and U8' and two second AND gates U9 and U9', and may also include a second midpoint sampling conversion circuit 222 and a second output driving circuit 232. Specifically: The second midpoint voltage signals LV_VS1 and LV_VS2 are connected to the input of the XOR gate U6, and are respectively connected to the input of each first AND gate U7 and U7', the output of the XOR gate U6 is respectively connected to the input of each first AND gate U7 and U7'; the outputs of the two first AND gates U7 and U7' are respectively connected to the inputs of the two OR gates U8 and U8', the second enable signal LV_SYN_EN is respectively connected to each OR gate U8 and U8'; the outputs of the two OR gates U8 and U8' are respectively connected to the two second AND gates U9 and U9', the two second control sub-signals PWM3 and PWM4 in the second control signal are respectively connected to the two second AND gates U9 and U9', and the outputs of the two second AND gates U9 and U9' are respectively connected to the driving end of the second full-bridge switch tube 130. Among them, the output of the XOR gate U6 will be connected to the control module 20.

[0035] In a specific implementation process, when the second midpoint voltage signal is connected to the drive generating circuit 212, a second midpoint sampling conversion circuit 222 can be used. The second midpoint sampling conversion circuit 222 is used to convert the second midpoint voltage signals LV_VS1 and LV_VS2, and connect the converted second midpoint voltage signals VS3 and VS4 to the input of the XOR gate U6.

[0036] When driving the second full-bridge switch tube 113, a driving signal can be directly output to the second full-bridge switch tube 113 through a second output driving circuit 232 (denoted as U10 and U10'). The second output driving circuit 232 is used to convert the output signals of the two second AND gates U9 and U9' into driving signals LV_G3A, LV_G4B, LV_G4A and LV_G3B, and connect the driving signals to the driving end of the second full-bridge switch tube 130.

[0037] Specifically, the XOR gate U6 can be used to perform XOR calculation on the signals VS3 and VS4 obtained after level conversion of the second midpoint voltage signals LV_VS1 and LV_VS2 to obtain the second comparison signal In0', which can ensure that when the potentials of the two converted second midpoint voltage signals VS3 and VS4 are changed to the right level, it can be reflected through the second comparison signal In0'. For example, when the converted second midpoint voltage signals VS3 and VS4 are both high or low, the second comparison signal In0' is low; when the converted second midpoint voltage signals VS3 and VS4 are at different levels, the second comparison signal In0' is high.

[0038] Further, the two first AND gates U7 and U7' are combined with the second comparison signal In0' to output synchronous rectification signals In3 and In3' respectively, which respectively reflect the transformation of the converted second midpoint voltage signals VS3 and VS4, and can also reflect the transformation of the second midpoint voltage signals LV_VS1 and LV_VS2. Then, the two OR gates U8 and U8' are respectively combined with the second enable signal, and the second enable signal can make the synchronous rectification process signal ignored when the second side timing control module 22 is in the active working mode, and when the second side timing control module 22 is in the synchronous rectification mode, the synchronous rectification process signals In4 and In4' are output respectively. Finally, in the synchronous rectification mode, the two second AND gates U9 and U9' can respectively correct the two second control sub-signals PWM3 and PWM4, that is, respectively correct them through the synchronous rectification process signals In4 and In4', and the correction time is the second phase shift time, so that the transformation of the obtained second corrected signal is consistent with the transformation of the second midpoint voltage signal.

[0039] It can be seen that the control system of synchronous rectification in this embodiment includes a control module 20, a first-side timing control module 21 and a second-side timing control module 22, which can perform timing control on the switch tube in the synchronous rectification system of the bidirectional switching power supply, and when the timing control module on one side is in the synchronous rectification mode, it can generate a timing control signal according to the midpoint voltage signal of the two bridge arms in the synchronous rectification system to drive the corresponding full-bridge switch tube, so that the signal transformation of driving the full-bridge switch tube is consistent with the transformation of the midpoint voltage signal. In this way, as the frequency of the input voltage on one side of the active working mode changes, the phase of the input voltage and the current phase of the resonant inductor after passing through the resonant network will not increase, thereby achieving a better synchronous rectification turn-on time, thereby maximizing efficiency.

[0040] A specific embodiment of the present invention provides a synchronous rectification control system, which is mainly used to perform timing control on the synchronous rectification system. In this embodiment, the synchronous rectification system can be as follows: Figure 4 As shown, where: The first side full-bridge circuit 10 is specifically a high-voltage side full-bridge circuit, and a high-voltage power supply HVDC is input. The first full-bridge switch tubes included in the high-voltage side full-bridge circuit are Q1A, Q2A, Q1B and Q2B, and the signals driving these full-bridge switch tubes are HV_G1A, HV_G2A, HV_G1B and HV_G2B respectively, and the first midpoint voltage signals of the two first bridge arms are HV_VS1 and HV_VS2 respectively; the second side full-bridge circuit 13 is specifically a low-voltage side full-bridge circuit, and a low-voltage power supply LVDC is input. The second full-bridge switch tubes included in the low-voltage side full-bridge circuit are Q3A, Q4A, Q3B and Q4B, and the signals driving these full-bridge switch tubes are LV_G3A, LV_G4A, LV_G3B and LV_G4B respectively, and the second midpoint voltage signals of the two second bridge arms are LV_VS1 and LV_VS2 respectively.

[0041] The resonant network 11 is specifically a DC-DC resonant network, including an inductor Lr, an inductor Lm and a capacitor Cr, and the isolation transformer 12 is T1.

[0042] The first side timing control module 21 and the second side timing control module 22 in the synchronous rectification control system of this embodiment can be specifically as described above. Figure 3a and Figure 3b As shown, the control module 20 in the control system is specifically as follows Figure 5 The controller U0 shown can generate a first enable signal HV_SYN_EN, a second enable signal LV_SYN_EN, two first control sub-signals PWM1 and PWM2 in the first control signal, and two second control sub-signals PWM3 and PWM4 in the second control signal.

[0043] Thus, in this embodiment, the synchronous rectification control system can perform timing control on the synchronous rectification system in the following two modes of the synchronous rectification system: 1. Synchronous rectification system in buck mode When the synchronous rectification system is in the buck mode, Lr, Cr and Lm in the resonant network 11 form an LLC resonant circuit, and the switching frequency of the first full-bridge switch tubes Q1A, Q1B, Q2A and Q2B in the high-voltage side full-bridge circuit is changed to convert the high-voltage input voltage HVDC into a low-voltage output voltage LVDC through the isolation transformer T1. The second full-bridge switch tubes Q3A, Q3B, Q4A and Q4B in the low-voltage side full-bridge circuit are synchronous rectifier tubes. In this case, in the synchronous rectification control system: (1) When the synchronous rectification system is in the buck mode, the first enable signal HV_SYN_EN generated by the controller U0 is low, controlling the first-side timing control module 21 to be in the active working mode; and generating two first control sub-signals PWM1 and PWM2. These two first control sub-signals have a certain dead zone, a duty cycle of about 50%, and high and low complementarity, and are square waves with variable frequency.

[0044] (2) The first midpoint sampling conversion circuit 221 in the first-side timing control module 21 will collect the first midpoint voltage signals HV_VS1 and HV_VS2 of the two bridge arms of the high-voltage side full-bridge circuit in the synchronous rectification system, and the obtained converted signals VS1 and VS2 are output to the two first AND gates U2 and U2' respectively, and are also connected to the input of the XOR gate U1 respectively, so that the XOR gate U1 outputs the signal In0 according to the two converted signals VS1 and VS2.

[0045] The first AND gate U2 outputs a signal In1 according to the converted signal VS1 and the signal In0, and the first AND gate U2' outputs a signal In1' according to the converted signal VS2 and the signal In0. The OR gate U3 outputs a signal In2 according to the signal In1 and the first enable signal HV_SYN_EN, and the OR gate U3' outputs a signal In2' according to the signal In1' and the first enable signal HV_SYN_EN, and the signals In2 ​​and In2' are high. The second AND gate U4 outputs a PWM signal following the first control sub-signal PWM1 according to the signal In2 and a first control sub-signal PWM1, and the second AND gate U4' outputs a PWM signal following the first control sub-signal PWM2 according to the signal In2' and another first control sub-signal PWM2.

[0046] The outputs of the second AND gates U4 and U4' are respectively connected to two first output drive circuits 231 (denoted as U5 and U5') to output drive signals to drive the first full-bridge switch tubes Q1A and Q2B and Q2A and Q1B respectively.

[0047] (3) The second midpoint sampling conversion circuit 222 in the second side timing control module 22 will collect the second midpoint voltage signals LV_VS1 and LV_VS2 of the two bridge arms of the low-voltage side full-bridge circuit in the synchronous rectification system, and the obtained converted signals VS3 and VS4 are output to the two first AND gates U7 and U7' respectively, and are also connected to the input of the XOR gate U6 respectively, so that the XOR gate U6 outputs the signal In0' according to the two converted signals VS3 and VS4.

[0048] The first AND gate U7 outputs the signal In3 according to the converted signal VS3 and the signal In0', and the first AND gate U7' outputs the signal In3' according to the converted signal VS4 and the signal In0'. The OR gate U8 outputs the signal In4 according to the signal In3 and the second enable signal LV_SYN_EN, and the OR gate U8' outputs the signal In4' according to the signal In3' and the second enable signal LV_SYN_EN. The second enable signal LV_SYN_EN is constantly at a low level, and the signals In4 and In4' follow the signals In3 and In3' respectively. The second AND gate U9 outputs a signal to the second output drive circuit 232 (denoted as U10) according to the signal In4 and a second control sub-signal PWM3, and the second AND gate U9' outputs a signal to the second output drive circuit 232 (denoted as U10') according to the signal In4' and another second control sub-signal PWM4.

[0049] The second output driving circuit 232 outputs driving signals to drive the second full-bridge switch tubes Q3A and Q4B and Q4A and Q3B respectively.

[0050] In this process, the controller U0 can calculate the first phase shift time of the synchronous rectification (relative to the rising edge signal of In0) according to the rising edge signal of the signal In0', and set the starting point of the high-level signals of the two second control sub-signals PWM3 and PWM4 based on the first phase shift time, and the falling edges of the two second control sub-signals PWM3 and PWM4 are moved backward by the first phase shift time based on the falling edges of the above-mentioned two first control sub-signals PWM1 and PWM2 to set the end point of the high-level signals of the two second control sub-signals PWM3 and PWM4.

[0051] Since the signal In0′ is output according to the two second midpoint voltage signals, the first phase shift time is determined based on the second midpoint voltage signal.

[0052] Since the signal driving the first full-bridge switch tube 110 follows the first control sub-signals PWM1 and PWM2, and the signal driving the second full-bridge switch tube 113 follows the second control sub-signals PWM3 and PWM4, the phase shift between the second full-bridge switch tube 113 and the first full-bridge switch tube 110 is the first phase shift time.

[0053] (4) When the synchronous rectification system is in the buck mode, the XOR gate U6 in the second-side timing control module 22 is an interlocking circuit. When the converted signals VS3 and VS4 pass through a high or low level, the output signal In0' is a low level, thereby making the synchronous rectification signals In4 and In4' low, turning off the synchronous rectification drive.

[0054] The function of the two first AND gates U7 and U7' is to insert the signal In0' into the synchronous rectification signal of the converted signals VS3 and VS4, thereby outputting the synchronous rectification signals In4 and In4'. The function of the two OR gates U8 and U8' is to output the synchronous rectification signals In4 and In4' under the condition of the buck mode. The function of the two second AND gates U9 and U9' is to add the synchronous rectification signals In4 and In4' to the second control sub-signals PWM3 and PWM4 respectively to improve reliability.

[0055] 2. Synchronous rectification system in boost mode When the synchronous rectification system is in boost mode, Lr and Cr in the resonant network 11 form an LC resonant circuit, and the switching frequency of the second full-bridge switch tubes Q3A, Q3B, Q4A and Q4B in the low-voltage side full-bridge circuit is changed to convert the low-voltage input voltage LVDC into a high-voltage output voltage HVDC through the isolation transformer T1. The first full-bridge switch tubes Q1A, Q1B, Q2A and Q2B in the high-voltage side full-bridge circuit are synchronous rectifier tubes. In this case, in the synchronous rectification control system: (1) When the synchronous rectification system is in the boost mode, the second enable signal LV_SYN_EN generated by the controller U0 is low, controlling the second-side timing control module 22 to be in the active working mode; and generating two second control sub-signals PWM3 and PWM4. These two second control sub-signals have a certain dead zone, a duty cycle of about 50%, and high and low complementarity, and are square waves with variable frequency.

[0056] (2) The second midpoint sampling conversion circuit 222 in the second-side timing control module 22 will collect the second midpoint voltage signals LV_VS1 and LV_VS2 of the two bridge arms of the low-voltage side full-bridge circuit in the synchronous rectification system, and the obtained converted signals VS3 and VS4 are output to the two first AND gates U7 and U7' respectively, and are also connected to the input of the XOR gate U6 respectively, so that the XOR gate U6 outputs the signal In0' according to the two converted signals VS3 and VS4.

[0057] The first AND gate U7 outputs the signal In3 according to the converted signal VS3 and the signal In0', and the first AND gate U7' outputs the signal In3' according to the converted signal VS4 and the signal In0'. The OR gate U8 outputs the signal In4 according to the signal In4 and the second enable signal LV_SYN_EN, and the OR gate U8' outputs the signal In4' according to the signal In3' and the second enable signal LV_SYN_EN, and the signals In4 and In4' are high. The second AND gate U9 outputs the PWM signal following the second control sub-signal PWM3 according to the signal In4 and a second control sub-signal PWM3, and the second AND gate U9' outputs the PWM signal following the second control sub-signal PWM4 according to the signal In4' and another second control sub-signal PWM4.

[0058] The outputs of the second AND gates U9 and U9' are respectively connected to two second output drive circuits 232 (denoted as U10 and U10') to output drive signals, respectively driving the second full-bridge switch tubes Q3A and Q4B and Q4A and Q3B, following the second control sub-signal.

[0059] (3) The first midpoint sampling conversion circuit 221 in the first-side timing control module 21 will collect the first midpoint voltage signals HV_VS1 and HV_VS2 of the two bridge arms of the high-voltage side full-bridge circuit in the synchronous rectification system, and the obtained converted signals VS1 and VS2 are output to the two first AND gates U2 and U2' respectively, and are also connected to the input of the XOR gate U1 respectively, so that the XOR gate U1 outputs the signal In0 according to the two converted signals VS1 and VS2.

[0060] The first AND gate U2 outputs the signal In1 according to the converted signal VS1 and the signal In0, and the first AND gate U2' outputs the signal In1' according to the converted signal VS2 and the signal In0. The OR gate U3 outputs the signal In2 according to the signal In1 and the first enable signal HV_SYN_EN, and the OR gate U3' outputs the signal In2' according to the signal In1' and the first enable signal HV_SYN_EN. The first enable signal HV_SYN_EN is always at a low level, and the signals In2 ​​and In2' follow the signals In1 and In1' respectively. The second AND gate U4 outputs a signal to the first output drive circuit 231 (denoted as U5) according to the signal In2 and a first control sub-signal PWM1, and the second AND gate U4' outputs a signal to the first output drive circuit 231 (denoted as U5') according to the signal In2' and another first control sub-signal PWM2.

[0061] The first output driving circuit 231 outputs driving signals to drive the first full-bridge switch tubes Q1A and Q2B and Q2A and Q1B respectively.

[0062] In this process, the controller U0 can calculate the second phase shift time of the synchronous rectification (relative to the rising edge signal of In0') according to the rising edge signal of the signal In0, and set the starting point of the high-level signal of the two first control sub-signals PWM1 and PWM2 based on the second phase shift time, and the falling edges of the two first control sub-signals PWM1 and PWM2 are moved backward by the second phase shift time based on the falling edges of the above-mentioned two second control sub-signals PWM3 and PWM4 to set the end point of the high-level signals of the two first control sub-signals PWM1 and PWM2.

[0063] Since the signal In0 is output according to the two first midpoint voltage signals, the second phase shift time is determined based on the first midpoint voltage signal.

[0064] Since the signal driving the second full-bridge switch tube 113 follows the second control sub-signals PWM3 and PWM4, and the signal driving the first full-bridge switch tube 110 follows the first control sub-signals PWM1 and PWM2, the phase shift between the first full-bridge switch tube 110 and the second full-bridge switch tube 113 is the second phase shift time.

[0065] (4) When the synchronous rectification system is in the boost mode, the XOR gate U1 in the first-side timing control module 21 is an interlocking circuit. When the converted signals VS1 and VS2 pass through a high or low level, the output signal In0 is a low level, thereby making the synchronous rectification signals In2 ​​and In2' low, turning off the synchronous rectification drive.

[0066] The function of the two first AND gates U2 and U2' is to insert the signal In0 into the synchronous rectification signal of the converted signals VS1 and VS2, thereby outputting the synchronous rectification signals In2 ​​and In2'. The function of the two OR gates U3 and U3' is to output the synchronous rectification signals In2 ​​and In2' under the condition of the boost mode. The function of the two second AND gates U4 and U4' is to add the synchronous rectification signals In2 ​​and In2' to the first control sub-signals PWM1 and PWM2 respectively to improve reliability.

[0067] An embodiment of the present invention also provides a power supply system, which is a bidirectional switching power supply, and mainly applies the above-mentioned synchronous rectification system. The synchronous rectification system may include: a first-side full-bridge circuit, a resonant network, an isolation transformer and a second-side full-bridge circuit, and the first-side full-bridge circuit and the second-side full-bridge circuit respectively include two bridge arms; and the control system of the synchronous rectification is the control system of the synchronous rectification as described in the above-mentioned embodiment, which will not be repeated here.

[0068] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0069] The above is a detailed introduction to a synchronous rectification control system and a power supply system provided by an embodiment of the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A synchronous rectification control system, characterized in that: Used to perform timing control on a synchronous rectification system, the synchronous rectification system comprising: a first-side full-bridge circuit, a resonant network, an isolation transformer, and a second-side full-bridge circuit, the first-side full-bridge circuit and the second-side full-bridge circuit each comprising two bridge arms, and the synchronous rectification control system comprising: A control module, configured to generate a first control signal, a first enable signal, a second control signal, and a second enable signal, wherein the first enable signal is configured to control the first-side timing control module to be in an active working mode, and the second enable signal is configured to control the second-side timing control module to be in a synchronous rectification mode; A first-side timing control module, used for driving the first full-bridge switch tubes in the two first bridge arms according to the first control signal; The second-side timing control module is used to respectively detect the second midpoint voltage signals corresponding to the two second bridge arms in the second-side full-bridge circuit, and drive the second full-bridge switches in the two second bridge arms according to the second midpoint voltage signal and the second control signal, so that the phase shift time of the synchronous rectification of the second full-bridge switch is the first phase shift time, and the first phase shift time is the voltage conversion time of the second midpoint voltage signal.

2. The system according to claim 1, characterized in that The second-side timing control module is specifically configured to obtain a second comparison signal according to the second midpoint voltage signal, the control module determines the first phase shift time according to the second comparison signal, and generates the second control signal according to the first phase shift time, and the second-side timing control module drives the second full-bridge switch tube to follow the second control signal; The first phase shift time is the time difference between the start time and the rising edge time of the second comparison signal.

3. The system according to claim 2, characterized in that The second-side timing control module drives the second full-bridge switch tube to follow the second control signal, specifically including: The second-side timing control module corrects the second control signal according to the second midpoint voltage signal to obtain a second corrected signal, and drives the second full-bridge switch tube to follow the second corrected signal.

4. The system according to claim 1, characterized in that The first enable signal generated by the control module is also used to control the first-side timing control module to be in a synchronous rectification mode, and the second enable signal is also used to control the second-side timing control module to be in an active working mode; The first-side timing control module is used to respectively detect the first midpoint voltage signals respectively corresponding to the two first bridge arms in the first-side full-bridge circuit, and drive the first full-bridge switch tubes in the two first bridge arms according to the first midpoint voltage signal and the first control signal, so that the phase shift time of the synchronous rectification of the first full-bridge switch tube is the second phase shift time, and the second phase shift time is the voltage conversion time of the first midpoint voltage signal; The second-side timing control module is further used to drive the second full-bridge switch tubes in the two second bridge arms according to the second control signal.

5. The system according to claim 4, characterized in that The first-side timing control module is specifically used to obtain a first comparison signal based on the two first midpoint voltage signals, the control module determines the second phase shift time based on the first comparison signal, and generates the first control signal based on the second phase shift time, and the first-side timing control module drives the first full-bridge switch tube to follow the first control signal; the second phase shift time is the time difference between the starting time and the rising edge time of the first comparison signal.

6. The system according to any one of claims 1 to 5, characterized in that: The first-side timing control module includes: an XOR gate, two first AND gates, two OR gates and two second AND gates; The first midpoint voltage signal is connected to the input of the XOR gate and is respectively connected to the input of each of the first AND gates, and the output of the XOR gate is respectively connected to the input of each of the first AND gates; The outputs of the two first AND gates are respectively connected to the inputs of the two OR gates, and the first enable signal is respectively connected to each of the OR gates; The outputs of the two OR gates are respectively connected to the two second AND gates, the two first control sub-signals in the first control signal are respectively connected to the two second AND gates, and the outputs of the two second AND gates are respectively connected to the driving end of the first full-bridge switch tube.

7. The system according to claim 6, characterized in that The first-side timing control module further includes: a first midpoint sampling conversion circuit and a first output drive circuit, wherein: The first midpoint sampling conversion circuit is used to convert the first midpoint voltage signal and connect the converted first midpoint voltage signal to the input of the XOR gate; The first output drive circuit is used to convert the output signals of the two second AND gates into drive signals, and connect the drive signals to the drive end of the first full-bridge switch tube.

8. The system according to any one of claims 1 to 5, characterized in that: The second-side timing control module includes: an XOR gate, two first AND gates, two OR gates and two second AND gates; The second midpoint voltage signal is connected to the input of the XOR gate and is respectively connected to the input of each of the first AND gates, and the output of the XOR gate is respectively connected to the input of each of the first AND gates; The outputs of the two first AND gates are respectively connected to the inputs of the two OR gates, and the second enable signal is respectively connected to each of the OR gates; The outputs of the two OR gates are respectively connected to the two second AND gates, the two second control sub-signals in the second control signal are respectively connected to the two second AND gates, and the outputs of the two second AND gates are respectively connected to the driving end of the second full-bridge switch tube.

9. The system according to claim 8, characterized in that The second-side timing control module further includes: a second midpoint sampling conversion circuit and a second output drive circuit, wherein: The second midpoint sampling conversion circuit is used to convert the second midpoint voltage signal and connect the converted second midpoint voltage signal to the input of the XOR gate in the second-side timing control module; The second output drive circuit is used to convert the output signal of the second AND gate in the two second-side timing control modules into a drive signal, and connect the drive signal to the drive end of the second full-bridge switch tube.

10. A power supply system, characterized in that: include: A synchronous rectification system and a control system of the synchronous rectification, wherein: The synchronous rectification system comprises: a first-side full-bridge circuit, a resonant network, an isolation transformer, and a second-side full-bridge circuit, wherein the first-side full-bridge circuit and the second-side full-bridge circuit each comprise two bridge arms; The synchronous rectification control system is the synchronous rectification control system as claimed in any one of claims 1 to 9.

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