Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a substrate; forming a gate structure protruding out of the substrate; removing a part of thickness of the substrate on one side of the gate structure, so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure; and executing a source-drain injection process on the substrate at two sides of the gate structure, forming a source region in the substrate at one side of the gate structure, and forming a drain region in the substrate at the other side of the gate structure. According to the technical scheme in the embodiment of the invention, the performance of the formed semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] As the feature size of integrated circuits continues to decrease, in order to adapt to the smaller feature size, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also continuously shortened accordingly.

[0004] However, as the device channel length shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's ability to control the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage, making sub-threshold leakage, the so-called short-channel effect (SCE), more likely to occur. Summary of the invention

[0005] The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the formed semiconductor structure.

[0006] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, the method comprising:

[0007] providing a substrate, the substrate comprising a backing;

[0008] forming a gate structure protruding from the substrate;

[0009] Removing a portion of the thickness of the substrate on one side of the gate structure so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure;

[0010] A source-drain implantation process is performed on the substrate at both sides of the gate structure to form a source region in the substrate at one side of the gate structure and a drain region in the substrate at the other side of the gate structure.

[0011] Optionally, a height difference between a top surface of the substrate on one side of the gate structure and a top surface of the substrate on the other side of the gate structure is 10 nm to 100 nm.

[0012] Optionally, a partial thickness of the substrate on one side of the gate structure is removed by an etch-back process, so that a top surface of the substrate on one side of the gate structure is lower than a top surface of the substrate on the other side of the gate structure.

[0013] Optionally, after removing a portion of the thickness of the substrate on one side of the gate structure so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure, the method further includes: performing an ion implantation process on the substrate on one side of the gate structure so that the substrate on one side of the gate structure is connected by implanted ions to form a conductive power line;

[0014] After forming the conductive source wire, a source-drain implantation process is performed on the substrate at both sides of the gate structure to form a source region in the substrate at one side of the gate structure and a drain region in the substrate at the other side of the gate structure.

[0015] Optionally, the process parameters of the ion implantation process include: the implanted ions are arsenic to phosphorus, and the implantation dose is 1E14 atoms / cm 2 To 9E15 atoms / cm 2 , the implantation energy is 5KeV to 50KeV.

[0016] Optionally, after forming a discrete gate structure on the substrate and before removing a portion of the thickness of the substrate on one side of the gate structure so that the top surface of the substrate on one side of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the substrate on the other side of the gate structure, the method further includes: forming a sidewall structure on the sidewall of the gate structure.

[0017] Optionally, before forming the sidewall structure on the sidewall of the gate structure, the method further comprises: performing a light doping process to form light doping regions in the substrate on both sides of the gate structure.

[0018] Optionally, the gate structure includes a gate insulating layer, a floating gate layer located on the gate insulating layer, an inter-gate dielectric layer located on the floating gate layer, and a control gate layer located on the inter-gate dielectric layer.

[0019] Optionally, the base further comprises an isolation structure located within the substrate;

[0020] The steps of forming the isolation structure and the gate structure and making the top surface of the substrate on one side of the gate structure lower than the top surface of the substrate on the other side of the gate structure include: patterning a portion of the thickness of the substrate to form a first trench; forming a gate insulating film on the bottom and sidewalls of the first trench; forming a floating gate material layer filling the first trench on the gate insulating film; patterning the floating gate material layer and a portion of the thickness of the substrate to form a second trench; filling the second trench with an isolation material layer; removing a portion of the height of the isolation material layer to form the remaining isolation material layer as an isolation structure; forming a conformal covering layer of the isolation structure, the substrate and The invention relates to a method for forming a floating gate material layer, an initial inter-gate dielectric layer of the floating gate material layer; forming a control gate material layer on the initial inter-gate dielectric layer; patterning the control gate material layer, the initial inter-gate dielectric layer and the floating gate material layer until the top surface of a portion of the substrate at the bottom of the first trench is exposed, and forming the floating gate layer, the inter-gate dielectric layer located on the floating gate layer and the control gate layer located on the inter-gate dielectric layer and spanning the floating gate layer on the gate insulating layer, wherein the gate insulating layer, the floating gate layer, the inter-gate dielectric layer and the control gate layer constitute the gate structure, and make the top surface of the substrate on one side of the gate structure lower than the top surface of the substrate on the other side of the gate structure.

[0021] Optionally, before forming the first groove, a liner layer is further formed on the substrate;

[0022] During patterning of the substrate of a partial thickness, the liner layer is also patterned;

[0023] In the process of patterning the control gate material layer, the initial inter-gate dielectric layer and the floating gate material layer, after patterning the control gate material layer and the initial inter-gate dielectric layer to form the inter-gate dielectric layer and the control gate layer, the liner layer is used as an etching stop layer to remove the floating gate material layer located on one side of the control gate layer and in the first trench until the top surface of a portion of the substrate at the bottom of the first trench is exposed, so that the floating gate material layer forms a floating gate layer, and the top surface of the substrate located on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure.

[0024] Optionally, the pad layer includes a first sub-pad layer and a second sub-pad layer located on the first sub-pad layer.

[0025] Optionally, a material of the first subpad layer includes silicon oxide, and a material of the second subpad layer includes silicon nitride.

[0026] Optionally, after performing a source-drain implantation process on the substrate at both sides of the gate structure, the method further comprises: performing a metal silicide process to convert the top of the gate structure into a first metal silicide layer.

[0027] Accordingly, an embodiment of the present invention further provides a semiconductor structure, including:

[0028] a substrate, the substrate comprising a backing;

[0029] A gate structure protruding from the substrate;

[0030] A source region located in the substrate on one side of the gate structure;

[0031] The drain region is located in the substrate at the other side of the gate structure, and the top surface of the drain region is higher than the top surface of the source region.

[0032] Optionally, a height difference between a top surface of the source region and a top surface of the drain region is 10 nm to 100 nm.

[0033] Optionally, the semiconductor structure further includes: a sidewall structure located on a sidewall of the gate structure.

[0034] Optionally, the semiconductor structure further includes: a lightly doped region located in the substrate on both sides of the gate structure.

[0035] Optionally, the gate structure includes a gate insulating layer, a floating gate layer located on the gate insulating layer, an inter-gate dielectric layer located on the floating gate layer, and a control gate layer located on the inter-gate dielectric layer.

[0036] Optionally, the base further includes an isolation structure located within the substrate.

[0037] Optionally, the semiconductor structure further includes: a first metal silicide layer located on top of the gate structure.

[0038] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0039] The method for forming a semiconductor structure provided by an embodiment of the present invention includes: providing a base, the base including a substrate; forming a gate structure protruding from the substrate; removing part of the thickness of the substrate on one side of the gate structure so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure; performing a source-drain implantation process on the substrate on both sides of the gate structure to form a source region in the substrate on one side of the gate structure and a drain region in the substrate on the other side of the gate structure.

[0040] The method for forming a semiconductor structure provided by an embodiment of the present invention first removes part of the thickness of the substrate on one side of the gate structure so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure, and then performs a source-drain implantation process on the substrate on both sides of the gate structure to form a source region in the substrate on one side of the gate structure and a drain region in the substrate on the other side of the gate structure, so that the top surface of the source region is lower than the top surface of the drain region, thereby increasing the channel length between the source region and the drain region, avoiding the occurrence of a short channel effect, and correspondingly improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figures 1 to 14 It is a schematic diagram of an intermediate structure formed in each step of an embodiment of a method for forming a semiconductor structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] As can be seen from the background technology, the performance of current semiconductor structures still needs to be improved.

[0043] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a base, the base comprising a substrate; forming a gate structure protruding from the substrate; removing part of the thickness of the substrate on one side of the gate structure, so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure; performing a source-drain implantation process on the substrate on both sides of the gate structure, forming a source region in the substrate on one side of the gate structure, and forming a drain region in the substrate on the other side of the gate structure.

[0044] The method for forming a semiconductor structure provided by an embodiment of the present invention first removes part of the thickness of the substrate on one side of the gate structure so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure, and then performs a source-drain implantation process on the substrate on both sides of the gate structure to form a source region in the substrate on one side of the gate structure and a drain region in the substrate on the other side of the gate structure, so that the top surface of the source region is lower than the top surface of the drain region, thereby increasing the channel length between the source region and the drain region, avoiding the occurrence of a short channel effect, and correspondingly improving the performance of the formed semiconductor structure.

[0045] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] See also Figure 1 , a base (not shown) is provided, wherein the base includes a substrate 100 .

[0047] The substrate 100 provides a process platform for the subsequent formation of a flash memory. In this embodiment, the substrate 100 is used to provide a process platform for the subsequent formation of a NOR Flash device.

[0048] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In some other embodiments, the substrate may also include a semiconductor layer and a second semiconductor layer epitaxially grown on the semiconductor layer, the semiconductor layer is used to provide a process basis for the subsequent formation of the substrate, and the second semiconductor layer is used to provide a process basis for the subsequent formation of the fin. In other embodiments, the substrate may also include other functional layers to be etched, and the target pattern is formed by etching the functional layers to be etched.

[0049] Combined with reference Figures 2 to 9 , forming a gate structure 200 protruding from the substrate 100 .

[0050] In this embodiment, the substrate 100 includes a storage region I. Accordingly, the gate structure 200 includes a storage gate structure 210 protruding from the storage region I of the substrate 100 .

[0051] Specifically, the storage gate structure 210 includes a gate insulating layer 211 , a floating gate layer 212 located on the gate insulating layer 211 , an inter-gate dielectric layer 213 located on the floating gate layer 212 , and a control gate layer 214 located on the inter-gate dielectric layer 213 .

[0052] The gate insulating layer 211 serves as a tunnel oxide (TO) layer of the NOR flash memory device, and is used to achieve electrical isolation between the substrate 100 and the floating gate layer 212, thereby preventing electrons from entering the substrate 100 and further reducing the loss of electrons. That is, the gate insulating layer 211 is used to prevent the loss of data stored in the NOR flash memory device.

[0053] In this embodiment, the gate insulating layer 211 is made of silicon oxide. In other embodiments, the gate insulating layer can also be made of other suitable materials.

[0054] The floating gate layer 212 is used to store electrons during the operation of the NOR flash memory device.

[0055] In this embodiment, the floating gate layer 212 is made of polysilicon.

[0056] The inter-gate dielectric layer 213 is used as an insulating layer between the floating gate layer 212 and the control gate layer 214 to achieve electrical isolation between the floating gate layer 212 and the control gate layer 214 .

[0057] In this embodiment, the inter-gate dielectric layer 213 is a stacked structure. Specifically, the inter-gate dielectric layer 213 is an oxide layer-nitride layer-oxide layer (Oxide-Nitride-Oxide, ONO) structure, wherein the oxide layer is a silicon oxide layer, and the nitride layer is a silicon oxide layer. In other embodiments, the inter-gate dielectric layer can also be a single-layer structure.

[0058] The control gate layer 214 is used as a part of a word line of a NOR flash memory device.

[0059] In this embodiment, the material of the control gate layer 214 is the same as that of the floating gate layer 212 , that is, the material of the control gate layer 214 is polysilicon.

[0060] In this embodiment, the base further includes an isolation structure 105 located within the substrate 100 of the storage area I.

[0061] In this embodiment, the isolation structure 105 is used to achieve electrical isolation between storage areas I.

[0062] In this embodiment, the isolation structure 105 is a shallow trench isolation (STI) structure. Specifically, the material of the isolation structure 105 is silicon oxide. In other embodiments, the material of the isolation structure can also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0063] In this embodiment, the isolation structure 105 and the storage gate structure 210 are formed in the same process step to simplify the process steps and save process costs. Figures 2 to 9 .

[0064] See also Figure 2 , a liner layer 250 is formed on the substrate 100 .

[0065] In this embodiment, the pad layer 250 includes a first sub-pad layer 250 a and a second sub-pad layer 250 b located on the first sub-pad layer 250 a .

[0066] The first sub-pad layer 250a is used to prevent the second sub-pad layer 250b from damaging the active area formed in the substrate 100 during the subsequent removal of the second sub-pad layer 250b, thereby protecting the active area formed in the substrate 100 from chemical contamination.

[0067] In this embodiment, the material of the first subpad layer 250 a includes silicon oxide.

[0068] In this embodiment, the first sub-pad layer 250a is formed by a thermal oxidation process. In other embodiments, the first sub-pad layer can be formed by at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.

[0069] The thickness of the first sub-pad layer 250a can be set according to actual needs. As an example, the thickness of the first sub-pad layer 250a is 100 angstroms to 200 angstroms.

[0070] The second sub-pad layer 250 b is used to protect the active area formed in the substrate 100 during the subsequent process of forming the isolation structure 105 in the substrate 100 , and is also used as an etching hard mask for the first trench formed subsequently.

[0071] In this embodiment, the material of the second subpad layer 250 b includes silicon nitride.

[0072] In this embodiment, the second sub-pad layer 250b is formed by a low pressure chemical vapor deposition process. In other embodiments, the second sub-pad layer can be formed by at least one of a chemical vapor deposition process, a physical vapor deposition process and an atomic layer deposition process.

[0073] The thickness of the second sub-pad layer 250b can be set according to actual needs. As an example, the thickness of the second sub-pad layer 250b is 600 angstroms to 1200 angstroms.

[0074] See also Figure 3 , patterning the liner layer 250 and a portion of the thickness of the substrate 100 to form a first trench 252 .

[0075] The first trench 252 is used to provide a foundation for subsequently forming a floating gate material layer therein, and is also used to define the regional position of an active area (Active Area, AA).

[0076] In this embodiment, the liner layer 250 and a portion of the thickness of the substrate 100 are patterned by a dry etching process to form a first trench 252. The dry etching process has the characteristic of anisotropic etching, so by selecting the dry etching process, the etching is more directional, which is beneficial to improving the dimensional accuracy of the formed first trench 252, and further to improving the dimensional accuracy of the floating gate material layer subsequently formed in the first trench 252.

[0077] Specifically, the step of patterning the liner layer 250 and a portion of the thickness of the substrate 100 to form the first groove 252 includes: forming an anti-reflection layer (not shown) on the liner layer 250; forming a patterned photoresist layer (not shown) on the anti-reflection layer; using the photoresist layer as a mask to sequentially etch the anti-reflection layer, the liner layer 250 and a portion of the thickness of the substrate 100 to form the first groove 252; after forming the first groove 252, removing the remaining photoresist layer and anti-reflection layer. The anti-reflection layer is a dielectric anti-reflection layer (DARC).

[0078] In other embodiments, the first groove may be formed by a wet etching process or a dry etching process combined with a wet etching process. Those skilled in the art may make a selection according to actual needs and no limitation is made here.

[0079] The depth of the first groove 252 can be set according to actual needs. As an example, the first groove 252 is 10 nanometers to 100 nanometers.

[0080] See also Figure 4 , Figure 4 (a) is a schematic top view of the intermediate structure formed, Figure 4 (b) Figure 4 (a) is a schematic cross-sectional structural diagram along line AA1, wherein a gate insulating film 211a is formed on the bottom and sidewalls of the first trench 252, and a floating gate material layer 212a filling the first trench 252 is formed on the gate insulating film 211a.

[0081] The gate insulating film 211 a provides a basis for subsequently forming a gate insulating layer.

[0082] In this embodiment, the gate insulating film 211a is made of silicon oxide. In other embodiments, the gate insulating film can also be made of other suitable materials.

[0083] The floating gate material layer 212a provides a basis for the subsequent formation of a floating gate layer.

[0084] In this embodiment, the floating gate material layer 212a is made of polysilicon.

[0085] In this embodiment, the steps of forming a gate insulating film 211a on the bottom and sidewalls of the first trench 252, and forming a floating gate material layer 212a filling the first trench 252 on the gate insulating film 211a include: forming an initial gate insulating film (not shown) conformally covering the bottom and sidewalls of the first trench 252 and the substrate 100; forming an initial floating gate material layer on the initial gate insulating film, and the floating gate material layer also fills the first trench 252; and planarizing the initial floating gate material layer and the initial gate insulating film until the top surface of the substrate 100 is exposed to form the gate insulating film 211a and the floating gate material layer 212a.

[0086] In this embodiment, a liner layer 250 is formed on the substrate 100. Accordingly, after the initial gate insulating film is formed, the initial gate insulating film covers the liner layer 250 located on the substrate 100. The initial floating gate material layer and the initial gate insulating film are planarized until the top surface of the liner layer 250 is exposed to form the gate insulating film 211a and the floating gate material layer 212a.

[0087] In this embodiment, the process of forming the initial gate insulating film is an atomic layer deposition (ALD) process.

[0088] The atomic layer deposition process has good step coverage capability, which is beneficial to improving the conformal coverage of the initial gate insulating film on the top of the liner layer 250 and the bottom and sidewall of the first groove 252. The use of the atomic layer deposition process is also beneficial to accurately control the thickness of the initial gate insulating film formed, thereby enabling accurate control of the thickness of the subsequently formed gate insulating film.

[0089] In other embodiments, the process of forming the initial gate insulating film may also be an oxidation process or the like.

[0090] In this embodiment, the process for planarizing the initial floating gate material layer and the initial gate insulation film is a chemical mechanical polishing (CMP) process.

[0091] In this embodiment, the initial floating gate material layer and the initial gate insulation film are planarized until the top surface of the pad layer 250 is exposed. Accordingly, the floating gate material layer 212a is flush with the top surface of the pad layer 250 remaining after etching the first groove 252. Specifically, the floating gate material layer 212a is flush with the top surface of the second sub-pad layer 250b in the pad layer 250 remaining after etching the first groove 252.

[0092] See also Figure 5 , Figure 5 (a) is a schematic top view of the intermediate structure formed, Figure 5 (b) and Figure 5 (c) are Figure 5 (a) A schematic diagram of the cross-sectional structure along lines BB1 and CC1, wherein the floating gate material layer 212a, the liner layer 250 and a partial thickness of the substrate 100 are patterned to form a second trench (not shown); and an isolation material layer 105a is filled in the second trench.

[0093] The second trench provides a foundation for subsequently forming an isolation material layer therein.

[0094] In this embodiment, a wet etching process is used to pattern the liner layer 250 , the floating gate material layer 212 a , and a partial thickness of the substrate 100 to form a second trench.

[0095] In other embodiments, the second trench may be formed by using a dry etching process or a dry etching process combined with a wet etching process.

[0096] The isolation material layer 105 a is prepared for the subsequent formation of an isolation structure.

[0097] In this embodiment, the step of forming the isolation material layer 105a includes: forming an initial isolation material layer (not shown) on the covering liner layer 250, the gate insulation film 211a and the floating gate material layer 212a, and the initial isolation material layer is also filled in the second trench; planarizing the initial isolation material layer until the top surfaces of the liner layer 250 and the floating gate material layer 212a are exposed to form the isolation material layer 105a.

[0098] In this embodiment, the process for forming the initial isolation material layer is a high-density plasma deposition process. In other embodiments, other processes can be used to form the initial isolation material layer, such as a physical vapor deposition process, an atomic layer deposition process, or a furnace process.

[0099] In this embodiment, the process for planarizing the initial isolation material layer is a chemical mechanical polishing process. In other embodiments, the initial isolation material layer can also be planarized by an etch-back process.

[0100] See also Figure 6 , Figure 6 (a) is a schematic top view of the intermediate structure formed, Figure 6 (b) and Figure 6 (c) are Figure 6 (a) is a schematic cross-sectional structural diagram along lines BB1 and CC1, in which a portion of the isolation material layer 105 a is removed, so that the remaining isolation material layer 105 a forms an isolation structure 105 .

[0101] In this embodiment, after a portion of the isolation material layer 105 a is removed, the top surface of the isolation structure 105 formed is flush with the bottom surface of the floating gate material layer 212 a .

[0102] In other embodiments, the top surface of the isolation structure may be higher or lower than the bottom surface of the floating gate material layer, which is not limited here.

[0103] In this embodiment, a wet etching process is used to remove a portion of the height of the isolation material layer 105a, so that the isolation material layer 105a forms an isolation structure 105. In other embodiments, a dry etching process or a dry and wet etching process combined with a wet etching process can also be used to remove a portion of the height of the isolation material layer, and those skilled in the art can select according to actual needs, and no limitation is made here.

[0104] See also Figure 7 , Figure 7 (a) is a schematic top view of the intermediate structure formed, Figure 7 (b) and Figure 7 (c) are Figure 7 (a) A schematic cross-sectional view of the structure along lines BB1 and CC1, wherein an initial inter-gate dielectric layer 213a is formed to conformally cover the isolation structure 105, the liner layer 250 and the floating gate material layer 212a.

[0105] The initial inter-gate dielectric layer 213 a provides a basis for the subsequent formation of an inter-gate dielectric layer.

[0106] In this embodiment, an atomic layer deposition process is used to form the initial inter-gate dielectric layer 213 a conformally covering the isolation structure 105 , the liner layer 250 , and the floating gate material layer 212 a .

[0107] The atomic layer deposition process has good step coverage capability, which is beneficial to improving the conformal coverage of the initial inter-gate dielectric layer 213a on the top and side walls of the floating gate material layer 212a, the top of the isolation structure 105, and the top and side walls of the pad layer 250. The use of the atomic layer deposition process is also beneficial to accurately control the thickness of the initial inter-gate dielectric layer 213a formed, thereby facilitating accurate control of the thickness of the subsequently formed inter-gate dielectric layer 213.

[0108] See also Figure 8 , Figure 8 (a) is a schematic top view of the intermediate structure formed, Figure 8 (b) Figure 8 (c) and Figure 8 (d) Figure 8(a) is a schematic cross-sectional structural diagram along lines AA1, BB1 and CC1. After the initial inter-gate dielectric layer 213a is formed, a control gate material layer 214a is formed on the initial inter-gate dielectric layer 213a.

[0109] The control gate material layer 214 a is used for subsequent patterning to form a control gate layer on the substrate 100 located in the storage area I.

[0110] The process of forming the control gate material layer 214a includes at least one of an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process and a furnace process. In this embodiment, the control gate material layer 214a is formed by a chemical vapor deposition process.

[0111] See also Fig. 9 , Fig. 9 (a) is a schematic top view of the intermediate structure formed, Fig. 9 (b) Fig. 9 (c) and Fig. 9 (d) Fig. 9 (a) A schematic diagram of the cross-sectional structure along lines AA1, BB1 and CC1, wherein a control gate material layer 214a, an initial inter-gate dielectric layer 213a and the floating gate material layer 212a are patterned, the floating gate layer 212, the inter-gate dielectric layer 213 located on the floating gate layer 212 and the control gate layer 214 located on the inter-gate dielectric layer 213 and spanning the floating gate layer 212 are formed on the gate insulating layer 211, the gate insulating layer 211, the floating gate layer 212, the inter-gate dielectric layer 213 and the control gate layer 214 constitute the gate structure 200, and the top surface of the substrate on one side of the gate structure 200 is lower than the top surface of the substrate 100 on the other side of the gate structure 200.

[0112] In this embodiment, the gate insulating layer 211 , the floating gate layer 212 , the inter-gate dielectric layer 213 and the control gate layer 214 constitute a storage gate structure 210 .

[0113] In this embodiment, the step of patterning the control gate material layer 214a, the initial inter-gate dielectric layer 213a and the floating gate material layer 212a includes: forming a first patterned layer (not shown) on the control gate material layer 214a, the first patterned layer having a plurality of first openings, the bottom of the first openings exposing a portion of the control gate material layer 214a; sequentially etching the control gate material layer 214a, the initial inter-gate dielectric layer 213a and the floating gate material layer 212a using the first patterned layer as a mask until the top surfaces of the substrate 100 and the isolation structure 105a are exposed, and forming the floating gate layer 212, the inter-gate dielectric layer 213 located on the floating gate layer 212 and the control gate layer 214 located on the inter-gate dielectric layer 213 and spanning the floating gate layer 212 on the gate insulation layer 211; after forming the floating gate layer 212, the inter-gate dielectric layer 213 and the control gate layer 214, removing the remaining first patterned layer.

[0114] In this embodiment, a liner layer 250 is formed on the substrate 100, and the liner layer 250 includes a first sub-liner layer 250a and a second sub-liner layer 250b located on the first sub-liner layer 250a. Accordingly, after the control gate material layer 214a and the initial inter-gate dielectric layer 213a are sequentially etched using the first patterned layer as a mask to form the control gate layer 214 and the inter-gate dielectric layer 213, the second sub-liner layer 250b in the liner layer 250 is used as an etching stop layer to etch away the floating gate material layer 212a located on one side of the control gate layer 214 until the top surface of the substrate 100 at the bottom of a portion of the first trench 252 is exposed, so that the floating gate material layer 212a forms a floating gate layer 212, and the top surface of the substrate 100 located on one side of the gate structure 200 is lower than the top surface of the substrate 100 on the other side of the gate structure 200.

[0115] Specifically, the second sub-pad layer 250b in the pad layer 250 is used as an etching stop layer, and the floating gate material layer 212a located on one side of the control gate layer 214 is etched away until the top surface of the substrate 100 at the bottom of a portion of the first trench 252 is exposed. This means that the etching process has a much higher etching rate for the floating gate material layer 212a than for the second sub-pad layer 250b, and the control gate material layer 214a and the initial inter-gate dielectric layer 213a are sequentially etched to form a control gate. After the control gate layer 214 and the inter-gate dielectric layer 213, the existence of the second sub-pad layer 250b in the pad layer 250 makes the etching on the other side of the storage gate structure 210 stop at the second sub-pad layer 250b in the pad layer 250. At the same time, the floating gate material layer 212a located on one side of the storage gate structure 210 is completely etched away, exposing the substrate 100 originally located on one side of the control gate layer 214 and below the floating gate material layer 212a in the first groove.

[0116] At this time, the top surface of the substrate 100 located on one side of the storage gate structure 210 is lower than the bottom surface of the floating gate layer 212 and is flush with the bottom surface of the floating gate layer 212, while the top surface of the substrate 100 located on the other side of the storage gate structure 210 is higher than the bottom surface of the floating gate layer 212, so that the top surface of the substrate 100 located on one side of the storage gate structure 210 is lower than the top surface of the substrate 100 located on the other side of the storage gate structure 210.

[0117] Correspondingly, after the floating gate layer 212, the inter-gate dielectric layer 213 located on the floating gate layer 212, and the control gate layer 214 located on the inter-gate dielectric layer 213 and spanning the floating gate layer 212 are formed on the gate insulation layer 211, the first sub-pad layer 250a in the pad layer 250 is still retained on the substrate 100 located on the other side of the storage gate structure 210 to protect the substrate 100 located under the first sub-pad layer 250a in subsequent processes.

[0118] In this embodiment, the formed control gate layer 214 spans the floating gate layer 212, that is, the control gate layer 214 surrounds the floating gate layer 212 from three sides, which is beneficial to improve the coupling coefficient of the control gate layer 214 to the floating gate layer 212, thereby improving the reaction speed of the formed semiconductor structure.

[0119] In this embodiment, the first patterned layer is a photoresist layer. Accordingly, the process of forming the first patterned layer on the control gate material layer 214a includes a spin coating process.

[0120] In this embodiment, the first patterned layer is a photoresist layer. Accordingly, an ashing process or a wet resist stripping process can be used to remove the remaining first patterned layer.

[0121] In this embodiment, an isolation structure 105 is also formed in the substrate 100 on one side of the gate structure 200. Accordingly, in the process of etching away part of the floating gate material layer 212a on one side of the gate structure 200, the isolation structure 105 on one side of the floating gate material layer 212a is also etched away.

[0122] The floating gate material layer 212a on one side of the gate structure 200 is etched so that the height difference between the top surface of the substrate 100 on one side of the gate structure 200 and the top surface of the substrate 100 on the other side of the gate structure 200 can be set according to actual needs.

[0123] Specifically, the floating gate material layer 212a on one side of the gate structure 200 is etched so that the height difference between the top surface of the substrate 100 on one side of the gate structure 200 and the top surface of the substrate 100 on the other side of the gate structure 200 is related to the depth of the first trench 252. Accordingly, the depth of the first trench 252 can be set according to the requirement of etching the floating gate material layer 212a on one side of the gate structure 200 so that the height difference between the top surface of the substrate 100 on one side of the gate structure 200 and the top surface of the substrate 100 on the other side of the gate structure 200 is reduced.

[0124] It should be noted that after etching the floating gate material layer 212a on one side of the gate structure 200, the height difference between the top surface of the substrate 100 on one side of the gate structure 200 and the top surface of the substrate 100 on the other side of the gate structure 200 should not be too large or too small.

[0125] If the height difference between the top surface of the substrate 100 on one side of the gate structure 200 and the top surface of the substrate 100 on the other side of the gate structure 200 is too small after etching the floating gate material layer 212a on one side of the gate structure 200, it will not be much helpful to increase the channel length between the source region and the drain region formed subsequently; if the height difference between the top surface of the substrate 100 on one side of the gate structure 200 and the top surface of the substrate 100 on the other side of the gate structure 200 is too large, it will be disadvantageous for the previous deposition of the floating gate material layer 212a and the subsequent etching of the conductive source contact hole. To this end, in this embodiment, considering the subsequent channel source and drain position, the top surface of the substrate 100 on one side of the gate structure 200 should be kept flush with the bottom of the floating gate, so after etching the floating gate material layer 212a on one side of the gate structure 200, the height difference between the top surface of the substrate 100 on one side of the gate structure 200 and the top surface of the substrate 100 on the other side of the gate structure 200 is 10 to 100 nanometers.

[0126] In the present embodiment, after etching the floating gate material layer 212a on one side of the gate structure 200 so that the top surface of the substrate 100 on one side of the gate structure 200 is lower than the top surface of the substrate 100 on the other side of the gate structure 200, the method for forming the semiconductor structure further includes: performing an ion implantation process on the substrate 100 on one side of the gate structure 200 so that the substrates on one side of the gate structure 200 are connected by the implanted ions to form a conductive source line.

[0127] The process parameters of the ion implantation process can be set according to actual needs. As an example, the process parameters of the ion implantation process include: the implanted ion is arsenic, the implantation dose is 1E14 atoms / cm 2To 9E15 atoms / cm 2 , the implantation energy is 5KeV to 50KeV.

[0128] See also Fig.10 After forming the gate structure 200 , the method for forming the semiconductor structure further includes: forming a spacer structure 260 on the sidewall of the gate structure 200 .

[0129] The spacer structure 260 is used to protect the sidewall of the gate structure 200 , and is also used to define the area position of the subsequent ion implantation process and source / drain doping process.

[0130] In this embodiment, the gate structure 200 includes a storage gate structure 210 protruding from the substrate 100 of the storage region I. Accordingly, the spacer structure 260 is located on the sidewall of the storage gate structure 210 .

[0131] In this embodiment, the sidewall structure 260 is a stacked structure. Specifically, the sidewall structure 260 is an ONO structure.

[0132] In other embodiments, the spacer structure can also be a single-layer structure. Accordingly, the material of the spacer structure can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0133] Specifically, the step of forming the sidewall structure 260 includes: forming a dielectric material layer (not shown) that conformally covers the top and sidewalls of the gate structure 200 and the substrate 100; using a maskless etching process to etch away the dielectric material layer located on the top of the gate structure 200 and the substrate 100, and retaining the dielectric material layer located on the sidewalls of the gate structure 200 as the sidewall structure 260.

[0134] In this embodiment, a maskless etching process is used to etch away the dielectric material layer located on the top of the gate structure 200 and the substrate 100 , and a portion of the first sub-pad layer 250a is also removed. Only a portion of the first sub-pad layer 250a remains on a portion of the sidewall of the gate structure 200 and at the bottom of the sidewall structure 260 .

[0135] In this embodiment, before forming the spacer structure 260 on the sidewall of the gate structure 200 , the method for forming the semiconductor structure further includes: forming lightly doped regions (not shown) in the substrate 100 on both sides of the gate structure 200 .

[0136] The lightly doped region is used to reduce the hot carrier injection effect (hot carrier injection) between the subsequently formed source and drain doped regions.

[0137] See also Fig.11 , a source-drain implantation process is performed on the substrate 100 on both sides of the gate structure 200 to form a source region 151 in the substrate 100 on one side of the gate structure 200 , and a drain region 152 is formed in the substrate 100 on the other side of the gate structure 200 .

[0138] The source region 151 is used as a source terminal of the formed semiconductor structure, and the drain region 152 is used as a drain terminal of the formed semiconductor structure.

[0139] In this embodiment, the gate structure 200 includes a storage gate structure 210 protruding from the substrate 100 of the storage region I. Accordingly, a source-drain implantation process is performed on the substrate 100 on both sides of the storage gate structure 210 to form a source region 151 in the substrate 100 on one side of the storage gate structure 210, and a drain region 152 is formed in the substrate 100 on one side of the storage gate structure 210.

[0140] According to the different conductivity types of the formed semiconductor structure, the doping types of the source region 151 and the drain region 152 are different accordingly. Specifically, when the formed semiconductor structure is a nano OS device, the doping type of the source region 151 and the drain region 152 is N-type; when the formed semiconductor structure is a PMOS device, the doping type of the source region 151 and the drain region 152 is P-type doping ions. Among them, the doping ions of N-type doping are phosphorus (P) or arsenic (As), etc., and the doping ions used for P-type doping are boron (B) or gallium (Ga), etc.

[0141] In this embodiment, after forming the source region 151 and the drain region 152, the method for forming the semiconductor structure further includes: annealing the source region 151 and the drain region 152 to repair lattice damage in the source region 151 and the drain region 152, and activate the doped ions in the source region 151 and the drain region 152, and also to promote further isotropic diffusion of the doped ions.

[0142] Combined with reference Fig.12 In this embodiment, after the source region 151 and the drain region 152 are annealed, the method for forming the semiconductor structure further includes: performing a metal silicide process to convert the top of the gate structure 200 into a first metal silicide layer (Salicide Layer) 270.

[0143] Among them, the first metal silicide layer 270 is used to reduce the gate resistance of the NOR flash memory device, thereby improving the programming operation capability and efficiency of the NOR flash memory device, improving the repeated read and write capability of the NOR flash memory device, and improving the resistance capacitance (RC) delay, thereby improving the performance of the NOR flash memory device.

[0144] In this embodiment, during the process of converting the top of the gate structure 200 into the first metal silicide layer 270 , a second metal silicide layer (not shown) is also formed on the conductive source line and the drain region 152 .

[0145] In this embodiment, the steps of forming the first metal silicide layer 270 and the second metal silicide layer include: forming a barrier layer (not shown) between adjacent gate structures 200, wherein the barrier layer exposes the top of the gate structure 200, the conductive source line, and the drain region 152; forming a metal layer covering the barrier layer and the top of the gate structure 200, the conductive source line, and the drain region 152 exposed by the barrier layer; after forming the metal layer, performing an annealing process on the metal layer so that the metal layer is respectively connected to the gate structure 200, the conductive source line, and the drain region 152 exposed by the barrier layer. The conductive line and the drain region 152 react to form an initial metal silicide layer (not shown); after the initial metal silicide layer is formed, the unreacted remaining metal layer is removed; after the unreacted remaining metal layer is removed, a second annealing process is performed to convert the initial metal silicide layer on the top of the gate structure 200 into a first metal silicide layer 270, and convert the initial metal silicide layer on the conductive power line and the drain region 152 into a second metal silicide layer; after the first metal silicide layer 270 and the second metal silicide layer are formed, the blocking layer is removed.

[0146] In this embodiment, the material of the metal layer is nickel, and accordingly, the materials of the first metal silicide layer 270 and the second metal silicide layer are nickel silicon compounds. In another embodiment, the material of the metal layer is titanium, and the materials of the first metal silicide layer and the second metal silicide layer are titanium silicon compounds. In other embodiments, the material of the metal layer may also be cobalt, and the materials of the first metal silicide layer and the second metal silicide layer are cobalt silicon compounds.

[0147] In this embodiment, a metal silicide process is performed to convert the top of the gate structure 200 into a first metal silicide layer 270 , and a second metal silicide layer (not shown) covering a portion of the conductive source line and a portion of the drain region 152 is also formed.

[0148] The gate plug, the power line plug and the drain plug formed subsequently are electrically connected to the gate structure 200, the power line and the drain region 152 through the first metal silicide layer 270 and the second metal silicide layer respectively. The first metal silicide layer 270 and the second metal silicide layer can improve the adhesion between the gate plug, the power line plug and the drain plug formed subsequently and the gate structure 200, the power line and the drain region 152 respectively, and reduce the contact resistance between the gate plug, the power line plug and the drain plug formed subsequently and the gate structure 200, the power line and the drain region 152 respectively.

[0149] Combined with reference Fig.13 In this embodiment, after forming the first metal silicide layer 270 and the second metal silicide layer, the method for forming the semiconductor structure further includes: forming a dielectric layer 300 covering the substrate 100 , the isolation structure 105 and the gate structure 200 .

[0150] The dielectric layer 300 is used to achieve electrical isolation between conductive structures formed therein and between the conductive structures and other electrical connection structures.

[0151] The material of the dielectric layer 300 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the dielectric layer 300 is silicon oxide.

[0152] In this embodiment, the gate structure 200 includes a storage gate structure 210 protruding from the substrate 100 of the storage region I. Accordingly, the dielectric layer 300 covers the storage gate structure 210 protruding from the substrate 100 of the storage region I.

[0153] In this embodiment, a sidewall structure 260 is further formed on the sidewall of the storage gate structure 200 on the substrate 100 of the storage area I. Accordingly, after the dielectric layer 300 is formed, the dielectric layer 300 also covers the sidewall structure 260.

[0154] In this embodiment, a chemical vapor deposition process is used to form the dielectric layer 300. In other embodiments, the dielectric layer can also be formed by a physical vapor deposition process, an atomic layer deposition process, a furnace process, or the like.

[0155] Combined with reference Fig.14 In this embodiment, after the dielectric layer 300 is formed, it also includes: forming a conductive power line plug (not shown) and a drain plug 320 that penetrate the dielectric layer 300 on the top of the conductive power line and the drain region 152, and forming a gate plug 340 that penetrates the dielectric layer 300 on the top of the gate structure 200, the conductive power line plug is in contact with the conductive power line, the drain plug 320 is in contact with the drain region 152, and the gate plug 340 is in contact with the gate structure 200.

[0156] The conductive source plug is used to electrically lead out the conductive source line, the drain plug 320 is used to electrically lead out the drain region 152 , and the gate plug 340 is used to electrically lead out the gate structure 200 .

[0157] In this embodiment, the gate structure 200 includes a storage gate structure 210 protruding from the substrate 100 of the storage region I. Accordingly, the conductive source line plug contacts the conductive source line on one side of the storage gate structure 210, and the drain plug 320 contacts the drain region 152 on the other side of the storage gate structure 210.

[0158] In this embodiment, the conductive source plug, the drain plug 320 and the gate plug 340 are made of tungsten (W). In other embodiments, the conductive source plug, the drain plug and the gate plug may also be made of cobalt (Co) or ruthenium (Ru).

[0159] In this embodiment, the steps of forming the conductive power line plug, the drain plug 320 and the gate plug 340 include: forming a second patterned layer (not shown) on the dielectric layer 300, the second patterned layer having a second opening on the top surface of the dielectric layer 300 exposing a portion of the conductive power line, a portion of the drain region 152 and the top of the gate structure 200; etching the dielectric layer 300 using the second patterned layer as a mask to form a contact hole (not shown) penetrating the conductive power line, the drain region 152 and the dielectric layer 300 on the top of the gate structure 200; after forming the contact hole, filling the contact hole with a conductive material to form the conductive power line plug, the drain plug 320 and the gate plug 340; after forming the conductive power line plug, the drain plug 320 and the gate plug 340, removing the remaining second patterned layer.

[0160] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the top surface of the source region formed is lower than the top surface of the drain region, thereby forming an L-shaped channel in the substrate, increasing the channel length, and avoiding the occurrence of a short channel effect. At the same time, the increase in the channel length can effectively reduce the width of the floating gate layer and the control gate layer in the formed gate structure, so that the aspect ratio of the groove between the drain region and the control gate layer is smaller, and the process window of the sidewall structure and the dielectric layer can be increased accordingly, avoiding the occurrence of void filling. At the same time, the smaller aspect ratio is also conducive to the increase of the process window of the drain contact hole formed in the dielectric layer later, avoiding etching to the sidewall structure during the formation of the drain contact hole, and avoiding the loss of the sidewall structure. Therefore, the method for forming a semiconductor structure in the embodiment of the present invention is helpful to improve the performance of the formed semiconductor structure.

[0161] The above describes the method for forming a semiconductor structure in an embodiment of the present invention by taking the case where the gate structure 200 is a stacked structure, wherein a portion of the gate structure 200 is located inside the substrate 100 and a portion of the gate structure 200 protrudes from the substrate 100, and during the process of forming the gate structure 200, the top surface of the substrate 100 on one side of the gate structure 200 is lower than the top surface of the substrate 100 on the other side of the gate structure 200.

[0162] It can be understood that in other embodiments, the gate structure can also be a single-layer structure, and the gate structure can also be entirely located on the substrate, and after the gate structure is formed, a portion of the thickness of the substrate on one side of the gate structure is removed by etching, so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure.

[0163] Accordingly, an embodiment of the present invention further provides a semiconductor structure.

[0164] Please continue to see Fig.14 A semiconductor structure in an embodiment of the present invention may include: a substrate (not shown), the substrate including a substrate 100; a gate structure 200, separated on the substrate 100; a source region 151, located in the substrate 100 on one side of the gate structure 200; a drain region 152, located in the substrate 100 on the other side of the gate structure 200, and the top surface of the drain region 152 is higher than the top surface of the source region 151.

[0165] The substrate 100 provides a process platform for the subsequent formation of a flash memory. In this embodiment, the substrate 100 is used to provide a process platform for the subsequent formation of a NOR Flash device.

[0166] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In some other embodiments, the substrate may also include a semiconductor layer and a second semiconductor layer epitaxially grown on the semiconductor layer, the semiconductor layer is used to provide a process basis for the subsequent formation of the substrate, and the second semiconductor layer is used to provide a process basis for the subsequent formation of the fin. In other embodiments, the substrate may also include other functional layers to be etched, and the target pattern is formed by etching the functional layers to be etched.

[0167] In this embodiment, the substrate 100 includes a storage region I. Accordingly, the gate structure 200 includes a storage gate structure 210 protruding from the storage region I of the substrate 100 .

[0168] Specifically, the storage gate structure 210 includes a gate insulating layer 211 , a floating gate layer 212 located on the gate insulating layer 211 , an inter-gate dielectric layer 213 located on the floating gate layer 212 , and a control gate layer 214 located on the inter-gate dielectric layer 213 .

[0169] The gate insulating layer 211 serves as a tunneling oxide layer of the NOR flash memory device, and is used to achieve electrical isolation between the substrate 100 and the floating gate layer 212, thereby preventing electrons from entering the substrate 100 and further reducing the loss of electrons. That is, the gate insulating layer 211 is used to prevent the loss of data stored in the NOR flash memory device.

[0170] In this embodiment, the gate insulating layer 211 is made of silicon oxide. In other embodiments, the gate insulating layer can also be made of other suitable materials.

[0171] The floating gate layer 212 is used to store electrons during the operation of the NOR flash memory device.

[0172] In this embodiment, the floating gate layer 212 is made of polysilicon.

[0173] The inter-gate dielectric layer 213 is used as an insulating layer between the floating gate layer 212 and the control gate layer 214 to achieve electrical isolation between the floating gate layer 212 and the control gate layer 214 .

[0174] In this embodiment, the inter-gate dielectric layer 213 is a stacked structure. Specifically, the inter-gate dielectric layer 213 is an oxide layer-nitride layer-oxide layer (Oxide-Nitride-Oxide, ONO) structure, wherein the oxide layer is a silicon oxide layer, and the nitride layer is a silicon oxide layer. In other embodiments, the inter-gate dielectric layer can also be a single-layer structure.

[0175] The control gate layer 214 is used as a part of a word line of a NOR flash memory device.

[0176] In this embodiment, the material of the control gate layer 214 is the same as that of the floating gate layer 212 , that is, the material of the control gate layer 214 is polysilicon.

[0177] In this embodiment, the control gate layer 214 spans the floating gate layer 212, that is, the control gate layer 214 surrounds the floating gate layer 212 from three sides, which is beneficial to improve the coupling coefficient of the control gate layer 214 to the floating gate layer 212, thereby improving the reaction speed of the formed semiconductor structure.

[0178] In this embodiment, the base further includes an isolation structure 105 located within the substrate 100 of the storage area I.

[0179] The isolation structure 105 is used to achieve electrical isolation between the storage areas I.

[0180] In this embodiment, the isolation structure 105 is a shallow trench isolation structure. Specifically, the material of the isolation structure 105 is silicon oxide. In other embodiments, the material of the isolation structure can also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0181] In this embodiment, the semiconductor structure further includes: a spacer structure 260 located on the sidewall of the gate structure 200 .

[0182] The spacer structure 260 is used to protect the sidewall of the gate structure 200 and is also used to define the area position of the ion implantation process and the source-drain doping process.

[0183] In this embodiment, the gate structure 200 includes a storage gate structure 210 protruding from the substrate 100 of the storage region I. Accordingly, the spacer structure 260 is located on the sidewall of the storage gate structure 210 .

[0184] In this embodiment, the sidewall structure 260 is a stacked structure. Specifically, the sidewall structure 260 is an ONO structure.

[0185] In other embodiments, the spacer structure can also be a single-layer structure. Accordingly, the material of the spacer structure can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0186] In this embodiment, the semiconductor structure further includes: a lightly doped region (not shown) located in the substrate 100 on both sides of the gate structure 200 .

[0187] The lightly doped region is used to reduce the hot carrier injection effect between the source region and the drain region.

[0188] The source region 151 is used as a source terminal of the formed semiconductor structure, and the drain region 152 is used as a drain terminal of the formed semiconductor structure.

[0189] In this embodiment, the gate structure 200 includes a storage gate structure 210 protruding from the substrate 100 of the storage region I. Accordingly, the source region 151 is located in the substrate 100 on one side of the storage gate structure 210 , and the drain region 152 is located in the substrate 100 on the other side of the storage gate structure 210 .

[0190] According to the different conductivity types of the formed semiconductor structure, the doping types of the source region 151 and the drain region 152 are different accordingly. Specifically, when the formed semiconductor structure is a nano OS device, the doping type of the source region 151 and the drain region 152 is N-type; when the formed semiconductor structure is a PMOS device, the doping type of the source region 151 and the drain region 152 is P-type doping ions. Among them, the doping ions of N-type doping are phosphorus (P) or arsenic (As), etc., and the doping ions used for P-type doping are boron (B) or gallium (Ga), etc.

[0191] In this embodiment, the semiconductor structure further includes: a first metal silicide layer 270 located on the top of the gate structure 200 .

[0192] In this embodiment, the semiconductor structure further includes: a second metal silicide layer (not shown) located on the conductive source line and the drain region 152 .

[0193] Among them, the first metal silicide layer 270 and the second metal silicide layer are used to reduce the gate resistance of the NOR flash memory device, thereby improving the programming operation capability and efficiency of the NOR flash memory device, improving the repeated read and write capability of the NOR flash memory device, and improving the resistance and capacitance delay, thereby improving the performance of the NOR flash memory device.

[0194] In this embodiment, the materials of the first metal silicide layer 270 and the second metal silicide layer are nickel silicon compounds. In another embodiment, the materials of the first metal silicide layer and the second metal silicide layer are titanium silicon compounds. In other embodiments, the materials of the first metal silicide layer and the second metal silicide layer are cobalt silicon compounds.

[0195] The first metal silicide layer 270 and the second metal silicide layer are in contact with the gate plug, the conductive power line plug, the drain plug, the gate structure 200, the conductive power line and the drain area 152, respectively, so as to realize electrical connection between the gate plug, the conductive power line plug and the drain plug and the gate structure 200, the conductive power line and the drain area 152, respectively. The first metal silicide layer 270 and the second metal silicide layer can also improve the adhesion between the subsequently formed gate plug, the conductive power line plug and the drain plug and the gate structure 200, the conductive power line and the drain area 152, respectively, and reduce the contact resistance between the gate plug, the conductive power line plug and the drain plug and the gate structure 200, the conductive power line and the drain area 152, respectively.

[0196] In this embodiment, the semiconductor structure further includes: a dielectric layer 300 covering the substrate 100 , the isolation structure 105 and the gate structure 200 .

[0197] The dielectric layer 300 is used to achieve electrical isolation between conductive structures formed therein and between the conductive structures and other electrical connection structures.

[0198] The material of the dielectric layer 300 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the dielectric layer 300 is silicon oxide.

[0199] In this embodiment, the gate structure 200 includes a storage gate structure 210 protruding from the substrate 100 of the storage region I. Accordingly, the dielectric layer 300 covers the storage gate structure 210 protruding from the substrate 100 of the storage region I.

[0200] In this embodiment, a sidewall structure 260 is further formed on the sidewall of the storage gate structure 210 of the substrate 100 protruding from the storage area I. Accordingly, after the dielectric layer 300 is formed, the dielectric layer 300 also covers the sidewall structure 260.

[0201] In this embodiment, the semiconductor structure further includes: a conductive power line plug (not shown) and a drain plug 320, which penetrate the conductive power line and the dielectric layer 300 on the top of the drain region 152, and are in contact with the conductive power line and the drain region 152 respectively; a gate plug 340, which penetrates the dielectric layer 300 on the top of the gate structure 200 and is in contact with the gate structure 200.

[0202] The conductive source plug is used to electrically lead out the conductive source line, the drain plug 320 is used to electrically lead out the drain region 152 , and the gate plug 340 is used to electrically lead out the gate structure 200 .

[0203] In this embodiment, the gate structure 200 includes a storage gate structure 210 protruding from the substrate 100 of the storage region I. Accordingly, the conductive source line plug contacts the conductive source line on one side of the storage gate structure 210, and the drain plug 320 contacts the drain region 152 on the other side of the storage gate structure 210.

[0204] In this embodiment, the conductive source plug, the drain plug 320 and the gate plug 340 are made of tungsten (W). In other embodiments, the conductive source plug, the drain plug and the gate plug may also be made of cobalt (Co) or ruthenium (Ru).

[0205] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a backing; forming a gate structure protruding from the substrate; Removing a portion of the thickness of the substrate on one side of the gate structure so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure; A source-drain implantation process is performed on the substrate at both sides of the gate structure to form a source region in the substrate at one side of the gate structure and a drain region in the substrate at the other side of the gate structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: A height difference between a top surface of the substrate on one side of the gate structure and a top surface of the substrate on the other side of the gate structure is 10 nm to 100 nm.

3. The method for forming a semiconductor structure according to claim 1, wherein: A partial thickness of the substrate on one side of the gate structure is removed by an etch-back process, so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure.

4. The method for forming a semiconductor structure according to claim 1, wherein: After removing a portion of the thickness of the substrate on one side of the gate structure so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure, the method further includes: performing an ion implantation process on the substrate on one side of the gate structure so that the substrate on one side of the gate structure is connected by implanted ions to form a conductive power line; After forming the conductive source wire, a source-drain implantation process is performed on the substrate at both sides of the gate structure to form a source region in the substrate at one side of the gate structure and a drain region in the substrate at the other side of the gate structure.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: The process parameters of the ion implantation process include: implanted ions are arsenic to phosphorus, and the implantation dose is 1E14 atoms / cm 2 To 9E15 atoms / cm 2 , the implantation energy is 5KeV to 50KeV.

6. The method for forming a semiconductor structure according to claim 1, wherein: After forming a discrete gate structure on the substrate, and before removing part of the thickness of the substrate on one side of the gate structure so that the top surface of the substrate on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure, it also includes: forming a sidewall structure on the sidewall of the gate structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: Before forming the sidewall structure on the sidewall of the gate structure, the method further includes: performing a light doping process to form light doping regions in the substrate on both sides of the gate structure.

8. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure includes a gate insulating layer, a floating gate layer located on the gate insulating layer, an inter-gate dielectric layer located on the floating gate layer, and a control gate layer located on the inter-gate dielectric layer.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: The base also includes an isolation structure located within the substrate; The steps of forming the isolation structure and the gate structure and making the top surface of the substrate on one side of the gate structure lower than the top surface of the substrate on the other side of the gate structure include: patterning a portion of the thickness of the substrate to form a first trench; forming a gate insulating film on the bottom and sidewalls of the first trench; forming a floating gate material layer filling the first trench on the gate insulating film; patterning the floating gate material layer and a portion of the thickness of the substrate to form a second trench; filling the second trench with an isolation material layer; removing a portion of the height of the isolation material layer to form the remaining isolation material layer as an isolation structure; forming a conformal covering layer of the isolation structure, the substrate and The invention relates to a method for forming a floating gate material layer, an initial inter-gate dielectric layer of the floating gate material layer; forming a control gate material layer on the initial inter-gate dielectric layer; patterning the control gate material layer, the initial inter-gate dielectric layer and the floating gate material layer until the top surface of a portion of the substrate at the bottom of the first trench is exposed, and forming the floating gate layer, the inter-gate dielectric layer located on the floating gate layer and the control gate layer located on the inter-gate dielectric layer and spanning the floating gate layer on the gate insulating layer, wherein the gate insulating layer, the floating gate layer, the inter-gate dielectric layer and the control gate layer constitute the gate structure, and make the top surface of the substrate on one side of the gate structure lower than the top surface of the substrate on the other side of the gate structure.

10. The method for forming a semiconductor structure according to claim 9, characterized in that: Before forming the first groove, a liner layer is formed on the substrate; During patterning of the substrate of a partial thickness, the liner layer is also patterned; In the process of patterning the control gate material layer, the initial inter-gate dielectric layer and the floating gate material layer, after patterning the control gate material layer and the initial inter-gate dielectric layer to form the inter-gate dielectric layer and the control gate layer, the liner layer is used as an etching stop layer to remove the floating gate material layer located on one side of the control gate layer and in the first trench until the top surface of a portion of the substrate at the bottom of the first trench is exposed, so that the floating gate material layer forms a floating gate layer, and the top surface of the substrate located on one side of the gate structure is lower than the top surface of the substrate on the other side of the gate structure.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: The pad layer includes a first subpad layer and a second subpad layer located on the first subpad layer.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: A material of the first subpad layer includes silicon oxide, and a material of the second subpad layer includes silicon nitride.

13. The method for forming a semiconductor structure according to claim 1, wherein: After performing a source-drain implantation process on the substrate at both sides of the gate structure, the method further includes: performing a metal silicide process to transform the top of the gate structure into a first metal silicide layer.

14. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising a backing; A gate structure protruding from the substrate; A source region located in the substrate on one side of the gate structure; The drain region is located in the substrate at the other side of the gate structure, and the top surface of the drain region is higher than the top surface of the source region.

15. The semiconductor structure according to claim 14, characterized in that: A height difference between a top surface of the source region and a top surface of the drain region is 10 nm to 100 nm.

16. The semiconductor structure according to claim 14, characterized in that Also includes: The sidewall structure is located on the sidewall of the gate structure.

17. The semiconductor structure according to claim 14, characterized in that Also includes: The lightly doped regions are located in the substrate on both sides of the gate structure.

18. The semiconductor structure according to claim 14, characterized in that The gate structure includes a gate insulating layer, a floating gate layer located on the gate insulating layer, an inter-gate dielectric layer located on the floating gate layer, and a control gate layer located on the inter-gate dielectric layer.

19. The semiconductor structure according to claim 14, characterized in that The base also includes an isolation structure located within the substrate.

20. The semiconductor structure according to claim 14, wherein: Also includes: A first metal silicide layer is located on top of the gate structure.

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