Memory structure and forming method of memory structure

Abstract

The invention discloses a memory structure and a forming method of the memory structure, and the structure comprises a substrate which comprises a plurality of first regions which are arranged along a second direction and are separated from each other, and second regions which are located between the adjacent first regions; a plurality of first grooves located in the substrate, wherein the plurality of first grooves are arranged along the first direction and stretch across the plurality of first areas and the plurality of second areas along the second direction; and the storage gate structure is at least partially positioned in the first groove between the first region and the second region. In the memory structure, a part of the memory gate structure is located in the first groove, so that the thickness of the memory structure is reduced, the integration level of the memory structure is improved, the depth of the groove between the memory structures is reduced, the resistance of the memory structure is reduced, and the performance of the memory structure and the uniformity and stability of a manufacturing process are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a memory structure and a method for forming the memory structure. Background Art

[0002] NOR Flash is developed based on the ETOX structure proposed by Intel. It is a non-volatile memory, which means that the stored data will not be lost after the chip is powered off. At the same time, NOR Flash is a voltage-controlled device that uses hot electron injection to write data and erases data based on the tunnel effect. One of its notable features is its fast random read speed. As a non-volatile memory, NOR Flash has the characteristics of non-volatility, high device density, low power consumption and electrical rewritability. It is widely used in portable electronic products such as mobile phones, digital cameras, smart cards, etc.

[0003] However, existing NOR Flash devices still have many problems during their formation. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a memory structure and a method for forming the memory structure, so as to improve the performance of the device structure.

[0005] To solve the above technical problems, an embodiment of the present invention provides a memory structure, including: a substrate, the substrate including a plurality of mutually discrete first regions arranged along a second direction, and a second region located between adjacent first regions; a plurality of first grooves located in the substrate, the plurality of first grooves being arranged along the first direction and spanning across the plurality of first regions and the plurality of second regions along the second direction; and a storage gate structure at least partially located in the first grooves between the first regions and the second regions.

[0006] Optionally, the storage gate structure includes: a floating gate located in the first trench and a control gate located on the floating gate.

[0007] Optionally, the storage gate structure further includes: a first gate dielectric layer located between the floating gate and the substrate; and a second gate dielectric layer located between the floating gate and the control gate.

[0008] Optionally, the memory structure also includes: a source line structure located on the substrate surface of the second region and in the first groove, the material of the source line structure is a semiconductor material, and the source line structure is doped with conductive ions; a drain line structure located in the first groove of the first region, the material of the drain line structure is a semiconductor material, and the drain line structure is doped with conductive ions.

[0009] Optionally, the source line structure includes: a first structure layer located on the substrate surface of the second region and in the first trench, and a second structure layer located on the surface of the first structure layer.

[0010] Optionally, the drain line structure includes: a third structure layer located in the first groove in the first region and a fourth structure layer located on the surface of the third structure layer.

[0011] Optionally, the memory structure further includes: a plurality of second trenches located between adjacent memory gate structures, wherein the plurality of second trenches are arranged along the second direction and penetrate the plurality of first trenches along the first direction.

[0012] Correspondingly, the technical solution of the present invention also provides a method for forming a memory structure, including: providing a substrate, the substrate including a plurality of mutually discrete first regions arranged along a second direction, and a second region located between adjacent first regions; forming a plurality of first grooves in the substrate, the plurality of first grooves being arranged along the first direction and spanning across a plurality of first regions and a plurality of second regions along the second direction; and forming at least a portion of a storage gate structure in the first groove between the first region and the second region.

[0013] Optionally, the method for forming the storage gate structure includes: forming a floating gate in the first trench; and forming a control gate on the floating gate.

[0014] Optionally, the method for forming a memory structure also includes: forming a source line structure on the substrate surface and in the first groove of the second region, the material of the source line structure is a semiconductor material, and the source line structure is doped with conductive ions; forming a drain line structure in the first groove of the first region, the material of the drain line structure is a semiconductor material, and the drain line structure is doped with conductive ions.

[0015] Optionally, the method for forming a source line structure includes: forming a first structure layer on the substrate surface and in the first groove in the second region; forming a second structure layer on the surface of the first structure layer; the method for forming a drain line structure includes: forming a third structure layer in the first groove in the first region; forming a fourth structure layer on the surface of the third structure layer.

[0016] Optionally, the storage gate structure, the source line structure and the drain line structure are formed simultaneously.

[0017] Optionally, the method for forming a storage gate structure further includes: forming a first gate dielectric layer between the floating gate and the substrate; and forming a second gate dielectric layer between the floating gate and the control gate.

[0018] Optionally, the method for forming a storage gate structure, a source line structure and a drain line structure includes: forming a first gate dielectric layer in a first trench, the first gate dielectric layer exposing surfaces of a first region and a second region; forming a first gate material layer on the surface of the first gate dielectric layer of the substrate and the surface of the substrate; forming a second gate dielectric layer on the surface of the first gate material layer, the second gate dielectric exposing the first gate material layer on the surface of the first region and the second region; forming a second gate material layer on the surface of the first gate material layer and the surface of the second gate dielectric layer; forming a patterned layer on the surface of the second gate material layer, the patterned layer exposing a portion of the surface of the second gate material layer; etching a portion of the first gate material layer and the second gate material layer using the patterned layer as a mask until the top surface of the substrate is exposed, thereby forming a floating gate, a control gate, a first structure layer, a second structure layer, a third structure layer and a fourth structure layer.

[0019] Optionally, the first gate material layer is doped with first doping ions, and the first doping ions include P-type ions or N-type ions; the second gate material layer is doped with second doping ions, and the second doping ions include P-type ions or N-type ions.

[0020] Optionally, the process of doping the first doping ions in the first gate material layer is an ion implantation process or an in-situ doping process; and the process of doping the second doping ions in the second gate material layer is an ion implantation process or an in-situ doping process.

[0021] Optionally, the method for forming a memory structure further includes: forming second trenches between adjacent memory gate structures, wherein the second trenches are arranged along the second direction and penetrate through a plurality of first trenches along the first direction.

[0022] Optionally, a width of the first trench ranges from 550 angstroms to 850 angstroms, and a height of the first trench ranges from 50 nanometers to 85 nanometers.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the memory structure of the technical solution of the present invention, part of the memory gate structure is located in the first groove, which reduces the thickness of the memory structure, improves the integration of the memory structure, and further reduces the depth of the grooves between the memory structures, reduces the resistance of the memory structure, and improves the performance of the memory structure as well as the uniformity and stability of the manufacturing process.

[0025] In the method for forming a memory structure of the technical solution of the present invention, a first groove is formed on a substrate, and a memory gate structure is formed on the first groove, so that the longitudinal dimension of the memory gate structure is reduced, thereby reducing the depth of the grooves between the memory structures, reducing the resistance of the memory structure, and improving the performance of the memory structure as well as the uniformity and stability of the manufacturing process.

[0026] Furthermore, in the technical solution of the present invention, a storage gate structure, a source line structure and a drain line structure are formed simultaneously by etching the first gate material layer and the second gate material layer, thereby reducing the influence of the distance between the storage gate structures on the formation of the source line structure and the drain line structure, and no additional deposition of conductive materials is required, thereby reducing process costs and process difficulty.

[0027] Furthermore, in the technical solution of the present invention, by performing high-concentration ion doping on the source line structure and the drain line structure, the resistance of the memory structure is reduced, thereby reducing the power consumption of the memory structure and improving the performance of the memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of a memory structure formation process in one embodiment;

[0029] Figures 2 to 19 It is a schematic diagram of the memory structure formation process in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0031] As described in the background art, the existing NOR Flash device needs to be further improved. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0032] Figure 1 is a schematic diagram of a memory structure forming process in one embodiment.

[0033] Please refer to Figure 1 The memory structure includes: a substrate 100, the substrate 100 includes a plurality of mutually discrete first regions I arranged along a second direction Y, and a second region II located between adjacent first regions I; a plurality of storage gate structures 101 located on the surface of the substrate 100 between the first region I and the second region II; a first trench located in the first region I (not shown in the figure); a second trench located in the second region II (not shown in the figure); a first doped layer 102 located in the first trench; a second doped layer 103 located in the second trench; a source line structure located on the first doped layer 102 (not shown in the figure); and a drain line structure located on the second doped layer 103 (not shown in the figure).

[0034] In the above scheme, since the storage gate structure 101 is formed on the surface of the active area, the thickness of the memory structure is increased. The preparation process of the first doping layer and the second doping layer is to perform ion implantation on the substrate 100 between adjacent storage gate structures 101 to make it conductive and then lead out from the common source. However, as the area of ​​the memory structure decreases, the above preparation method is limited by the gap between adjacent storage gate structures 101. When the gap between adjacent storage gate structures 101 is too small, it is difficult for the doped ions to be doped into the substrate 100, which can easily lead to increased resistance, increase device power consumption and process difficulty.

[0035] In order to reduce the thickness of the memory structure and improve the performance of the memory structure, the present invention proposes a memory structure and a method for forming the memory structure, by forming a first groove on a substrate and forming a memory gate structure on the first groove, so that the longitudinal dimension of the memory gate structure is reduced, thereby reducing the depth of the grooves between the memory structures, reducing the resistance of the memory structure, and improving the performance of the memory structure as well as the uniformity and stability of the manufacturing process.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 2 to 19 It is a schematic diagram of the memory structure formation process in an embodiment of the present invention.

[0038] Please refer to Figure 2 , Figure 2 As a schematic diagram of a top view structure, a substrate 200 is provided. The substrate 200 includes a plurality of mutually separated first regions I arranged along a second direction Y, and a second region II located between adjacent first regions I.

[0039] In this embodiment, the material of the substrate 200 is silicon.

[0040] In other embodiments, the material of the substrate 200 includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0041] Please refer to Figure 3 and Figure 4 , Figure 3 This is a top view of the structure. Figure 4 yes Figure 3 In the cross-sectional view along line AA1, a plurality of first trenches 201 are formed in the substrate 200. The plurality of first trenches 201 are arranged along a first direction X and cross a plurality of first regions I and a plurality of second regions II along a second direction Y.

[0042] In this embodiment, the method for forming the first trench 201 includes: forming an initial mask layer 202 on the surface of the substrate 200 , wherein the initial mask layer 202 exposes a portion of the surface of the substrate 200 ; and etching the substrate 200 using the initial mask layer 202 as a mask to form the first trench 201 .

[0043] In this embodiment, the first trench 201 is used to accommodate a floating gate 212 to be formed subsequently, so that the vertical thickness of the memory structure is reduced.

[0044] In this embodiment, after the first trench 201 is formed, an initial first gate dielectric layer 215 is formed in the first trench 201 .

[0045] In this embodiment, the width of the first trench 201 ranges from 550 angstroms to 850 angstroms, the height of the first trench 201 ranges from 50 nanometers to 85 nanometers, and the shapes of the first trench 201 include an inverted trapezoid, an inverted pyramid, and an inverted hemisphere.

[0046] In this embodiment, the method of forming the first trench 201 includes one of a wet etching process and a dry etching process or a combination of both.

[0047] The wet etching process parameters include: the etching solution includes at least two solutions of ammonia, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is 0wt% to 30wt%, and the reaction temperature range is 0 degrees Celsius to 80 degrees Celsius.

[0048] The process parameters of the dry etching process include: the etching gas includes at least three gases among fluorine, hydrogen, nitrogen, argon and ammonia, and the flow rate range of each gas is 0mL / min to 2000mL / min, the reaction pressure range is 0mT to 3000mT, the reaction temperature range is 0 degrees Celsius to 250 degrees Celsius, and the etching power range is 0W to 1000W.

[0049] Please refer to Figure 5 and Figure 6 , Figure 5 This is a top view of the structure. Figure 6 yes Figure 5 In the cross-sectional schematic diagram along line AA1, after the initial first gate dielectric layer 215 is formed, the initial first gate dielectric layer 215 and the initial mask layer 202 on the first region I and the second region II are removed to form a first gate dielectric layer 203 and a mask layer, and the first gate dielectric layer 203 exposes the surfaces of the first region I and the second region II.

[0050] In this embodiment, the material of the first gate dielectric layer 203 includes: silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0051] In this embodiment, the formation method of the first gate dielectric layer 203 includes: one or more of: chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, the deposition gas includes: hydrogen and monosilane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0052] Please refer to Figure 7 , Figure 8 and Fig. 9 , Figure 7 This is a top view of the structure. Figure 8 yes Figure 7 Schematic diagram of the cross section along line AA1, Fig. 9 yes Figure 7 In the cross-sectional schematic diagram along line BB1 ​​, a first gate material layer 204 is formed on the surface of the first gate dielectric layer 203 and the surface of the substrate 200 .

[0053] In this embodiment, the method for forming the first gate material layer 204 includes: depositing an initial first gate material layer (not shown in the figure) on the surface of the substrate 200; removing the initial first gate material layer (not shown in the figure) on the first groove 201 that is higher than the surface of the substrate 200 to form the first gate material layer 204 and the first opening 205.

[0054] In this embodiment, the height of the first opening 205 determines the thickness of the control gate 208 , the first structure layer 213 , and the third structure layer 214 that are subsequently formed.

[0055] In this embodiment, the first gate material layer 204 is doped with first doping ions, and the first doping ions include P-type ions or N-type ions, wherein the first doping ions include phosphorus ions, boron ions, and arsenic ions.

[0056] In this embodiment, the process of doping the first doping ions in the first gate material layer 204 is an ion implantation process or an in-situ doping process, and the activation temperature range of the ion implantation process or the in-situ doping process is 800 degrees Celsius to 1200 degrees Celsius.

[0057] In this embodiment, after forming the first gate material layer 204, the first gate material layer 204 on the first region I and the second region II is subjected to ion implantation again, and the dose range of the ion implantation is 1.0E12 ions / cm 2 To 1.0E20 ions / cm 2 .

[0058] Please refer to Fig.10 and Fig.11 , Fig.10 This is a top view of the structure. Fig.11 yes Fig.10In the cross-sectional diagram along line AA1, a second gate dielectric layer 206 is formed on the surface of the first gate material layer 204 between the first region I and the second region II, and the second gate dielectric layer 206 exposes the first gate material layer 204 on the surfaces of the first region I and the second region II.

[0059] In this embodiment, the second gate dielectric layer 206 is formed by a furnace tube method. Reactants of the furnace tube method include silicon-containing gas and nitrogen-containing gas. The reaction temperature ranges from 500 degrees Celsius to 800 degrees Celsius.

[0060] In this embodiment, the thickness of the second gate dielectric layer 206 ranges from 100 angstroms to 200 angstroms.

[0061] In this embodiment, the material of the second gate dielectric layer 206 includes: silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0062] In this embodiment, the second gate dielectric layer 206 can accurately control the width of the second gate material layer 207 subsequently formed in the first opening 205, thereby accurately controlling the size of the control gate 208 subsequently formed, and achieving precise alignment of the storage gate structure.

[0063] Please refer to Fig.12 , Fig.13 as well as Fig.14 , Fig.12 This is a top view of the structure. Fig.13 yes Fig.12 Schematic diagram of the cross section along line AA1, Fig.14 yes Fig.12 In the cross-sectional view along line BB1 ​​, a second gate material layer 207 is formed on the surface of the first gate material layer 204 and the surface of the second gate dielectric layer 206 .

[0064] In this embodiment, the second gate material layer 207 is doped with second doping ions, and the second doping ions include P-type ions or N-type ions, wherein the second doping ions include phosphorus ions, boron ions and arsenic ions.

[0065] In this embodiment, the process of doping the second doping ions in the second gate material layer 207 is an ion implantation process or an in-situ doping process, wherein the activation temperature range of the ion implantation process or the in-situ doping process is 800 degrees Celsius to 1200 degrees Celsius.

[0066] In this embodiment, after forming the second gate material layer 207, the second gate material layer 207 on the first region I and the second region II is subjected to ion implantation again, and the concentration range of the ion implantation is 1.0E12 ions / cm 2 To 1.0E20 ions / cm 2.

[0067] In the above scheme, the first gate material layer 204 and the second gate material layer 207 on the first region I and the second region II (i.e., the source line structure and the drain line structure formed subsequently) are locally doped with high-concentration ions, and ion activation is performed by high temperature, so that the first gate material layer 204 and the second gate material layer 207 on the first region I and the second region II after doping have a lower resistance than the floating gate 212 and the control gate 208.

[0068] Please refer to Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 , Fig.15 This is a top view of the structure. Fig.16 yes Fig.15 Schematic diagram of the cross section along line AA1, Fig.17 yes Fig.15 Schematic diagram of the cross section along line BB1, Fig.18 yes Fig.15 Schematic diagram of the cross section along the CC1 line, Fig.19 yes Fig.15 In the schematic cross-sectional view along line DD1, a patterned layer (not shown in the figure) is formed on the surface of the second gate material layer 207, and the patterned layer (not shown in the figure) exposes a portion of the surface of the second gate material layer 207; a portion of the first gate material layer 204 and the second gate material layer 207 is etched using the patterned layer (not shown in the figure) as a mask until the top surface of the substrate 200 is exposed, thereby forming a storage gate structure located on the first trench 201 between the first region I and the second region II, a source line structure located on the surface of the substrate 200 in the second region II and in the first trench 201, and A drain line structure located in the first trench 201 in the first region I, a storage gate structure including: a floating gate 212 located on the surface of the first gate dielectric layer 203 and a control gate 208 located on the surface of the second gate dielectric layer 206, a source line structure including: a first structure layer 213 located on the surface of the substrate 200 in the second region II and in the first trench 201 and a second structure layer 210 located on the surface of the first structure layer 213, and a drain line structure including: a third structure layer 214 located in the first trench 201 in the first region I and a fourth structure layer 209 located on the surface of the third structure layer 214.

[0069] In this embodiment, the method of forming the storage gate structure, the source line structure and the drain line structure comprises dry etching, and the dry etching gas comprises: tetrafluoromethane, dichlorotrifluoromethane gas and hydrogen chloride.

[0070] In this embodiment, the material of the floating gate 212 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0071] In this embodiment, the material of the control gate 208 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0072] In this embodiment, the material of the source line structure includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0073] In this embodiment, the material of the drain line structure includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0074] In this embodiment, the storage gate structure, the source line structure and the drain line structure are formed simultaneously.

[0075] In the above scheme, the storage gate structure, the source line structure and the drain line structure are formed simultaneously by etching the first gate material layer 204 and the second gate material layer 207, thereby reducing the influence of the distance between the storage gate structures on the formation of the source line structure and the drain line structure, and no additional deposition of conductive materials is required, thereby reducing the process cost and process difficulty.

[0076] In this embodiment, second trenches 211 are formed between adjacent storage gate structures. The second trenches 211 are arranged along the second direction Y and penetrate through a plurality of first trenches 201 along the first direction X.

[0077] In this embodiment, the width of the second trench 211 ranges from 550 angstroms to 850 angstroms, the height of the second trench 211 ranges from 50 nanometers to 85 nanometers, and the shapes of the second trench 211 include an inverted trapezoid, an inverted pyramid, and an inverted hemisphere.

[0078] In other embodiments not shown in the figure, the further comprising: forming an interlayer dielectric layer on the substrate 200 between the first region I and the second region II and in the second groove.

[0079] Among them, the method for forming the interlayer dielectric layer includes: depositing an initial interlayer dielectric layer (not shown in the figure) on the substrate 200 between the first region I and the second region II and in the second groove; planarizing the initial interlayer dielectric layer (not shown in the figure) until the surfaces of the storage gate structure, the source line structure and the drain line structure are exposed, thereby forming an interlayer dielectric layer (not shown in the figure).

[0080] In this embodiment, the planarization process adopts a chemical mechanical polishing process.

[0081] In this embodiment, the material of the interlayer dielectric layer (not shown in the figure) includes: silicon oxide, nitrogen-doped silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0082] Please continue to refer to Figures 15 to 19The technical solution of the present invention also provides a memory structure, including: a substrate 200, the substrate 200 includes a plurality of mutually discrete first regions I arranged along a second direction Y, and a second region II located between adjacent first regions I; a plurality of first trenches 201 located in the substrate 200, the plurality of first trenches 201 are arranged along a first direction X and span across a plurality of first regions I and a plurality of second regions II along a second direction Y; and a memory gate structure at least partially located in the first trenches 201 between the first region I and the second region II.

[0083] In this embodiment, the material of the substrate 200 is silicon.

[0084] In other embodiments, the material of the substrate 200 includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0085] In this embodiment, the width of the first trench 201 ranges from 550 angstroms to 850 angstroms, the height of the first trench 201 ranges from 50 nanometers to 85 nanometers, and the shapes of the first trench 201 include an inverted trapezoid, an inverted pyramid, and an inverted hemisphere.

[0086] In this embodiment, the storage gate structure includes: a floating gate 212 located in the first trench 201 and a control gate 208 located on the floating gate 212 .

[0087] In this embodiment, the material of the floating gate 212 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0088] In this embodiment, the material of the control gate 208 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0089] In this embodiment, the memory structure also includes: a source line structure located on the surface of the substrate 200 in the second region II and in the first groove 201, the material of the source line structure is a semiconductor material, and the source line structure is doped with conductive ions; a drain line structure located in the first groove 201 in the first region I, the material of the drain line structure is a semiconductor material, and the drain line structure is doped with conductive ions.

[0090] In this embodiment, the source line structure includes: a first structure layer 213 located on the surface of the substrate 200 in the second region II and in the first trench 201 , and a second structure layer 210 located on the surface of the first structure layer 213 .

[0091] In this embodiment, the material of the source line structure includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0092] In this embodiment, the drain line structure includes: a third structure layer 214 located in the first trench 201 in the first region I and a fourth structure layer 209 located on the surface of the third structure layer 214 .

[0093] In this embodiment, the material of the drain line structure includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0094] In this embodiment, the storage gate structure further includes: a first gate dielectric layer 203 located between the floating gate 212 and the substrate 200 ; and a second gate dielectric layer 206 located between the floating gate 212 and the control gate 208 .

[0095] In this embodiment, the materials of the first gate dielectric layer 203 and the second gate dielectric layer 206 include: silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0096] In this embodiment, the memory structure further includes: a plurality of second trenches 211 located between adjacent memory gate structures, wherein the plurality of second trenches 211 are arranged along the second direction Y and penetrate the plurality of first trenches 201 along the first direction X.

[0097] In this embodiment, the width of the second trench 211 ranges from 550 angstroms to 850 angstroms, the height of the second trench 211 ranges from 50 nanometers to 85 nanometers, and the shapes of the second trench 211 include an inverted trapezoid, an inverted pyramid, and an inverted hemisphere.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory structure, characterized in that: include: A substrate, the substrate comprising a plurality of mutually discrete first regions arranged along a second direction, and a second region located between adjacent first regions; A plurality of first grooves are located in the substrate, the plurality of first grooves are arranged along a first direction and cross a plurality of first regions and a plurality of second regions along a second direction; A storage gate structure is at least partially located within the first trench between the first region and the second region.

2. The memory structure according to claim 1, characterized in that: The storage gate structure includes: a floating gate located in a first trench and a control gate located on the floating gate.

3. The memory structure according to claim 2, characterized in that: The storage gate structure further includes: a first gate dielectric layer located between the floating gate and the substrate; and a second gate dielectric layer located between the floating gate and the control gate.

4. The memory structure according to claim 1, wherein: Also includes: A source line structure located on the substrate surface of the second region and in the first trench, wherein the source line structure is made of a semiconductor material and is doped with conductive ions; A drain line structure is located in the first trench of the first region, wherein the material of the drain line structure is a semiconductor material and conductive ions are doped in the drain line structure.

5. The memory structure according to claim 4, characterized in that: The source line structure includes: a first structure layer located on the substrate surface of the second region and in the first trench, and a second structure layer located on the surface of the first structure layer.

6. The memory structure according to claim 4, characterized in that: The drain line structure includes: a third structure layer located in the first groove in the first region and a fourth structure layer located on the surface of the third structure layer.

7. The memory structure according to claim 1, characterized in that: Also includes: A plurality of second trenches are located between adjacent storage gate structures, the plurality of second trenches are arranged along the second direction and penetrate the plurality of first trenches along the first direction.

8. A method for forming a memory structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of mutually discrete first regions arranged along a second direction, and a second region located between adjacent first regions; forming a plurality of first grooves in the substrate, wherein the plurality of first grooves are arranged along a first direction and cross a plurality of first regions and a plurality of second regions along a second direction; At least a portion of a storage gate structure is formed in the first trench between the first region and the second region.

9. The method for forming a memory structure according to claim 8, wherein: The method for forming the storage gate structure includes: forming a floating gate in a first trench; and forming a control gate on the floating gate.

10. The method for forming a memory structure according to claim 9, wherein: Also includes: forming a source line structure on the substrate surface of the second region and in the first trench, wherein the source line structure is made of a semiconductor material and is doped with conductive ions; A drain line structure is formed in the first trench of the first region. The material of the drain line structure is a semiconductor material and conductive ions are doped in the drain line structure.

11. The method for forming a memory structure according to claim 10, wherein: The method for forming the source line structure includes: forming a first structure layer on the substrate surface and in the first groove of the second region; forming a second structure layer on the surface of the first structure layer; the method for forming the drain line structure includes: forming a third structure layer in the first groove of the first region; forming a fourth structure layer on the surface of the third structure layer.

12. The method for forming a memory structure according to claim 11, wherein: The storage gate structure, source line structure and drain line structure are formed simultaneously.

13. The method for forming a memory structure according to claim 12, wherein: The method for forming the storage gate structure further includes: forming a first gate dielectric layer between the floating gate and the substrate; and forming a second gate dielectric layer between the floating gate and the control gate.

14. The method for forming a memory structure according to claim 13, wherein: The method for forming the storage gate structure, the source line structure and the drain line structure includes: forming a first gate dielectric layer in a first trench, the first gate dielectric layer exposing the surfaces of the first region and the second region; forming a first gate material layer on the surface of the first gate dielectric layer and the surface of the substrate; forming a second gate dielectric layer on the surface of the first gate material layer, the second gate dielectric layer exposing the first gate material layer on the surfaces of the first region and the second region; forming a second gate material layer on the surface of the first gate material layer and the surface of the second gate dielectric layer; forming a patterned layer on the surface of the second gate material layer, the patterned layer exposing a portion of the surface of the second gate material layer; etching a portion of the first gate material layer and the second gate material layer using the patterned layer as a mask until the top surface of the substrate is exposed, thereby forming a floating gate, a control gate, a first structure layer, a second structure layer, a third structure layer and a fourth structure layer.

15. The method for forming a memory structure according to claim 13, wherein: The first gate material layer is doped with first doping ions, which include P-type ions or N-type ions; the second gate material layer is doped with second doping ions, which include P-type ions or N-type ions.

16. The method for forming a memory structure according to claim 15, wherein: The process of doping the first doping ions in the first gate material layer is an ion implantation process or an in-situ doping process; the process of doping the second doping ions in the second gate material layer is an ion implantation process or an in-situ doping process.

17. The method for forming a memory structure according to claim 8, wherein: Also includes: Second trenches are formed between adjacent storage gate structures. The second trenches are arranged along the second direction and penetrate through a plurality of first trenches along the first direction.

18. The method for forming a memory structure according to claim 8, wherein: The width of the first trench is in a range of 550 angstroms to 850 angstroms, and the height of the first trench is in a range of 50 nanometers to 85 nanometers.

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