Semiconductor structure, preparation method thereof and storage system

Abstract

The invention provides a semiconductor structure, a preparation method thereof and a storage system, relates to the technical field of semiconductor chips, and aims to solve the problem of poor performance of a capacitor. The semiconductor structure comprises a stacked structure, a second conductive layer and a storage function layer. The stacked structure comprises a plurality of first conductive layers and a plurality of isolation layers which are alternately stacked; the second conductive layer penetrates through the stacked structure; the storage function layer is located between the first conductive layer and the second conductive layer and surrounds the second conductive layer. The first conductive layer comprises a board line layer and a conductive pattern, and the conductive pattern is located between the board line layer and the storage function layer and surrounds the storage function layer. Through the arrangement, the storage function layer is prevented from being directly formed on the side wall of the board line layer, so that the board line layer is prevented from being oxidized into the silicon oxide layer, the problem that polarization overturning of the storage function layer is hindered is solved, and the performance of the capacitor is improved. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, and a storage system. Background Art

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues.

[0003] To overcome the limitations of 2D or planar memory cells, the industry has developed memories with three-dimensional structures (3D) to increase storage density by arranging memory cells three-dimensionally on a substrate. Currently, capacitors in three-dimensional memories are still space-optimized. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a storage system, which are intended to solve the problem of poor performance of capacitors in three-dimensional storage.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a semiconductor structure is provided, comprising: a stacked structure, a second conductive layer, and a storage function layer. The stacked structure comprises a plurality of first conductive layers and a plurality of isolation layers alternately stacked; the second conductive layer runs through the stacked structure; the storage function layer is located between the first conductive layer and the second conductive layer, and surrounds the second conductive layer. The first conductive layer comprises a plate line layer and a conductive pattern, and the conductive pattern is located between the plate line layer and the storage function layer, and surrounds the storage function layer.

[0007] In the embodiment of the present application, since the first conductive layer and the isolation layer are alternately stacked, the conductive pattern in the first conductive layer and the isolation layer are also alternately stacked, so that two adjacent conductive patterns are electrically isolated, thereby avoiding short circuits between the formed capacitors. Furthermore, since the conductive pattern is located between the plate line layer and the storage function layer, the storage function layer is prevented from directly contacting the plate line layer, thereby avoiding the storage function layer from being directly formed on the side wall of the plate line layer, thereby avoiding the oxidation of part of the plate line layer close to the storage function layer into a silicon oxide layer, which is conducive to improving the problem of hindered polarization reversal of the storage function layer, thereby improving the performance of the capacitor.

[0008] In some implementations, a plurality of the conductive patterns that surround the same storage functional layer and are stacked in a direction perpendicular to the plate line layer are arranged in the same layer.

[0009] In some implementations, the isolation layer has a first gap therein.

[0010] In some implementations, the first gap is located between two adjacent plate line layers along a first direction, and the first gap is also located between two adjacent storage function layers; the first direction is perpendicular to the plate line layers.

[0011] In some implementations, in the adjacent conductive patterns and the board line layers: the first surface of the conductive pattern is recessed relative to the board line layer, and part of the isolation layer is located in a first recessed area enclosed by the first surface, the board line layer and the storage functional layer, and / or the second surface of the conductive pattern is recessed relative to the board line layer, and part of the isolation layer is located in a second recessed area enclosed by the second surface, the board line layer and the storage functional layer; the first surface and the second surface are arranged relative to each other in a direction perpendicular to the board line layer.

[0012] In some implementations, the semiconductor structure further includes an isolation portion, wherein the isolation portion penetrates the stacked structure and is connected to the isolation layer.

[0013] In some implementations, the isolation layer and the isolation portion are integrally formed.

[0014] In some implementations, the isolation portion has a second gap therein, and the second gap is connected to at least one of the first gaps.

[0015] In some implementations, the second gap is located between two adjacent storage functional layers and extends in a direction perpendicular to the plate line layer.

[0016] In some implementations, the semiconductor structure includes a substrate and a dielectric layer, the substrate is located on one side of the stacked structure, the dielectric layer is located on the other side of the stacked structure, and the isolation portion also penetrates the dielectric layer and extends into a portion of the substrate.

[0017] In some implementations, the material of the storage function layer includes a ferroelectric material.

[0018] In another aspect, a method for preparing a semiconductor structure is provided, comprising:

[0019] Providing a stacked structure, the stacked structure comprising a plurality of plate line layers and a plurality of sacrificial layers alternately stacked;

[0020] forming a capacitor hole, wherein the capacitor hole penetrates the stacked structure;

[0021] A plurality of conductive patterns, a storage function layer and a second conductive layer are formed in the capacitor hole, wherein one of the conductive patterns and one of the plate line layers constitute a first conductive layer, the storage function layer is located between the plurality of first conductive layers and the second conductive layer and surrounds the second conductive layer, and the plurality of conductive patterns are located between the plate line layer and the storage function layer and surround the storage function layer;

[0022] The sacrificial layer is replaced by the isolation layer to form a stacked structure.

[0023] In some implementations, the forming of a plurality of conductive patterns, a storage function layer, and a second conductive layer includes:

[0024] forming a third conductive layer, a storage function layer and a second conductive layer in the capacitor hole in sequence;

[0025] removing the sacrificial layer to form a first filling space;

[0026] A portion of the third conductive layer exposed to the first filling space is removed to form a plurality of conductive patterns.

[0027] In some implementations, after sequentially forming a third conductive layer, a storage functional layer, and a second conductive layer in the capacitor hole and before removing the sacrificial layer, the preparation method further includes:

[0028] forming a second filling space, wherein the second filling space penetrates the stacked structure;

[0029] The removing the sacrificial layer includes: removing the sacrificial layer through the second filling space.

[0030] In some implementations, before providing the stacked structure, a substrate is also provided, and the substrate is located on one side of the stacked structure;

[0031] After providing the stacked structure and before forming the capacitor hole, the preparation method further includes: providing a dielectric layer, wherein the dielectric layer is located on a side of the stacked structure away from the substrate;

[0032] The forming of the second filling space includes: the second filling space also penetrates the dielectric layer and extends into a portion of the substrate.

[0033] In some implementations, replacing the sacrificial layer with the isolation layer includes:

[0034] An isolation material is deposited in the first filling space and between two adjacent conductive patterns to form an isolation layer, wherein the isolation layer has a first gap therein.

[0035] In some implementations, when the preparation method further includes forming a second space,

[0036] During the process of depositing the isolation material in the first filling space, the isolation material is also deposited in the second filling space to form an isolation portion having a second gap therein, and the second gap is connected to at least one of the first gaps.

[0037] On the other hand, a storage system is provided, comprising: a semiconductor structure, wherein the semiconductor structure is the semiconductor structure described in any one of the above embodiments; and a controller coupled to the semiconductor structure.

[0038] It can be understood that the beneficial effects that can be achieved by the semiconductor structure, the method for preparing the semiconductor structure, and the storage system provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0040] Figure 1 is a block diagram of a storage system according to some embodiments;

[0041] Figure 2 is a block diagram of a storage system according to some other embodiments;

[0042] Figure 3 is a structural diagram of a semiconductor structure according to some embodiments;

[0043] Figure 4 A structural diagram of a semiconductor structure of some embodiments;

[0044] Figure 5 is a structural diagram of a semiconductor structure according to some embodiments;

[0045] Figure 6 is a structural diagram of a semiconductor structure according to some embodiments;

[0046] Figure 7 is a structural diagram of a semiconductor structure according to some embodiments;

[0047] Figure 8 is a structural diagram of a semiconductor structure according to some embodiments;

[0048] Fig. 9 for Figure 8 A cross-sectional view of a semiconductor structure along section line AA;

[0049] Fig.10 for Figure 8 A cross-sectional view of another semiconductor structure along section line AA;

[0050] Fig.11 for Figure 8 A cross-sectional view of another semiconductor structure along the BB section line;

[0051] Fig.12 for Figure 8 A cross-sectional view of another semiconductor structure along the BB section line;

[0052] Fig.13 is a flowchart of steps of a method for preparing a semiconductor structure according to some embodiments;

[0053] Fig.14 is a structural diagram of a capacitor hole formed in a method for preparing a semiconductor structure according to some embodiments;

[0054] Fig.15 A structural diagram after a material is filled in a capacitor hole in a method for preparing a semiconductor structure according to some embodiments;

[0055] Fig.16 is a structural diagram of a second filling space formed in a method for preparing a semiconductor structure according to some embodiments;

[0056] Fig.17 is a structural diagram of a first filling space formed in a method for preparing a semiconductor structure according to some embodiments;

[0057] Fig.18 A structural diagram after removing a portion of the third conductive layer exposed to the first filling space in a method for preparing a semiconductor structure according to some embodiments;

[0058] Fig.19 FIG. 1 is a structural diagram of forming an isolation layer and an isolation portion in a method for preparing a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0059] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0060] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0061] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0062] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0063] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0064] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0065] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0066] As used herein, "about", "substantially" or "approximately" includes the stated value and an average value within an acceptable deviation range of the particular value, wherein the acceptable deviation range is determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, that the difference between the two is less than or equal to 5% of either.

[0067] As used herein, "parallel" and "perpendicular" include the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.

[0068] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0069] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0070] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0071] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0072] Some embodiments of the present disclosure provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0073] The electronic device may include a storage system 1000, and may also include at least one of a processor and a cache. The processor is the control center of the electronic device, and uses various interfaces and lines to connect various parts of the entire electronic device. By running or executing software programs and / or modules stored in the storage system 1000, and calling data stored in the storage system 1000, the processor performs various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. Optionally, the processor may include one or more processing units. For example, the processor may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), etc. Different processing units may be independent devices or integrated into one or more processors. For example, the processor may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and an application program, and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor. The above-mentioned application processor may be, for example, a central processing unit (CPU).

[0074] Those skilled in the art will appreciate that the structure of the electronic device described above does not limit the electronic device, and the electronic device may include more or fewer components than the above components, or may combine some of the above components, or may have a different arrangement than the above components.

[0075] The storage system 1000 may be the storage system 1000 provided in any of the following embodiments of the present disclosure.

[0076] Figure 1 is a block diagram of a storage system according to some embodiments. Figure 2 is a block diagram of a storage system according to some other embodiments.

[0077] See also Figure 1 and Figure 2 Some embodiments of the present disclosure further provide a storage system 1000. The storage system 1000 includes a controller 200 and a semiconductor structure 100, wherein the controller 200 is coupled to the semiconductor structure 100. The semiconductor structure 100 may be a three-dimensional memory, and the controller 200 is used to control the semiconductor structure 100 to store data.

[0078] The following description will only take the semiconductor structure 100 as a three-dimensional memory as an example.

[0079] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0080] In some embodiments, see Figure 1 , the memory system 1000 includes a controller 200 and a semiconductor structure 100, and the memory system 1000 can be integrated into a memory card.

[0081] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0082] In other embodiments, see Figure 2 The storage system 1000 includes a controller 200 and a plurality of semiconductor structures 100, and the storage system 1000 is integrated into a solid state drive (SSD).

[0083] In the storage system 1000, in some embodiments, the controller 200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0084] In other embodiments, the controller 200 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0085] In some embodiments, the controller 200 may be configured to manage data stored in the semiconductor structure 100 and communicate with an external device (e.g., a host). In some embodiments, the controller 200 may also be configured to control operations of the semiconductor structure 100, such as read, erase, and program operations. In some embodiments, the controller 200 may also be configured to manage various functions regarding data stored or to be stored in the semiconductor structure 100, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 200 is also configured to process error correction codes for data read from or written to the semiconductor structure 100.

[0086] Of course, the controller 200 may also perform any other suitable functions, such as formatting the semiconductor structure 100 ; for example, the controller 200 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0087] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0088] The semiconductor structure 100 may be, for example, a ferroelectric random access memory (FeRAM). Ferroelectric random access memory is a high-performance, low-power non-volatile memory that can combine the advantages of conventional non-volatile memories (flash memory and EEPROM) and high-speed RAM (SRAM and DRAM). FeRAM can outperform existing memories such as EEPROM and flash memory due to its lower power consumption, faster response speed, and greater endurance for multiple read and write operations.

[0089] The semiconductor structure 100 may include a core region and a connection region, and the core region and the connection region are adjacent to each other. The connection region includes a plurality of contact structures, and the core region includes a plurality of storage cells, and the storage cells are electrically connected to the contact structures to realize functions such as reading. The semiconductor structure 100 provided in the embodiment of the present application may be, for example, a semiconductor structure 100 located in the core region.

[0090] Figure 3 FIG. 1 is a structural diagram of a semiconductor structure 100 according to some embodiments. Figure 3 As shown, the semiconductor structure 100 includes a stack structure 20 . The semiconductor structure 100 may also include a substrate 10 and a dielectric layer 30 . The substrate 10 may be located on one side of the stack structure 20 , and the dielectric layer 30 may be located on the other side of the stack structure 20 .

[0091] The material of the dielectric layer 30 may include insulating materials such as silicon dioxide, silicon nitride, silicon oxynitride, etc. The dielectric layer 30 and the stacked structure 20 are made of different materials, and under the same process conditions, the etching speed of the dielectric layer 30 is different from the etching speed of the stacked structure 20. The dielectric layer 30 can prevent the etching solution from entering the stacked structure 20, and the dielectric layer 30 can protect the stacked structure 20 from being etched when the structure located on the side of the stacked structure 201 away from the substrate 10 is subsequently removed.

[0092] The stacked structure 20 includes a first conductive layer 22 and an isolation layer 21 which are alternately stacked. The material of the isolation layer 21 may include an insulating material, and the insulating material may include a combination of one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide) and Si3N4 (silicon nitride).

[0093] The semiconductor structure 100 further includes a second conductive layer 42 and a storage function layer 41 that penetrate the stacked structure 20, and the storage function layer 41 is located between the first conductive layer 22 and the second conductive layer 42, and surrounds the second conductive layer 42. Exemplarily, the storage function layer 41 may be roughly cylindrical. In some embodiments, the second conductive layer 42 may be roughly cylindrical, and accordingly, the semiconductor structure 100 may further include a support column 43, the support column 43 penetrates the stacked structure 20, and the support column 43 is located in the cylindrical structure surrounded by the second conductive layer 42. Among them, the material of the support column 43 may include an insulating material or a conductive material.

[0094] Of course, in some other embodiments, the second conductive layer 42 may also be substantially in a columnar structure, and the second conductive layer 42 may play a supporting role. Accordingly, the semiconductor structure 100 may also omit the supporting column 43 .

[0095] Through the above arrangement, at least part of the first conductive layer 22 surrounding the outer surface of the storage function layer 41 constitutes a first capacitor plate, the second conductive layer 42 is a second capacitor plate, and the storage function layer 41 is a capacitor dielectric layer, so that the first conductive layer 22, the second conductive layer 42 and the storage function layer 41 constitute a plurality of stacked capacitors C1. The stacked plurality of capacitors C1 share the same second capacitor plate, and the stacked plurality of capacitors C1 share the same storage function layer 41. Figure 3 The plurality of capacitors C1 stacked in a direction perpendicular to the substrate 10 may be referred to as a capacitor group C2, and the semiconductor structure 100 may include a plurality of capacitor groups C2 that penetrate the stack structure 20. In some embodiments, the plurality of capacitor groups C2 are arranged in a plurality of rows and columns.

[0096] The material of the storage function layer 41 may include a ferroelectric material. For example, the storage function layer 41 may be a ferroelectric material such as ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, or a material doped with other elements based on the material and any combination thereof. When the material of the storage function layer 41 includes a ferroelectric material, the capacitor C1 is a ferroelectric capacitor C1, and accordingly, the three-dimensional memory is a ferroelectric memory.

[0097] It is worth noting that the semiconductor structure 100 may further include a transistor, and the transistor is electrically connected to the capacitor C1. The transistor may be located on the side of the stacked structure 20 away from the substrate 10, or the transistor may be located on the side of the stacked structure 20 close to the transistor. The embodiment of the present application does not limit the number of transistors electrically connected to the capacitor group C2.

[0098] For example, a transistor may be electrically connected to a capacitor group C2, so that a plurality of capacitors C1 in the capacitor group C2 and a transistor constitute a storage unit, and the storage unit has a 1TnC (1-transistor-n-capacitor) structure, that is, a storage unit includes a transistor and n capacitors C1. Accordingly, in some embodiments, a plurality of storage units may also be arranged in the form of multiple rows and columns.

[0099] Based on the above structure, when the ferroelectric memory is working, the first conductive layer 22 can receive the line control signal, and the plate line control signal is connected to the corresponding capacitor C1 through the first conductive layer 22, and the storage function layer 41 of the selected capacitor C1 is positively polarized or negatively polarized, so as to write different logic information in the selected capacitor C1. For example, when the storage function layer 41 is positively polarized, the logic signal "0" is written, and for another example, when the storage function layer 41 is negatively polarized, the logic signal "1" is written.

[0100] Figure 4 FIG. 1 is a structural diagram of a semiconductor structure 100 ′ in some embodiments. Figure 4 As shown, in some embodiments, the first conductive layer 22' is a plate line layer 221', and the plate line layer 221' surrounds the storage function layer 41'. Through the above configuration, at least part of the plate line layer 221' surrounding the storage function layer 41' constitutes a first capacitor plate.

[0101] In some embodiments, the process of preparing the semiconductor structure 100' includes: forming a capacitor hole 40' penetrating the plate line layer 221'; and then sequentially depositing a ferroelectric material and a conductive material in the capacitor hole 40' to form a storage function layer 41' and a second conductive layer 42'.

[0102] However, the material of the plate line layer 221' usually includes heavily doped polysilicon. In the process of depositing ferroelectric material in the capacitor hole 40' to form the storage function layer 41' (the storage function layer 41' may include a hafnium-based ferroelectric film, for example), the oxidant in the preparation process usually oxidizes the heavily doped polysilicon, so that the portion of the plate line layer 221' close to the storage function layer 41' is oxidized into a silicon oxide layer. The silicon oxide layer is located between the plate line layer 221' and the storage function layer 41', and the dielectric constant of the silicon oxide layer is much lower than that of the storage function layer 41', resulting in the actual partial voltage of the storage function layer 41' being much lower than the external voltage. At the same time, the defect states in the silicon oxide layer capture electrons, which has a depolarizing effect, hindering the polarization reversal of the ferroelectric domain, that is, hindering the storage function layer 41' from being positively polarized or negatively polarized, thereby resulting in poor performance of the capacitor.

[0103] In view of this, refer to Figure 3In the embodiment of the present application, the first conductive layer 22 includes a plate line layer 221 and a conductive pattern 222 . The conductive pattern 222 is located between the plate line layer 221 and the storage function layer 41 , and surrounds the storage function layer 41 .

[0104] Exemplarily, the conductive pattern 222 may be roughly tubular, and the outer peripheral surface of the conductive pattern 222 is in contact with the plate line layer 221, and the inner peripheral surface of the conductive pattern 222 is in contact with the storage function layer 41. The material of the conductive pattern 222 may include metal. For example, the material of the conductive pattern 222 may include a combination of one or more conductive materials such as Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc. Of course, in some other embodiments, the material of the conductive pattern 222 may also be other conductive materials, which is not limited in the embodiments of the present application.

[0105] In some embodiments, the conductive pattern 222 is made of the same material as the second conductive layer 42. For example, the conductive pattern 222 and the second conductive layer 42 may include TiN (titanium nitride). The above configuration is helpful to ensure the conductive performance of the conductive pattern 222 and the second conductive layer 42, thereby ensuring the performance of the capacitor group C2.

[0106] For the convenience of description, the direction perpendicular to the board line layer 221 is referred to as the first direction X, and the direction parallel to the board line layer 221 is referred to as the second direction Y and the third direction Z, and the third direction Z is perpendicular to the second direction Y.

[0107] Furthermore, since the first conductive layer 22 and the isolation layer 21 are alternately stacked, and the first conductive layer 22 includes the conductive pattern 222, the conductive pattern 222 and the isolation layer 21 are alternately stacked. Through the above arrangement, two adjacent conductive patterns 222 in the first direction X are electrically isolated, thereby preventing a short circuit from occurring between the first capacitor plates of two adjacent capacitors C1.

[0108] Through the above arrangement, during the preparation process of the semiconductor structure 100, a capacitor hole 40 penetrating the plate line layer 221 can be formed, and then a conductive pattern 222 is first formed in the capacitor hole 40, and then a storage function layer 41 is formed in the capacitor hole 40 having the conductive pattern 222, and then a second conductive layer 42 is further formed in the capacitor hole 40 having the conductive pattern 222 and the storage function layer 41. Through the above arrangement, since the conductive pattern 222 is located between the plate line layer 221 and the storage function layer 41, the storage function layer 41 is prevented from directly contacting the plate line layer 221, so as to avoid the storage function layer 41 being directly formed on the side wall of the plate line layer 221, and further avoid the oxidation of the part of the plate line layer 221 close to the storage function layer 41 into a silicon oxide layer, which is conducive to improving the problem of obstruction of polarization reversal of the storage function layer 41, and further improves the performance of the capacitor C1.

[0109] As described in the above embodiment, during the preparation of the semiconductor structure 100, a plurality of capacitor holes 40 can be made, and a capacitor group C2 can be formed in the corresponding capacitor holes 40. Furthermore, a plurality of conductive patterns 222 stacked around the same storage functional layer 41 and arranged in a direction perpendicular to the plate line layer 221 can be arranged in the same layer. Here, "arranged in the same layer" can be understood as a layer structure formed by the same film forming process, and the material of the layer structure is the same. The specific graphics in the formed layer structure can be continuous or discontinuous, and these specific graphics may also be at different heights or have different thicknesses.

[0110] Exemplarily, in the same capacitor group C2, since the multiple capacitors C1 are stacked along the first direction X, the multiple conductive patterns 222 are also stacked along the first direction X; and since the multiple capacitors C1 share the same storage function layer 41, the multiple conductive patterns 222 surround the same storage function layer 41. Through the above arrangement, the multiple capacitors C1 in the same capacitor group C2 are prepared together, which is conducive to simplifying the preparation process of the capacitor C1 and improving the preparation efficiency of the capacitor C1.

[0111] like Figure 3 As shown, in some embodiments, the isolation layer 21 may be a solid structure. Of course, in some other embodiments, the isolation layer 21 may also include a hollow structure.

[0112] Figure 5 FIG. 1 is a structural diagram of a semiconductor structure 100 according to some embodiments. Figure 5As shown, the isolation layer 21 may have a first gap 211. Exemplarily, the isolation layer 21 may enclose the first gap 211. Among the multiple isolation layers 21 in the stacked structure 20, at least one isolation layer 21 may have a first gap 211. Further, one isolation layer 21 may include one first gap 211. Alternatively, one isolation layer 21 may also include multiple first gaps 211 spaced apart from each other, and the multiple first gaps 211 are not connected.

[0113] In the preparation process of forming the isolation layer 21, a deposition process may be used to deposit in the corresponding filling space, and the deposited material first covers the sidewalls of the filling space. At the same time, since the deposition process may not achieve uniform coverage, the thickness of the material deposited on the sidewalls of the filling space is different. In the process of further depositing material into the filling space, the thicker deposited material will be closed first, resulting in the formation of a first gap 211 with air inside.

[0114] It is understandable that the first gap 211 includes air, and the dielectric constant of air is approximately 1. Compared with the isolation layer 21 of a solid structure, the isolation layer 21 having the first gap 211 has a lower dielectric constant, which is beneficial to further improve the electrical isolation effect between two adjacent plate line layers 221, thereby reducing the parasitic capacitance between the two adjacent plate line layers 221.

[0115] Continue to refer to Figure 5 , the first gap 211 may be located between two plate line layers 221 adjacent to each other along the first direction X, and the first gap 211 may also be located between two adjacent storage function layers 41. Exemplarily, the first gap 211 is located inside the isolation layer 21, and the first gap 211 is spaced apart from the plate line layer 221, and the first gap 211 is spaced apart from the storage function layer 41. Here, "spaced apart" means that the first gap 211 is not in contact with the plate line layer 221, and the first gap 211 is not in contact with the storage function layer 41. The above arrangement is also conducive to improving the electrical isolation effect between two adjacent capacitor groups C2, thereby reducing the parasitic capacitance between two adjacent capacitor groups C2.

[0116] Continue to refer to Figure 5, the conductive pattern 222 may include a first surface 222a and a second surface 222b that are arranged opposite to each other along a first direction X. Here, "arranged opposite to each other along a first direction X" should be interpreted in the broadest way, and can be understood as: the orthographic projection of the first surface 222a on the conductive pattern 222 caused by the light parallel to the direction overlaps with the orthographic projection of the second surface 222b on the conductive pattern 222 caused by the light in the direction. The overlap may be, for example, a complete overlap or a partial overlap. The first surface 222a may be farther away from the substrate 10 than the second surface 222b. For example, the first surface 222a may be Figure 5 The upper surface of the conductive pattern 222 in the second surface 222b may be Figure 5 The lower surface of the conductive pattern 222 in the embodiment.

[0117] In some embodiments, in the adjacent conductive pattern 222 and plate line layer 221: the first surface 222a of the conductive pattern 222 may be recessed relative to the plate line layer 221, and part of the isolation layer 21 may be located in a first recessed region enclosed by the first surface 222a, the plate line layer 221, and the storage function layer 41. Exemplarily, in the first recessed region M1 enclosed by the first surface 222a, the plate line layer 221, and the storage function layer 41, part of the isolation layer 21 is located in the first recessed region M1, that is, part of the isolation layer 21 extends between the storage function layer 41 and the plate line layer 221. The above arrangement is conducive to further improving the electrical isolation effect between two adjacent capacitor groups C2, thereby reducing the parasitic capacitance between two adjacent capacitor groups C2.

[0118] Similarly, in some embodiments, the second surface 222b of the conductive pattern 222 may be recessed relative to the plate line layer 221, and part of the isolation layer 21 may be located in a second recessed region enclosed by the second surface 222b, the plate line layer 221, and the storage function layer 41. Exemplarily, in the second recessed region M2 enclosed by the second surface 222b, the plate line layer 221, and the storage function layer 41, part of the isolation layer 21 is located in the second recessed region M2, that is, part of the isolation layer 21 extends between the storage function layer 41 and the plate line layer 221. The above arrangement is conducive to further improving the electrical isolation effect between two adjacent capacitor groups C2, thereby reducing the parasitic capacitance between two adjacent capacitor groups C2.

[0119] Figure 6 FIG. 1 is a structural diagram of a semiconductor structure 100 according to some embodiments. Figure 6The semiconductor structure 100 may further include an isolation portion 50, which may penetrate the stacked structure 20 and be connected to the isolation layer 21. Exemplarily, the isolation portion 50 may be located between two adjacent capacitor groups C2. The above arrangement is conducive to further improving the electrical isolation effect between the two adjacent capacitor groups C2, thereby reducing the parasitic capacitance between the two adjacent capacitor groups C2. At the same time, the isolation portion 50 can also provide mechanical support and / or load balancing.

[0120] In some examples, the isolation portion 50 may be a columnar structure. Alternatively, in some other examples, the isolation portion 50 may also be an isolation sidewall. Of course, the shape of the isolation portion 50 is not limited to the above structure, and the embodiment of the present application does not limit the shape of the isolation portion 50. Among them, the number of isolation portions 50 may be one or more, and the present application does not limit the number of isolation portions 50.

[0121] In the embodiment where the semiconductor structure 100 further includes a substrate 10 and a dielectric layer 30 , the isolation portion 50 may also penetrate the dielectric layer 30 and extend into a portion of the substrate 10 .

[0122] In some embodiments, the isolation layer 21 and the isolation portion 50 can be integrally formed. Here, "integrated forming" means that during the preparation process of the semiconductor structure 100, the isolation layer 21 and the isolation portion 50 can be made simultaneously using the same material, and the isolation portion 50 and the isolation layer 21 are combined into a whole. For example, a filling space can be formed first, and then a thin film deposition process such as CVD (Chemical Vapor Deposition), PVD (Physical Vapour Deposition) or ALD (Atomic Layer Deposition) is used to deposit the same material in the filling space, thereby forming the isolation layer 21 and the isolation portion 50 simultaneously.

[0123] The above configuration is conducive to further reducing the difficulty of preparing the isolation layer 21 and the isolation part 50, and improving the preparation efficiency of the semiconductor structure 100. At the same time, since the isolation layer 21 and the isolation part 50 are made of the same material, it is conducive to reducing the preparation cost of the semiconductor structure 100.

[0124] like Figure 6 As shown, in some embodiments, the isolation part 50 may be a solid structure. Of course, in some other embodiments, the isolation part 50 may also include a hollow structure.

[0125] Figure 7 is a structural diagram of a semiconductor structure 100 according to some embodiments; Figure 8 FIG. 1 is a structural diagram of a semiconductor structure 100 according to some embodiments. Figure 7 and Figure 8 As shown, the isolation part 50 may have a second gap 51 therein, and the second gap 51 may be connected to at least one first gap 211. Exemplarily, the isolation part 50 may enclose the second gap 51. In the embodiment where each isolation layer 21 has a first gap 211, each first gap 211 may be connected to the second gap 51.

[0126] In the preparation process of forming the isolation part 50, a deposition process can be used to deposit in the corresponding filling space, and the deposited material first covers the sidewalls of the filling space. At the same time, since the deposition process may not achieve uniform coverage, the thickness of the material deposited on the sidewalls of the filling space is different. In the process of further depositing material into the filling space, the thicker deposited material will be closed first, resulting in the formation of a second gap 51 with air inside.

[0127] It is understandable that the first gap 211 includes air, and the dielectric constant of air is approximately 1. Compared with the isolation part 50 of a solid structure, the isolation part 50 having the second gap 51 has a lower dielectric constant, which is beneficial to further improve the electrical isolation effect between two adjacent capacitor groups C2, thereby reducing the parasitic capacitance between the two adjacent capacitor groups C2.

[0128] Reference Figure 7 , the second gap 51 can be located between two adjacent storage function layers 41 and extend along the first direction X. Exemplarily, since the isolation layer 21 penetrates the plate line layer 221 and the isolation layer 21, the second gap 51 is also located in the plate line layer 221, so that the plate line layer 221 is arranged around the second gap 51; the second gap 51 is also connected to the first gap 211, so that the isolation layer 21 is also arranged around the second gap 51. At the same time, the second gap 51 is also spaced apart from the plate line layer 221. Here, "spaced apart" means that the second gap 51 is not in contact with the plate line layer 221. Through the above arrangement, it is also beneficial to further improve the electrical isolation effect between the two adjacent capacitor groups C2, thereby further reducing the parasitic capacitance between the two adjacent capacitor groups C2.

[0129] Above Figure 6 , Figure 7 as well as Figure 8 , shows an embodiment of different structures formed by combining the isolation part 50 and the isolation layer 21 provided by the present application. For example, Figure 6 The isolation layer 21 is a solid structure, and the isolation part 50 is also a solid structure; Figure 7 The isolation layer 21 is a solid structure, and the isolation part 50 is a hollow structure; Figure 8 The isolation layer 21 in the embodiment is a hollow structure, and the isolation part 50 is also a hollow structure.

[0130] When both the isolation layer 21 and the isolation column are solid structures, it is beneficial to improve the stability of the semiconductor structure 100; when both the isolation layer 21 and the isolation column are hollow structures, it is beneficial to reduce parasitic capacitance and improve the performance of the semiconductor structure 100. In the application process of the semiconductor structure 100, the corresponding combination structure of the isolation layer 21 and the isolation part 50 can be selected according to actual needs.

[0131] The following is only Figure 8 The semiconductor structure 100 shown in FIG. is used as an example for explanation. Fig. 9 for Figure 8 A cross-sectional view of a semiconductor structure 100 along the AA section line; Fig.10 for Figure 8 FIG. 1 is a cross-sectional view of another semiconductor structure 100 along the AA section line. It is worth noting that: Fig. 9 and Fig.10 The blank area in ? indicates that the interior of the partition 50 is not filled.

[0132] Reference Fig. 9 In some embodiments, the isolation portion 50 may be substantially a columnar structure. For example, the isolation portion 50 may be substantially a cylindrical structure, wherein the second gap 51 in the isolation portion 50 may also be substantially a columnar structure.

[0133] Reference Fig.10 In some embodiments, the isolation portion 50 may be substantially a sidewall structure, and the second gap 51 in the isolation portion 50 may also be substantially in the shape of a sidewall. Of course, the shape of the second gap 51 in the embodiment of the present application is not limited to the above two types, and the present application does not specifically limit the shape of the second gap 51 in the isolation portion 50.

[0134] Fig.11 for Figure 8 A cross-sectional view of another semiconductor structure 100 along the cross-sectional line BB; Fig.12 for Figure 8 FIG. 1 is a cross-sectional view of another semiconductor structure 100 along the BB cross-sectional line. It is worth noting that when the isolation portion is substantially a cylindrical structure, Fig.11 and Fig.12 The area in the dotted line frame in the figure may be the second filling space 62 where the isolation part is located (the second filling space 62 is a hole), and an isolation part having a second gap 51 needs to be formed in the second filling space 62, wherein: Fig.11 and Fig.12 The area in the middle dotted line frame may be the second gap 51. It is worth noting that Fig.11 and Fig.12 The blank area in φ indicates that the interior of the isolation layer 21 and the isolation portion 50 are not filled.

[0135] In some embodiments, Fig.11 As shown, the first gap 211 is located between two adjacent storage function layers 41 arranged along the second direction Y; the distance between two adjacent storage function layers 41 arranged along the third direction Z is small, so that there may be no first gap 211 between two adjacent storage function layers 41 arranged along the third direction Z. Through the above arrangement, part of the isolation layer 21 surrounds the storage function layer 41, and the isolation layers 21 surrounding different storage function layers 41 may contact each other.

[0136] In some other embodiments, such as Fig.12 As shown, the first gap 211 may be located between two adjacent storage function layers 41 arranged along the second direction Y, and the first gap 211 may also be located between two adjacent storage function layers 41 arranged along the third direction Z. Through the above arrangement, part of the isolation layer 21 surrounds the storage function layer 41, and is spaced between the isolation layers 21 outside different storage function layers 41.

[0137] As described in the above embodiments, the isolation portion 50 and the isolation layer 21 can be integrally formed. During the preparation of the isolation portion 50 and the isolation layer 21, material can be deposited in the filling space, and the deposited material first covers the sidewalls of the filling space. At the same time, since the deposition process may not be able to achieve uniform coverage, the thickness of the material deposited on the sidewalls of the filling space is different (for example, the deposition process may cause the material on the side away from the substrate 10 to be thicker, that is, the material at the top of the figure is thicker). In the process of further depositing material into the filling space, the thicker deposited material will close first (for example, the material at the top of the figure will close first), resulting in the formation of a connected first gap 211 and a second gap 51.

[0138] When the filling space for forming the isolation part 50 is narrower than the filling space for forming the isolation layer 21: in the process of depositing material into the filling space, the narrower filling space may be filled first, thereby causing the isolation part 50 to form a solid structure and the isolation layer 21 to form a hollow structure, that is, there is no gap in the isolation part 50, but there is a first gap 211 in the isolation layer 21.

[0139] On the contrary, when the filling space for forming the isolation layer 21 is narrower than the filling space for forming the isolation part 50: in the process of depositing material into the filling space, the narrower filling space may be filled first, resulting in the isolation layer 21 forming a solid structure and the isolation part 50 forming a hollow structure, that is, there is no gap in the isolation layer 21, but there is a second gap 51 in the isolation part 50.

[0140] The embodiment of the present application further provides a method for preparing a semiconductor structure 100 , which is used to prepare the semiconductor structure 100 in any of the above embodiments. Fig.13FIG. 1 is a flow chart of steps of a method for preparing a semiconductor structure 100 according to some embodiments. Fig.13 , the preparation method includes steps S1-S4.

[0141] S1. Provide a stacked structure, wherein the stacked structure includes a plurality of board line layers and a plurality of sacrificial layers that are alternately stacked.

[0142] Fig.14 FIG. 4 is a structural diagram of a capacitor hole 40 formed in a method for preparing a semiconductor structure 100 according to some embodiments. Fig.14 The step of providing the stacked structure 201 is explained.

[0143] It is worth noting that before forming the stacked structure 201, the process may further include: providing a substrate 10, wherein the substrate 10 is located at one side of the stacked structure 201. Fig.14 The substrate 10 may include, for example, a composite substrate 10, the material of which may include a combination of multiple materials including silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), and any other suitable materials. Of course, in some embodiments, the substrate 10 may also include a single-layer structure, which is not limited in the embodiments of the present disclosure.

[0144] Reference Fig.14 The step of forming the stacked structure 201 includes: alternately forming a plurality of plate line layers 221 and a plurality of sacrificial layers 223. The sacrificial layers 223 and the plate line layers 221 are made of two different materials, and under the same process conditions, the etching rate of the sacrificial layers 223 is different from the etching rate of the plate line layers 221. In some examples, the sacrificial layers 223 include nitride (e.g., silicon nitride), and the plate line layers 221 include heavily doped polysilicon.

[0145] The number of layers of the sacrificial layer 223 and the number of layers of the plate line layer 221 may be equal. It is understood that the number of layers of the sacrificial layer 223 and the number of layers of the plate line layer 221 may be adjusted accordingly according to the number of capacitors in a capacitor group. For example, for a capacitor group including three capacitors, three layers of sacrificial layer 223 and three layers of plate line layer 221 may be stacked.

[0146] After providing the stacked structure 201 and before forming the capacitor hole 40, the preparation method further includes: providing a dielectric layer 30, the dielectric layer 30 being located on a side of the stacked structure 201 facing away from the substrate 10. The dielectric layer 30 may be, for example, an etch stop layer, which is used to protect the stacked structure 201 from being etched when the structure on the stacked structure 201 is subsequently removed.

[0147] In the embodiment of the present application, after the stacked structure 201 is formed, the preparation process of the semiconductor structure 100 further includes step S2.

[0148] S2. A capacitor hole is formed, and the capacitor hole penetrates the laminated structure.

[0149] Continue to refer to Fig.14 In an embodiment where the semiconductor structure further includes a dielectric layer 30 and a substrate 10 , the capacitor hole 40 also penetrates the dielectric layer 30 , and the capacitor hole 40 also extends into the interior of the substrate 10 .

[0150] There may be a plurality of capacitor holes 40. In some embodiments, the plurality of capacitor holes 40 may be distributed in an array.

[0151] In the embodiment of the present application, after the capacitor hole 40 is formed, the preparation process of the semiconductor structure 100 further includes step S3.

[0152] S3. Multiple conductive patterns, storage functional layers and second conductive layers are formed in the capacitor hole, wherein a conductive pattern and a plate line layer constitute a first conductive layer, the storage functional layer is located between the multiple first conductive layers and the second conductive layer and surrounds the second conductive layer, and multiple conductive patterns are located between the plate line layer and the storage functional layer and surround the storage functional layer.

[0153] Fig.15 FIG. 4 is a structural diagram of a method for manufacturing a semiconductor structure 100 according to some embodiments after a material is filled in a capacitor hole 40. Fig.15 In the embodiment of the present application, the step of forming a plurality of conductive patterns 222 , a storage function layer 41 and a second conductive layer 42 may include: sequentially forming a third conductive layer 44 , a storage function layer 41 and a second conductive layer 42 in the capacitor hole 40 .

[0154] Exemplarily, the third conductive layer 44 may cover the side walls and bottom walls of the capacitor hole 40, so that the third conductive layer 44 encloses a groove, the storage function layer 41 may cover the side walls and bottom walls of the groove enclosed by the third conductive layer 44, and the second conductive layer 42 may cover the side walls and bottom walls of the groove enclosed by the storage function layer 41. In the above steps, the third conductive layer 44, the storage function layer 41 and the second conductive layer 42 may also be formed by a thin film deposition process such as CVD, PVD or ALD.

[0155] As described in the above embodiments, the third conductive layer 44 and the second conductive layer 42 may be made of the same material, such as metal or other conductive materials. In some preferred embodiments, the third conductive layer 44 and the second conductive layer 42 may be made of TiN (titanium nitride).

[0156] Furthermore, a support column 43 may be formed in the groove surrounded by the second conductive layer 42, wherein the material of the support column 43 may include an insulating material or a conductive material. In some other examples, the second conductive layer 42 may also fill the groove surrounded by the storage function layer 41. Based on the above structure, the support column 43 may be omitted in the semiconductor structure 100.

[0157] Fig.16 FIG. 4 is a structural diagram of a second filling space 62 formed in a method for manufacturing a semiconductor structure 100 according to some embodiments. Fig.17 FIG. 4 is a structural diagram of a first filling space 61 formed in a method for manufacturing a semiconductor structure 100 according to some embodiments.

[0158] Combination Fig.16 and Fig.17 As shown, in the embodiment of the present application, the step of forming a plurality of conductive patterns 222 , a storage function layer 41 and a second conductive layer 42 may further include: removing the sacrificial layer 223 to form a first filling space 61 .

[0159] Exemplarily, after the sacrificial layer 223 is removed, the location of the original sacrificial layer 223 is the first filling space 61. Since the sacrificial layer 223 and the board line layer 221 are alternately stacked, in order to facilitate the removal of the sacrificial layer 223 and realize the side excavation of the stacked structure 201, before removing the sacrificial layer 223, a second filling space 62 penetrating the stacked structure 201 can be formed to expose the sacrificial layer 223.

[0160] Reference Fig.16 After forming the third conductive layer 44, the storage function layer 41 and the first conductive layer 22 in the capacitor hole 40 in sequence, and before removing the sacrificial layer 223, the preparation method of the semiconductor structure 100 also includes: forming a second filling space 62, and the second filling space 62 penetrates the stacked structure 201.

[0161] In some embodiments, the second filling space 62 may be a hole. It is understood that the semiconductor structure 100 may also include a plurality of virtual capacitor groups that penetrate the stacked structure 201, and the structure of the virtual capacitor group may be the same as that of the capacitor group C2. It should be noted that the virtual capacitor group may not actually be used as a storage unit, but rather serves to provide mechanical support and / or load balancing for the three-dimensional memory. In the process of preparing the virtual capacitor group, a through hole that penetrates the stacked structure 201 may be formed, and then a virtual capacitor group may be formed in the through hole. Among them, the through hole may include the second filling space 62.

[0162] For example, part of the stacked structure 201 may be removed to form a through hole that penetrates the stacked structure 201. The step of forming the second filling space 62 further includes: the second filling space 62 also penetrates the dielectric layer 30 and extends into part of the substrate 10. Exemplarily, the through hole may also penetrate the dielectric layer 30 and part of the substrate 10. The present application does not specifically limit the number or position of the through hole.

[0163] In some other embodiments, the second filling space 62 may also be a groove. It is understood that the semiconductor structure 100 may also include a slit that penetrates the stacked structure 201. In the process of preparing the slit, a groove that penetrates the stacked structure 201 may be formed, and then a slit is formed in the through hole. The groove may include the second filling space 62.

[0164] For example, part of the stacked structure 201 may be removed to form a groove that penetrates the stacked structure 201. The step of forming the second filling space 62 further includes: the second filling space 62 also penetrates the dielectric layer 30 and extends into part of the substrate 10. Exemplarily, the orthographic projection of the groove on the substrate 10 may be roughly rectangular, and the groove may also penetrate the dielectric layer 30 and part of the substrate 10. The present application does not specifically limit the number or position of the grooves.

[0165] Reference Fig.16 and 17 , removing the sacrificial layer 223 may include: removing the sacrificial layer 223 through the second filling space 62. For example, since the sacrificial layer 223 is exposed in the second filling space 62, an etching liquid may be added into the second filling space 62, and the sacrificial layer 223 may be removed using a wet etching process. In some examples, by selecting an etching liquid corresponding to the material of the sacrificial layer 223, under the etching conditions created by the etching liquid, the etching rate of the sacrificial layer 223 is greater than the etching rate of the board line layer 221.

[0166] For example, an isotropic etching process may be used to remove the sacrificial layer 223. Isotropic etching is etching that is equal in all directions, which means that the direction of the substrate does not affect the way the etchant removes the material. Removing the sacrificial layer 223 by an isotropic etching process is beneficial to improving the manufacturing efficiency of the semiconductor structure 100.

[0167] Fig.18 FIG. 4 is a structural diagram after removing a portion of the third conductive layer 44 exposed to the first filling space 61 in a method for preparing the semiconductor structure 100 according to some embodiments. Fig.18 As shown, in the embodiment of the present application, the step of forming a plurality of conductive patterns 222 , a storage function layer 41 and a second conductive layer 42 may further include: removing a portion of the third conductive layer 44 exposed to the first filling space 61 to form a plurality of conductive patterns 222 .

[0168] Exemplarily, after the sacrificial layer 223 is removed, the space where the sacrificial layer 223 was originally located is the first filling space 61. Since the sacrificial layer 223 is removed through the second filling space 62, the second filling space 62 is connected to the first filling space 61, and part of the third conductive layer 44 is exposed to the first filling space 61, so that the third conductive layer 44 is removed through the first filling space 61 and the second filling space 62.

[0169] Continue to refer to Fig.18 When removing the portion of the third conductive layer 44 exposed to the first filling space 61, the portion of the third conductive layer 44 between the plate line layer 221 and the storage function layer 41 is also removed. For example, when removing the portion of the third conductive layer 44 exposed to the first filling space 61, etching can be continued toward the side away from the substrate 10. Through the above arrangement, in the adjacent conductive pattern 222 and the plate line layer 221, the first surface 222a of the conductive pattern 222 can be recessed relative to the plate line layer 221, and the first surface 222a, the plate line layer 221 and the storage function layer 41 can enclose a first recessed area M1. For example, when removing the portion of the third conductive layer 44 exposed to the first filling space 61, etching can be continued toward the side close to the substrate 10. Through the above arrangement, in the adjacent conductive patterns 222 and the board line layer 221, the second surface 222b of the conductive pattern 222 can be recessed relative to the board line layer 221, and the second surface 222b, the board line layer 221 and the storage function layer 41 can enclose a second recessed area M2.

[0170] In the embodiment of the present application, after the conductive pattern 222 is formed, the manufacturing process of the semiconductor structure 100 further includes step S4.

[0171] S4. Replace the sacrificial layer with an isolation layer to form a stacked structure.

[0172] Fig.19 FIG. 1 is a structural diagram of forming an isolation layer 21 and an isolation portion 50 in a method for preparing a semiconductor structure 100 according to some embodiments. Fig.19 , and combined with Fig.16 The step of replacing the sacrificial layer 223 with the isolation layer 21 may include: depositing an isolation material in the first filling space 61 and between two adjacent conductive patterns 222 to form an isolation layer 21 having a first gap 211 therein.

[0173] Exemplarily, a deposition process may be used to deposit an isolation material in the first filling space 61 and between two adjacent conductive patterns 222, so that the isolation material covers the surface of the plate line layer 221, the surface of the conductive pattern 222, and the surface of the storage function layer 41. In addition, part of the isolation material covering the surface of the conductive pattern 222 is also located between the plate line layer 221 and the storage function layer 41. The isolation layer 21 formed by deposition encloses a first gap 211, wherein the specific shape and position of the first gap 211 may be as described in the above embodiment, and will not be repeated here.

[0174] Furthermore, the isolation layer 21 is formed in the first filling space 61, that is, the original sacrificial layer 223 is replaced by the isolation layer 21. The isolation layer 21 and the plate line layer 221 are alternately stacked, so that multiple isolation layers 21 and multiple plate line layers 221 together form a stacking structure 20.

[0175] When the preparation method also includes forming a second filling space 62: during the process of depositing the isolation material in the first filling space 61, the isolation material is also deposited in the second filling space 62 to form an isolation part 50, wherein the isolation part 50 has a second gap 51, and the second gap 51 is connected to at least one first gap 211.

[0176] like Fig.19 As shown, the first filling space 61 and the second filling space 62 are connected, and while the isolation material is deposited in the first filling space 61, the isolation material is also deposited in the second filling space 62. The isolation material in the first filling space 61 forms the isolation layer 21, and the isolation material in the second filling space 62 forms the isolation portion 50.

[0177] Through the above steps, the isolation layer 21 and the isolation portion 50 can be in contact with each other, and the isolation layer 21 and the isolation portion 50 can be formed as one piece, which is beneficial to improving the manufacturing efficiency of the semiconductor structure 100 .

[0178] Furthermore, during the deposition of the isolation material in the second filling space 62, the isolation material is also deposited on the surface of the board line layer 221, the surface of the dielectric layer 30, and the surface of the substrate 10, so that the isolation material can enclose a second gap 51. As shown in the above embodiment, the second gap 51 is connected to at least one first gap 211.

[0179] When the second filling space 62 is formed to be narrower than the first filling space 61: in the process of depositing material into the filling space, the second filling space 62 may be filled first, thereby causing the isolation part 50 to form a solid structure and the isolation layer 21 to form a hollow structure, that is, there is no gap in the isolation part 50, but there is a first gap 211 in the isolation layer 21.

[0180] On the contrary, when the first filling space 61 is narrower than the second filling space 62: in the process of depositing material into the filling space, the first filling space 61 may be filled first, thereby causing the isolation layer 21 to form a solid structure and the isolation part 50 to form a hollow structure, that is, there is no gap in the isolation layer 21, but there is a second gap 51 in the isolation part 50.

[0181] As described in the above embodiments, the semiconductor structure 100 may be a semiconductor structure 100 located in the core area. The semiconductor structure 100 located in the connection area also includes a stacked structure in which a plate line layer and a sacrificial layer are alternately stacked. In the process of replacing the sacrificial layer 223 in the stacked structure 201 in the core area with the isolation layer 21, there is no need to replace the sacrificial layer in the stacked structure in the connection area. Since the connection area includes a contact structure, the contact structure can contact the plate line layer in the connection area so that the contact structure is electrically connected to the corresponding capacitor through the plate line layer. Since the sacrificial layer in the stacked structure in the connection area does not need to be replaced, it is beneficial to reduce the manufacturing process of the semiconductor structure located in the connection area.

[0182] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A stacked structure, comprising a plurality of first conductive layers and a plurality of isolation layers alternately stacked; A second conductive layer, running through the stacked structure; A storage function layer, located between the first conductive layer and the second conductive layer, and surrounding the second conductive layer; The first conductive layer includes a plate line layer and a conductive pattern, and the conductive pattern is located between the plate line layer and the storage function layer and surrounds the storage function layer.

2. The semiconductor structure according to claim 1, characterized in that: The plurality of conductive patterns surrounding the same storage functional layer and stacked in a direction perpendicular to the plate line layer are arranged in the same layer.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The isolation layer has a first gap therein.

4. The semiconductor structure according to claim 3, characterized in that: The first gap is located between two adjacent plate line layers along a first direction, and the first gap is also located between two adjacent storage function layers; the first direction is perpendicular to the plate line layers.

5. The semiconductor structure according to claim 3, characterized in that: In the adjacent conductive patterns and the board line layers: the first surface of the conductive pattern is recessed relative to the board line layer, and part of the isolation layer is located in a first recessed area enclosed by the first surface, the board line layer and the storage functional layer, and / or the second surface of the conductive pattern is recessed relative to the board line layer, and part of the isolation layer is located in a second recessed area enclosed by the second surface, the board line layer and the storage functional layer; the first surface and the second surface are arranged relative to each other along a direction perpendicular to the board line layer.

6. The semiconductor structure according to claim 3, characterized in that: The semiconductor structure further includes an isolation portion, which penetrates the stacked structure and is connected to the isolation layer.

7. The semiconductor structure according to claim 6, characterized in that: The isolation layer and the isolation portion are integrally formed.

8. The semiconductor structure according to claim 6, characterized in that: The isolation portion has a second gap therein, and the second gap is communicated with at least one of the first gaps.

9. The semiconductor structure according to claim 8, characterized in that: The second gap is located between two adjacent storage function layers and extends in a direction perpendicular to the plate line layer.

10. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure comprises a substrate and a dielectric layer, wherein the substrate is located on one side of the stacked structure, and the dielectric layer is located on the other side of the stacked structure. The isolation portion also penetrates the dielectric layer and extends into a portion of the substrate.

11. The semiconductor structure according to claim 1 or 2, characterized in that: The material of the storage function layer includes ferroelectric material.

12. A method for preparing a semiconductor structure, characterized in that: include: Providing a stacked structure, the stacked structure comprising a plurality of plate line layers and a plurality of sacrificial layers alternately stacked; forming a capacitor hole, wherein the capacitor hole penetrates the stacked structure; A plurality of conductive patterns, a storage function layer and a second conductive layer are formed in the capacitor hole, wherein one of the conductive patterns and one of the plate line layers constitute a first conductive layer, the storage function layer is located between the plurality of first conductive layers and the second conductive layer and surrounds the second conductive layer, and the plurality of conductive patterns are located between the plate line layer and the storage function layer and surround the storage function layer; The sacrificial layer is replaced by the isolation layer to form a stacked structure.

13. The preparation method according to claim 12, characterized in that: The forming of a plurality of conductive patterns, a storage function layer and a second conductive layer comprises: forming a third conductive layer, a storage function layer and a second conductive layer in the capacitor hole in sequence; removing the sacrificial layer to form a first filling space; A portion of the third conductive layer exposed to the first filling space is removed to form a plurality of conductive patterns.

14. The preparation method according to claim 13, characterized in that: After the third conductive layer, the storage function layer and the second conductive layer are sequentially formed in the capacitor hole and before the sacrificial layer is removed, the preparation method further includes: forming a second filling space, wherein the second filling space penetrates the stacked structure; The removing the sacrificial layer includes: removing the sacrificial layer through the second filling space.

15. The preparation method according to claim 14, characterized in that: Before providing the stacked structure, a substrate is also provided, wherein the substrate is located on one side of the stacked structure; After providing the stacked structure and before forming the capacitor hole, the preparation method further includes: providing a dielectric layer, wherein the dielectric layer is located on a side of the stacked structure away from the substrate; The forming of the second filling space includes: the second filling space also penetrates the dielectric layer and extends into a portion of the substrate.

16. The preparation method according to any one of claims 12 to 15, characterized in that: The step of replacing the sacrificial layer with the isolation layer comprises: An isolation material is deposited in the first filling space and between two adjacent conductive patterns to form an isolation layer, wherein the isolation layer has a first gap therein.

17. The preparation method according to claim 16, characterized in that: In the case where the preparation method further comprises forming a second space, During the process of depositing the isolation material in the first filling space, the isolation material is also deposited in the second filling space to form an isolation portion having a second gap therein, and the second gap is connected to at least one of the first gaps.

18. A storage system, characterized in that: include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 17; A controller is coupled to the semiconductor structure.

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