Planar SiGe heterojunction transistor compatible with SOI CMOS process and manufacturing method thereof

Abstract

The invention discloses a planar SiGe heterojunction transistor compatible with an SOI CMOS technology and a manufacturing method thereof, the planar SiGe heterojunction transistor compatible with the SOI CMOS technology comprises an emitting electrode, a base electrode and a collector electrode which are arranged on an SOI wafer, the three areas are arranged in a planar mode, current flows transversely, and the emitting electrode and the collector electrode are completely symmetrical and are formed by n-type doped silicon on an insulating layer; the base electrode is composed of p-type doped silicon-germanium alloy with a certain component structure, and the emitter electrode, the base electrode and the collector electrode are in contact through polycrystalline silicon. The invention discloses a planar SiGe heterojunction transistor compatible with an SOI (Silicon On Insulator) CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process and a manufacturing method of the planar SiGe heterojunction transistor, which are used for solving the problem that a traditional vertical SiGe HBT is difficult to be compatible with an advanced CMOS process node.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a planar SiGe heterojunction transistor compatible with SOI CMOS process and a method for manufacturing the planar SiGe heterojunction transistor compatible with SOI CMOS process. Background Art

[0002] Compared with other types of device structures, bipolar transistors have at least the following four unique advantages:

[0003] 1. High working speed.

[0004] 2. Extremely high driving capability and transconductance.

[0005] 3. Excellent threshold voltage controllability.

[0006] 4. Good application capability of analog devices (low noise, high signal-to-noise ratio, low offset and large gain bandwidth).

[0007] In bipolar devices, SiGe heterojunction transistors mainly introduce additional potential barriers in the valence band, thereby inhibiting the injection of holes from the base region to the emitter, resulting in improved injection efficiency of the emitter. Therefore, without increasing the emitter resistance, SiGe HBT can obtain a higher current gain. SiGe HBT devices have the advantages of high speed and high performance, and are compatible with mature CMOS process technology, injecting new vitality into the development of integrated circuits towards high speed and high performance.

[0008] At present, foreign SiGe BiCMOS research has made great progress and has played an important role in high-speed, high-performance integrated circuits. SiGe heterojunction devices and integrated circuits have very important applications and a broad market in both military and civilian fields. However, traditional vertical SiGe HBT is difficult to be compatible with advanced CMOS process nodes and is more difficult to manufacture. Therefore, further improvements are made to the above problems. Summary of the invention

[0009] The main purpose of the present invention is to provide a planar SiGe heterojunction transistor compatible with SOI CMOS process and a manufacturing method thereof, so as to solve the problem that the traditional vertical SiGe HBT is difficult to be compatible with advanced CMOS process nodes.

[0010] To achieve the above object, the present invention provides a method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process, comprising the following steps:

[0011] Step S1: patterning a base region on an SOI wafer (including SOI and silicon dioxide), and depositing and growing a (low-quality) silicon-germanium alloy on the substrate by an MBE (molecular beam epitaxy) or CVD (chemical vapor deposition) process;

[0012] Step S2: thermal oxidation is performed to separate germanium from silicon dioxide in the SOI wafer and drive it to the base region to form a silicon germanium base region with (good) crystallinity (the mole fraction of germanium is 20% to 30%, uniformly distributed or distributed in a linear gradient. The field effect generated by the linear gradient will increase the cutoff frequency of the device);

[0013] Step S3: etching the silicon dioxide to expose the silicon germanium base region and performing p-type doping on the silicon germanium base region, and depositing polysilicon as an extended base region on the silicon germanium base region after annealing to serve as the base of the transistor;

[0014] Step S4: patterning the emitter region and the collector region on the SOI wafer and performing n-type doping to form contact electrodes, respectively, so as to serve as the emitter and collector of the transistor, thereby completing the manufacture of the planar SiGe heterojunction transistor.

[0015] As a further preferred technical solution of the above technical solution, in step S1, the SOI wafer needs to be pretreated before growing the silicon-germanium alloy, which is divided into wet chemical cleaning and heat treatment. The wet chemical cleaning uses the standard RCA cleaning steps, and the heat treatment is used to decompose the natural oxide layer on the surface of the silicon wafer at high temperature (the composition and thickness of the grown silicon-germanium alloy need to be determined according to the design performance parameters of the device, and the MBE or CVD equipment is corrected based on this).

[0016] As a further preferred technical solution of the above technical solution, in step S3, the method of etching silicon dioxide is reactive ion etching; the annealing method includes rapid thermal annealing, flash lamp annealing and laser annealing; the method of depositing extended base region polysilicon includes sputtering, chemical vapor deposition and molecular beam epitaxy.

[0017] As a further preferred technical solution of the above technical solution, in step S4, a nitride barrier layer is formed around the extended base region before placing the contact electrode to prevent the electrodes in the emitter region and the collector region from short-circuiting with the extended base region.

[0018] To achieve the above purpose, the present invention also provides a planar SiGe heterojunction transistor (HBT) compatible with SOI CMOS process, including an emitter, a base and a collector arranged on an SOI wafer, the three regions are arranged in a planar manner, and current flows laterally, wherein the emitter and the collector are completely symmetrical and are composed of n-type doped silicon on an insulating layer (i.e., silicon dioxide of the SOI wafer); the base is composed of a p-type doped silicon-germanium alloy with a certain component structure, and polycrystalline silicon is used to contact the emitter, the base and the collector respectively.

[0019] As a further preferred technical solution of the above technical solution, the width of the emitter and the collector is 30-100 nanometers, and the width of the base is 30-50 nanometers (to ensure partial depletion of the base region); the SOI wafer includes an insulating layer and an SOI layer, the thickness of the insulating layer and the SOI layer is 20-60 nanometers, and the lateral length of the overall transistor is 100-200 nanometers.

[0020] As a further preferred technical solution of the above technical solution, the n-type silicon doping of the substrate in the SOI wafer is 10^16 per cubic centimeter to 10^18 per cubic centimeter.

[0021] As a further preferred technical solution of the above technical solution, the n-type silicon doping of the emitter and the collector is 1×10^20 per cubic centimeter to 5×10^20 per cubic centimeter, and the p-type silicon germanium doping of the base is 10^18 per cubic centimeter to 10^19 per cubic centimeter.

[0022] The invention has the following beneficial effects: the manufacturing method of the invention is fully compatible with the standard SOI CMOS process, the manufacturing of the SiGe base region does not require an additional mask, and is generated in the first step, and there is no need to transfer the silicon wafer in the subsequent steps. Compared with the traditional vertical SiGe HBT, the invention can match a smaller CMOS process node, and has the advantages of higher cutoff frequency and easier integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 (a) is a schematic diagram of an SOI wafer.

[0024] Figure 1 (b) is a schematic diagram of depositing silicon-germanium alloy on the substrate surface using MBE or CVD.

[0025] Figure 2 Schematic diagram of a silicon germanium base region having good crystallinity formed after thermal oxidation.

[0026] Figure 3 (a) is a schematic diagram of ion implantation into the doped base region after etching silicon oxide.

[0027] Figure 3 (b) is a schematic diagram of depositing polysilicon above the base region to form an extended base region.

[0028] Figure 4 (a) is a schematic diagram of ion implantation after patterning the emitter and collector regions.

[0029] Figure 4 (b) is a schematic diagram of the device structure after the process is completed (electrodes are not drawn). DETAILED DESCRIPTION

[0030] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0031] In the preferred embodiment of the present invention, those skilled in the art should note that the SOI wafer and the like involved in the present invention may be regarded as prior art.

[0032] Preferred embodiments.

[0033] like Figure 1-4 As shown, the present invention discloses a method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process, comprising the following steps:

[0034] Step S1: Figure 1 As shown in (a) to (b), a base region is patterned on an SOI wafer (including SOI and silicon dioxide), and a (low-quality) silicon-germanium alloy is deposited and grown on the substrate by MBE (molecular beam epitaxy) or CVD (chemical vapor deposition) process;

[0035] Step S2: Figure 2 As shown, thermal oxidation is performed to separate germanium from silicon dioxide in the SOI wafer and drive it into the base region to form a silicon germanium base region with (good) crystallinity (the mole fraction of germanium is 20% to 30%, uniformly distributed or distributed in a linear gradient. The field effect generated by the linear gradient will increase the cutoff frequency of the device);

[0036] Step S3: Figure 3 As shown in (a), silicon dioxide is etched to expose the silicon germanium base region and the silicon germanium base region is p-type doped. After annealing, polysilicon is deposited on the silicon germanium base region as an extended base region to serve as the base of the transistor, as shown in FIG. Figure 3 (b)

[0037] Step S4: Figure 4As shown in (a), the emitter region and the collector region are patterned on the SOI wafer and n-type doped to form contact electrodes, which serve as the emitter and collector of the transistor respectively, thereby completing the manufacture of the planar SiGe heterojunction transistor, as shown in FIG. Figure 4 (b) as shown.

[0038] Specifically, in step S1, the SOI wafer needs to be pre-treated before growing the silicon-germanium alloy, which is divided into wet chemical cleaning and heat treatment. The wet chemical cleaning uses the standard RCA cleaning procedure, and the heat treatment is used to decompose the natural oxide layer on the surface of the silicon wafer at high temperature (the composition and thickness of the grown silicon-germanium alloy need to be determined according to the design performance parameters of the device, and the MBE or CVD equipment is corrected based on this).

[0039] More specifically, in step S3, the method for etching silicon dioxide is reactive ion etching; the annealing methods include rapid thermal annealing, flash lamp annealing and laser annealing; the methods for depositing extended base region polysilicon include sputtering, chemical vapor deposition and molecular beam epitaxy.

[0040] Furthermore, in step S4, a nitride barrier layer is formed around the extended base region before placing the contact electrode, so as to prevent the electrodes of the emitter region and the collector region from being short-circuited with the extended base region.

[0041] The present invention also discloses a planar SiGe heterojunction transistor (HBT) compatible with SOI CMOS process, including an emitter, a base and a collector arranged on an SOI wafer, the three regions are arranged in a planar manner, and current flows laterally, wherein the emitter and the collector are completely symmetrical and are composed of n-type doped silicon on an insulating layer (i.e., silicon dioxide of the SOI wafer); the base is composed of a p-type doped silicon-germanium alloy with a certain component structure, and polycrystalline silicon is used to contact the emitter, the base and the collector respectively.

[0042] Specifically, the width of the emitter and collector is 30-100 nanometers, the width of the base is 30-50 nanometers (to ensure partial depletion of the base region); the SOI wafer includes an insulating layer and an SOI layer, the thickness of the insulating layer and the SOI layer is 20-60 nanometers, and the lateral length of the overall transistor is 100-200 nanometers.

[0043] More specifically, the n-type silicon doping of the substrate in the SOI wafer is 10^16 per cubic centimeter to 10^18 per cubic centimeter.

[0044] More specifically, the n-type silicon doping of the emitter and the collector is 1×10^20 per cubic centimeter to 5×10^20 per cubic centimeter, and the p-type silicon germanium doping of the base is 10^18 per cubic centimeter to 10^19 per cubic centimeter.

[0045] Furthermore, the electrode materials of the emitter, base and collector are selected from tungsten, aluminum, nickel, copper or polysilicon.

[0046] It is worth mentioning that the technical features such as SOI wafer involved in the patent application of this invention should be regarded as the prior art. The specific structure, working principle and possible control method and spatial arrangement method of these technical features can be selected by conventional methods in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated.

[0047] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process, characterized in that: The following steps are involved: Step S1: patterning a base region on an SOI wafer, and depositing and growing a silicon-germanium alloy on a substrate by an MBE or CVD process; Step S2: thermal oxidation is performed to separate germanium from silicon dioxide in the SOI wafer and drive it to the base region to form a crystalline silicon germanium base region; Step S3: etching the silicon dioxide to expose the silicon germanium base region and performing p-type doping on the silicon germanium base region, and depositing polysilicon as an extended base region on the silicon germanium base region after annealing to serve as the base of the transistor; Step S4: patterning the emitter region and the collector region on the SOI wafer and performing n-type doping to form contact electrodes, respectively, so as to serve as the emitter and collector of the transistor, thereby completing the manufacture of the planar SiGe heterojunction transistor.

2. The method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 1, characterized in that: In step S1, the SOI wafer needs to be pre-treated before growing the silicon-germanium alloy, which is divided into wet chemical cleaning and heat treatment. The wet chemical cleaning uses the standard RCA cleaning step, and the heat treatment is used to decompose the natural oxide layer on the surface of the silicon wafer at high temperature.

3. The method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 2, characterized in that: In step S3, the method for etching silicon dioxide is reactive ion etching; the annealing methods include rapid thermal annealing, flash lamp annealing and laser annealing; the methods for depositing extended base region polysilicon include sputtering, chemical vapor deposition and molecular beam epitaxy.

4. The method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 3, characterized in that: In step S4, a nitride barrier layer is formed around the extended base region before placing the contact electrode, so as to prevent the electrodes of the emitter region and the collector region from being short-circuited with the extended base region.

5. A planar SiGe heterojunction transistor compatible with SOI CMOS process, implemented in the method for manufacturing a planar SiGe heterojunction transistor compatible with SOI CMOS process according to any one of claims 1 to 4, characterized in that: It includes an emitter, a base and a collector arranged on a SOI wafer. The three regions are arranged in a planar manner, and the current flows laterally. The emitter and the collector are completely symmetrical and are composed of n-type doped silicon on an insulating layer. The base is composed of a p-type doped silicon-germanium alloy with a certain component structure, and polysilicon is used to contact the emitter, base and collector respectively.

6. A planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 5, characterized in that: The width of the emitter and collector is 30-100 nanometers, and the width of the base is 30-50 nanometers; the SOI wafer includes an insulating layer and an SOI layer, the thickness of the insulating layer and the SOI layer is 20-60 nanometers, and the lateral length of the overall transistor is 100-200 nanometers.

7. A planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 6, characterized in that: The n-type silicon doping of the substrate in the SOI wafer is 10^16 per cubic centimeter to 10^18 per cubic centimeter.

8. The planar SiGe heterojunction transistor compatible with SOI CMOS process according to claim 7, characterized in that: The n-type silicon doping of the emitter and collector is 1×10^20 per cubic centimeter to 5×10^20 per cubic centimeter, and the p-type silicon germanium doping of the base is 10^18 per cubic centimeter to 10^19 per cubic centimeter.

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