Short-channel field effect transistor, preparation method thereof and electronic device

Abstract

The invention provides a short-channel field effect transistor, a preparation method thereof and an electronic device. The short-channel field effect transistor comprises a substrate; the first insulating layer is of a step structure and comprises a first part and a second part which are arranged in sequence, and the top surface of the second part is higher than that of the first part; a gate over the second portion; the second insulating layer is of a step structure, and the top surface of the second insulating layer on the grid electrode is higher than the top surface of the second insulating layer on the second part which is not covered by the grid electrode; a third insulating layer covering the second insulating layer and the first portion; the third insulating layer is formed by adopting an atomic layer deposition process; the source electrode and the drain electrode are located on the two sides of the grid electrode respectively; the semiconductor layer is electrically connected with the source electrode and the drain electrode, and the semiconductor layer is formed by adopting an atomic layer deposition process; and a step structure among the first insulating layer, the grid electrode and the second insulating layer is formed by adopting an etching process. According to the invention, large-area and low-cost preparation of the short-channel field effect transistor can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a short channel field effect transistor, a preparation method thereof and an electronic device. Background Art

[0002] Phased array antenna arrays with the advantages of strong directivity, high gain, and good reconfigurability are currently the mainstream antenna arrays. Generally speaking, in order to obtain higher gain, narrower main lobe, stronger plasticity, beamforming capability and multi-beam generation capability, phased array antennas are generally composed of many antenna units to form an array, and the feeding parameters of each unit are controlled by active phase control technology. The amplifier is an important component. The materials of monolithic integrated RF integrated circuits that are currently mainly used, such as GaAs, Si, and GaN, can achieve amplification functions in the X-band and even higher frequency bands, but have the disadvantages of complex process, high cost, high requirements for materials and equipment, and cannot meet the large-area preparation required for phased array antennas.

[0003] Therefore, how to prepare large-area short-channel field-effect transistors on a large scale and at low cost for application in phased array antenna arrays is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the defects in the prior art, an object of the present invention is to provide a short channel field effect transistor, a preparation method thereof and an electronic device.

[0005] According to a first aspect of the present invention, there is provided a short channel field effect transistor, the transistor comprising:

[0006] substrate;

[0007] A first insulating layer, located above the substrate, wherein the first insulating layer is in a stepped structure, including a first portion and a second portion arranged in sequence, wherein a top surface of the second portion is higher than a top surface of the first portion;

[0008] A gate is located above the second part, and the gate is arranged at an end of the second part close to the first part;

[0009] a second insulating layer, located above the gate and the second portion not covered by the gate, the second insulating layer being in a stepped structure, and a top surface of the second insulating layer on the gate being higher than a top surface of the second insulating layer on the second portion not covered by the gate;

[0010] a third insulating layer, covering the second insulating layer and the first portion, and side walls formed by the second portion, the gate and the second insulating layer respectively; the third insulating layer is formed by an atomic layer deposition process;

[0011] A source electrode and a drain electrode, located above the third insulating layer, and the source electrode and the drain electrode are respectively located on two sides of the gate electrode;

[0012] A semiconductor layer is located above the third insulating layer, two ends of the semiconductor layer are electrically connected to the source electrode and the drain electrode respectively, and the semiconductor layer exposes the gate electrode, the source electrode and the drain electrode; the semiconductor layer is formed by an atomic layer deposition process;

[0013] A step structure is formed between the first insulating layer, the gate and the second insulating layer, and the step structure is formed by an etching process.

[0014] Optionally, the semiconductor layer includes:

[0015] A first portion of the semiconductor layer is located above the gate, and the first portion of the semiconductor layer covers the third insulating layer between the source electrode and the drain electrode;

[0016] a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer covers a portion of the source electrode;

[0017] a third portion of the semiconductor layer, wherein the third portion of the semiconductor layer covers a portion of the drain electrode;

[0018] The channel width of the semiconductor is the distance between the source and the drain, the channel length of the semiconductor is the distance between the two edges of the semiconductor layer perpendicular to the channel width direction, the length of the gate is the distance between the two edges perpendicular to the channel width direction, and the channel length is smaller than the length of the gate.

[0019] Optionally, the source and the drain partially overlap or do not overlap with the gate in the substrate normal direction.

[0020] Optionally, the transistor has one or more of the following options:

[0021] - a source electrode plate is provided on the third insulating layer, and the source electrode plate is electrically connected to the source electrode;

[0022] - a drain electrode plate is provided on the third insulating layer, and the drain electrode plate is electrically connected to the drain;

[0023] - A gate electrode plate is disposed on the first insulating layer, and the gate electrode plate is electrically connected to the gate.

[0024] Optionally, a protective layer is provided above the semiconductor layer, the protective layer covers the semiconductor layer, and the protective layer is provided with a first through hole exposing the gate, a second through hole exposing the source, and a third through hole exposing the drain.

[0025] Optionally, the first insulating layer, the second insulating layer and the third insulating layer are formed of the same material.

[0026] Optionally, the semiconductor layer is formed of a metal oxide material.

[0027] Optionally, the gate, the source and the drain all have a three-layer material structure formed of titanium, gold and nickel in sequence from bottom to top.

[0028] According to a second aspect of the present invention, there is provided a method for preparing the above-mentioned short channel field effect transistor, the method comprising:

[0029] providing a substrate;

[0030] forming a first insulating layer covering the substrate above the substrate, etching the first insulating layer to form a first portion and a second portion in a stepped shape, and forming a gate on the second portion;

[0031] forming a second insulating layer above the gate and the second portion not covered by the gate, etching the second insulating layer to form a step shape, and exposing the side surface of the gate electrode on the step sidewall parallel to the normal direction of the substrate;

[0032] Growing a third insulating layer as a gate oxide layer by atomic layer deposition on the second insulating layer and the first portion;

[0033] A source electrode and a drain electrode are formed on the third insulating layer, wherein the source electrode and the drain electrode are respectively located on two sides of the gate electrode;

[0034] A semiconductor layer is grown by atomic layer deposition over the source and the drain, wherein the semiconductor layer is electrically connected to the gate and the drain, and is patterned;

[0035] A through hole is etched to expose the gate, the source and the drain.

[0036] According to a third aspect of the present invention, there is provided an electronic device, comprising the above-mentioned short channel field effect transistor.

[0037] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0038] The present invention utilizes a larger-scale photolithography process to realize the structure and preparation method of a short-channel field-effect transistor. By verticalizing the channel, the channel length of the device is determined only by the thickness of the gate and is independent of the photolithography accuracy. Thus, a larger-scale process is utilized to realize large-area preparation of short-channel field-effect transistors. The invention can be widely used in the field of integrated circuit technology, and provides a good technical path for realizing large-area radio frequency amplification circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0040] Figure 1 is a cross-sectional schematic diagram of a short channel field effect transistor structure in one embodiment of the present invention;

[0041] Figure 2 1 is a cross-sectional schematic diagram corresponding to step S1 and step S2 of a method for preparing a short channel field effect transistor structure in one embodiment of the present invention;

[0042] Figure 3 is a cross-sectional schematic diagram corresponding to step S2 of a method for preparing a short channel field effect transistor structure in one embodiment of the present invention;

[0043] Figure 4 It is a cross-sectional schematic diagram corresponding to step S3 to step S7 of a method for preparing a short channel field effect transistor structure in one embodiment of the present invention;

[0044] Figure 5 It is a cross-sectional schematic diagram corresponding to step S8 of the method for preparing a short channel field effect transistor structure in one embodiment of the present invention.

[0045] In the figure: 100 is a substrate, 110 is a first insulating layer, 111 is a first part, 112 is a second part, 121 is a gate, 122 is a gate plate, 130 is a second insulating layer, 140 is a third insulating layer, 151 is a drain, 152 is a source, 153 is a source plate, 154 is a drain plate, 160 is a semiconductor layer, 161 is a first part of the semiconductor layer, 162 is a second part of the semiconductor layer, 163 is a third part of the semiconductor layer, 170 is a protective layer, and PR represents a photoresist pattern layer. DETAILED DESCRIPTION

[0046] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements may be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0047] It should be noted that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0048] Reference Figure 1-Figure 5 A short channel field effect transistor provided by an embodiment of the present invention includes a substrate 100, a first insulating layer 110, a gate 121, a second insulating layer 130, a third insulating layer 140, a source 152, a drain 151 and a semiconductor layer 160, wherein: the first insulating layer 110 is located above the substrate 100, and the first insulating layer 110 has a stepped structure, including a first part 111 and a second part 112 arranged in sequence, and the top surface of the second part 112 is higher than the top surface of the first part 111; the gate 121 is located above the second part 112, and the gate The area of ​​the gate 121 is smaller than the area of ​​the second portion 112, and the gate 121 is disposed at an end of the second portion 112 close to the first portion 111; the second insulating layer 130 is located above the gate 121 and the second portion 112 not covered by the gate 121, and the second insulating layer is in a stepped structure, and the top surface of the second insulating layer 130 on the gate 121 is higher than the top surface of the second insulating layer 130 on the second portion 112 not covered by the gate 121; the third insulating layer 140 covers the second insulating layer 130 and the first portion 111, as well as the second portion 112, the gate 121, and the second portion 112. 1 respectively forms a sidewall with the second insulating layer 130, thereby forming a uniform thin film on a non-flat area such as a sidewall; the third insulating layer 140 is formed by an atomic layer deposition process, and has good coverage of the sidewall of the step structure formed by the first insulating layer 110, the gate 121 and the second insulating layer 130; the source 152 and the drain 151 are located above the third insulating layer 140, and the source 152 and the drain 151 are respectively located on both sides of the gate 121; the semiconductor layer 160 is located above the third insulating layer, and the semiconductor layer 160 covers the source 152 and the drain 151, as well as a portion of the source 152 and a portion of the drain 151, the two ends of the semiconductor layer 160 are electrically connected to the source 152 and the drain 151 respectively, and the semiconductor layer 160 exposes the gate 121, the source 152 and the drain 151; the semiconductor layer 160 is formed by an atomic layer deposition process, and has good coverage of the side walls of the stepped structure formed by the third insulating layer 140; a stepped structure is formed between the first insulating layer 110, the gate 121 and the second insulating layer 130, and the stepped structure is formed by an etching process.

[0049] The short channel field effect transistor in the embodiment of the present invention may be, but is not limited to, a bottom gate bottom contact structure. A step structure is formed by etching the first insulating layer 110, the second insulating layer 130 and the gate 121, exposing the side wall of the gate 121, and forming the third insulating layer 140 (gate insulating layer) and the semiconductor layer 160 by using the good step coverage of atomic layer deposition. The gate 121 is in the normal direction of the substrate 100 ( Figure 1-Figure 3 The thickness in the direction indicated by ND in the figure is the length of the gate 121 of the field effect transistor, which regulates the switching of the channel. By verticalizing the channel, the length of the gate 121 modulating the semiconductor is no longer determined by the photolithography precision process, but is completely related to the thickness deposited when preparing the gate 121. The preparation of short-channel field effect transistors is realized under the conditions of a larger-scale photolithography preparation process, and the semiconductor layer 160 and the third insulating layer 140 are formed by an atomic layer deposition process, which is beneficial to improving device performance. Existing traditional high-frequency devices such as silicon-based, silicon nitride and gallium arsenide have the disadvantages of high cost and inability to be prepared on a large scale. The short-channel field effect transistor provided in the embodiment of the present invention can utilize the preparation process of the display panel to realize the preparation of large-area short-channel devices of 100 inches and above at low cost.

[0050] In the above embodiment, the first insulating layer 110 covers the substrate 100 and overlaps the substrate 100; the first portion 111 extends along the surface of the substrate 100 and directly contacts the substrate 100; the second portion 112 extends along the surface of the substrate 100 and directly contacts the substrate 100. The gate 121 extends along the surface of the second portion 112 of the first insulating layer 110. The second insulating layer 130 covers the gate 121 and part or all of the first insulating layer 110. The third insulating layer 140 covers the second insulating layer 130 and the first portion 111 of the first insulating layer 110, as well as the sidewalls formed by the second portion 112 of the first insulating layer 110, the gate 121, and the second insulating layer 130.

[0051] In some embodiments, the semiconductor layer 160 includes a first semiconductor layer portion 161, a second semiconductor layer portion 162, and a third semiconductor layer portion 163, wherein: the first semiconductor layer portion 161 is located above the gate 121, the first semiconductor layer portion 161 covers the third insulating layer 140 between the source 152 and the drain 151, the second semiconductor layer portion 162 covers a portion of the source 152, and the third semiconductor layer portion 163 covers a portion of the drain 151. Figure 4The channel width of the semiconductor is perpendicular to the normal direction of the substrate 100, the channel width of the semiconductor is the distance between the source 152 and the drain 151, and the width of the gate 121 can be greater than or less than the channel width; the channel length of the semiconductor is the distance between the two edges of the semiconductor layer 160 perpendicular to the channel width direction (i.e., along the normal direction of the substrate), the length of the gate 121 is the distance between the two edges perpendicular to the channel width direction (i.e., along the normal direction of the substrate), and the semiconductor channel length is less than the length of the gate 121, so that the gate 121 can fully control the semiconductor layer 160.

[0052] In some embodiments, the source 152 and the drain 151 partially overlap or do not overlap the gate 121 in the normal direction of the substrate 100 .

[0053] In the above embodiment, a gate electrode plate 122 is provided on the first insulating layer 110, and the gate electrode plate 122 is electrically connected to the gate 121. A source electrode plate 153 is provided on the third insulating layer 140, and the source electrode plate 153 is electrically connected to the source 152. A drain electrode plate 154 is provided on the third insulating layer 140, and the drain electrode plate 154 is electrically connected to the drain 151.

[0054] In some embodiments, a protection layer 170 is disposed above the semiconductor layer 160 , and the protection layer 170 covers the semiconductor layer 160 . The protection layer 170 defines a first through hole exposing the gate 121 , a second through hole exposing the source 152 , and a third through hole exposing the drain 151 .

[0055] The materials of the first insulating layer 110, the second insulating layer 130 and the third insulating layer 140 include high-performance inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, etc. Preferably, the first insulating layer 110, the second insulating layer 130 and the third insulating layer 140 are formed of the same material to simplify the manufacturing process and further reduce the cost.

[0056] The material of the semiconductor layer 160 is a metal oxide material prepared by an atomic layer deposition process, including any one of indium oxide, zinc oxide, gallium oxide and tin oxide, or a combination of two or more thereof, or other semiconductor materials.

[0057] The gate 121, the source 152 and the drain 151 are single-layer or multi-layer structures, and their materials include, for example, metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. Preferably, the gate 121, the source 152 and the drain 151 all have a three-layer material structure formed of titanium, gold and nickel from bottom to top, so as to reduce the contact resistance, improve the adhesion of the electrode and be suitable for the growth of atomic layer deposition.

[0058] The material of the substrate 100 may be glass, quartz, organic polymer or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. If a conductive material or metal is used, an insulating layer is covered on the substrate 100 to avoid short circuit problems. It should be noted that the first insulating layer 110 may not be grown if the insulation of the substrate 100 is good enough.

[0059] Based on the same inventive concept, another embodiment of the present invention provides a method for preparing the above-mentioned short channel field effect transistor, referring to Figure 1-Figure 5 , the method comprises the following steps:

[0060] S1, providing a substrate 100;

[0061] S2, forming a first insulating layer 110 covering the substrate 100 above the substrate 100, etching the first insulating layer 110 to form a stepped first portion 111 and a second portion 112, and forming a gate 121 on the second portion 112;

[0062] S3, forming a second insulating layer 130 above the gate 121 and the second portion 112 not covered by the gate 121, and using the photoresist pattern layer PR as a mask, etching the second insulating layer 130 to form a step shape and expose the side of the gate electrode parallel to the normal direction of the substrate 100 so as to directly contact the third insulating layer 140, thereby regulating the semiconductor layer 160; the structure formed by etching is as follows Figure 3 As shown;

[0063] S4, growing a third insulating layer 140 as a gate oxide layer on the second insulating layer 130 and the first portion 111 by atomic layer deposition to isolate the gate 121 from the source 152 and the drain 151;

[0064] S5, preparing a source electrode 152 and a drain electrode 151 on the third insulating layer 140, wherein the source electrode 152 and the drain electrode 151 are respectively located on two sides of the gate electrode 121;

[0065] S6, growing a semiconductor layer 160 by atomic layer deposition above the source 152 and the drain 151, the semiconductor layer 160 is electrically connected to the source 152 and the drain 151, and is patterned to reduce leakage current of the gate 121, avoid crosstalk between adjacent devices, and reduce overall power consumption of the circuit;

[0066] S7 , etching through holes to expose the gate 121 , the source 152 , and the drain 151 .

[0067] In the above method, in step S2, a gate electrode plate 122 is also formed on the second portion 112; in step S5, a source electrode plate 153 and a drain electrode plate 154 are also formed on the third insulating layer 140, and in step S7, through holes are correspondingly etched to expose the gate electrode plate 122, the source electrode plate 153 and the drain electrode plate 154.

[0068] In some embodiments, after step S7, step S8 is further included: preparing a protective layer 170, and etching through holes to expose the gate 121, the source 152, the drain 151, etc., such as Figure 5 shown.

[0069] Another embodiment of the present invention further provides an electronic device, which includes the above-mentioned short channel field effect transistor. Due to the technical effects of the above-mentioned short channel field effect transistor, the electronic device in the embodiment of the present invention also has the same technical effects, which will not be repeated here.

[0070] The above-mentioned embodiment of the present invention utilizes a larger-scale photolithography process to realize the structure and preparation method of a short-channel field effect transistor. By verticalizing the channel, the channel length of the device is determined only by the thickness of the gate and does not rely on the photolithography accuracy, thereby utilizing a larger-scale process to realize large-area preparation of short-channel field effect transistors, thereby solving the existing problem of being unable to prepare short-channel devices in a large area at low cost. The embodiment of the present invention can be applied to the field of large-area integrated circuit technology that requires short-channel devices, for example, the preparation of phased array antenna radio frequency amplifier circuits, and provides a good technical path for realizing large-area radio frequency amplifier circuits.

[0071] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various modifications or variations within the scope of the claims, which does not affect the essence of the present invention. The above preferred features can be used in any combination without conflicting with each other.

Claims

1. A short channel field effect transistor, characterized in that: include: substrate; A first insulating layer, located above the substrate, wherein the first insulating layer is in a stepped structure, including a first portion and a second portion arranged in sequence, wherein a top surface of the second portion is higher than a top surface of the first portion; A gate is located above the second part, and the gate is arranged at an end of the second part close to the first part; a second insulating layer, located above the gate and the second portion not covered by the gate, the second insulating layer being in a stepped structure, and a top surface of the second insulating layer on the gate being higher than a top surface of the second insulating layer on the second portion not covered by the gate; a third insulating layer, covering the second insulating layer and the first portion, and side walls formed by the second portion, the gate and the second insulating layer respectively; the third insulating layer is formed by an atomic layer deposition process; A source electrode and a drain electrode, located above the third insulating layer, and the source electrode and the drain electrode are respectively located on two sides of the gate electrode; A semiconductor layer is located above the third insulating layer, two ends of the semiconductor layer are electrically connected to the source electrode and the drain electrode respectively, and the semiconductor layer exposes the gate electrode, the source electrode and the drain electrode; the semiconductor layer is formed by an atomic layer deposition process; A step structure is formed between the first insulating layer, the gate and the second insulating layer, and the step structure is formed by an etching process.

2. The short channel field effect transistor according to claim 1, characterized in that: The semiconductor layer comprises: A first portion of the semiconductor layer is located above the gate, and the first portion of the semiconductor layer covers the third insulating layer between the source electrode and the drain electrode; a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer covers a portion of the source electrode; a third portion of the semiconductor layer, wherein the third portion of the semiconductor layer covers a portion of the drain electrode; The channel width of the semiconductor is the distance between the source and the drain, the channel length of the semiconductor is the distance between the two edges of the semiconductor layer perpendicular to the channel width direction, the length of the gate is the distance between the two edges perpendicular to the channel width direction, and the channel length is smaller than the length of the gate.

3. The short channel field effect transistor according to claim 1, characterized in that: The source and the drain partially overlap or do not overlap with the gate in the substrate normal direction.

4. The short channel field effect transistor according to claim 1, characterized in that: One or more of the following options: - a source electrode plate is provided on the third insulating layer, and the source electrode plate is electrically connected to the source electrode; - a drain electrode plate is provided on the third insulating layer, and the drain electrode plate is electrically connected to the drain; - A gate electrode plate is disposed on the first insulating layer, and the gate electrode plate is electrically connected to the gate.

5. The short channel field effect transistor according to claim 1, characterized in that: A protection layer is disposed above the semiconductor layer, the protection layer covers the semiconductor layer, and the protection layer is provided with a first through hole exposing the gate electrode, a second through hole exposing the source electrode, and a third through hole exposing the drain electrode.

6. The short channel field effect transistor according to claim 1, characterized in that: The first insulating layer, the second insulating layer and the third insulating layer are formed of the same material.

7. The short channel field effect transistor according to claim 1, characterized in that: The semiconductor layer is formed of metal oxide material.

8. The short channel field effect transistor according to claim 1, characterized in that: The gate electrode, the source electrode and the drain electrode all have a three-layer material structure formed of titanium, gold and nickel in sequence from bottom to top.

9. A method for preparing a short channel field effect transistor according to any one of claims 1 to 8, characterized in that: include: providing a substrate; forming a first insulating layer covering the substrate above the substrate, etching the first insulating layer to form a first portion and a second portion in a stepped shape, and forming a gate on the second portion; forming a second insulating layer above the gate and the second portion not covered by the gate, etching the second insulating layer to form a step shape, and exposing the side surface of the gate electrode on the step sidewall parallel to the normal direction of the substrate; Growing a third insulating layer as a gate oxide layer by atomic layer deposition on the second insulating layer and the first portion; A source electrode and a drain electrode are formed on the third insulating layer, wherein the source electrode and the drain electrode are respectively located on two sides of the gate electrode; A semiconductor layer is grown by atomic layer deposition over the source and the drain, wherein the semiconductor layer is electrically connected to the gate and the drain, and is patterned; A through hole is etched to expose the gate, the source and the drain.

10. An electronic device, characterized in that: A short channel field effect transistor comprising any one of claims 1 to 8.

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