Three-dimensional field effect transistor and method of manufacturing three-dimensional field effect transistor

Abstract

The invention provides a three-dimensional field effect transistor and a method of manufacturing the three-dimensional field effect transistor. The three-dimensional field effect transistor includes an upper field effect transistor stacked on a lower field effect transistor. The method includes epitaxially growing a source / drain region of a lower field effect transistor, growing a sacrificial layer on an upper surface of the source / drain region, and epitaxially growing a source / drain region of an upper field effect transistor on the sacrificial layer. The sacrificial layer is a seed layer of the source / drain region of the upper field effect transistor. The method further includes selectively etching the sacrificial layer to form a gap between the source / drain region of the lower field effect transistor and the source / drain region of the upper field effect transistor, and depositing an oxide layer in the gap.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 63 / 533,982, filed in the U.S. Patent and Trademark Office on August 22, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a method of manufacturing a three-dimensional field effect transistor. Background Art

[0004] In order to maintain Moore's Law-like growth in the semiconductor industry, it has been proposed to manufacture stacked three-dimensional field effect transistors (3D FETs), in which p-type (PMOS) field effect transistors are stacked on n-type (NMOS) field effect transistors (or vice versa). 3D FETs increase scaling by reducing physical constraints on gate length, spacer thickness, and contact size. In this way, 3D FETs enable gates, spacers, and contacts to be optimized for performance or energy consumption. However, 3D FETs present the challenge of separating NMOS and PMOS transistors from each other in the vertical direction. The 3D FETs of the related art have tight process margin issues, which makes vertical separation challenging.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] The present disclosure relates to various embodiments of a method for manufacturing a three-dimensional field effect transistor (3D-FET), which includes an upper field effect transistor stacked on a lower field effect transistor. In one embodiment, the method includes epitaxially growing the source / drain region of the lower field effect transistor, growing a sacrificial layer on the upper surface of the source / drain region, and epitaxially growing the source / drain region of the upper field effect transistor on the sacrificial layer. The sacrificial layer is a seed layer of the source / drain region of the upper field effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source / drain region of the lower field effect transistor and the source / drain region of the upper field effect transistor, and depositing an oxide layer in the gap.

[0007] The sacrificial layer may include silicon germanium (SiGe), such as Si x Ge 1-x .

[0008] The lower field effect transistor may be an n-type field effect transistor, and the upper field effect transistor may be a p-type field effect transistor.

[0009] The lower field effect transistor may be a p-type field effect transistor, and the upper field effect transistor may be an n-type field effect transistor.

[0010] The thickness of the sacrificial layer may be smaller than the thickness of each of the source / drain region of the upper field effect transistor and the source / drain region of the lower field effect transistor.

[0011] The thickness of the oxide layer may be smaller than the thickness of each of the source / drain region of the upper field effect transistor and the source / drain region of the lower field effect transistor.

[0012] The present disclosure also relates to various embodiments of a three-dimensional field effect transistor. In one embodiment, the three-dimensional field effect transistor includes a lower field effect transistor and an upper field effect transistor stacked on the lower field effect transistor. Each of the lower field effect transistor and the upper field effect transistor includes a source region, a drain region, a channel region between the source region and the drain region, and a gate on the channel. The source region and the drain region of the lower field effect transistor are separated from the source region and the drain region of the upper field effect transistor by an oxide layer.

[0013] The lower field effect transistor may be an n-type field effect transistor, and the upper field effect transistor may be a p-type field effect transistor.

[0014] The lower field effect transistor may be a p-type field effect transistor, and the upper field effect transistor may be an n-type field effect transistor.

[0015] The thickness of the oxide layer may be smaller than the thickness of each of the source / drain region of the upper field effect transistor and the source / drain region of the lower field effect transistor.

[0016] This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. One or more of the described features and / or tasks can be combined with one or more other described features and / or tasks to provide a feasible device and / or a feasible method. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The features and advantages of the embodiments of the present disclosure will be better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings. In the accompanying drawings, the same reference numerals are used throughout the drawings to represent the same features and components. The drawings are not necessarily drawn to scale.

[0018] Figure 1 is a flow chart illustrating tasks of a method of manufacturing a three-dimensional field effect transistor (3D-FET) according to one embodiment of the present disclosure; and

[0019] Figure 2A-2E Describes the basis Figure 1 The task of the method of manufacturing a 3D-FET of an embodiment. DETAILED DESCRIPTION

[0020] The present disclosure relates to various embodiments of a method for manufacturing a three-dimensional field effect transistor (3D-FET), the three-dimensional field effect transistor (3D-FET) comprising an upper field effect transistor stacked on a lower field effect transistor. The method according to various embodiments of the present invention isolates the source / drain region of the lower field effect transistor from the source / drain region of the upper field effect transistor.

[0021] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. However, the present invention may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present invention to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present invention may not be described. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals represent the same elements, and therefore, their descriptions may not be repeated.

[0022] In the accompanying drawings, for the sake of clarity, the relative sizes of elements, layers and regions may be exaggerated and / or simplified. For ease of explanation, spatial relative terms, such as "below", "under", "lower", "below", "above", "upper", etc., may be used herein to describe the relationship between an element or feature and another element or feature as shown in the figure. It should be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as "under" or "below" or "below" of other elements or features will be oriented to be "above" other elements or features. Therefore, the example terms "under" and "below" can cover the orientations above and below. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0023] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present invention, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0024] It should be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected to or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it should be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0025] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular "one" and "an" are intended to also include plural forms, unless the context clearly states otherwise. It will be further understood that when used in this specification, the terms "include" and "comprising" specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Expressions such as "at least one of ... " modify the entire element list when before the element list, rather than modifying the individual elements in the list.

[0026] As used herein, the terms "substantially," "approximately," and similar terms are used as approximate terms rather than terms of degree, and are intended to take into account the inherent variations in measurements or calculations that one of ordinary skill in the art will recognize. In addition, when describing embodiments of the present invention, the use of "may" refers to "one or more embodiments of the present invention." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. In addition, the term "exemplary" is intended to refer to an example or illustration.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0028] Reference now Figure 1 and Figure 2A-2E, a method 100 for manufacturing a stacked three-dimensional field effect transistor (3D FET) according to one embodiment of the present disclosure includes a task 110 of forming (e.g., epitaxially growing) a source / drain region 201 of a lower field effect transistor (lower FET) on opposite sides of a channel region (e.g., epitaxially growing the source / drain region 201 on a substrate such as a bulk silicon (Si) substrate).

[0029] In the illustrated embodiment, method 100 also includes task 120 of forming (e.g., growing) a sacrificial layer 202 on upper surface 203 of source / drain region 201 formed in task 110. In one or more embodiments, sacrificial layer 202 may be made of silicon germanium (SiGe) (e.g., Si x Ge 1-x In one or more embodiments, the thickness of the sacrificial layer 202 can be less than the thickness of the source / drain region 201 formed in task 110 (eg, the thickness of the sacrificial layer 202 can be less than half the thickness of the source / drain region 201).

[0030] In the illustrated embodiment, method 100 also includes task 130 of forming (e.g., epitaxially growing) source / drain regions 204 of the upper field effect transistor on upper surface 205 of sacrificial layer 202 formed in task 120. Sacrificial layer 202 formed in task 120 is a seed layer for source / drain regions 204 formed in task 130. x Ge 1-x In one or more embodiments formed, the sacrificial layer 202 is configured to improve the controllability and quality of the source / drain region 204 grown from the sacrificial layer 202. In addition, in one or more embodiments, the thickness of the source / drain region 204 of the upper field effect transistor can be the same (or substantially the same) as the thickness of the source / drain region 201 of the lower field effect transistor.

[0031] In the illustrated embodiment, method 100 also includes task 140 of removing (e.g., selectively etching) sacrificial layer 202 formed in task 120. In one or more embodiments, the etch can be selective to SiGe. After task 140 of removing sacrificial layer 202, a gap 206 is formed between source / drain region 201 of the lower field effect transistor and source / drain region 204 of the upper field effect transistor.

[0032] In the illustrated embodiment, method 100 also includes task 150 of depositing an oxide layer 207 in gap 206 (formed in task 140) between source / drain region 201 of the lower field effect transistor and source / drain region 204 of the upper field effect transistor. In the illustrated embodiment, oxide layer 207 fills gap 206 left by removing sacrificial layer 202 (e.g., oxide layer 207 contacts upper surface 203 of source / drain region 201 of the lower field effect transistor and lower surface 208 of source / drain region 204 of the upper field effect transistor). Oxide layer 207 isolates source / drain region 201 of the lower field effect transistor from source / drain region 204 of the upper field effect transistor.

[0033] In this way, the method 100 for manufacturing a 3D FET is configured to achieve proper isolation between the source / drain regions 201, 204 of the upper field effect transistor and the lower field effect transistor, and to improve the controllability and quality of the source / drain region 204 of the upper field effect transistor because the sacrificial layer 202 (including SiGe) is the seed layer of the source / drain region 204 of the upper field effect transistor.

[0034] In one or more embodiments, the method 100 further includes one or more tasks of forming source / drain contacts contacting the source / drain regions 201 , 204 of the upper FET and the lower FET and forming metal gate structures of the upper FET and the lower FET.

[0035] Although the present invention has been described in detail with specific reference to embodiments of the present invention, the embodiments described herein are not intended to be exhaustive or to limit the scope of the present invention to the exact forms disclosed. Those skilled in the art and technology to which the present invention belongs will appreciate that modifications and changes to the described structures and assembly and operating methods may be practiced without meaningfully departing from the principles, spirit and scope of the present invention.

Claims

1. A method for manufacturing a three-dimensional field effect transistor, the three-dimensional field effect transistor comprising an upper field effect transistor stacked on a lower field effect transistor, the method comprising: epitaxially growing the source / drain region of the lower field effect transistor; growing a sacrificial layer on an upper surface of the source / drain region of the lower field effect transistor; epitaxially growing the source / drain region of the upper field effect transistor on the sacrificial layer, wherein the sacrificial layer is a seed layer of the source / drain region of the upper field effect transistor; selectively etching the sacrificial layer to form a gap between the source / drain region of the lower field effect transistor and the source / drain region of the upper field effect transistor; as well as An oxide layer is deposited in the gap.

2. The method according to claim 1, wherein: The sacrificial layer includes silicon germanium (SiGe).

3. The method according to claim 1, wherein: The sacrificial layer includes Si x Ge 1-x .

4. The method according to claim 1, wherein: The thickness of the sacrificial layer is smaller than the thickness of each of the source / drain region of the upper field effect transistor and the source / drain region of the lower field effect transistor.

5. The method according to claim 1, wherein: The oxide layer has a thickness smaller than a thickness of each of the source / drain region of the upper field effect transistor and the source / drain region of the lower field effect transistor.

6. The method according to claim 1, wherein: The lower field effect transistor is an n-type field effect transistor, and the upper field effect transistor is a p-type field effect transistor.

7. The method according to claim 1, wherein: The lower field effect transistor is a p-type field effect transistor, and the upper field effect transistor is an n-type field effect transistor.

8. A three-dimensional field effect transistor, comprising: A lower field effect transistor, comprising a source region, a drain region, a channel region between the source region and the drain region, and a gate on the channel; an upper field effect transistor, stacked on the lower field effect transistor, Each of the lower field effect transistor and the upper field effect transistor includes a source region, a drain region, a channel region between the source region and the drain region, and a gate on the channel, and The source region and the drain region of the lower field effect transistor are separated from the source region and the drain region of the upper field effect transistor by an oxide layer.

9. The three-dimensional field effect transistor according to claim 8, wherein: The lower field effect transistor is an n-type field effect transistor, and the upper field effect transistor is a p-type field effect transistor.

10. The three-dimensional field effect transistor according to claim 8, wherein: The lower field effect transistor is a p-type field effect transistor, and the upper field effect transistor is an n-type field effect transistor.

11. The three-dimensional field effect transistor according to claim 8, wherein: The oxide layer has a thickness smaller than a thickness of each of the source / drain region of the upper field effect transistor and the source / drain region of the lower field effect transistor.

Images