Semiconductor structure, semiconductor module and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a semiconductor module and electronic equipment, relates to the technical field of electronics, and is used for reducing the occupied area of ESD (Electro-Static Discharge) protection. The semiconductor structure comprises a first switch tube, a second switch tube and an electrostatic protection circuit. The electrostatic protection circuit comprises a control circuit and a bleeder circuit. The control circuit comprises a common circuit, a first branch circuit and a second branch circuit, the common circuit and the first branch circuit form a first ESD control circuit, and the common circuit and the second branch circuit form a second ESD control circuit. The bleeder circuit includes a first ESD bleeder circuit and a second ESD bleeder circuit. The first ESD control circuit and the first ESD discharge circuit can realize discharge of the first switch tube, and the second ESD control circuit and the second ESD discharge circuit can realize ESD discharge of the second switch tube. Due to the existence of the common circuit, the control circuit can be less provided with one or more structures corresponding to the common circuit. The bleeder circuit may also include a common portion to reduce an area of the electrostatic protection circuit.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a semiconductor structure, a semiconductor module and an electronic device. Background Art

[0002] Electrostatic discharge (ESD) refers to the physical phenomenon of charge transfer between two objects with unequal potentials. It exists in any aspect of people's daily work and life. In the semiconductor industry, electrostatic discharge may occur on the pins of circuits during production, transportation, testing, and even user use, causing circuit failure. As the characteristic size of semiconductor devices such as transistors in semiconductor structures continues to decrease and the integration level continues to increase, semiconductor structures are becoming more and more sensitive to ESD impacts, making ESD protection of semiconductor structures one of the important indicators for measuring the reliability of semiconductor structures.

[0003] However, how to reduce the area occupied by ESD protection, thereby reducing the impact of ESD protection on the size of semiconductor structures, is a difficult problem that those skilled in the art need to overcome. Summary of the invention

[0004] Embodiments of the present application provide a semiconductor structure, a semiconductor module, and an electronic device for reducing the occupied area of ​​ESD protection.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect of an embodiment of the present application, a semiconductor structure is provided, including: a first switch tube, a second switch tube and an electrostatic protection circuit, wherein the electrostatic protection circuit is used to discharge the static electricity of the first switch tube and the second switch tube. The first switch tube includes a first gate, a first source and a first drain, and the second switch tube includes a second gate, a second source and a second drain, and the first source and the second source are insulated from each other. The electrostatic protection circuit includes a control circuit and a discharge circuit. The control circuit includes a first common circuit, a first node, a second node, a first branch circuit and a second branch circuit; the first node is coupled to the first gate and the second gate respectively, the first common circuit is coupled between the first node and the second node, the first branch circuit is coupled between the second node and the first source, and the second branch circuit is coupled between the second node and the second source. In other words, the control circuit includes a common part and a branch part. The discharge circuit is coupled to the second node; the discharge circuit is also coupled to the first gate and the first source to form a first discharge path; the discharge circuit is also coupled to the second gate and the second source to form a second discharge path.

[0007] In the semiconductor structure provided in the embodiment of the present application, the first common circuit and the first branch circuit constitute the first ESD control circuit of the first switch tube M1, the first common circuit and the second branch circuit constitute the second ESD control circuit of the second switch tube, the first ESD control circuit and the first discharge path constitute the ESD protection unit of the first switch tube, and the second ESD control circuit and the second discharge path constitute the ESD protection unit of the second switch tube. It is equivalent to that the ESD protection circuit in the semiconductor structure can realize the functions that can be realized by two ESD protection units, but it has to reduce the structure corresponding to the first common circuit by one compared with the two ESD protection units. If the semiconductor structure includes n second switch tubes, the ESD protection circuit can realize the functions that can be realized by n+1 ESD protection units, but it has to reduce the structure corresponding to n first common circuits by n+1 ESD protection units. Therefore, the area of ​​the ESD protection circuit can be reduced to reduce the cost of the semiconductor structure and facilitate the miniaturization of the semiconductor structure. It has been found through simulation verification that, under the premise of the same effect, the area of ​​the ESD protection circuit in the embodiment of the present application can be reduced by about 20% compared with the area of ​​the ESD protection circuit composed of 2 ESD protection units, and the area of ​​the final semiconductor structure can be reduced by about 5%. In addition, simulation verification shows that the ESD protection capability (ESD discharge capability) of the ESD protection circuit in the embodiment of the present application and the ESD protection circuit composed of n+1 ESD protection units are almost the same. Moreover, the control circuit also includes a first branch circuit and a second branch circuit, and the first source and the second source are isolated by the first branch circuit and the second branch circuit, which can also meet the requirements of electrical isolation, and there will be no signal crosstalk between different switch tubes.

[0008] In a possible implementation, the first gate and the second gate are coupled. This is an application scenario in which the first gate and the second gate are coupled.

[0009] In a possible implementation, the first gate and the second gate are insulated from each other, and the control circuit further includes a third branch circuit and a fourth branch circuit; the third branch circuit is coupled between the first node and the first gate, and the fourth branch circuit is coupled between the first node and the second gate. This is an application scenario in which the first gate and the second gate are not coupled.

[0010] In a possible implementation, the control circuit further includes a common branch circuit; the common branch circuit is coupled between the first branch circuit, the second branch circuit and the second node. By providing a common part in the branch circuit, the occupied area of ​​the control circuit can be further reduced.

[0011] In a possible implementation, the first common circuit includes a first diode. This is an implementation with a simple structure.

[0012] In a possible implementation, the first common circuit includes a first capacitor and a first resistor coupled in parallel. This is an implementation with a simple structure.

[0013] In a possible implementation, the first branch circuit includes a second resistor. This is an implementation with a simple structure.

[0014] In a possible implementation, the first branch circuit includes a third resistor and a second diode, and the third resistor is connected in parallel or in series with the second diode. This is an implementation with a simple structure.

[0015] In a possible implementation, the first branch circuit includes a fourth resistor and a second capacitor connected in parallel. This is an implementation with a simple structure.

[0016] In a possible implementation, the common branch circuit includes a fifth resistor, and the first branch circuit includes a third diode. This is an implementation with a simple structure.

[0017] In a possible implementation, the third branch circuit includes a fourth diode. The fourth diode is used as an electrical isolation structure, which has a simple structure, a larger equivalent resistance, a smaller leakage current, and a better electrical isolation effect between the first gate and the second gate.

[0018] In a possible implementation manner, the structure of the third branch circuit is the same as that of the first branch circuit.

[0019] In one possible implementation, the discharge circuit includes a first common part, a first branch part and a second branch part; the first common part is coupled to the second node, the first gate and the second gate respectively, the first branch part is coupled between the first common part and the first source, and the second branch part is coupled between the first common part and the second source.

[0020] In this way, the first common part and the first branch part constitute the first ESD discharge circuit of the first switch tube, the first common part and the second branch part constitute the second ESD discharge circuit of the second switch tube, the first ESD discharge circuit and the first control signal path constitute the ESD protection unit of the first switch tube, and the second ESD discharge circuit and the second control signal path constitute the ESD protection unit of the second switch tube. It is equivalent to that the ESD protection circuit in the semiconductor structure can realize the functions that can be realized by two ESD protection units, but the structure corresponding to the first common part is reduced by one compared with the two ESD protection units. If the semiconductor structure includes n second switch tubes, the ESD protection circuit can realize the functions that can be realized by n+1 ESD protection units, but the structure corresponding to the first common part is reduced by n compared with the n+1 ESD protection units. Therefore, the area of ​​the ESD protection circuit can be reduced to reduce the cost of the semiconductor structure and facilitate the miniaturization of the semiconductor structure. Through simulation verification, it is found that, under the premise of the same effect, the area of ​​the ESD protection circuit in the embodiment of the present application can be reduced by about 10%-30% compared with the area of ​​the ESD protection circuit composed of two ESD protection units, and the area of ​​the semiconductor structure 10 can be reduced by about 5%. In addition, the discharge circuit also includes a first branch part and a second branch part, and the first source and the second source are isolated by the first branch part and the second branch part, which can also meet the requirements of electrical isolation, and signal crosstalk will not occur between different switch tubes.

[0021] In a possible implementation, the discharge circuit further includes a third branch portion and a fourth branch portion; the third branch portion is coupled between the first common portion and the first gate, and the fourth branch portion is coupled between the first common portion and the second gate. This is an application scenario in which the first gate and the second gate are not coupled.

[0022] In a possible implementation, the first common part includes a third gate and a third drain, the first branch part includes a plurality of third sources, and the second branch part includes a plurality of fourth sources; the plurality of third sources and the plurality of fourth sources are alternately arranged in a direction parallel to the third drain; the plurality of third sources are coupled to the first source, the plurality of fourth sources are coupled to the second source, the third gate is coupled to the second node, and the third drain is directly coupled to the first gate and the second gate. This is a simple structure and low cost implementation.

[0023] In a possible implementation, the semiconductor structure further includes an integrated circuit. The semiconductor structure provided in the present application can be applied to a variety of application scenarios.

[0024] According to a second aspect of an embodiment of the present application, a semiconductor structure is provided, including: a first switching tube, including a first gate, a first source and a first drain; a second switching tube, including a second gate, a second source and a second drain, the first source and the second source are insulated from each other; an electrostatic protection circuit, including a discharge circuit; the discharge circuit includes a first common part, a third node, a fourth node, a first branch part and a second branch part; the third node is coupled to the first gate and the second gate respectively, the first common part is coupled between the third node and the fourth node, the first branch part is coupled between the fourth node and the first source, and the second branch part is coupled between the fourth node and the second source.

[0025] The beneficial effects of the semiconductor structure provided by the second aspect are the same as the beneficial effects of the semiconductor structure provided by the first aspect, and will not be repeated here.

[0026] In a possible implementation manner, the first gate and the second gate are coupled.

[0027] In a possible implementation, the first gate and the second gate are insulated from each other, and the discharge circuit further includes a third branch portion and a fourth branch portion; the third branch portion is coupled between the third node and the first gate, and the fourth branch portion is coupled between the third node and the second gate.

[0028] In one possible implementation, the first common part includes a third gate and a third drain, the first branch part includes a plurality of third sources, and the second branch part includes a plurality of fourth sources; the plurality of third sources and the plurality of fourth sources are alternately arranged in a direction parallel to the third drain; the plurality of third sources are coupled to the first source, the plurality of fourth sources are coupled to the second source, the third gate is coupled to the second node, and the third drain is coupled to the third node.

[0029] In a possible implementation, the electrostatic protection circuit also includes a control circuit; one end of the control circuit is coupled to the first gate and the second gate, the other end of the control circuit is coupled to the first source and the second source, and the control circuit is also coupled to the first common part.

[0030] In a possible implementation, the first common part includes a fifth diode; and the first branch part includes a sixth diode. This is an ESD protection circuit that does not require a control circuit.

[0031] In a possible implementation manner, the third branch portion includes a seventh diode.

[0032] According to a third aspect of the embodiments of the present application, a semiconductor structure is provided, including: a first switch tube, including a first gate, a first source and a first drain; a second switch tube, including a second gate, a second source and a second drain; the first source and the second source are coupled, and the first gate and the second gate are insulated from each other. An electrostatic protection circuit includes a control circuit and a discharge circuit; the control circuit includes a second common circuit, a fifth node, a sixth node, a fifth branch circuit and a sixth branch circuit; the fifth node is coupled to the first source and the second source respectively, the second common circuit is coupled between the fifth node and the sixth node, the fifth branch circuit is coupled between the sixth node and the first gate, and the sixth branch circuit is coupled between the sixth node and the second gate; the discharge circuit is coupled to the sixth node; the discharge circuit is also coupled to the first gate and the first source to form a first discharge path; the discharge circuit is also coupled to the second gate and the second source to form a second discharge path.

[0033] In a possible implementation manner, the fifth branch circuit includes an eighth diode.

[0034] In a possible implementation manner, the fifth branch circuit is coupled in parallel to a sixth resistor and a third capacitor.

[0035] In a possible implementation manner, the second shared circuit includes a seventh resistor.

[0036] In a possible implementation, the second common circuit includes an eighth resistor and a ninth diode coupled in parallel.

[0037] In a possible implementation, the second shared circuit includes a ninth resistor and a fourth capacitor coupled in parallel.

[0038] In one possible implementation, the discharge circuit includes a second common part, a fifth branch part and a sixth branch part; the fifth branch part is coupled to the sixth node, the first gate and the second common part respectively, and the sixth branch part is coupled to the sixth node, the second gate and the second common part respectively; the second common part is also coupled to the first source and the second source.

[0039] According to a fourth aspect of the embodiments of the present application, a semiconductor structure is provided, including: a first switching tube, including a first gate, a first source and a first drain; a second switching tube, including a second gate, a second source and a second drain, the first source and the second source are coupled, and the first gate and the second gate are insulated from each other; an electrostatic protection circuit, including a discharge circuit; the discharge circuit includes a second common part, a seventh node, an eighth node, a fifth branch part and a sixth branch part; the seventh node is coupled to the first source and the second source respectively, the second common part is coupled between the seventh node and the eighth node, the fifth branch part is coupled between the eighth node and the first gate, and the sixth branch part is coupled between the eighth node and the second gate.

[0040] In a possible implementation manner, the seventh node is directly coupled to the first source and the second source.

[0041] In a possible implementation manner, the fifth branch portion includes an eleventh diode; and the second common portion includes a tenth diode.

[0042] According to a fifth aspect of an embodiment of the present application, a semiconductor module is provided, comprising: a semiconductor structure and an integrated circuit; the semiconductor structure comprises the semiconductor structure of any one of the first to fourth aspects, and the integrated circuit is coupled to the semiconductor structure.

[0043] According to a sixth aspect of an embodiment of the present application, there is provided an electronic device, comprising a semiconductor module and a circuit board, wherein the semiconductor module is arranged on the circuit board; the semiconductor module comprises the semiconductor module of the fifth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 An application scenario diagram of an electronic device provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of the layout of a power adapter provided in an embodiment of the present application;

[0046] Figure 3A-Figure 3F A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0047] Figure 4A-4D A schematic diagram of an interconnection method of multiple switch tubes in a semiconductor structure provided in an embodiment of the present application;

[0048] Figure 5 A topological schematic diagram of a semiconductor structure illustrated in an embodiment of the present application;

[0049] Figure 6A-6C A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0050] Figure 7 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0051] Figure 8 A curve diagram of the number of switch tubes and the degree of area reduction provided in an embodiment of the present application;

[0052] Fig. 9A A method provided in the embodiment of the present application Figure 5 The ESD discharge effect diagram of the semiconductor structure shown;

[0053] Fig. 9B A method provided in the embodiment of the present application Fig. 6AThe ESD discharge effect diagram of the semiconductor structure shown;

[0054] Fig. 10A A schematic diagram of a topological structure of an ESD protection circuit provided in an embodiment of the present application;

[0055] Fig. 10B A schematic diagram of a topological structure of an ESD protection circuit according to an embodiment of the present application;

[0056] Fig.11 A schematic diagram of a topological structure of an ESD protection circuit provided in an embodiment of the present application;

[0057] Fig.12 A schematic diagram of a topological structure of an ESD protection circuit provided in an embodiment of the present application;

[0058] Fig.13 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0059] Fig.14 A schematic diagram of a topological structure of an ESD protection circuit provided in an embodiment of the present application;

[0060] Fig.15 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0061] Fig.16A and Fig. 16B A schematic diagram of a topological structure of an ESD protection circuit provided in an embodiment of the present application;

[0062] Fig.17 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0063] Fig.18 A schematic diagram of the structure of a discharge circuit provided in an embodiment of the present application;

[0064] Fig.19 A schematic diagram of a topological structure of an ESD protection circuit provided in an embodiment of the present application

[0065] Fig. 20 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0066] Fig.21 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0067] Fig. 22 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0068] Fig.23A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0069] Fig.24 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0070] Fig.25 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0071] Fig.26 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0072] Fig. 27 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0073] Figure 28A-Figure 30 A schematic diagram of a topological structure of an ESD protection circuit provided in an embodiment of the present application;

[0074] Fig.31 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0075] Fig.32 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0076] Fig.33 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application;

[0077] Fig.34 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0078] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0079] In the following, the terms "second", "first", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0080] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to the change of the orientation of the components in the drawings.

[0081] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

[0082] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0083] The embodiment of the present application provides an electronic device, which is, for example, a consumer electronic product with a charging demand, a home electronic product, a vehicle-mounted electronic product, and a financial terminal product. Consumer electronic products include power adapters, mobile phones, tablet computers, laptop computers, electronic readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. The embodiment of the present application does not impose any special restrictions on the specific forms of the above-mentioned electronic devices.

[0084] Figure 1 An application scenario diagram of an electronic device provided in an embodiment of the present application.

[0085] like Figure 1 As shown, the electronic device provided in the embodiment of the present application can be used in a charging scenario. For example, the charging scenario includes a power adapter 100 and a mobile phone 200, the power adapter 100 is connected to the mains via a plug, and the mobile phone 200 is connected to the power adapter 100 via a data cable 300.

[0086] Figure 2 A schematic diagram of the layout of a power adapter provided in an embodiment of the present application.

[0087] The semiconductor module with switch tube in electronic equipment is an important module to realize the charging and discharging function of electronic equipment, such as Figure 2 As shown, taking the electronic device power adapter 100 as an example, the power adapter 100 includes a semiconductor module, a circuit board and a housing ( Figure 2 not shown).

[0088] The semiconductor module is arranged on the circuit board, and the circuit board may also be arranged on the other integrated circuits included in the power adapter 100. The semiconductor module and the circuit board are arranged in the housing.

[0089] The semiconductor module includes a semiconductor structure 10 including a switch tube and an integrated circuit (IC). The IC includes, for example, a control or driver IC, and may also include passive components such as resistors and capacitors. The semiconductor structure 10 is controlled to be turned on and off by the control or driver IC to achieve functions such as AC / DC conversion, DC / DC conversion, and filtering. Of course, in addition to the switch tube, the semiconductor module may also include passive components such as resistors and capacitors to assist the control or driver IC in responding to the switch of the semiconductor structure 10; the switch tube, passive components, and the control or driver IC are interconnected to form a charging switch circuit. The semiconductor module is, for example, a gallium nitride (GaN) device.

[0090] As the charging requirements of terminal electronic devices develop towards faster charging, smaller size and better efficiency, the core components (switching tubes) of their charging topology semiconductor modules have also been developing towards smaller area, lower on-resistance and better dynamic parameters (such as total gate charge Qg, output capacitance Coss, etc.).

[0091] In recent years, semiconductor devices with high thermal conductivity, high temperature resistance, wide band gap (WBG), high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, greater electron saturation rate, and stable chemical properties have been widely used as power devices.

[0092] For example, the third-generation semiconductor GaN material has excellent properties, such as a large bandgap (3.4eV), a high breakdown electric field (3.3MV / cm), a large saturation rate (2.5e7cm / s), and a high 2DEG density at the interface of the aluminum gallium nitride (AlGaN) / GaN heterostructure due to the polarization effect, which enables AlGaN / GaN high-electron-mobility transistor (HEMT) devices prepared on silicon carbide (SiC) substrates or silicon (Si) substrates to operate at higher voltages, higher temperatures, and higher frequencies. HEMT devices have higher electron mobility and a larger bandgap than metal-oxide semiconductor field-effect transistor (MOSFET) devices. Under the same withstand voltage specifications, the conduction loss and switching loss of power devices can be further reduced, and the performance and competitiveness of electronic devices such as power adapters can be improved, so they are widely used as power devices.

[0093] Based on this, in some embodiments, the switch tube included in the semiconductor structure 10 is a HEMT.

[0094] However, HEMT devices are limited by their structure and materials, resulting in weak gate voltage resistance. The gate-source electrostatic discharge (ESD) tolerance of HEMT devices is only 100V to 200V (MOSFET devices are at the level of 1000V to 2000V), and premature breakdown failure is prone to occur during the use or assembly of HEMT devices. Therefore, ESD protection of HEMT devices is particularly important.

[0095] In some embodiments, a solution to achieve ESD protection is to integrate an ESD protection circuit in the semiconductor structure 10 to improve the ESD tolerance of the HEMT device.

[0096] Figure 3A-Figure 3F A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0097] In some embodiments, Figure 3A As shown, the semiconductor structure 10 includes a switch tube M and an ESD protection unit 20 ′.

[0098] For example, the switch tube M includes a gate (gate, G), a source (source, S) and a drain (drain, D). The ESD protection unit 20' includes an ESD discharge circuit 40', which is coupled between the gate G and the source S of the switch tube M, and is used to turn on the ESD discharge circuit 40' when the gate G voltage is greater than a set value, so as to form a discharge path between the gate G and the source S.

[0099] For example, Figure 3B As shown, the ESD protection unit 20 ′ includes a plurality of diodes d. The diodes d may be arranged in a plurality of rows and columns, for example.

[0100] Or, for example, Figure 3C As shown, the ESD protection unit 20' includes an ESD control circuit 30' and an ESD discharge circuit 40'. The ESD control circuit 30' is coupled between the gate G and the source S of the switch tube M. The ESD discharge circuit 40' is coupled between the gate G and the source S of the switch tube M and is coupled to the ESD control circuit 30'. When the gate G voltage is greater than the set value, the ESD control circuit 30' outputs a start control signal to the ESD discharge circuit 40'. The ESD discharge circuit 40' is used to be turned on under the control of the ESD control circuit 30' to form a discharge path between the gate G and the source S.

[0101] For example, Figure 3D As shown, the ESD control circuit 30′ includes a first voltage dividing unit composed of a plurality of diodes d and a second voltage dividing unit composed of a resistor R, wherein the plurality of diodes d and the resistor R are coupled in series between the gate G and the source S of the switch tube M. The ESD discharge circuit 40′ includes a discharge transistor T, wherein the gate of the discharge transistor T is coupled between the plurality of diodes d and the resistor R, the drain of the discharge transistor T is coupled to the gate G of the switch tube M, and the source of the discharge transistor T is coupled to the source S of the switch tube M.

[0102] Or, for example, Figure 3E As shown, the ESD control circuit 30′ includes a first voltage dividing unit formed by a plurality of diodes d and a second voltage dividing unit formed by a plurality of diodes d connected in parallel with a resistor R, wherein the first voltage dividing unit and the second voltage dividing unit are coupled in series between the gate G and the source S of the switch tube M. The ESD discharge circuit 40′ includes a discharge transistor T, wherein the gate of the discharge transistor T is coupled between the first voltage dividing unit and the second voltage dividing unit, the drain of the discharge transistor T is coupled to the gate G of the switch tube M, and the source of the discharge transistor T is coupled to the source S of the switch tube M.

[0103] Or, for example, Figure 3FAs shown, the ESD control circuit 30′ includes a first voltage dividing unit composed of a capacitor C and a resistor R in parallel and a second voltage dividing unit composed of a capacitor C and a resistor R in parallel, and the first voltage dividing unit and the second voltage dividing unit are coupled in series between the gate G and the source S of the switch tube M. The ESD discharge circuit 40′ includes a discharge transistor T, the gate of the discharge transistor T is coupled between the first voltage dividing unit and the second voltage dividing unit, the drain of the discharge transistor T is coupled to the gate G of the switch tube M, and the source of the discharge transistor T is coupled to the source S of the switch tube M.

[0104] Typically, the area required for the ESD protection unit 20' is about 0.2 mm 2 Up to 0.3mm 2 Therefore, in the application scenario where the semiconductor structure 10 includes one switch tube M, the ESD protection unit 20' is integrated in the semiconductor structure 10, and the impact on the area of ​​the semiconductor structure 10 is still within an acceptable range. However, in the application scenario where the semiconductor structure 10 includes multiple switch tubes M, the structure in the semiconductor structure 10 includes multiple Figure 3A-Figure 3F As shown in the repetitive unit, the ESD protection unit 20 ′ will have a greater impact on the area of ​​the semiconductor structure 10 .

[0105] Figure 4A-4D A schematic diagram of the interconnection method of multiple switch tubes in a semiconductor structure provided in an embodiment of the present application.

[0106] In some application scenarios, in order to meet the requirements of smaller size, lower cost, higher integration, etc., the semiconductor structure 10 contains multiple interrelated switch tubes M for multiple signal transmission or detection. For example, a semiconductor structure 10 with integrated current sampling function, or a semiconductor structure 10 with integrated half-bridge structure.

[0107] For example, Figure 4A As shown, in addition to the first switch tube M1 (for example, as a main switch tube), one or more second switch tubes M2 (for example, as auxiliary switch tubes) are also provided in the semiconductor structure 10. Figure 4A A second switch tube M2 is used as an example for illustration. The second gate G2 of each second switch tube M2 and the first gate G1 of the first switch tube M1 can be coupled, but the second source S2 of the second switch tube M2 and the first source S1 of the first switch tube M1 are insulated from each other to avoid signal crosstalk. The second drain D2 of the second switch tube M2 and the first drain D1 of the first switch tube M1 can be coupled or not coupled. Figure 4A The figure is for illustration only.

[0108] For example, Figure 4BAs shown, the first switch tube M1 and the second switch tube M2 are power switch tubes in a conventional flyback topology, and the first switch tube M1 and the second switch tube M2 are electrically connected to the capacitor C, the resistor R, and the transformer. The first switch tube M1 is used as a power device, and the second switch tube M2 is mainly used to provide the IC with a current signal for collecting the system current after current shunting. The first gate G1 and the second gate G2 are coupled, and the first source S1 and the second source S2 need to be electrically isolated so as not to affect the current sampling accuracy.

[0109] Or, for example, Figure 4C As shown, in addition to the first switch tube M1, one or more second switch tubes M2 are also provided in the semiconductor structure 10. Figure 4C A second switch tube M2 is used as an example for illustration. The second gate G2 of the second switch tube M2 and the first gate G1 of the first switch tube M1 are coupled and insulated from each other, and the second source S2 of the second switch tube M2 and the first source S1 of the first switch tube M1 are insulated from each other to avoid signal crosstalk. The first source S1 of the first switch tube M1 and the second drain D2 of the second switch tube M2 may be coupled or not coupled. Figure 4C It is only an illustration. Among the multiple second switch tubes M2, the second gate G2 of each second switch tube M2 may not be coupled to the first gate G1 of the first switch tube M1, or the second gate G2 of some second switch tubes M2 may be coupled to the first gate G1 of the first switch tube M1. The semiconductor structure 10 provided in the embodiment of the present application may be any combination of the multiple schemes illustrated in the embodiment of the present application.

[0110] For example, Figure 4D As shown, the first switch tube M1 and the second switch tube M2 are power switch tubes in the active clamp flyback topology, and the first switch tube M1 and the second switch tube M2 are electrically connected to the capacitor C, the inductor L, and the transformer. The first switch tube M1 is an upper power tube, and the second switch tube M2 is a lower power tube. The first source S1 of the first switch tube M1 is coupled to the second drain D2 of the second switch tube M2 to form a half-bridge structure. The first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 need to be electrically isolated.

[0111] Of course, the above application scenarios are only for illustration and are not intended to be limiting.

[0112] For the structure including multiple switch tubes in the semiconductor structure 10, if the ESD protection unit 20' is only set between the first gate G1 and the first source S1 of the first switch tube M1, then ESD will preferentially break down the second switch tube M2. In particular, when the second switch tube M2 has a smaller area and a larger impedance, it is more likely to be preferentially broken down. Therefore, in order to provide ESD protection for both the first gate G1 and the first source S1 of the first switch tube M1 and the second gate G2 and the second source S2 of the second switch tube M2, while not affecting the signal isolation between the first switch tube M1 and the second switch tube M2, each second switch tube M2 also needs to be provided with a corresponding ESD protection unit 20'. Then, if Figure 5 As shown, for each additional second switch tube M2, an additional set of ESD protection units 20 ′ needs to be added for protection.

[0113] The area of ​​a single ESD protection unit 20' is about 0.2mm 2 Up to 0.3mm 2 , accounting for about 10% or more of the area of ​​the semiconductor structure 10. The impedance of the switch tube is different, and the area of ​​the ESD protection unit 20' is different. Then, if the semiconductor structure 10 includes n switch tubes M, and the n switch tubes M are all main switch tubes. Then the area of ​​the n ESD protection units 20' is about n*0.2mm 2 To n*0.3mm 2 , accounting for about 10% or more of the area of ​​the semiconductor structure 10. If the semiconductor structure 10 includes n switch tubes M, one switch tube M is a main switch tube, and the remaining n-1 switch tubes M are auxiliary switch tubes. Then the area of ​​n ESD protection units 20' is still about n*0.2mm 2 To n*0.3mm 2 , but occupies about 20% or even more of the area of ​​the semiconductor structure 10.

[0114] This results in that the more switch tubes M are integrated in the semiconductor structure 10, the larger the area of ​​the multiple ESD protection units 20', resulting in a larger area of ​​the semiconductor structure 10. This will affect the number of wafers produced by the semiconductor structure 10, gradually increase the cost of the semiconductor structure 10, and hinder the miniaturization of the semiconductor structure 10.

[0115] Based on this, an embodiment of the present application provides a semiconductor structure 10, which reduces the occupied area of ​​multiple ESD protection units 20' on the basis of ensuring that each switch tube M has a high ESD protection capability and isolating the signals between multiple switch tubes M, so as to reduce the area of ​​the semiconductor structure 10.

[0116] Figure 6A-6C A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0117] The present application also provides a semiconductor structure 10, such as Fig. 6A As shown, the semiconductor structure 10 includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 . The ESD protection circuit 20 includes a control circuit 30 and a discharge circuit 40 .

[0118] The first switch tube M1 includes a first gate G1, a first source S1 and a first drain D1, the second switch tube M2 includes a second gate G2, a second source S2 and a second drain D2, and the first gate G1 and the second gate G2 are coupled.

[0119] In the first possible implementation, Fig. 6A As shown, the first gate G1 and the second gate G2 are coupled, and the first source S1 and the second source S2 are insulated from each other.

[0120] In some embodiments, the control circuit 30 includes a first common control circuit part and two separate control circuit parts respectively coupled to the first source S1 and the second source S2. The first common control circuit part and the separate control circuit part constitute Figure 5 The ESD control circuit 30′ is composed of a first common part of the control circuit and another discrete part of the control circuit. Figure 5 Another ESD control circuit 30' in the control circuit. The first common part of the control circuit is used to output a control signal to the discharge circuit 40 to control the first switch tube M1 and / or the second switch tube M2 to release static electricity quickly when static electricity exists between them.

[0121] In some other embodiments, the discharge circuit 40 includes a first common discharge circuit part and two separate discharge circuit parts respectively coupled to the first source S1 and the second source S2. The first common discharge circuit part and the separate discharge circuit part constitute Figure 5 The ESD discharge circuit 40 ′ is composed of a first common part of the discharge circuit and another discrete part of the discharge circuit. Figure 5 Another ESD discharge circuit 40' in.

[0122] In the second possible implementation, Figure 6B As shown, the first gate G1 and the second gate G2 are insulated from each other, and the first source S1 and the second source S2 are coupled.

[0123] In some embodiments, the control circuit 30 includes a first common control circuit portion and two separate control circuit portions coupled to the first gate G2 and the second gate G2, respectively.

[0124] In some other embodiments, the discharge circuit 40 includes a first common discharge circuit part and two separate discharge circuit parts respectively coupled to the first gate G1 and the second gate G2 , so that the first gate G1 and the second gate G2 can be electrically isolated.

[0125] In a third possible implementation, if Figure 6C As shown, the first gate G1 and the second gate G2 are insulated from each other, and the first source S1 and the second source S2 are also insulated from each other.

[0126] In some embodiments, the control circuit 30 includes a first common control circuit part and two discrete control circuit parts coupled to the first source S1 and the second source S2 respectively, and also includes two discrete control circuit parts coupled to the first gate G2 and the second gate G2 respectively.

[0127] In some other embodiments, the discharge circuit 40 includes the first common part of the discharge circuit and two separate parts of the discharge circuit respectively coupled to the first source S1 and the second source S2, and the discharge circuit 40 also includes two separate parts of the discharge circuit respectively coupled to the first gate G2 and the second gate G2. In this way, the electrical isolation of the first gate G1 and the second gate G2 can be achieved.

[0128] In this way, the semiconductor structure 10 and Figure 5 Compared with the semiconductor structure 10 shown in FIG. 1 , both can realize ESD protection for the first switch tube M1 and the second switch tube M2, but the ESD protection circuit 20 is Figure 5 The ESD protection circuit composed of the two ESD protection units 20′ shown needs to reduce the structure of the first common part of the control circuit and the structure of the first common part of the discharge circuit. If the semiconductor structure 10 includes N switch tubes M, the ESD protection part can reduce the structure of the first common part of the control circuit and the structure of the first common part of the discharge circuit by N-1. Therefore, the semiconductor structure 10 provided in the embodiment of the present application can reduce the area of ​​the ESD protection circuit 20, thereby reducing the area of ​​the semiconductor structure 10. At the same time, by setting the discrete part of the control circuit and the discrete part of the discharge circuit to electrically isolate the first switch tube M1 and the second switch tube M2, the function of the semiconductor structure 10 and the flow capacity of the discharge circuit 40 can be not affected.

[0129] The semiconductor structure 10 provided in the embodiment of the present application is schematically described below with reference to several examples.

[0130] Example 1

[0131] Figure 7 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0132] like Figure 7 As shown, an embodiment of the present application provides a semiconductor structure 10, and the semiconductor structure 10 includes a first switch tube M1, a second switch tube M2, and an ESD protection circuit 20. The first switch tube M1, the second switch tube M2, and the ESD protection circuit 20 are arranged on the same substrate, and the ESD protection circuit 20 is used to perform gate-source electrostatic protection on the first switch tube M1 and the second switch tube M2.

[0133] The first switch tube M1 and the second switch tube M2 are, for example, power switch tubes, for example, the first switch tube M1 and the second switch tube M2 are HEMT devices. In some embodiments, the first switch tube M1 is used as a main switch tube, and the second switch tube M2 is used as an auxiliary switch tube, and the area of ​​the second switch tube M2 is smaller than that of the first switch tube M1. Of course, the semiconductor structure 10 provided in the embodiment of the present application may include one second switch M2, or may include multiple second switches M2. Figure 7 The semiconductor structure 10 includes a second switch M2 as an example for illustration.

[0134] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1, and a first drain D1, and the second switch tube M2 includes a second gate G2, a second source S2, and a second drain D2. The first gate G1 is coupled to the second gate G2, and the first gate G1 and the second gate G2 can be coupled through a signal line. The first gate G1 and the second gate G2 can also be an integrated structure, and the first gate G1 is reused as the second gate G2. The first source S1 and the second source S2 are insulated from each other.

[0135] The ESD protection circuit 20 includes a control circuit 30 and a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0136] In some embodiments, the control circuit 30 includes a first common circuit 35 , a first node N1 , a second node N2 , a first branch circuit 31 , and a second branch circuit 32 .

[0137] The first node N1 is directly coupled to the first gate G1 and the second gate G2, and no other device structure is set between the first node N1 and the first gate G1, and no other device structure is set between the first node N1 and the second gate G2. The first common circuit 35 is coupled between the first node N1 and the second node N2, the first branch circuit 31 is coupled between the second node N2 and the first source S1, and the second branch circuit 32 is coupled between the second node N2 and the second source S2. Then, the first common circuit 35 and the first branch circuit 31 constitute the first ESD control circuit of the first switch tube M1, and the first gate G1-first node N1-first common circuit 35-second node N2-first branch circuit 31-first source S1 is the flow path of the first ESD control circuit. The first common circuit 35 and the second branch circuit 32 constitute the second ESD control circuit of the second switch tube M2, and the second gate G2-first node N1-first common circuit 35-second node N2-second branch circuit 32-second source S2 constitutes the flow path of the second ESD control circuit.

[0138] Although the first ESD control circuit and the second ESD control circuit share the first common circuit 35, it does not affect the function of the first ESD control circuit and the second ESD control circuit to output control signals to the discharge circuit 40. Functionally speaking, the first ESD control circuit and the second ESD control circuit can still realize the functions of two independent ESD control circuits 30'. That is, when static electricity exists between the first gate G1 and the first source S1 of the first switch tube M1, and / or when static electricity exists between the second gate G2 and the second source S2 of the second switch tube M2, the control circuit 30 can output a discharge control signal to the discharge circuit 40 to quickly discharge static electricity.

[0139] In some embodiments, the discharge circuit 40 is coupled to the second node N2, and the discharge circuit 40 receives a control signal at the second node N2. The discharge circuit 40 is also coupled to the first gate G1 and the first source S1 to form a first discharge path, and the second node N2 is used to control whether the first discharge path is turned on or off to achieve ESD protection for the first switch tube M1. The discharge circuit 40 is also coupled to the second gate G2 and the second source S2 to form a second discharge path, and the second node N2 is used to control whether the second discharge path is turned on or off to achieve ESD protection for the second switch tube M2.

[0140] For example, the discharge circuit 40 includes a first ESD discharge circuit 48 and a second ESD discharge circuit 49. The first ESD discharge circuit 48 is coupled between the first gate G1 and the first source S1. The first ESD discharge circuit 48 is also coupled to the second node N2, and is used to receive the control signal 1 output by the second node N2. The first ESD discharge circuit 48 is a first discharge path. The second ESD discharge circuit 49 is coupled between the second gate G2 and the second source S2. The second ESD discharge circuit 49 is also coupled to the second node N2, and is used to receive the control signal 2 output by the second node N2. The second ESD discharge circuit 49 is a second discharge path.

[0141] Based on this, in the semiconductor structure 10 provided in the embodiment of the present application, the first common circuit 35 and the first branch circuit 31 constitute the first ESD control circuit of the first switch tube M1, the first common circuit 35 and the second branch circuit 32 constitute the second ESD control circuit of the second switch tube M2, the first ESD control circuit and the first discharge path constitute the ESD protection unit 20' of the first switch tube M1, and the second ESD control circuit and the second discharge path constitute the ESD protection unit 20' of the second switch tube M2. It is equivalent to that the ESD protection circuit 20 in the semiconductor structure 10 can realize the functions that can be realized by two ESD protection units 20', but the structure corresponding to the first common circuit 35 is reduced by one compared with the two ESD protection units 20'. If the semiconductor structure 10 includes n second switch tubes M2, the ESD protection circuit 20 can realize the functions that can be realized by n+1 ESD protection units 20', but the structure corresponding to the first common circuit 35 is reduced by n compared with the n+1 ESD protection units 20'. Therefore, the area of ​​the ESD protection circuit 20 can be reduced to reduce the cost of the semiconductor structure 10 and facilitate the miniaturization of the semiconductor structure 10. Through simulation verification, it is found that under the premise of the same effect, the area of ​​the ESD protection circuit 20 in the embodiment of the present application can be reduced by about 20% compared with the area of ​​the ESD protection circuit composed of two ESD protection units 20', and the area of ​​the semiconductor structure 10 can be reduced by about 5%. Figure 8 As shown, it is found through calculation that as the number of second switch tubes M2 in the semiconductor structure 10 increases, the proportion of the ESD protection circuit area reduction will gradually increase, the proportion of the semiconductor structure 10 area reduction will gradually increase (20%-50%), and the proportion of the semiconductor structure 10 area reduction will gradually increase (5%-20%). Moreover, as the impedance of the first switch tube M1 increases, the proportion of the semiconductor structure 10 area reduction will gradually increase. In addition, as Fig. 9A and Fig. 9BAs shown, it is found through simulation verification that the ESD protection capability (ESD discharge capability) of the ESD protection circuit 20 including the common circuit and the ESD protection circuit composed of n+1 ESD protection units 20' in the embodiment of the present application is almost the same. In addition, the control circuit 30 also includes a first branch circuit 31 and a second branch circuit 32. The first source S1 and the second source S2 are isolated by the first branch circuit 31 and the second branch circuit 32, which can also meet the requirements of electrical isolation, and no signal crosstalk will occur between different switch tubes.

[0142] The structures of the first common circuit 35 , the first branch circuit 31 , the second branch circuit 32 , the first ESD discharge circuit 40 and the second ESD discharge circuit 40 are schematically described below, but the following schematic is not intended to limit the embodiments of the present application.

[0143] Fig. 10A A schematic diagram of the topological structure of an ESD protection circuit provided in an embodiment of the present application.

[0144] In some embodiments, Fig. 10A As shown, the first ESD discharge circuit 48 includes a first discharge transistor T1, a control electrode of the first discharge transistor T1 is coupled to the second node N2 for receiving a control signal 1, a first electrode of the first discharge transistor T1 is coupled to the first gate G1, and a second electrode of the first discharge transistor T1 is coupled to the first source S1.

[0145] In some embodiments, the second ESD discharge circuit 49 includes a second discharge transistor T2, a control electrode of the second discharge transistor T2 is coupled to the second node N2 for receiving the control signal 2, a first electrode of the second discharge transistor T2 is coupled to the second gate G2, and a second electrode of the second discharge transistor T2 is coupled to the second source S2.

[0146] In a possible embodiment, Fig. 10A As shown, the first common circuit 35 includes at least one first diode d1, Fig. 10A In the figure, the first common circuit 35 includes a plurality of first diodes d1 as an example for illustration.

[0147] For example, the first diode d1 is a diode, the first common circuit 35 includes a plurality of diodes, the plurality of diodes are coupled in series or in parallel, the first node N1 is coupled to the anode of the diode, and the second node N2 is coupled to the cathode of the diode. Optionally, the first common circuit 35 includes 5-8 first diodes d1.

[0148] Alternatively, for example, the first diode d1 is a Zener diode (also called a voltage-stabilizing diode zener diode), the first common circuit 35 includes one or more Zener diodes, the multiple Zener diodes are coupled in series or in parallel, the first node N1 is coupled to the cathode of the Zener diode, and the second node N2 is coupled to the anode of the Zener diode. Alternatively, the first node N1 is coupled to the anode of the Zener diode, and the second node N2 is coupled to the cathode of the Zener diode.

[0149] In some embodiments, the first common circuit 35 includes at least one transistor, the control electrode and the first electrode of the transistor are coupled, which is equivalent to the first diode d1 , and a plurality of transistors are coupled in series or in parallel.

[0150] For the diodes mentioned below, reference may be made to the relevant description about the first diode d1 in the embodiment of the present application.

[0151] In some embodiments, Fig. 10A As shown, the first branch circuit 31 includes a second resistor R2 , and the second resistor R2 is coupled between the second node N2 and the first source S1 .

[0152] The first branch circuit 31 may include one or more second resistors R2, and the multiple second resistors R2 may be connected in series or in parallel. Fig. 10A The second resistor R2 is used as an example for illustration. The resistance of the second resistor R2 may be, for example, tens of kΩ to hundreds of kΩ.

[0153] based on Fig. 10A In the semiconductor structure 10 shown, when the voltage between the first gate G1 and the first source S1 is low (no static electricity exists), the voltage of the first gate G1 is less than the clamping voltage of the first diode d1, and the first common circuit 35 is in the off state, which is equivalent to a high-resistance voltage-dividing structure. Then, the voltage of the second node N2 is almost equal to the voltage of the first source S1 and the second source S2. In this case, the first discharge transistor T1 and the second discharge transistor T2 are both in the off state.

[0154] When there is high voltage (static electricity) between the first gate G1 and the first source S1, the voltage of the first gate G1 is greater than the clamping voltage (conduction voltage drop) of the first diode d1, the first diode d1 is turned on instantly, and the first common circuit 35 is in the on state, which is equivalent to a low-resistance voltage-dividing structure. At this time, the current Ig flows from the first gate G1 through the first diode d1 through the second resistor R2, and after voltage division on the second resistor R2, the voltage value of the second node N2 reaches the start-up voltage of the first discharge transistor T1, that is, the voltage drop of the second node N2 relative to the first source S1 is greater than the threshold voltage (Vth1) of the first discharge transistor T1. At this time, the first discharge transistor T1 is turned on, and the high voltage between the first gate G1 and the first source S1 is discharged through the first discharge transistor T1. However, the voltage drop of the second node N2 relative to the second source S2 is less than the threshold voltage (Vth2) of the second discharge transistor T2, and at this time, the second discharge transistor T2 remains in the off state.

[0155] When a high voltage exists between the second gate G2 and the second source S2 , the discharge principle is the same as the discharge principle when a high voltage exists between the first gate G1 and the first source S1 .

[0156] When there is high voltage between the first gate G1 and the first source S1 and between the second gate G2 and the second source S2, after the voltage value of the second node N2 reaches the starting voltage, the voltage drop of the second node N2 relative to the first source S1 is greater than the threshold voltage (Vth1) of the first discharge transistor T1, and the voltage drop of the second node N2 relative to the second source S2 is greater than the threshold voltage (Vth2) of the second discharge transistor T2, the first discharge transistor T1 and the second discharge transistor T2 are both turned on, the high voltage between the first gate G1 and the first source S1 is discharged through the first discharge transistor T1, and the high voltage between the second gate G2 and the second source S2 is discharged through the second discharge transistor T2. At the same time, the first source S1 and the second source S2 are electrically isolated by two second resistors R2, and when there is no high voltage between the first source S1 and the second source S2, the first source S1 and the second source S2 can be better isolated.

[0157] Fig. 10B A schematic diagram of a topological structure of an ESD protection circuit according to an embodiment of the present application.

[0158] like Fig. 10B As shown, if the first common circuit 35 is not provided in the ESD protection circuit 20, the ESD protection circuit 20 requires two independent ESD protection units 20', and then two structures corresponding to the first common circuit 35 (multiple first diodes d1) must be provided, which will obviously increase the occupied area of ​​the ESD protection circuit 20.

[0159] Fig.11A schematic diagram of the topological structure of an ESD protection circuit provided in an embodiment of the present application.

[0160] In other embodiments, Fig.11 As shown, the first branch circuit 31 includes a third resistor R3 and at least one second diode d2, and the third resistor R3 is connected in parallel with the at least one second diode d2.

[0161] At least one second diode d2 can be regarded as a diode unit, coupled in parallel with the third resistor R3 between the second node N2 and the first source S1. For example, the second diode d2 is a conventional diode, the second node N2 is coupled to the anode of the second diode d2 in the diode unit, and the first source S1 is coupled to the cathode of the second diode d2 in the diode unit. When the first branch circuit 31 includes a plurality of second diodes d2, the plurality of second diodes d2 can be coupled in series and / or in parallel.

[0162] In some other embodiments, the first branch circuit 31 includes a third resistor R3 and at least one second diode d2 , and the third resistor R3 is connected in series with the at least one second diode d2 .

[0163] Similarly, at least one second diode d2 can be regarded as a diode unit, which is coupled in series with the third resistor R3 between the second node N2 and the first source S1, and the third resistor R3 can be coupled close to the second node N2, or the diode unit can be coupled close to the second node N2. The second node N2 is coupled to the anode of the second diode d2 in the diode unit, and the first source S1 is coupled to the cathode of the second diode d2 in the diode unit. When the first branch circuit 31 includes multiple second diodes d2, the multiple second diodes d2 can be coupled in series and / or in parallel.

[0164] Fig.12 A schematic diagram of the topological structure of an ESD protection circuit provided in an embodiment of the present application.

[0165] In another possible embodiment, Fig.12 As shown, the first sharing circuit 35 includes a first capacitor C1 and a first resistor R1 coupled in parallel between the first node N1 and the second node N2.

[0166] In some embodiments, the first branch circuit 31 includes a fourth resistor R4 and a second capacitor C2 coupled in parallel between the second node N2 and the first source S1 .

[0167] certainly, Fig.12 The first common circuit 35 shown in FIG. 3 can also be replaced by Fig.11 The first common circuit 35 shown, and / or Fig.12 The first branch circuit 31 shown in FIG. 3 can also be replaced by Fig. 10A or Fig.11 The first branch circuit 31 shown. In the embodiment of the present application, the first common circuit 35 and the first branch circuit 31 can be any combination of diodes, capacitors, resistors, etc., and the above is only an illustration.

[0168] Fig.13 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0169] In another possible implementation, Fig.13 As shown, the control circuit 30 further includes a common branch circuit 51, which is coupled between the first branch circuit 31, the second branch circuit 32 and the second node N2. Along the signal flow direction, one end of the common branch circuit 51 is coupled to the second node N2, and the other end of the common branch circuit 51 is coupled to the first branch circuit 31 and the second branch circuit 32, respectively.

[0170] Fig.14 A schematic diagram of the topological structure of an ESD protection circuit provided in an embodiment of the present application.

[0171] In some embodiments, Fig.14 As shown, the common branch circuit 51 includes a fifth resistor R5, and the first branch circuit 31 includes at least one third diode d3. For example, the third diode d3 is a conventional diode, the fifth resistor R5 is coupled to the anode of the third diode d3, and the cathode of the third diode d3 is coupled to the first source S1.

[0172] The third diode d3 is used as the electrical isolation structure. The third diode d3 has a larger equivalent resistance and a smaller leakage current, and the electrical isolation effect between the first source S1 and the second source S2 is better.

[0173] The first common circuit 35 may be Fig.12 or Fig.13 The structure of the first common circuit 35 shown in FIG. 4 is a structure of the discharge circuit 40, which can be Fig.13 The bleeder circuit 40 is shown.

[0174] In some embodiments, the structure of the second branch circuit 32 may be the same as that of any of the first branch circuits 31 , except that the first branch circuit 31 is coupled to the first source S1 , and the second branch circuit 32 is coupled to the second source S2 .

[0175] In the semiconductor structure 10 provided in the embodiment of the present application, the first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 are coupled. At the same time, the control circuit 30 in the ESD protection circuit 20 includes a first common circuit 35, and may further include a common branch circuit 51. If each switch tube M needs to match an ESD protection unit 20′, multiple ESD protection units 20′ share the same first common circuit 35 and common branch circuit 51, and the first common circuit 35 and the common branch circuit 51 do not need to be repeatedly set, which can reduce the area of ​​the ESD protection circuit 20, thereby reducing the area of ​​the semiconductor structure 10.

[0176] The semiconductor structure 10 provided in the embodiment of the present application may be a bare chip or a packaged chip. The semiconductor structure 10 may be packaged alone or together with other chips. In some embodiments, the semiconductor structure 10 further includes an IC (for example, the IC includes a control IC or a driver IC), and the IC is packaged in one chip with the first switch tube M1, the second switch tube M2, and the ESD protection circuit 20.

[0177] Example 2

[0178] The main difference between Example 2 and Example 1 is that the first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 are insulated from each other.

[0179] Fig.15 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0180] like Fig.15 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0181] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1 and a first drain D1, and the second switch tube M2 includes a second gate G2, a second source S2 and a second drain D2. The first gate G1 and the second gate G2 are insulated from each other. The first source S1 and the second drain D2 may be coupled or uncoupled.

[0182] The ESD protection circuit 20 includes a control circuit 30 and a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0183] In some embodiments, the control circuit 30 includes a first common circuit 35, a first node N1, a second node N2, a first branch circuit 31, and a second branch circuit 32. The structures of the first common circuit 35, the first branch circuit 31, and the second branch circuit 32 can refer to the relevant description in Example 1, which will not be repeated here.

[0184] On this basis, the control circuit 30 further includes a third branch circuit 33 and a fourth branch circuit 34. The third branch circuit 33 is coupled between the first node N1 and the first gate G1, and the fourth branch circuit 34 is coupled between the first node N2 and the second gate G2.

[0185] The first gate G1 and the second gate G2 are isolated from each other by the third branch circuit 33 and the fourth branch circuit 34 , which can also meet the requirement of electrical isolation, and signal crosstalk will not occur between different switch tubes.

[0186] In some embodiments, the structure of the third branch circuit 35 is the same as that of the first branch circuit 31 .

[0187] For example, the structure of the third branch circuit 35 is similar to Fig. 10A , Fig.11 , Fig.12 The structure of the first branch circuit 31 shown in FIG. 1 is the same as that of the first branch circuit 31 shown in FIG. 1 , and reference may be made to the above related description.

[0188] Fig.16A and Fig. 16B A schematic diagram of the topological structure of an ESD protection circuit provided in an embodiment of the present application.

[0189] In other embodiments, Fig.16A and Fig. 16B As shown, the third branch circuit 33 includes at least one fourth diode d4.

[0190] For example, the fourth diode d4 is a conventional diode, the first gate G1 is coupled to the anode of the fourth diode d4 , and the first node N1 is coupled to the cathode of the fourth diode d4 . Fig.16A In the figure, the third branch circuit 33 includes one fourth diode d4 as an example for illustration. When the third branch circuit 33 includes a plurality of fourth diodes d4, the plurality of fourth diodes d4 are coupled in series or in parallel.

[0191] The fourth diode d4 is used as the electrical isolation structure, which has a simple structure, and the fourth diode d4 has a larger equivalent resistance and a smaller leakage current, so that the electrical isolation effect between the first gate G1 and the second gate G2 is better.

[0192] In the semiconductor structure 10 provided in the embodiment of the present application, the first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 are insulated from each other. Then, the control circuit 30 in the ESD protection circuit 20 includes a first common circuit 35, and may further include a common branch circuit 51, which can reduce the area of ​​the ESD protection circuit 20. On this basis, the control circuit 30 also includes a third branch circuit 33 and a fourth branch circuit 34, which are used to achieve electrical isolation between the first gate G1 and the second gate G2. In this way, while reducing the area of ​​the ESD protection circuit 20 and thus reducing the area of ​​the semiconductor structure 10, the electrical isolation between the first switch tube M1 and the second switch tube M2 is not affected.

[0193] Example 3

[0194] The main difference between Example 3 and Example 1 and Example 2 is that the control circuit 30 does not include the first common circuit 35, and the discharge circuit includes the first common part.

[0195] Fig.17 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0196] like Fig.17 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0197] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1 and a first drain D1, the second switch tube M2 includes a second gate G2, a second source S2 and a second drain D2, the first gate G1 is coupled to the second gate G2, and the first source S1 and the second source SS2 are insulated from each other.

[0198] The ESD protection circuit 20 includes a control circuit 30 and a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0199] In some embodiments, the discharge circuit 40 includes a first common portion 45 , a third node N3 , a fourth node N4 , a first branch portion 41 , and a second branch portion 42 .

[0200] The third node N3 is coupled to the first gate G1 and the second gate G2 respectively, the first common portion 45 is coupled between the third node N3 and the fourth node N4, the first branch portion 41 is coupled between the fourth node N4 and the first source S1, and the second branch portion 42 is coupled between the fourth node N4 and the second source S2.

[0201] The third node N3 is directly coupled to the first gate G1 and the second gate G2, and no other device structure is set between the third node N3 and the first gate G1, and no other device structure is set between the third node N3 and the second gate G2. The first common part 45 is coupled between the third node N3 and the fourth node N4, the first branch part 41 is coupled between the fourth node N4 and the first source S1, and the second branch part 42 is coupled between the fourth node N4 and the second source S2. Then, the first common part 45 and the first branch part 41 constitute the first ESD discharge circuit of the first switch tube M1, and the first gate G1-third node N3-first common part 45-fourth node N4-first branch part 41-first source S1 is the flow path of the first ESD control circuit. The first common part 45 and the second branch part 42 constitute the second ESD discharge circuit of the second switch tube M2, and the second gate G2-third node N3-first common part 45-fourth node N4-second branch part 42-second source S2 constitutes the flow path of the second ESD discharge circuit.

[0202] Although the first ESD discharge circuit and the second ESD discharge circuit share the first common part 45, it does not affect the function of the first ESD discharge circuit and the second ESD discharge circuit to discharge static electricity. Functionally speaking, the first ESD discharge circuit and the second ESD discharge circuit can still realize the functions of two independent ESD discharge circuits 40'. That is, the discharge circuit 40 can reduce its own occupied area, but does not affect its own flow capacity.

[0203] In some embodiments, the control circuit 30 is coupled to the first common part 45 of the discharge circuit 40 to provide a control signal to the discharge circuit 40. The control circuit 30 is also coupled to the first gate G1 and the first source S1 to form a first control circuit path to determine whether to send a control signal to the discharge circuit 40 to achieve ESD protection for the first switch tube M1. The discharge circuit 40 is also coupled to the second gate G2 and the second source S2 to form a second control circuit path to determine whether to send a control signal to the discharge circuit 40 to achieve ESD protection for the second switch tube M2.

[0204] For example, the control circuit 30 includes a first ESD control circuit 38 and a second ESD control circuit 39. The first ESD control circuit 38 is coupled between the first gate G1 and the first source S1. The first ESD control circuit 38 is also coupled to the first common part 45, and is used to send a control signal 1 to the first common part 45. The first ESD control circuit 38 is a first control signal path. The second ESD control circuit 39 is coupled between the second gate G2 and the second source S2. The second ESD control circuit 39 is also coupled to the first common part 45, and is used to send a control signal 2 to the first common part 45. The second ESD control circuit 39 is a second control signal path.

[0205] Based on this, in the semiconductor structure 10 provided in the embodiment of the present application, the first common part 45 and the first branch part 41 constitute the first ESD discharge circuit of the first switch tube M1, the first common part 45 and the second branch part 42 constitute the second ESD discharge circuit of the second switch tube M2, the first ESD discharge circuit and the first control signal path constitute the ESD protection unit 20' of the first switch tube M1, and the second ESD discharge circuit and the second control signal path constitute the ESD protection unit 20' of the second switch tube M2. It is equivalent to that the ESD protection circuit 20 in the semiconductor structure 10 can realize the functions that can be realized by two ESD protection units 20', but the structure corresponding to the first common part 45 is reduced by one compared with the two ESD protection units 20'. If the semiconductor structure 10 includes n second switch tubes M2, the ESD protection circuit 20 can realize the functions that can be realized by n+1 ESD protection units 20', but the structure corresponding to the first common part 45 is reduced by n compared with the n+1 ESD protection units 20'. Therefore, the area of ​​the ESD protection circuit 20 can be reduced to reduce the cost of the semiconductor structure 10 and facilitate the miniaturization of the semiconductor structure 10. Through simulation verification, it is found that under the premise of the same effect, the area of ​​the ESD protection circuit 20 in the embodiment of the present application can be reduced by about 10%-30% compared with the area of ​​the ESD protection circuit composed of two ESD protection units 20', and the area of ​​the semiconductor structure 10 can be reduced by about 5%. Moreover, the discharge circuit 40 also includes a first branch part 41 and a second branch part 42. The first source S1 and the second source S2 are isolated by the first branch part 41 and the second branch part 42, which can also meet the requirements of electrical isolation, and no signal crosstalk will occur between different switch tubes.

[0206] Fig.18 A schematic diagram of a discharge circuit provided in an embodiment of the present application is shown in FIG. Fig.19 A schematic diagram of the topological structure of an ESD protection circuit provided in an embodiment of the present application.

[0207] In some embodiments, Fig.18As shown, the first common portion 45 includes a third gate G3 and a third drain D3, the first branch portion 41 includes a plurality of third sources S3, and the second branch portion 42 includes a plurality of fourth sources S4.

[0208] Along the direction parallel to the third drain D3 (first direction X), multiple third sources S3 and multiple fourth sources S4 are arranged alternately, multiple third sources S3 are coupled to each other, and multiple fourth sources S4 are coupled to each other. An isolation portion is provided between adjacent third sources S3 and fourth sources S4 to achieve electrical isolation of the third source S3 and the fourth source S4. Along the first direction X, the widths of the multiple third sources S3 may be equal, the widths of the multiple third sources S3 may not be completely equal, and the widths of the multiple third sources S3 may not be completely equal. Similarly, along the first direction X, the widths of the multiple fourth sources S4 may be equal, the widths of the multiple fourth sources S4 may not be completely equal, and the widths of the multiple fourth sources S4 may not be completely equal. In addition, along the first direction X, the widths of the third source S3 and the fourth source S4 may be equal or unequal.

[0209] like Fig.19 As shown, the third source S3 is coupled to the first source S1, the fourth source S4 is coupled to the second source S2, the third gate G3 is coupled to the second node N2, and the third drain D3 is coupled to the third node N3.

[0210] The discharge circuit 40 adopts a structure of a shared third drain D3, a shared third gate G3, a plurality of third sources S3 and a plurality of fourth sources S4. The third source S3, the third drain D3 and the third gate G3 constitute a first discharge transistor T1, and the fourth source S4, the third drain D3 and the third gate G3 constitute a second discharge transistor T2. Since the first discharge transistor T1 and the second discharge transistor T2 can share the gate resistance under the third gate G3, the resistance of the drift region (the region between the third gate G and the third drain D3) and the contact resistance of the third drain D3, even if the width of the third source S3 of the first discharge transistor T1 and the width of the fourth source S4 of the second discharge transistor T2 are reduced, the existence of sharing can increase the flow density between the third source S3 and the third drain D3 and the flow density between the fourth source S4 and the fourth drain D4. Thus, it is possible to reduce the equivalent area of ​​the first discharge transistor T1 and the second discharge transistor T2 by sharing the third drain D3 and the third gate G3 while keeping the current capacity of the first discharge transistor T1 and the second discharge transistor T2 unchanged, so as to reduce the area of ​​the discharge circuit 40. That is to say, the discharge circuit 40 in the present application can be equivalent to the functions of the first discharge transistor T1 and the second discharge transistor T2, but is smaller than the sum of the areas of the first discharge transistor T1 and the second discharge transistor T2. For example, the area of ​​a discharge transistor is 0.2-0.3mm 2, the area of ​​the discharge circuit 40 is 0.4mm 2 When , the function of two discharge transistors can be realized.

[0211] Example 4

[0212] The main difference between Example 4 and Example 3 is that the first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 are insulated from each other.

[0213] Fig. 20 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0214] like Fig. 20 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0215] In some embodiments, the first switch transistor M1 includes a first gate G1, a first source S1 and a first drain D1, and the second switch transistor M2 includes a second gate G2, a second source S2 and a second drain D2. The first gate G1 and the second gate G2 are insulated from each other.

[0216] The ESD protection circuit 20 includes a control circuit 30 and a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0217] In some embodiments, the discharge circuit 40 includes a first common portion 45, a third node N3, a fourth node N4, a first branch portion 41, and a second branch portion 42. The structures of the first common portion 45, the first branch portion 41, and the second branch portion 42 can refer to the relevant description in Example 3, which will not be repeated here.

[0218] On this basis, the discharge circuit 40 further includes a third branch portion 43 and a fourth branch portion 44. The third branch portion 43 is coupled between the third node N3 and the first gate G1, and the fourth branch portion 44 is coupled between the third node N3 and the second gate G2.

[0219] The first gate G1 and the second gate G2 are isolated from each other by the third branch portion 43 and the fourth branch portion 44 , which can also meet the requirement of electrical isolation, and signal crosstalk will not occur between different switch tubes.

[0220] In the semiconductor structure 10 provided in the embodiment of the present application, the first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 are insulated from each other. Then, the discharge circuit 40 in the ESD protection circuit 20 includes a first common part 45, which can reduce the area of ​​the ESD protection circuit 20. On this basis, the discharge circuit 40 also includes a third branch part 43 and a fourth branch part 44, which are used to achieve electrical isolation between the first gate G1 and the second gate G2. In this way, while reducing the area of ​​the ESD protection circuit 20 and thus reducing the area of ​​the semiconductor structure 10, the electrical isolation between the first switch tube M1 and the second switch tube M2 is not affected.

[0221] Example 5

[0222] In Example 5, the first gate G1 and the second gate G2 are coupled, the control circuit 30 includes a first common circuit 35 , and the discharge circuit includes a first common part 45 .

[0223] Fig.21 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0224] like Fig.21 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0225] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1 and a first drain D1, the second switch tube M2 includes a second gate G2, a second source S2 and a second drain D2, the first gate G1 is coupled to the second gate G2, and the first source S1 and the second source SS2 are insulated from each other.

[0226] The ESD protection circuit 20 includes a control circuit 30 and a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0227] In some embodiments, the control circuit 30 includes a first common circuit 35, a first node N1, a second node N2, a first branch circuit 31 and a second branch circuit 32. For the structure of the control circuit 30, reference may be made to the related description of Example 1, which will not be repeated here.

[0228] The discharge circuit 40 includes a first common part 45, a third node N3, a fourth node N4, a first branch part 41, and a second branch part 42. The second node N2 is coupled to the first branch part 41 and the second branch part 42. For the structure of the discharge circuit 40, reference may be made to the relevant description of Example 3, which will not be repeated here.

[0229] In the semiconductor structure 10 provided in the embodiment of the present application, the first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 are coupled. Then, the control circuit 30 in the ESD protection circuit 20 includes a first common circuit 35, and the discharge circuit 40 includes a first common part 45, which can reduce the area of ​​the ESD protection circuit 20. On this basis, the control circuit also includes a first branch circuit 31 and a second branch circuit 32, and the discharge circuit 40 also includes a first branch part 41 and a second branch part 42, which are used to achieve electrical isolation of the first source S1 and the second source S2. In this way, while reducing the area of ​​the ESD protection circuit 20 (for example, it can be reduced by 10%-50%), thereby reducing the area of ​​the semiconductor structure 10 (for example, it can be reduced by 5%-20%), the electrical isolation of the first switch tube M1 and the second switch tube M2 is not affected.

[0230] Example 6

[0231] In Example 6, the first gate G1 and the second gate G2 are insulated from each other, the control circuit 30 includes a first common circuit 35 , and the discharge circuit includes a first common part 45 .

[0232] Fig. 22 A schematic diagram of a topological structure of a semiconductor structure provided in an embodiment of the present application.

[0233] like Fig. 22 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0234] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1 and a first drain D1, the second switch tube M2 includes a second gate G2, a second source S2 and a second drain D2, and the first gate G1 and the second gate G2 are insulated from each other.

[0235] The ESD protection circuit 20 includes a control circuit 30 and a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0236] In some embodiments, the control circuit 30 includes a first common circuit 35, a first node N1, a second node N2, a first branch circuit 31, a second branch circuit 32, a third branch circuit 33, and a fourth branch circuit 34. For the structure of the control circuit 30, reference may be made to the relevant description of Example 2, which will not be repeated here.

[0237] The discharge circuit 40 includes a first common part 45, a third node N3, a fourth node N4, a first branch part 41, a second branch part 42, a third branch part 43 and a fourth branch part 44. For the structure of the discharge circuit 40, reference may be made to the relevant description of Example 4, which will not be repeated here.

[0238] In the semiconductor structure 10 provided in the embodiment of the present application, the first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 are insulated from each other. Then, the control circuit 30 in the ESD protection circuit 20 includes a first common circuit 35, and the discharge circuit 40 includes a first common part 45, which can reduce the area of ​​the ESD protection circuit 20. On this basis, the control circuit also includes a third branch circuit 33 and a fourth branch circuit 34, and the discharge circuit 40 also includes a third branch part 43 and a fourth branch part 44, which are used to achieve electrical isolation between the first gate G1 and the second gate G2. In this way, while reducing the area of ​​the ESD protection circuit 20 and thus reducing the area of ​​the semiconductor structure 10, the electrical isolation between the first switch tube M1 and the second switch tube M2 is not affected.

[0239] Example 7

[0240] The main difference between Example 7 and Examples 1 to 6 is that the ESD protection circuit 20 does not include the control circuit 30 but only includes the discharge circuit 40 .

[0241] Fig.23 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0242] like Fig.23 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0243] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1 and a first drain D1, the second switch tube M2 includes a second gate G2, a second source S2 and a second drain D2, the first gate G1 is coupled to the second gate G2, and the first source S1 and the second source SS2 are insulated from each other.

[0244] The ESD protection circuit 20 includes a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0245] In some embodiments, the discharge circuit 40 includes a first common portion 45 , a third node N3 , a fourth node N4 , a first branch portion 41 , and a second branch portion 42 .

[0246] The third node N3 is coupled to the first gate G1 and the second gate G2 respectively, the first common portion 45 is coupled between the third node N3 and the fourth node N4, the first branch portion 41 is coupled between the fourth node N4 and the first source S1, and the second branch portion 42 is coupled between the fourth node N4 and the second source S2.

[0247] In some embodiments, the third node N3 is directly coupled to the first gate G1 and the second gate G2, and no other device structure is provided between the third node N3 and the first gate G1, and no other device structure is provided between the third node N3 and the second gate G2. The first common portion 45 is coupled between the third node N3 and the fourth node N4, the first branch portion 41 is coupled between the fourth node N4 and the first source S1, and the second branch portion 42 is coupled between the fourth node N4 and the second source S2.

[0248] Then, the first common part 45 and the first branch part 41 constitute the first ESD discharge circuit of the first switch tube M1, and the first gate G1-third node N3-first common part 45-fourth node N4-first branch part 41-first source S1 is the flow path of the first ESD control circuit. The first common part 45 and the second branch part 42 constitute the second ESD discharge circuit of the second switch tube M2, and the second gate G2-third node N3-first common part 45-fourth node N4-second branch part 42-second source S2 constitutes the flow path of the second ESD discharge circuit.

[0249] Although the first ESD discharge circuit and the second ESD discharge circuit share the first common part 45, it does not affect the functions of the first ESD discharge circuit and the second ESD discharge circuit. Functionally speaking, the first ESD discharge circuit and the second ESD discharge circuit can still realize the functions of two independent ESD protection units 20'.

[0250] Fig.24 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0251] In some embodiments, Fig.24 As shown, the first common part 45 includes at least one fifth diode d5. For example, the fifth diode d5 is a conventional diode, the third node N3 is coupled to the anode of the fifth diode d5, and the fourth node N4 is coupled to the cathode of the fifth diode d5.

[0252] For example, the first common part 45 includes a plurality of fifth diodes d5, and the plurality of fifth diodes d5 are arranged in an array of i rows and j columns, where i and j are integers greater than 0. For example, the value of i is 1-10, and the value of j is 1-10.

[0253] The first branch portion 41 includes at least one sixth diode d6 . For example, the sixth diode d6 is a conventional diode. The fourth node N4 is coupled to an anode of the sixth diode d6 . The first source S1 is coupled to a cathode of the sixth diode d6 .

[0254] In some embodiments, the number j of columns of the fifth diodes d5 included in the first common portion 45 is the same as the number j of columns of the sixth diodes d6 included in the first branch portion 41 . Fig.24 In the figure, the first branch portion 41 includes a row of sixth diodes d6 as an example for illustration.

[0255] By making the number j of columns of the fifth diodes d5 included in the first common part 45 and the number j of columns of the sixth diodes d6 included in the first branch part 41 the same, the first common part 45 and the first branch part 45 can have the same flow capacity, avoiding waste of diodes on the column.

[0256] In some embodiments, the structure of the first branch portion 41 is the same as the structure of the second branch portion 42 .

[0257] For example, in the embodiment of the present application, the first common part 45 includes i*j diodes, and the first branch part 41 includes 1*j diodes. The second branch part 42 includes 1*j diodes. A total of (i+2)*j diodes are required. Compared with one ESD discharge circuit 40′ including (i+1)*j diodes and two sets of ESD discharge circuits 40′ requiring 2*(i+1)*j diodes, the number of diodes in the discharge circuit 40 in the present application can be reduced by i*j, and the benefit area ratio is i / 2(i+1).

[0258] Based on this, in the semiconductor structure 10 provided in the embodiment of the present application, the first common part 45 and the first branch part 41 constitute the first ESD discharge circuit of the first switch tube M1, the first common part 45 and the second branch part 42 constitute the second ESD discharge circuit of the second switch tube M2, the first ESD discharge circuit constitutes the ESD protection unit 20' of the first switch tube M1, and the second ESD discharge circuit constitutes the ESD protection unit 20' of the second switch tube M2. It is equivalent to that the ESD protection circuit 20 in the semiconductor structure 10 can realize the functions that can be realized by two ESD protection units 20', but it has one less structure corresponding to the first common part 45 than the two ESD protection units 20'. If the semiconductor structure 10 includes n second switch tubes M2, the ESD protection circuit 20 can realize the functions that can be realized by n+1 ESD protection units 20', but it has n less structures corresponding to the first common part 45 than the n+1 ESD protection units 20'. Therefore, the area of ​​the ESD protection circuit 20 can be reduced to reduce the cost of the semiconductor structure 10 and facilitate the miniaturization of the semiconductor structure 10. Moreover, the discharge circuit 40 also includes a first branch part 41 and a second branch part 42. The first source S1 and the second source S2 are isolated by the first branch part 41 and the second branch part 42, which can also meet the electrical isolation requirements, and no signal crosstalk occurs between different switch tubes.

[0259] Example 8

[0260] The main difference between Example 8 and Example 7 is that the first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 are insulated from each other.

[0261] Fig.25 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0262] like Fig.25 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0263] In some embodiments, the first switch transistor M1 includes a first gate G1, a first source S1 and a first drain D1, and the second switch transistor M2 includes a second gate G2, a second source S2 and a second drain D2. The first gate G1 and the second gate G2 are insulated from each other.

[0264] The ESD protection circuit 20 includes a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0265] In some embodiments, the discharge circuit 40 includes a first common portion 45, a third node N3, a fourth node N4, a first branch portion 41, and a second branch portion 42. The structures of the first common portion 45, the first branch portion 41, and the second branch portion 42 can refer to the relevant description in Example 7, which will not be repeated here.

[0266] On this basis, the discharge circuit 40 further includes a third branch portion 43 and a fourth branch portion 44. The third branch portion 43 is coupled between the third node N3 and the first gate G1, and the fourth branch portion 44 is coupled between the third node N3 and the second gate G2.

[0267] The first gate G1 and the second gate G2 are isolated from each other by the third branch portion 43 and the fourth branch portion 44 , which can also meet the requirement of electrical isolation, and signal crosstalk will not occur between different switch tubes.

[0268] Fig.26 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0269] In some embodiments, Fig.26 As shown, the third branch portion 43 includes at least one seventh diode d7. For example, the seventh diode d7 is a conventional diode, an anode of the seventh diode d7 is coupled to the first gate G1, and a cathode of the seventh diode d7 is coupled to the third node N3.

[0270] In some embodiments, the structure of the third branch portion 43 is the same as the structure of the fourth branch portion 44 .

[0271] For example, in the embodiment of the present application, the first common part 45 includes i*j diodes, and the first branch part 41 includes 1*j diodes. The second branch part 42 includes 1*j diodes, and the third branch part 43 includes 1*j diodes. The fourth branch part 44 includes 1*j diodes. A total of (i+4)*j diodes are required. Compared with one ESD discharge circuit 40′ including (i+2)*j diodes and two sets of ESD discharge circuits 40′ requiring 2*(i+2)*j diodes, the number of diodes in the discharge circuit 40 in the present application can be reduced by i*j, and the benefit area ratio is i / 2(i+1).

[0272] In the semiconductor structure 10 provided in the embodiment of the present application, the first gate G1 of the first switch tube M1 and the second gate G2 of the second switch tube M2 are insulated from each other. Then, the discharge circuit 40 in the ESD protection circuit 20 includes a first common part 45, which can reduce the area of ​​the ESD protection circuit 20. On this basis, the discharge circuit 40 also includes a third branch part 43 and a fourth branch part 44, which are used to achieve electrical isolation between the first gate G1 and the second gate G2. In this way, while reducing the area of ​​the ESD protection circuit 20 and thus reducing the area of ​​the semiconductor structure 10, the electrical isolation between the first switch tube M1 and the second switch tube M2 is not affected.

[0273] Example 9

[0274] The main difference between Example 9 and Examples 1 to 8 is that the first switch tube M1 and the first source S1 are coupled to the second source S2 of the second switch tube M2.

[0275] Fig. 27 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0276] like Fig. 27 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0277] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1, and a first drain D1, and the second switch tube M2 includes a second gate G2, a second source S2, and a second drain D2. The first gate G1 and the second gate G2 are insulated from each other, and the first source S1 and the second source S2 are coupled. The first source S1 and the second source S2 can be coupled through a signal line, and the first source S1 and the second source S2 can also be an integrated structure.

[0278] The ESD protection circuit 20 includes a control circuit 30 and a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0279] In some embodiments, the control circuit 30 includes a second common circuit 35 ′, a fifth node N5 , a sixth node N6 , a fifth branch circuit 37 , and a sixth branch circuit 36 ​​.

[0280] The fifth node N5 is coupled to the first source S1 and the second source S2 respectively, the second common circuit 35′ is coupled between the fifth node N5 and the sixth node N6, the fifth branch circuit 37 is coupled between the sixth node N6 and the first gate G1, and the sixth branch circuit 36 ​​is coupled between the sixth node N6 and the second gate G2.

[0281] Then, the second common circuit 35' and the fifth branch circuit 37 constitute the first ESD control circuit of the first switch tube M1, and the first gate G1-fifth branch circuit 37-sixth node N6-second common circuit 35'-fifth node N5-first source S1 is the flow path of the first ESD control circuit. The second common circuit 35' and the sixth branch circuit 36 ​​constitute the second ESD control circuit of the second switch tube M2, and the second gate G2-sixth branch circuit 36-sixth node N6-second common circuit 35'-fifth node N5-second source S2 constitutes the flow path of the second ESD control circuit.

[0282] Although the first ESD control circuit and the second ESD control circuit share the second common circuit 35', it does not affect the function of the first ESD control circuit and the second ESD control circuit to output control signals to the discharge circuit 40. Functionally speaking, the first ESD control circuit and the second ESD control circuit can still realize the functions of two independent ESD control circuits 30'. That is, when static electricity exists between the first gate G1 and the first source S1 of the first switch tube M1, and / or when static electricity exists between the second gate G2 and the second source S2 of the second switch tube M2, the control circuit 30 can output a discharge control signal to the discharge circuit 40 to quickly discharge static electricity.

[0283] In some embodiments, the discharge circuit 40 is coupled to the sixth node N6, and the discharge circuit 40 receives a control signal at the sixth node N6. The discharge circuit 40 is also coupled to the first gate G1 and the first source S1 to form a first discharge path, and the sixth node N6 is used to control whether the first discharge path is turned on or off to achieve ESD protection for the first switch tube M1. The discharge circuit 40 is also coupled to the second gate G2 and the second source S2 to form a second discharge path, and the sixth node N6 is used to control whether the second discharge path is turned on or off to achieve ESD protection for the second switch tube M2.

[0284] For example, the discharge circuit 40 includes a first ESD discharge circuit 48 and a second ESD discharge circuit 49. The first ESD discharge circuit 48 is coupled between the first gate G1 and the first source S1. The first ESD discharge circuit 48 is also coupled to the sixth node N6, and is used to receive the control signal 1 output from the sixth node N6. The first ESD discharge circuit 48 is a first discharge path. The second ESD discharge circuit 49 is coupled between the second gate G2 and the second source S2. The second ESD discharge circuit 49 is also coupled to the sixth node N6, and is used to receive the control signal 2 output from the second node N2. The second ESD discharge circuit 49 is a second discharge path.

[0285] In some embodiments, the fifth node N5 is directly coupled to the first source S1 and the second source S2 .

[0286] Figure 28A-Figure 30 A schematic diagram of the topological structure of an ESD protection circuit provided in an embodiment of the present application.

[0287] like Fig.28A As shown, in some embodiments, the first ESD discharge circuit 48 includes a first discharge transistor T1, a control electrode of the first discharge transistor T1 is coupled to the sixth node N6 for receiving a control signal 1, a first electrode of the first discharge transistor T1 is coupled to the first gate G1, and a second electrode of the first discharge transistor T1 is coupled to the first source S1.

[0288] In some embodiments, the second ESD discharge circuit 49 includes a second discharge transistor T2, a control electrode of the second discharge transistor T2 is coupled to the sixth node N6 for receiving the control signal 2, a first electrode of the second discharge transistor T2 is coupled to the second gate G2, and a second electrode of the second discharge transistor T2 is coupled to the second source S2.

[0289] like Fig.28A As shown, in some embodiments, the fifth branch circuit 37 includes at least one eighth diode d8, and the at least one eighth diode d8 is coupled between the first gate G1 and the sixth node N6. For example, the eighth diode d8 is a conventional diode, the first gate G1 is coupled to the anode of the eighth diode d8, and the sixth node N6 is coupled to the cathode of the eighth diode d8. In the case where the fifth branch circuit 37 includes a plurality of eighth diodes d8, the plurality of eighth diodes d8 can be coupled in series and / or in parallel.

[0290] like Fig.28B As shown, in some embodiments, the control circuit 30 further includes a second common branch circuit 52 , one end of the second common branch circuit 52 is coupled to the sixth node N6 , and the other end of the second common branch circuit 52 is coupled to the fifth branch circuit 37 and the sixth branch circuit 36 ​​.

[0291] Illustratively, the second common branch circuit 52 includes at least a thirteenth diode d13, and the fifth branch circuit 37 and the sixth branch circuit 36 ​​include at least an eighth diode d8.

[0292] For example, Fig.28B The sum of the number of the thirteenth diodes d13 in the second common branch circuit 52 and the number of the eighth diodes d8 in the fifth branch circuit 37 is equal to Fig.28A The number of the eighth diodes d8 in the fifth branch circuit 37 is equal. Similarly, Fig.28B The sum of the number of the thirteenth diodes d13 in the second common branch circuit 52 and the number of the eighth diodes d8 in the sixth branch circuit 36 ​​is equal to Fig.28A The number of the eighth diodes d8 in the sixth branch circuit 36 ​​is equal. Then, Fig.28A The effect of the semiconductor structure 10 is similar to Fig.28B The effect of the semiconductor structure shown is equivalent, but Fig.28B The semiconductor structure 10 shown is Fig.28A The semiconductor structure 10 shown does not include the thirteenth diode d13 in the fifth branch circuit 37 , which can further reduce the occupied area of ​​the ESD protection circuit 20 .

[0293] In some embodiments, the second sharing circuit 35 ′ includes a seventh resistor R7 coupled between the sixth node N6 and the fifth node N5 .

[0294] like Fig.29 As shown, in some other embodiments, the second common circuit 35 ′ includes an eighth resistor R8 and a ninth diode d9 coupled in parallel.

[0295] like Fig.30 As shown, in some embodiments, the fifth branch circuit 37 includes a sixth resistor R6 and a third capacitor C3 coupled in parallel. The second common circuit 35' includes a ninth resistor R9 and a fourth capacitor C4 coupled in parallel.

[0296] Of course, any of the fifth branch circuits 37 and the second common circuit 35 ′ mentioned above can be combined arbitrarily, and the embodiment of the present application is only an illustration.

[0297] In some embodiments, the structure of the fifth branch circuit 37 is the same as that of the first common circuit 35 in Example 1, and the above description may be referred to. For example, the structure of the second common circuit 35' may be the same as that of the first branch circuit 31 in Example 1, and the above description may be referred to.

[0298] In some embodiments, the structure of the fifth branch circuit 37 is the same as that of the sixth branch circuit 36 ​​, and will not be described in detail herein.

[0299] In the semiconductor structure 10 provided in the embodiment of the present application, the second common circuit 35′ and the fifth branch circuit 37 constitute the first ESD control circuit of the first switch tube M1, the second common circuit 35′ and the sixth branch circuit 36 ​​constitute the second ESD control circuit of the second switch tube M2, the first ESD control circuit and the first discharge path constitute the ESD protection unit 20′ of the first switch tube M1, and the second ESD control circuit and the second discharge path constitute the ESD protection unit 20′ of the second switch tube M2. It is equivalent to that the ESD protection circuit 20 in the semiconductor structure 10 can realize the functions that can be realized by two ESD protection units 20′, but the structure corresponding to the second common circuit 35′ is reduced by one compared with the two ESD protection units 20′. If the semiconductor structure 10 includes n second switch tubes M2, the ESD protection circuit 20 can realize the functions that can be realized by n+1 ESD protection units 20′, but the structure corresponding to the second common circuit 35′ is reduced by n compared with the n+1 ESD protection units 20′. Therefore, the area of ​​the ESD protection circuit 20 can be reduced to reduce the cost of the semiconductor structure 10 and facilitate miniaturization of the semiconductor structure 10 .

[0300] Example 10

[0301] The main difference between Example 10 and Example 9 is that the control circuit 30 does not include the second common circuit 35 ′, and the discharge circuit includes the second common part.

[0302] Fig.31 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0303] like Fig.31 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0304] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1 and a first drain D1, the second switch tube M2 includes a second gate G2, a second source S2 and a second drain D2, the first source S1 is coupled to the second source S2, and the first gate G1 and the second gate G2 are insulated from each other.

[0305] The ESD protection circuit 20 includes a control circuit 30 and a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0306] In some embodiments, the bleeder circuit 40 includes a second common portion 45 ′, a seventh node N7 , an eighth node N8 , a fifth branch portion 47 , and a sixth branch portion 46 .

[0307] The fifth branch portion 47 is coupled to the first gate G1 and the eighth node N8, respectively. The sixth branch portion 46 is coupled to the second gate G2 and the eighth node N8, respectively. The seventh node N7 is coupled to the first source S1 and the second source S2, respectively. The second common portion 45' is coupled between the seventh node N7 and the eighth node N8.

[0308] The seventh node N7 is directly coupled to the first source S1 and the second source S2, and no other device structure is set between the seventh node N7 and the first source S1, and no other device structure is set between the seventh node N7 and the second source S2. The second common portion 45' is coupled between the seventh node N7 and the eighth node N8, the fifth branch portion 47 is coupled between the eighth node N8 and the first gate G1, and the sixth branch portion 46 is coupled between the eighth node N8 and the second gate G2.

[0309] Then, the second common part 45' and the fifth branch part 47 constitute the first ESD discharge circuit of the first switch tube M1, and the first gate G1-fifth branch part 47-eighth node N8-second common part 45'-seventh node N7-first source S1 is the flow path of the first ESD control circuit. The second common part 45' and the sixth branch part 46 constitute the second ESD discharge circuit of the second switch tube M2, and the second gate G2-sixth branch part 46-eighth node N8-second common part 45'-seventh node N7-second source S2 constitutes the flow path of the second ESD discharge circuit.

[0310] Although the first ESD discharge circuit and the second ESD discharge circuit share the second common part 45', it does not affect the function of the first ESD discharge circuit and the second ESD discharge circuit to discharge static electricity. Functionally speaking, the first ESD discharge circuit and the second ESD discharge circuit can still realize the functions of two independent ESD discharge circuits 40'. That is, the discharge circuit 40 can reduce its own occupied area, but does not affect its own flow capacity.

[0311] In some embodiments, the control circuit 30 is coupled to the fifth branch portion 47 and the sixth branch portion 46 of the discharge circuit 40 to provide a control signal to the discharge circuit 40. The control circuit 30 is also coupled to the first gate G1 and the first source S1 to form a first control circuit path to determine whether to send a control signal to the fifth branch portion 47 to achieve ESD protection for the first switch tube M1. The discharge circuit 40 is also coupled to the second gate G2 and the second source S2 to form a second control circuit path to determine whether to send a control signal to the sixth branch portion 46 to achieve ESD protection for the second switch tube M2.

[0312] For example, the control circuit 30 includes a first ESD control circuit 38 and a second ESD control circuit 39. The first ESD control circuit 38 is coupled between the first gate G1 and the first source S1. The first ESD control circuit 38 is also coupled to the fifth branch portion 47, and is used to send a control signal 1 to the fifth branch portion 47. The first ESD control circuit 38 is a first control signal path. The second ESD control circuit 39 is coupled between the second gate G2 and the second source S2. The second ESD control circuit 39 is also coupled to the sixth branch portion 46, and is used to send a control signal 2 to the sixth branch portion 46. The second ESD control circuit 39 is a second control signal path.

[0313] Based on this, in the semiconductor structure 10 provided in the embodiment of the present application, the second common part 45' and the fifth branch part 47 constitute the first ESD discharge circuit of the first switch tube M1, the second common part 45' and the sixth branch part 46 constitute the second ESD discharge circuit of the second switch tube M2, the first ESD discharge circuit and the first control signal path constitute the ESD protection unit 20' of the first switch tube M1, and the second ESD discharge circuit and the second control signal path constitute the ESD protection unit 20' of the second switch tube M2. It is equivalent to that the ESD protection circuit 20 in the semiconductor structure 10 can realize the functions that can be realized by two ESD protection units 20', but the structure corresponding to the second common part 45' is reduced by one compared with the two ESD protection units 20'. If the semiconductor structure 10 includes n second switch tubes M2, the ESD protection circuit 20 can realize the functions that can be realized by n+1 ESD protection units 20', but the structure corresponding to the second common part 45' is reduced by n compared with the n+1 ESD protection units 20'. Therefore, the area of ​​the ESD protection circuit 20 can be reduced to reduce the cost of the semiconductor structure 10 and facilitate miniaturization of the semiconductor structure 10 .

[0314] Example 11

[0315] In Example 11, the first gate G1 and the second gate G2 are insulated from each other, the first source S1 and the second source S2 are coupled, the control circuit 30 includes a second common circuit 35 ′, and the discharge circuit includes a second common part 45 ′.

[0316] Fig.32 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0317] like Fig.32 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0318] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1 and a first drain D1, the second switch tube M2 includes a second gate G2, a second source S2 and a second drain D2, the first source S1 is coupled to the second source S2, and the first gate G1 and the second gate G2 are insulated from each other.

[0319] In some embodiments, the control circuit 30 includes a second common circuit 35', a fifth node N5, a sixth node N6, a fifth branch circuit 37 and a sixth branch circuit 36. For the structure of the control circuit 30, reference may be made to the description of Example 9, which will not be repeated here.

[0320] The discharge circuit 40 includes a second common part 45', a seventh node N7, an eighth node N8, a fifth branch part 47 and a sixth branch part 46. The sixth node N6 is respectively coupled to the fifth branch part 47 and the sixth branch part 46. For the structure of the discharge circuit 40, reference may be made to the relevant description of Example 10, which will not be repeated here.

[0321] In the semiconductor structure 10 provided in the embodiment of the present application, the first source S1 of the first switch tube M1 and the second source S2 of the second switch tube M2 are coupled. Then, the control circuit 30 in the ESD protection circuit 20 includes a second common circuit 35', and the discharge circuit 40 includes a second common part 45', which can reduce the area of ​​the ESD protection circuit 20. On this basis, the control circuit 30 also includes a fifth branch circuit 37 and a sixth branch circuit 36, and the discharge circuit 40 also includes a fifth branch part 47 and a sixth branch part 46, which are used to achieve electrical isolation between the first gate G1 and the second gate G2. In this way, while reducing the area of ​​the ESD protection circuit 20 (for example, it can be reduced by 10%-50%), thereby reducing the area of ​​the semiconductor structure 10 (for example, it can be reduced by 5%-20%), the electrical isolation between the first switch tube M1 and the second switch tube M2 is not affected.

[0322] Example 12

[0323] The main difference between Example 12 and Examples 9 to 11 is that the ESD protection circuit 20 does not include the control circuit 30 but only includes the discharge circuit 40 .

[0324] Fig.33 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0325] like Fig.33 As shown, an embodiment of the present application provides a semiconductor structure 10 , which includes a first switch tube M1 , a second switch tube M2 , and an ESD protection circuit 20 .

[0326] In some embodiments, the first switch tube M1 includes a first gate G1, a first source S1 and a first drain D1, the second switch tube M2 includes a second gate G2, a second source S2 and a second drain D2, the first source S1 is coupled to the second source S2, and the first gate G1 and the second gate G2 are insulated from each other.

[0327] The ESD protection circuit 20 includes a discharge circuit 40 . The ESD protection circuit 20 can implement ESD protection between the first gate G1 and the first source S1 . Meanwhile, the ESD protection circuit 20 can also implement ESD protection between the second gate G2 and the second source S2 .

[0328] In some embodiments, the bleeder circuit 40 includes a second common portion 45 ′, a seventh node N7 , an eighth node N8 , a fifth branch portion 47 , and a sixth branch portion 46 .

[0329] The fifth branch portion 47 is coupled to the first gate G1 and the eighth node N8, respectively. The sixth branch portion 46 is coupled to the second gate G2 and the eighth node N8, respectively. The seventh node N7 is coupled to the first source S1 and the second source S2, respectively. The second common portion 45' is coupled between the seventh node N7 and the eighth node N8.

[0330] In some embodiments, the seventh node N7 is directly coupled to the first source S1 and the second source S2, and no other device structure is disposed between the seventh node N7 and the first source S1, and no other device structure is disposed between the seventh node N7 and the second source S2.

[0331] Then, the second common part 45' and the fifth branch part 47 constitute the first ESD discharge circuit of the first switch tube M1, and the first gate G1-fifth branch part 47-eighth node N8-second common part 45'-seventh node N7-first source S1 is the flow path of the first ESD control circuit. The second common part 45' and the sixth branch part 46 constitute the second ESD discharge circuit of the second switch tube M2, and the second gate G2-sixth branch part 46-eighth node N8-second common part 45'-seventh node N7-second source S2 constitutes the flow path of the second ESD discharge circuit.

[0332] Although the first ESD discharge circuit and the second ESD discharge circuit share the second common part 45', it does not affect the functions of the first ESD discharge circuit and the second ESD discharge circuit. Functionally speaking, the first ESD discharge circuit and the second ESD discharge circuit can still realize the functions of two independent ESD protection units 20'.

[0333] Fig.34 A schematic diagram of the topological structure of a semiconductor structure provided in an embodiment of the present application.

[0334] In some embodiments, Fig.34 As shown, in some embodiments, the second common portion 45' includes at least one tenth diode d12. For example, the tenth diode d12 is a conventional diode, the eighth node N8 is coupled to the anode of the tenth diode d12, and the seventh node N7 is coupled to the cathode of the tenth diode d12.

[0335] For example, the second common part 45 ′ includes a plurality of twelfth diodes d12 , and the plurality of twelfth diodes d12 are arranged in an array of i rows and j columns, where i and j are integers greater than 0. For example, the value of i is 1-10, and the value of j is 1-10.

[0336] In some embodiments, the fifth branch portion 47 includes at least one eleventh diode d11. For example, the eleventh diode d11 is a conventional diode, the first gate G1 is coupled to the anode of the eleventh diode d11, and the eighth node N8 is coupled to the cathode of the eleventh diode d11.

[0337] In some embodiments, the number j of columns of the tenth diodes d12 included in the second common portion 45 ′ is the same as the number j of columns of the eleventh diodes d11 included in the fifth branch portion 47 . Fig.34 In the figure, the fifth branch portion 47 including a row of eleventh diodes d11 is taken as an example for illustration.

[0338] By making the number j of columns of the tenth diode d12 included in the second common part 45' the same as the number j of columns of the eleventh diode d11 included in the fifth branch part 47, the second common part 45' and the fifth branch part 47 can have the same flow capacity, avoiding waste of diodes on the column.

[0339] In some embodiments, the structure of the fifth branch portion 47 is the same as the structure of the sixth branch portion 46 , and will not be described again herein.

[0340] Based on this, in the semiconductor structure 10 provided in the embodiment of the present application, the second common part 45' and the fifth branch part 47 constitute the first ESD discharge circuit of the first switch tube M1, the second common part 45' and the sixth branch part 46 constitute the second ESD discharge circuit of the second switch tube M2, the first ESD discharge circuit constitutes the ESD protection unit 20' of the first switch tube M1, and the second ESD discharge circuit constitutes the ESD protection unit 20' of the second switch tube M2. It is equivalent to that the ESD protection circuit 20 in the semiconductor structure 10 can realize the functions that can be realized by two ESD protection units 20', but the structure corresponding to the second common part 45' is reduced by one compared with the two ESD protection units 20'. If the semiconductor structure 10 includes n second switch tubes M2, the ESD protection circuit 20 can realize the functions that can be realized by n+1 ESD protection units 20', but the structure corresponding to the second common part 45' is reduced by n compared with the n+1 ESD protection units 20'. Therefore, the area of ​​the ESD protection circuit 20 can be reduced to reduce the cost of the semiconductor structure 10, which is conducive to miniaturization of the semiconductor structure 10. Moreover, the discharge circuit 40 also includes a fifth branch portion 47 and a sixth branch portion 46, and the first gate G1 and the second gate G2 are isolated by the fifth branch portion 47 and the sixth branch portion 46, which can also meet the requirements of electrical isolation, and signal crosstalk will not occur between different switch tubes.

[0341] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first switch tube, comprising a first gate, a first source and a first drain; A second switch tube comprises a second gate, a second source and a second drain; the first source and the second source are insulated from each other; Electrostatic protection circuit, including control circuit and discharge circuit; The control circuit includes a first common circuit, a first node, a second node, a first branch circuit and a second branch circuit; The first node is coupled to the first gate and the second gate respectively, the first common circuit is coupled between the first node and the second node, the first branch circuit is coupled between the second node and the first source, and the second branch circuit is coupled between the second node and the second source; The discharge circuit is coupled to the second node; the discharge circuit is also coupled to the first gate and the first source to form a first discharge path; the discharge circuit is also coupled to the second gate and the second source to form a second discharge path.

2. The semiconductor structure according to claim 1, characterized in that: The first gate is coupled to the second gate.

3. The semiconductor structure according to claim 1, characterized in that: The first gate and the second gate are insulated from each other, and the control circuit further includes a third branch circuit and a fourth branch circuit; The third branch circuit is coupled between the first node and the first gate, and the fourth branch circuit is coupled between the first node and the second gate.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The control circuit further includes a common branch circuit; the common branch circuit is coupled between the first branch circuit, the second branch circuit and the second node.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The first common circuit includes a first diode.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The first common circuit includes a first capacitor and a first resistor coupled in parallel.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The first branch circuit includes a second resistor.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The first branch circuit includes a third resistor and a second diode, and the third resistor is connected in parallel or in series with the second diode.

9. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The first branch circuit includes a fourth resistor and a second capacitor connected in parallel.

10. The semiconductor structure according to claim 4, characterized in that: The common branch circuit includes a fifth resistor; and the first branch circuit includes a third diode.

11. The semiconductor structure according to any one of claims 3 to 10, characterized in that: The third branch circuit includes a fourth diode.

12. The semiconductor structure according to any one of claims 3 to 10, characterized in that: The structure of the third branch circuit is the same as that of the first branch circuit.

13. The semiconductor structure according to any one of claims 1 to 12, characterized in that: The discharge circuit includes a first common part, a first branch part and a second branch part; the first common part is coupled to the second node, the first gate and the second gate respectively, the first branch part is coupled between the first common part and the first source, and the second branch part is coupled between the first common part and the second source.

14. The semiconductor structure according to claim 13, characterized in that: The discharge circuit further includes a third branch portion and a fourth branch portion; The third branch portion is coupled between the first common portion and the first gate, and the fourth branch portion is coupled between the first common portion and the second gate.

15. The semiconductor structure according to claim 13, characterized in that The first common portion includes a third gate and a third drain, the first branch portion includes a plurality of third sources, and the second branch portion includes a plurality of fourth sources; Along a direction parallel to the third drain, the plurality of third sources and the plurality of fourth sources are arranged alternately; The plurality of third sources are coupled to the first source, the plurality of fourth sources are coupled to the second source, the third gate is coupled to the second node, and the third drain is directly coupled to the first gate and the second gate.

16. The semiconductor structure according to any one of claims 1 to 15, characterized in that: The semiconductor structure also includes an integrated circuit.

17. A semiconductor structure, characterized in that: include: A first switch tube, comprising a first gate, a first source and a first drain; A second switch tube comprises a second gate, a second source and a second drain; the first source and the second source are insulated from each other; Electrostatic protection circuit, including discharge circuit; The discharge circuit includes a first common part, a third node, a fourth node, a first branch part and a second branch part; The third node is coupled to the first gate and the second gate respectively, the first common part is coupled between the third node and the fourth node, the first branch part is coupled between the fourth node and the first source, and the second branch part is coupled between the fourth node and the second source.

18. The semiconductor structure according to claim 17, characterized in that: The first gate and the second gate are insulated from each other, and the discharge circuit further includes a third branch portion and a fourth branch portion; The third branch portion is coupled between the third node and the first gate, and the fourth branch portion is coupled between the third node and the second gate.

19. The semiconductor structure according to claim 17 or 18, characterized in that: The first common portion includes a fifth diode; and the first branch portion includes a sixth diode.

20. The semiconductor structure according to claim 18, characterized in that The third branch portion includes a seventh diode.

21. A semiconductor structure, characterized in that: include: A first switch tube, comprising a first gate, a first source and a first drain; A second switch tube includes a second gate, a second source and a second drain; the first source is coupled to the second source, and the first gate and the second gate are insulated from each other; Electrostatic protection circuit, including control circuit and discharge circuit; The control circuit includes a second common circuit, a fifth node, a sixth node, a fifth branch circuit and a sixth branch circuit; The fifth node is coupled to the first source and the second source respectively, the second common circuit is coupled between the fifth node and the sixth node, the fifth branch circuit is coupled between the sixth node and the first gate, and the sixth branch circuit is coupled between the sixth node and the second gate; The discharge circuit is coupled to the sixth node; the discharge circuit is also coupled to the first gate and the first source to form a first discharge path; the discharge circuit is also coupled to the second gate and the second source to form a second discharge path.

22. The semiconductor structure according to claim 21, characterized in that The fifth branch circuit includes an eighth diode.

23. The semiconductor structure according to claim 21, characterized in that The fifth branch circuit is coupled in parallel to a sixth resistor and a third capacitor.

24. The semiconductor structure according to any one of claims 21 to 23, characterized in that: The second common circuit includes a seventh resistor.

25. The semiconductor structure according to any one of claims 21 to 23, characterized in that: The second common circuit includes an eighth resistor and a ninth diode coupled in parallel.

26. The semiconductor structure according to any one of claims 21 to 23, characterized in that: The second common circuit includes a ninth resistor and a fourth capacitor coupled in parallel.

27. The semiconductor structure according to any one of claims 21 to 26, characterized in that: The discharge circuit includes a second common part, a fifth branch part and a sixth branch part; the fifth branch part is coupled to the sixth node, the first gate and the second common part respectively, and the sixth branch part is coupled to the sixth node, the second gate and the second common part respectively; the second common part is also coupled to the first source and the second source.

28. A semiconductor structure, characterized in that include: A first switch tube, comprising a first gate, a first source and a first drain; A second switch tube includes a second gate, a second source and a second drain; the first source is coupled to the second source, and the first gate and the second gate are insulated from each other; Electrostatic protection circuit, including discharge circuit; The discharge circuit includes a second common portion, a seventh node, an eighth node, a fifth branch portion, and a sixth branch portion; The seventh node is coupled to the first source and the second source respectively, the second common part is coupled between the seventh node and the eighth node, the fifth branch part is coupled between the eighth node and the first gate, and the sixth branch part is coupled between the eighth node and the second gate.

29. The semiconductor structure according to claim 28, characterized in that The fifth branch portion includes an eleventh diode; and the second common portion includes a tenth diode.

30. A semiconductor module, characterized in that: include: A semiconductor structure and an integrated circuit; the semiconductor structure comprises the semiconductor structure according to any one of claims 1 to 29, and the integrated circuit is coupled to the semiconductor structure.

31. An electronic device, characterized in that: It comprises a semiconductor module and a circuit board, wherein the semiconductor module is arranged on the circuit board; the semiconductor module comprises the semiconductor module according to claim 30.

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