Semiconductor structure

Abstract

The invention provides a semiconductor structure. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, a field oxide layer, a third well region and a fourth well region, the first well region has N-type doping. The second well region has P-type doping. The second well region is adjacent to the first well region and is in contact with the first well region at an interface. The first doped region has N-type doping and is formed in the first well region. The second doped region has P-type doping and is formed in the second well region. The field oxide layer is formed in the first well region and located between the first doped region and the second doped region. The third well region has N-type doping, is formed in the first well region and is located below the field oxide layer. The fourth well region has N-type doping, is formed in the first well region and is located below the field oxide layer. The third well region and the fourth well region are used for reducing the breakdown voltage of the interface.

Description

Technical Field

[0001] The invention relates to a high voltage junction terminal structure for isolating a high side region circuit and a low side region circuit, and more particularly to a high voltage junction terminal structure for reducing an electrostatic discharge trigger voltage and a high voltage transistor for increasing an electrostatic discharge trigger voltage. Background Art

[0002] Figure 1 Shows the circuit diagram of a high voltage integrated circuit. Figure 1 As shown, the high voltage integrated circuit 100 includes a low-end region driving circuit 110, a voltage level shifting circuit 120, a high-end region driving circuit 130, an upper bridge transistor Q1, and a lower bridge transistor Q2. The lower bridge driving circuit 110 controls the lower bridge transistor Q2 according to an input signal SIN, and controls the upper bridge transistor Q1 through the driving signal via the voltage level shifting circuit 120 and the high-end region circuit 130, wherein the low-end region driving circuit 110 is powered by a low voltage VD and a ground terminal GND.

[0003] The high-side driving circuit 130 is powered by a first high voltage VB and a floating voltage VS, wherein the first high voltage VB is greater than the second high voltage HV, and the upper bridge transistor Q1 and the lower bridge transistor Q2 are not turned on at the same time to generate the floating voltage VS. The voltage level shift circuit 120 includes a first N-type transistor N1, a second N-type transistor N2, a first resistor R1, and a second resistor R2, and is used to convert the driving signal generated by the low-side driving circuit 110 (i.e., ranging from the low voltage VD to the ground terminal GND) to the voltage level of the high-side driving circuit 130 (i.e., ranging from the first high voltage VB to the floating voltage VS). In order to isolate the low-side driving circuit 110 from the high-side driving circuit 130, the high-voltage integrated circuit 100 further includes a junction diode JD parasitic on a high-voltage junction termination structure, wherein the cathode terminal NC of the junction diode JD is coupled to the first high voltage VB, and the anode terminal NA of the junction diode JD is coupled to the ground terminal GND.

[0004] Since the junction diode JD occupies a larger circuit area than the first N-type transistor N1 and the second N-type transistor N2, when an electrostatic discharge event occurs in the first high voltage VB, the removal of electrostatic charge through the junction diode JD helps to protect the high-voltage integrated circuit 100 from burning. Since the junction diode JD, the first N-type transistor N1, and the second N-type transistor N2 are adjacent to each other in the circuit layout and have similar structures, they can all be used to remove electrostatic charge. In order to avoid the first N-type transistor N1 or the second N-type transistor N2 being turned on when an electrostatic discharge event occurs and causing circuit damage, it is necessary to ensure that the electrostatic charge is removed to the ground terminal GND through the junction diode JD. Summary of the invention

[0005] The present invention proposes a semiconductor structure of a high voltage junction terminal structure, which helps to reduce the breakdown voltage of the parasitic diode of the high voltage junction terminal structure by inserting a well region with a higher concentration into the well region of the high voltage junction terminal structure, thereby causing the electrostatic charge to be discharged to the ground terminal through the parasitic diode of the high voltage junction terminal structure. The present invention further proposes a transistor adjacent to the high voltage junction terminal structure, which helps to increase the breakdown voltage of the transistor by inserting a gap in the well region of the transistor, thereby causing the parasitic diode of the high voltage junction terminal structure adjacent to the transistor and having a lower breakdown voltage to be preferentially turned on and discharge the electrostatic charge.

[0006] In view of this, the present invention proposes a semiconductor structure, including a first well region, a second well region, a first doped region, a second doped region, a third well region and a fourth well region. The first well region has N-type doping. The second well region has P-type doping, is adjacent to the first well region and contacts the first well region at an interface. The first doped region has N-type doping and is formed in the first well region. The second doped region has P-type doping and is formed in the second well region. The field oxide layer is formed in the first well region and is located between the first doped region and the second doped region. The third well region has N-type doping, is formed in the first well region and is located below the field oxide layer. The fourth well region has N-type doping, is formed in the first well region and is located below the field oxide layer. The third well region and the fourth well region are used to reduce the breakdown voltage of the interface.

[0007] According to an embodiment of the present invention, the semiconductor elements in the first region are powered by a first high voltage and a first low voltage, and the semiconductor elements in the second region are powered by a second high voltage and a second low voltage. The first high voltage exceeds the first low voltage, and the second high voltage exceeds the second low voltage. The first high voltage exceeds the second high voltage, and the second low voltage is not greater than the first low voltage.

[0008] According to an embodiment of the present invention, the first well region has a first depth, the third well region has a second depth, and the second depth is not greater than the first depth.

[0009] According to one embodiment of the present invention, the semiconductor structure further includes a gate oxide layer and a gate electrode. The gate oxide layer covers the interface and is located between the first doped region and the second doped region. The gate electrode covers the field oxide layer and the gate oxide layer and contacts the gate oxide layer. At least a portion of the gate electrode covers the field oxide layer.

[0010] According to an embodiment of the present invention, the third well region has a first width, the fourth well region has a second width, and the first width is not less than the second width.

[0011] According to an embodiment of the present invention, there is a first distance between the third well region and the fourth well region. The third well region is adjacent to the first doped region, the fourth well region is adjacent to the gate electrode, and the first distance is greater than or equal to zero.

[0012] According to an embodiment of the present invention, there is a second distance between the fourth well region and the gate electrode, and the second distance is not less than zero.

[0013] According to one embodiment of the present invention, the semiconductor structure further includes a fifth well region. The fifth well region has N-type doping, is formed in the first well region and is located below the field oxide layer. The fifth well region is further located between the fourth well region and the gate electrode, and has a third width. The first width is not less than the second width, and the second width is not less than the third width.

[0014] According to one embodiment of the present invention, the semiconductor structure further includes a sixth well region and a seventh well region. The sixth well region has a P-type doping, is formed in the second well region and is adjacent to the second doping region. The seventh well region has a P-type doping, is formed in the second well region and is located between the sixth well region and the gate electrode. The sixth well region and the seventh well region are used to reduce the breakdown voltage of the interface.

[0015] According to an embodiment of the present invention, there is a third distance between the sixth well region and the seventh well region. The third distance and the fourth distance are greater than or equal to zero.

[0016] According to an embodiment of the present invention, the sixth well region has a fourth width, the seventh well region has a fifth width, and the fourth width is not less than the fifth width.

[0017] According to an embodiment of the present invention, the semiconductor structure further includes an eighth well region. The eighth well region has a P-type doping, is formed in the second well region and is located between the seventh well region and the gate electrode. The eighth well region has a sixth width, and the fifth width is not less than the sixth width.

[0018] According to an embodiment of the present invention, the eighth well region and the gate end have a fifth distance, and the fifth distance is greater than zero.

[0019] The present invention further proposes a semiconductor structure, comprising a substrate, a first well region, a second well region, a third well region, a first doped region, a second doped region, a third doped region and a field oxide layer. The first well region has N-type doping and is formed in the substrate. The second well region has N-type doping and is formed in the substrate and is adjacent to the first well region, and the first well region and the second well region have a first spacing. The third well region has P-type doping, is adjacent to the second well region and contacts the second well region at an interface. The first doped region has N-type doping and is formed in the first well region. The second doped region has P-type doping and is formed in the third well region. The third doped region has N-type doping and is formed in the third well region and is located between the first doped region and the second doped region. The field oxide layer covers the first well region, the second well region and the substrate, and is located between the first doped region and the third doped region. The first spacing is used to increase the breakdown voltage of the interface.

[0020] According to an embodiment of the present invention, the semiconductor structure forms a transistor.

[0021] According to one embodiment of the present invention, the semiconductor structure further includes a gate oxide layer and a gate electrode. The gate oxide layer covers the interface and is located between the first doped region and the third doped region. The gate electrode covers the field oxide layer and the gate oxide layer and contacts the gate oxide layer. At least a portion of the gate electrode covers the field oxide layer, and the semiconductor structure forms a transistor.

[0022] According to one embodiment of the present invention, the semiconductor structure further includes a fourth well region. The fourth well region has N-type doping, is formed in the substrate and is located between the second well region and the third well region. The fourth well region contacts the third well region at the interface, and the fourth well region and the second well region have a second spacing.

[0023] According to an embodiment of the present invention, the second interval is greater than the first interval.

[0024] According to another embodiment of the present invention, the second interval is equal to the first interval.

[0025] According to an embodiment of the present invention, there is a gap between the second well region and the fourth well region, the width of the gap is the second spacing, and there is a third spacing between the gap and the gate electrode, the third spacing is greater than zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Circuit diagram showing a high voltage integrated circuit;

[0027] Figure 2 A cross-sectional view showing a semiconductor structure according to an embodiment of the present invention;

[0028] Figure 3 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0029] Figure 4 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0030] Figure 5 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0031] Figure 6 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention; and

[0032] Figure 7 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown.

[0033] Reference numerals:

[0034] 100: High voltage integrated circuit

[0035] 110: Low-end area driving circuit

[0036] 120: Voltage level shift circuit

[0037] 130: High-end area drive circuit

[0038] 200,300,400,500,600,700:Semiconductor structure

[0039] Q1: Upper bridge transistor

[0040] Q2: Lower bridge transistor

[0041] SIN: Input signal

[0042] VD: Low voltage

[0043] GND: Ground terminal

[0044] VB: First high voltage

[0045] VS: floating voltage

[0046] HV: Second Highest Voltage

[0047] R1: The first resistor

[0048] R2: Second resistor

[0049] JD: Junction diode

[0050] NC: cathode terminal

[0051] NA: Anode terminal

[0052] SUB:Substrate

[0053] W1: First well region

[0054] W2: Second well region

[0055] W3: The third well region

[0056] W4: Fourth well region

[0057] W5: Fifth well region

[0058] W6: Sixth well region

[0059] W7: Seventh well region

[0060] W8: Eighth well region

[0061] W9: Ninth Well

[0062] W10: Tenth well area

[0063] W11: Eleventh well region

[0064] W12: Twelfth well region

[0065] W13: Thirteenth Well

[0066] W14: Fourteenth well area

[0067] W15: The fifteenth well

[0068] W16: Sixteenth well area

[0069] W17: Seventeenth well region

[0070] W18: Eighteenth well area

[0071] W19: Nineteenth well area

[0072] W20: 20th well region

[0073] W21: Twenty-first well region

[0074] RG1: First Region

[0075] RG2: Second Region

[0076] INT1: First interface

[0077] INT2: Second interface

[0078] D1: first doped region

[0079] D2: Second doping region

[0080] D3: The third doping region

[0081] D4: Fourth doping region

[0082] D5: Fifth doping region

[0083] FOX: Field Oxide

[0084] GOX: Gate Oxide

[0085] GATE: Gate electrode

[0086] DP1: First Depth

[0087] DP2: Second Depth

[0088] DP3: Depth 3

[0089] DP4: Depth 4

[0090] DP5: Fifth Depth

[0091] DP6: Sixth Depth

[0092] WD1: First width

[0093] WD2: Second width

[0094] WD3: Third Width

[0095] WD4: Fourth Width

[0096] WD5: Fifth Width

[0097] WD6: Sixth Width

[0098] WD7: Seventh Width

[0099] WD8: Eighth Width

[0100] WD9: Ninth Width

[0101] WD10: Tenth Width

[0102] WD11: Eleventh Width

[0103] WD12: 12th Width

[0104] SP1: First spacing

[0105] SP2: Second spacing

[0106] SP3: Third spacing

[0107] SP4: The fourth interval

[0108] SP5: The fifth interval

[0109] SP6: Sixth interval

[0110] SP7: The seventh interval

[0111] SP8: The eighth interval

[0112] SP9: Ninth Interval

[0113] SP10: The tenth interval

[0114] SP11: Eleventh Interval

[0115] SP12: The twelfth interval

[0116] SP13: Thirteenth Pitch

[0117] SP14: Fourteenth Pitch

[0118] SP15: Fifteenth Pitch

[0119] SP16: Sixteenth Pitch DETAILED DESCRIPTION

[0120] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the present invention and should not be regarded as limiting the present invention. The scope of the present invention should be based on the scope defined by the claims.

[0121] It is worth noting that the following disclosure may provide multiple embodiments or examples for practicing different features of the present invention. The specific component examples and arrangements described below are only used to briefly and concisely explain the spirit of the present invention and are not used to limit the scope of the present invention. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of reusing is only to provide a simplified and clear description, and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0122] In addition, the description below of a feature being connected to, coupled to and / or formed on another feature may actually include a plurality of different embodiments, including direct contact between the features, or including other additional features formed between the features, etc., so that the features are not in direct contact.

[0123] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side.

[0124] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present invention.

[0125] Some embodiments of the present invention may be understood in conjunction with the drawings, and the drawings of the embodiments of the present invention are also considered as part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present invention.

[0126] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "approximately" or "generally", the meanings of "about", "approximately" or "generally" can still be implied.

[0127] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0128] In some embodiments of the present invention, terms such as "connection" and "interconnection" may refer to two structures being in direct contact with each other, or two structures not being in direct contact with each other, with another structure disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed.

[0129] In the drawings, similar components and / or features may have the same reference numerals. Various components of the same type may be distinguished by adding letters or numbers after the reference numerals to distinguish similar components and / or similar features.

[0130] In some embodiments of the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in the paragraph and related drawings. Such relative terms are only used for convenience of explanation and do not mean that the device described therein needs to be manufactured or operated in a specific orientation. Terms related to bonding and connection, such as "connection" and "interconnection", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein there is another structure disposed between the two structures. Moreover, such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed.

[0131] Embodiments of the present invention disclose embodiments of semiconductor devices, and the embodiments may be included in integrated circuits (ICs) such as microprocessors, memory devices, and / or other devices. The ICs may also include various passive and active microelectronic components, such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAPs), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors, high-power MOS transistors, or other types of transistors. A person skilled in the art to which the present invention relates may understand that the semiconductor device may also be used to include other types of semiconductor components in an integrated circuit.

[0132] Figure 2A cross-sectional view of a semiconductor structure according to an embodiment of the present invention is shown. According to an embodiment of the present invention, the semiconductor structure 200 is a high voltage junction termination structure and corresponds to Figure 1 The junction diode JD. Figure 2 As shown, the semiconductor structure 200 includes a substrate SUB, a first well region W1 and a second well region W2 .

[0133] The substrate SUB has a first conductivity type. According to one embodiment of the present invention, the substrate SUB is a silicon substrate. According to another embodiment of the present invention, the substrate SUB may be a lightly doped semiconductor substrate having the first conductivity type. According to other embodiments of the present invention, the substrate SUB may also be an epitaxial substrate.

[0134] The first well region W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to one embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type. According to one embodiment of the present invention, the first well region W1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a predetermined region of the first well region W1 to form the first well region W1.

[0135] like Figure 2 As shown, the first well region W1 is adjacent to the first region RG1. According to some embodiments of the present invention, Figure 1 The high-side region driving circuit 130 is located in the first region RG1. According to some embodiments of the present invention, Figure 1 The voltage level shift circuit 120 may be located between the first region RG1 and the second region RG2.

[0136] The second well region W2 is formed in the semiconductor substrate SUB, and is adjacent to the first well region W1, and is in contact with the first well region W1 at the first interface INT1, wherein the second well region W2 has a first conductivity type. According to one embodiment of the present invention, the second well region W2 can also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the second well region W2 is to be formed to form the second well region W2. In this embodiment, the doping concentration of the second well region W2 is higher than the doping concentration of the semiconductor substrate SUB.

[0137] like Figure 2 As shown, the second well region W2 is adjacent to the second region RG2. According to some embodiments of the present invention, Figure 1 The low-end region driving circuit 110 is located in the second region RG2. According to some embodiments of the present invention, Figure 1 The voltage level shift circuit 120 may be located between the second region RG2 and the first region RG1. According to some embodiments of the present invention, the first region RG1 may be regarded as a high-end region, and the second region RG2 may be regarded as a low-end region. The high voltage junction terminal structure 200 is used to isolate the high-end region and the low-end region.

[0138] like Figure 2 As shown, the semiconductor structure 200 further includes a first doping region D1 and a second doping region D2. The first doping region D1 has a second conductivity type and is formed in the first well region W1. According to one embodiment of the present invention, the first doping region D1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a predetermined region of the first doping region D1 to form the first doping region D1. According to one embodiment of the present invention, the doping concentration of the first doping region D1 is higher than the doping concentration of the first well region W1.

[0139] The second doping region D2 has the first conductivity type and is formed in the second well region W2. According to one embodiment of the present invention, the second doping region D2 can also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the region where the second doping region D2 is to be formed to form the second doping region D2. According to one embodiment of the present invention, the doping concentration of the second doping region D2 is higher than the doping concentration of the second well region W2.

[0140] like Figure 2 As shown, the semiconductor structure 200 further includes a field oxide layer FOX, a gate oxide layer GOX and a gate electrode GATE. The field oxide layer FOX is formed in the first well region W1 and is adjacent to the first doped region D1. The gate oxide layer GOX covers the first interface INT1 and is formed between the field oxide layer FOX and the second doped region D2. The gate electrode GATE covers the field oxide layer FOX and the gate oxide layer GOX and is in contact with the gate oxide layer GOX. According to one embodiment of the present invention, part of the gate electrode GATE covers the field oxide layer FOX.

[0141] like Figure 2 As shown, the semiconductor structure 200 further includes a third well region W3, a fourth well region W4 and a fifth well region W5. The third well region W3 has a second conductivity type, is formed in the first well region W1 and is adjacent to the first doping region D1, wherein the field oxide layer FOX covers the third well region W3. According to one embodiment of the present invention, the third well region W3 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a predetermined area of ​​the third well region W3 to form the third well region W3. According to one embodiment of the present invention, the doping concentration of the third well region W3 is higher than the doping concentration of the first well region W1, and the doping concentration of the first doping region D1 is higher than the doping concentration of the third well region W3.

[0142] The fourth well region W4 has the second conductivity type, is formed in the first well region W1 and is adjacent to the third well region W3, wherein the field oxide layer FOX covers the fourth well region W4. According to one embodiment of the present invention, the fourth well region W4 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a predetermined region of the fourth well region W4 to form the fourth well region W4. According to one embodiment of the present invention, the doping concentration of the fourth well region W4 is higher than the doping concentration of the first well region W1, and the doping concentration of the first doping region D1 is higher than the doping concentration of the fourth well region W4.

[0143] The fifth well region W5 has the second conductivity type, is formed in the first well region W1 and is adjacent to the fourth well region W4, wherein the field oxide layer FOX covers the fifth well region W5. According to one embodiment of the present invention, the fifth well region W5 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of ​​the predetermined fifth well region W5 to form the fifth well region W5. According to one embodiment of the present invention, the doping concentration of the fifth well region W5 is higher than the doping concentration of the first well region W1, and the doping concentration of the first doping region D1 is higher than the doping concentration of the fifth well region W5.

[0144] According to an embodiment of the present invention, the first well region W1 has a first depth DP1, and the third well region W3, the fourth well region W4 and the fifth well region W5 have a second depth DP2, wherein the second depth DP2 is not greater than the first depth DP1. Figure 2 As shown, the third well region W3 has a first width WD1, the fourth well region W4 has a second width WD2, and the fifth well region W5 has a third width WD3. In this embodiment, the first width WD1, the second width WD2, and the third width WD3 are similar.

[0145] There is a first spacing SP1 between the third well region W3 and the fourth well region W4, and there is a second spacing SP2 between the fourth well region W4 and the fifth well region W5. According to one embodiment of the present invention, the first spacing SP1 and the second spacing SP2 are similar. According to another embodiment of the present invention, the first spacing SP1 and the second spacing SP2 are different. According to other embodiments of the present invention, the first spacing SP1 and the second spacing SP2 are both zero. In other words, the third well region W3, the fourth well region W4 and the fifth well region W5 can also be connected well regions. Here, three well regions are used as an explanation, but are not limited to this in any form.

[0146] like Figure 2As shown, there is a third spacing SP3 between the fifth well region W5 and the gate electrode GATE, wherein the third spacing SP3 is not less than zero. In other words, the gate electrode GATE cannot cover one of the third well region W3, the fourth well region W4 and the fifth well region W5. According to some embodiments of the present invention, the third well region W3, the fourth well region W4 and the fifth well region W5 are used to increase the doping concentration of the first well region W1, so that the breakdown voltage of the first interface INT1 of the semiconductor structure 200 is reduced.

[0147] In other words, when Figure 1 When an electrostatic discharge event occurs to the first high voltage VB, although the junction diode JD, the first N-type transistor N1 and the second N-type transistor N2 are adjacent to each other in the circuit layout and have similar structures, the junction diode JD having the third well region W3, the fourth well region W4 and the fifth well region W5 has a lower breakdown voltage, so that the junction diode JD is preferentially turned on and the electrostatic charge is eliminated through the junction diode JD, thereby protecting the first N-type transistor N1 and the second N-type transistor N2 from burning.

[0148] Figure 3 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. According to one embodiment of the present invention, the semiconductor structure 300 is a high voltage junction termination structure and corresponds to Figure 1 The junction diode JD. Figure 3 The semiconductor structure 300 and Figure 2 Compared with the semiconductor structure 200, the third well region W3, the fourth well region W4 and the fifth well region W5 are replaced by the sixth well region W6, the seventh well region W7 and the eighth well region W8 respectively.

[0149] The sixth well region W6 has a fourth width WD4, the seventh well region W7 has a fifth width WD5, and the eighth well region W8 has a sixth width WD6. According to an embodiment of the present invention, the fourth width WD4 is greater than the fifth width WD5, and the fifth width WD5 is greater than the sixth width WD6.

[0150] like Figure 3 As shown, there is a fourth interval SP4 between the sixth well region W6 and the seventh well region W7, and there is a fifth interval SP5 between the seventh well region W7 and the eighth well region W8. According to one embodiment of the present invention, the fourth interval SP4 and the fifth interval SP5 are similar. According to another embodiment of the present invention, the fourth interval SP4 and the fifth interval SP5 may also be greatly different. There is a sixth interval SP6 between the eighth well region W8 and the gate electrode GATE, wherein the sixth interval SP6 is not less than zero. In other words, the gate electrode GATE cannot cover any one of the fourth interval SP4, the seventh well region W7 and the eighth well region W8.

[0151] According to some embodiments of the present invention, the sixth well region W6, the seventh well region W7 and the eighth well region W8 are used to increase the doping concentration of the first well region W1, so that the breakdown voltage of the first interface INT1 of the semiconductor structure 300 is reduced. Figure 1 When an electrostatic discharge event occurs to the first high voltage VB, the sixth well region W6, the seventh well region W7 and the eighth well region W8 reduce the breakdown voltage of the junction diode JD, so that the electrostatic charge is preferentially discharged to the ground through the junction diode JD, thereby protecting the adjacent first N-type transistor N1 and the second N-type transistor N2 from burning out.

[0152] Figure 4 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. According to one embodiment of the present invention, the semiconductor structure 400 is a high voltage junction termination structure and corresponds to Figure 1 The junction diode JD. Figure 4 The semiconductor structure 400 and Figure 2 Compared with the semiconductor structure of FIG. 1 , the third well region W3 , the fourth well region W4 and the fifth well region W5 located in the first well region W1 are replaced by the ninth well region W9 , the tenth well region W10 and the eleventh well region W11 located in the second well region W2 .

[0153] The ninth well region W9 is adjacent to the second doping region D2 and has a seventh width WD7. The tenth well region W10 has an eighth width WD8. The eleventh well region W11 has a ninth width WD9. According to an embodiment of the present invention, the seventh width WD7, the eighth width WD8 and the ninth width WD9 are similar.

[0154] like Figure 4 As shown, there is a seventh interval SP7 between the ninth well region W9 and the tenth well region W10, and there is an eighth interval SP8 between the tenth well region W10 and the eleventh well region W11. According to one embodiment of the present invention, the seventh interval SP7 and the eighth interval SP8 are similar. According to another embodiment of the present invention, the seventh interval SP7 and the eighth interval SP8 may also be greatly different. There is a ninth interval SP9 between the eleventh well region W11 and the gate electrode GATE, wherein the ninth interval SP9 is not less than zero. In other words, the gate electrode GATE cannot cover any one of the ninth well region W9, the tenth well region W10 and the eleventh well region W11.

[0155] According to an embodiment of the present invention, the second well region W2 has a third depth DP3, and the ninth well region W9, the tenth well region W10 and the eleventh well region W11 have a fourth depth DP4, wherein the fourth depth DP4 is not greater than the third depth DP3.

[0156] According to some embodiments of the present invention, the ninth well region W9, the tenth well region W10 and the eleventh well region W11 are used to increase the doping concentration of the second well region W2, so that the breakdown voltage of the first interface INT1 of the semiconductor structure 400 is reduced. Figure 1 When an electrostatic discharge event occurs to the first high voltage VB, the ninth well region W9, the tenth well region W10 and the eleventh well region W11 reduce the breakdown voltage of the junction diode JD, so that the electrostatic charge is preferentially discharged to the ground through the junction diode JD, thereby protecting the adjacent first N-type transistor N1 and the second N-type transistor N2 from burning out.

[0157] Figure 5 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. According to one embodiment of the present invention, the semiconductor structure 500 is a high voltage junction termination structure and corresponds to Figure 1 The junction diode JD. Figure 5 The semiconductor structure 500 and Figure 4 Compared with the semiconductor structure 400, the ninth well region W9, the tenth well region W10 and the eleventh well region W11 are replaced by the twelfth well region W12, the thirteenth well region W13 and the fourteenth well region W14 respectively.

[0158] The twelfth well region W12 has a tenth width WD10, the thirteenth well region W13 has an eleventh width WD11, and the fourteenth well region W14 has a twelfth width WD12. According to an embodiment of the present invention, the tenth width WD10 is greater than the eleventh width WD11, and the eleventh width WD11 is greater than the twelfth width WD12.

[0159] like Figure 5 As shown, there is a tenth interval SP10 between the twelfth well region W12 and the thirteenth well region W13, and there is an eleventh interval SP11 between the thirteenth well region W13 and the fourteenth well region W14. According to one embodiment of the present invention, the tenth interval SP10 and the eleventh interval SP11 are similar. According to another embodiment of the present invention, the tenth interval SP10 and the eleventh interval SP11 may also be greatly different. There is a twelfth interval SP12 between the fourteenth well region W14 and the gate electrode GATE, wherein the twelfth interval SP12 is not less than zero. In other words, the gate electrode GATE cannot cover any one of the twelfth well region W12, the thirteenth well region W13 and the fourteenth well region W14.

[0160] According to some embodiments of the present invention, the breakdown voltage of the first interface INT1 of the semiconductor structure 500 can be adjusted to a suitable breakdown voltage by inserting the width and number of the well regions of the second well regions W2 to ensure Figure 1 The junction diode JD is turned on first in an electrostatic discharge event.

[0161] Figure 6 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. According to one embodiment of the present invention, the semiconductor structure 600 is a transistor, and corresponds to Figure 1 A first N-type transistor N1 and a second N-type transistor N2.

[0162] like Figure 6 As shown, the semiconductor structure 600 includes a substrate SUB, a fifteenth well region W15, a sixteenth well region W16, a seventeenth well region W17 and an eighteenth well region W18.

[0163] The substrate SUB has a first conductivity type. According to one embodiment of the present invention, the substrate SUB is a silicon substrate. According to another embodiment of the present invention, the substrate SUB may be a lightly doped semiconductor substrate having the first conductivity type. According to other embodiments of the present invention, the substrate SUB may also be an epitaxial substrate.

[0164] The fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17 are formed in the semiconductor substrate SUB and all have the second conductivity type. According to one embodiment of the present invention, the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the predetermined fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17 to form the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17, respectively. According to one embodiment of the present invention, the doping concentrations of the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17 are similar.

[0165] There is a thirteenth pitch SP13 between the fifteenth well region W15 and the sixteenth well region W16, and there is a fourteenth pitch SP14 between the sixteenth well region W16 and the seventeenth well region W17. According to one embodiment of the present invention, the thirteenth pitch SP13 and the fourteenth pitch SP14 are similar. According to one embodiment of the present invention, the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17 have a fifth depth DP5, the thirteenth pitch SP13 and the fourteenth pitch SP14 have a sixth depth DP6, wherein the fifth depth DP5 and the sixth depth DP6 are similar.

[0166] The eighteenth well region W18 is formed in the semiconductor substrate SUB, and is adjacent to the seventeenth well region W17, and is in contact with the seventeenth well region W17 at the second interface INT2, wherein the eighteenth well region W18 has a first conductivity type. According to one embodiment of the present invention, the eighteenth well region W18 can also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the eighteenth well region W18 is predetermined to be formed to form the eighteenth well region W18. In this embodiment, the doping concentration of the eighteenth well region W18 is higher than the doping concentration of the semiconductor substrate SUB.

[0167] like Figure 6 As shown, the semiconductor structure 600 further includes a third doping region D3, a fourth doping region D4 and a fifth doping region D5. The third doping region D3 has a second conductivity type and is formed in the fifteenth well region W15. According to one embodiment of the present invention, the third doping region D3 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the region of the predetermined third doping region D3 to form the third doping region D3. According to one embodiment of the present invention, the doping concentration of the third doping region D3 is higher than the doping concentrations of the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17.

[0168] The fourth doping region D4 has the first conductivity type and is formed in the eighteenth well region W18. According to one embodiment of the present invention, the fourth doping region D4 can also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the region where the fourth doping region D4 is to be formed to form the fourth doping region D4. According to one embodiment of the present invention, the doping concentration of the fourth doping region D4 is higher than the doping concentration of the eighteenth well region W18.

[0169] The fifth doping region D5 has the second conductivity type, is formed in the eighteenth well region W18 and is located between the third doping region D3 and the fourth doping region D4. According to one embodiment of the present invention, the fifth doping region D5 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of ​​the predetermined fifth doping region D5 to form the fifth doping region D5. According to one embodiment of the present invention, the doping concentration of the fifth doping region D5 is higher than the doping concentrations of the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17.

[0170] like Figure 6As shown, the semiconductor structure 600 further includes a field oxide layer FOX, a gate oxide layer GOX and a gate electrode GATE. The field oxide layer FOX is formed in the substrate SUB, the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17, and is adjacent to the third doped region D3, wherein the field oxide layer FOX is located between the third doped region D3 and the fifth doped region D5. The gate oxide layer GOX covers the second interface INT2 and is formed between the field oxide layer FOX and the fifth doped region D5. The gate electrode GATE covers the field oxide layer FOX and the gate oxide layer GOX, and is in contact with the gate oxide layer GOX. According to one embodiment of the present invention, part of the gate electrode GATE covers the field oxide layer FOX.

[0171] According to an embodiment of the present invention, the semiconductor structure 600 is formed Figure 1 The first N-type transistor N1 and the second N-type transistor N2, wherein the third doped region D3 forms a drain terminal, the gate electrode GATE forms a gate terminal, and the fifth doped region D5 forms a source terminal. According to one embodiment of the present invention, the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17 can be regarded as a virtual well region, wherein the breakdown voltage of the second interface INT2 is determined by the doping concentration of the virtual well region and the eighteenth well region W18.

[0172] The thirteenth spacing SP13 and the fourteenth spacing SP14 are used to reduce the doping concentration of the virtual well region, thereby increasing the breakdown voltage of the second interface INT2. Figure 1 When an electrostatic discharge event occurs to the first high voltage VB, since the first N-type transistor N1 and the second N-type transistor N2 have a higher breakdown voltage than the junction diode JD due to the thirteenth pitch SP13 and the fourteenth pitch SP14, the junction diode JD is preferentially turned on and the electrostatic charge is eliminated through the junction diode JD, thereby protecting the first N-type transistor N1 and the second N-type transistor N2 from being burned out.

[0173] Figure 7 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. According to one embodiment of the present invention, the semiconductor structure 700 is a transistor, and corresponds to Figure 1 The first N-type transistor N1 and the second N-type transistor N2. Figure 7 The semiconductor structure 700 and Figure 6 Compared with the semiconductor structure 600, the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17 are replaced by the nineteenth well region W19, the twentieth well region W20 and the twenty-first well region W21 respectively.

[0174] like Figure 7As shown, there is a fifteenth pitch SP15 between the nineteenth well region W19 and the twentieth well region W20, and a sixteenth pitch SP16 between the twentieth well region W20 and the twenty-first well region W21. According to an embodiment of the present invention, the sixteenth pitch SP16 is greater than the fifteenth pitch SP15.

[0175] The fifteenth spacing SP15 and the sixteenth spacing SP16 are used to reduce the doping concentration of the virtual well region formed by the fifteenth well region W15, the sixteenth well region W16 and the seventeenth well region W17, thereby increasing the breakdown voltage of the second interface INT2. Figure 1 When an electrostatic discharge event occurs to the first high voltage VB, since the first N-type transistor N1 and the second N-type transistor N2 have a higher breakdown voltage than the junction diode JD due to the fifteenth pitch SP15 and the sixteenth pitch SP16, the junction diode JD is preferentially turned on and the electrostatic charge is eliminated through the junction diode JD, thereby protecting the first N-type transistor N1 and the second N-type transistor N2 from burning out.

[0176] The present invention proposes a semiconductor structure of a high voltage junction terminal structure, which helps to reduce the breakdown voltage of the parasitic diode of the high voltage junction terminal structure by inserting a well region with a higher concentration into the well region of the high voltage junction terminal structure, thereby causing the electrostatic charge to be discharged to the ground terminal through the parasitic diode of the high voltage junction terminal structure. The present invention further proposes a transistor adjacent to the high voltage junction terminal structure, which helps to increase the breakdown voltage of the transistor by inserting a gap in the well region of the transistor, thereby causing the parasitic diode of the high voltage junction terminal structure adjacent to the transistor and having a lower breakdown voltage to be preferentially turned on and discharge the electrostatic charge.

[0177] Although the embodiments of the present invention and its advantages have been disclosed as above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art may understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present invention. As long as the same functions can be implemented or the same results can be obtained in the embodiments described herein, they can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment.

Claims

1. A semiconductor structure, characterized in that: include: a first well region having N-type doping; a second well region, having a P-type doping, adjacent to the first well region and in contact with the first well region at an interface; a first doped region having N-type doping and formed in the first well region; a second doped region having a P-type doping and formed in the second well region; A field oxide layer is formed in the first well region and is located between the first doped region and the second doped region; a third well region, having N-type doping, formed in the first well region and located below the field oxide layer; and a fourth well region, having N-type doping, formed in the first well region and located below the field oxide layer; The third well region and the fourth well region are used to reduce the breakdown voltage of the interface.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure is located in a first region and a second region, the first well region is located in the first region, the second well region is located in the second region, the semiconductor element in the first region is powered by a first high voltage and a first low voltage, the semiconductor element in the second region is powered by a second high voltage and a second low voltage, wherein the first high voltage exceeds the first low voltage, and the second high voltage exceeds the second low voltage; The first high voltage exceeds the second high voltage, and the second low voltage is not greater than the first low voltage.

3. The semiconductor structure according to claim 1, wherein: The first well region has a first depth, and the third well region has a second depth; The second depth is no greater than the first depth.

4. The semiconductor structure according to claim 1, wherein: Also includes: a gate oxide layer covering the interface and located between the first doped region and the second doped region; and a gate electrode, covering the field oxide layer and the gate oxide layer, and contacting the gate oxide layer; At least a portion of the gate electrode covers the field oxide layer.

5. The semiconductor structure according to claim 4, characterized in that The third well region has a first width; The fourth well region has a second width; The first width is not less than the second width.

6. The semiconductor structure according to claim 4, wherein: There is a first distance between the third well region and the fourth well region; wherein the third well region is adjacent to the first doped region; wherein the fourth well region is adjacent to the gate electrode; The first spacing is greater than or equal to zero.

7. The semiconductor structure according to claim 4, wherein: There is a second distance between the fourth well region and the gate electrode; The second spacing is not less than zero.

8. The semiconductor structure according to claim 5, wherein: Also includes: a fifth well region, having N-type doping, formed in the first well region and located below the field oxide layer, wherein the fifth well region is further located between the fourth well region and the gate electrode; The fifth well region has a third width; The first width is not less than the second width, and the second width is not less than the third width.

9. The semiconductor structure according to claim 4, characterized in that Also includes: a sixth well region, having a P-type doping, formed in the second well region and adjacent to the second doping region; and a seventh well region, having a P-type doping, formed in the second well region and located between the sixth well region and the gate electrode; The sixth well region and the seventh well region are used to reduce the breakdown voltage of the interface.

10. The semiconductor structure according to claim 9, wherein: There is a third distance between the sixth well region and the seventh well region; The third distance is greater than or equal to zero.

11. The semiconductor structure according to claim 9, wherein: The sixth well region has a fourth width; The seventh well region has a fifth width; The fourth width is not less than the fifth width.

12. The semiconductor structure according to claim 11, wherein: Also includes: an eighth well region, having a P-type doping, formed in the second well region and located between the seventh well region and the gate electrode; The eighth well region has a sixth width; The fifth width is not less than the sixth width.

13. The semiconductor structure according to claim 12, wherein: The eighth well region and the gate end have a fifth distance; The fifth spacing is greater than zero.

14. A semiconductor structure, characterized in that: include: a substrate; a first well region, having N-type doping, formed in the substrate; A second well region, having N-type doping, is formed in the substrate and adjacent to the first well region, wherein the first well region and the second well region have a first distance; a third well region, having a P-type doping, adjacent to the second well region and in contact with the second well region at an interface; a first doped region having N-type doping and formed in the first well region; a second doped region having a P-type doping function and formed in the third well region; a third doped region, having N-type doping, formed in the third well region and located between the first doped region and the second doped region; and a field oxide layer covering the first well region, the second well region and the substrate, and located between the first doped region and the third doped region; The first spacing is used to increase the breakdown voltage of the interface.

15. The semiconductor structure according to claim 14, wherein: The semiconductor structure forms a transistor.

16. The semiconductor structure according to claim 14, wherein: Also includes: a gate oxide layer covering the interface and located between the first doped region and the third doped region; and a gate electrode, covering the field oxide layer and the gate oxide layer, and contacting the gate oxide layer; wherein at least a portion of the gate electrode covers the field oxide layer; The semiconductor structure forms a transistor.

17. The semiconductor structure according to claim 16, wherein: Also includes: a fourth well region, having N-type doping, formed in the substrate and located between the second well region and the third well region; wherein the fourth well region contacts the third well region at the interface; The fourth well region and the second well region have a second interval.

18. The semiconductor structure according to claim 17, wherein: The second interval is greater than the first interval.

19. The semiconductor structure according to claim 17, wherein: The second interval is equal to the first interval.

20. The semiconductor structure according to claim 17, wherein: There is a gap between the second well region and the fourth well region; The width of the gap is the second spacing; There is a third distance between the gap and the gate electrode; The third distance is greater than zero.

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