Perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell preparation method and cell

Abstract

The invention specifically discloses a preparation method of a perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell and a cell, and relates to the technical field of solar cells. The method comprises the following steps: carrying out double-sided polishing on a silicon wafer, carrying out boron diffusion on the back surface, removing a front-surface BSG layer, preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front surface, depositing a mask SiOx layer on the front surface, carrying out laser texturing, corroding to remove damage, removing a redundant layer, depositing a film layer on the back surface, printing an electrode, sintering and the like. According to the method, the poly-Si / SiO2 passivation contact structure is prepared on the polished surface, the mask SiOx layer is deposited on the surface of the poly-Si / SiO2 passivation contact structure, and the light trapping structure is prepared on the basis of the passivation contact structure through laser, so that the problems of poor passivation performance of the front surface of the TOPCON bottom cell, contradiction between parasitic absorption and superposition of the light trapping structure and passivation and perovskite and the like are effectively solved; therefore, the perovskite laminated solar cell has important significance in the technical field of perovskite laminated solar cells.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon stacked solar cell and a cell. Background Art

[0002] In the field of high-efficiency crystalline silicon cells, tunneling oxide passivated contact solar cells (TOPCon) are based on the principle of selective carriers. Their cell structure is an n-type silicon substrate cell. The passivation contact structure formed by the ultra-thin silicon oxide and doped polysilicon thin layer on the back effectively reduces surface recombination and metal contact recombination. It has the advantages of high minority carrier lifetime, high metal contamination tolerance, low attenuation, and low surface recombination rate, making it an ideal choice for silicon bottom cells in stacked cells.

[0003] At present, the perovskite crystalline silicon tandem solar cell technology is mostly constructed in series, with the crystalline silicon cell as the bottom cell and the perovskite as the top cell. The two are connected by a composite layer or a tunneling layer, and light is incident from the perovskite end. However, there are many defects in the typical perovskite / TOPCon tandem solar cell. When the poly-Si / SiOx contact structure of the TOPCON cell is placed on the front surface of the bottom cell, the optical absorption characteristics of the polycrystalline silicon layer lead to significant parasitic absorption, which reduces the photogenerated current density of the crystalline silicon layer sub-cell. Reducing the polycrystalline silicon film thickness to increase the photogenerated current density will also deteriorate the passivation performance of the polycrystalline silicon layer and reduce the overall opening voltage of the perovskite tandem crystalline silicon cell. In addition, when making a velvet structure to enhance the light trapping ability of the crystalline silicon cell, on the one hand, the velvet structure is relatively large and requires a thicker polysilicon layer for passivation, which is contrary to the need to reduce the thickness of the polysilicon layer; on the other hand, the velvet pyramid is relatively high, which increases the difficulty of superimposing perovskite on the surface. Summary of the invention

[0004] The present invention aims at the above problems, makes up for the deficiencies of the prior art, and provides a method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon stacked solar cell and a cell to solve the problems arising from the above background technology.

[0005] The technical solution of the present invention is: a method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon stacked solar cell, comprising the following steps:

[0006] S1: Double-sided polishing of N-type silicon wafer;

[0007] S2: Diffusing boron on the back side of the silicon wafer to form a boron-doped single crystal silicon layer;

[0008] S3: removing the BSG layer on the front side of the silicon wafer;

[0009] S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front side of the silicon wafer;

[0010] S5: removing the PSG layer on the front side of the silicon wafer;

[0011] S6: Deposit mask SiO on the front side of the silicon wafer x layer;

[0012] S7: On the mask SiO x The surface of the layer is subjected to laser texturing;

[0013] S8: Remove the remaining mask SiO after laser removal x The melt layer and damage on the surface of the layer and phosphorus-doped poly silicon layer, as well as the PSG layer on the back side;

[0014] S9: remove the N-poly and BSG layers plated on the back of the silicon wafer;

[0015] S10: backside deposition of passivation and anti-reflection film;

[0016] S11: Print the back electrode and sinter it.

[0017] Furthermore, the depth of the recessed structure formed by laser texturing in S7 is greater than that of the mask SiO x The thickness of the layer is less than that of the SiO mask in S6 x The sum of the thickness of the layer and the poly silicon layer doped with phosphorus in S4.

[0018] Furthermore, the resistivity of the N-type silicon wafer in S1 is 0.5-5Ω / cm 2 , thickness is 100-200μm.

[0019] Preferably, the polishing treatment is a double-sided alkaline polishing treatment performed on the N-type silicon wafer using any one of KOH, NaOH or TMAH.

[0020] Furthermore, the temperature of the boron diffusion deposition in S2 is 800-1000°C, the time is 20-60 minutes, and the sheet resistance of the boron-doped single crystal silicon layer is 200-400Ω / cm 2 The thickness of the boron-doped single crystal silicon layer is 0.5 to 1.5 μm.

[0021] Preferably, the boron diffusion is to use BCl3 as a boron diffusion source to diffuse boron on the back side of the N-type silicon wafer to form a boron-doped single crystal silicon layer, which forms a PN junction with the N-type silicon wafer.

[0022] Furthermore, the thickness of the tunneling oxide layer in S4 is 1-2 nm; the thickness of the phosphorus-doped poly silicon layer is 20-100 nm, and the phosphorus doping concentration ranges from (0.1-2.0)E21.

[0023] Preferably, the tunneling oxide layer and the poly silicon layer are prepared on the front side of the N-type silicon wafer by LPCVD, PECVD or PVD; then the silicon wafer is loaded into a tubular phosphorus diffusion furnace, and phosphorus is diffused and annealed on the back side of the silicon wafer by POCl3 diffusion, so that the phosphorus-doped Poly layer is formed on the back side of the silicon wafer.

[0024] Furthermore, in S6, the deposition temperature is 500-600°C, the deposition time is 20-60 minutes, and the mask SiO x The thickness of the layer is 100 to 300 nm.

[0025] Preferably, the deposition process is any one of LPCVD, PECVD or PVD.

[0026] Furthermore, the single pulse energy of the laser in S7 is 80-100uJ, the pulse frequency is 1000-3000kHz, the scanning speed is 30000-50000mm / s, and the number of scanning times is 1 time.

[0027] Preferably, the laser texturing is performed on the mask SiO x The surface of the layer is prepared with an array hole velvet light trapping structure using a picosecond laser, with a hole pitch of 0 to 60 μm and a reflectivity of 5 to 15%.

[0028] Furthermore, the S8 is to use an isotropic etching method, using an etching solution with a HF mass fraction of 10-60wt% and a HNO3 mass fraction of 20-80wt%, to remove the mask SiO2 remaining after the laser within 2-5 minutes. x The melted layer and damage on the surface of the layer and the phosphorus-doped poly silicon layer are removed, and the PSG layer plated on the back is removed at the same time.

[0029] Furthermore, the passivation and anti-reflection film in S10 includes but is not limited to AlO x 、SiN x and SiO x membrane.

[0030] The present invention also provides a perovskite / silicon tandem solar cell, wherein the crystalline silicon bottom cell is prepared by the aforementioned preparation method and is applied to the perovskite crystalline silicon tandem solar cell.

[0031] Furthermore, the crystalline silicon bottom cell includes: an N-type silicon wafer, the front side of the N-type silicon wafer includes a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer in sequence, and the back side of the N-type silicon wafer includes a boron-doped single crystal silicon layer, a passivation and anti-reflection film layer, and a back electrode in sequence; wherein a light trapping structure appears on the surface of the phosphorus-doped poly silicon layer.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] (1) The present invention prepares a poly-Si / SiO2 passivation contact structure on the polished surface, reduces the front surface recombination, and effectively improves the passivation performance of the battery; at the same time, the phosphorus-doped poly silicon layer is thin, which greatly reduces the parasitic absorption of the long-wave band and improves the effective utilization efficiency of light; and laser-prepares a light-trapping structure on the basis of the passivation contact structure, avoiding the recombination problem caused by first texturing and then preparing the passivation structure. In addition, a mask SiO2 of a certain thickness is deposited on the surface of the poly-Si / SiO2 passivation contact structure. x layer, which greatly reduces the damage of laser texturing to the passivation contact structure; at the same time, the residual mask SiO2 is removed after texturing. x The layer forms a light-trapping structure on the surface of the passivation contact structure, which also increases the incident rate of light.

[0034] (2) Compared with the chemical etching texturing method, the laser texturing method used in the present invention has a very uniform silicon wafer surface morphology by using the laser-prepared array hole texture light-trapping structure, which is more conducive to the subsequent deposition of a perovskite layer on its surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 A process flow chart for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell provided in Examples 1-3 of the present invention DETAILED DESCRIPTION

[0037] The technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the protection scope of the present invention.

[0038] Example 1

[0039] This embodiment provides a method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell. Figure 1 As shown, the preparation method comprises the following steps:

[0040] S1: The selected resistivity is 0.5Ω / cm 2, N-type single crystal silicon wafers with a thickness of 100μm are treated with double-sided alkaline polishing using KOH to remove the damaged layer and impurities on the surface of the silicon wafer, making the surface of the silicon wafer smooth and clean, providing a good foundation for subsequent processes;

[0041] S2: Using BCl3 as a boron diffusion source, a diffusion deposition process is performed at 800°C for 20 minutes to diffuse boron atoms into the silicon wafer, forming a boron-doped single-crystalline silicon layer and a PN junction with the N-type silicon wafer. In this process, the flow rate, pressure and other parameters of the boron diffusion source are precisely controlled to ensure that the square resistance of the boron-doped single-crystalline silicon layer reaches 400Ω / cm 2 , with a thickness of 0.5μm, thus achieving good electrical properties;

[0042] S3: removing the boron-doped single crystal silicon layer and the BSG layer that are extended on the front and side surfaces of the silicon wafer;

[0043] S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front side of the silicon wafer; firstly, using the LPCVD (low pressure chemical vapor deposition) method, growing a tunneling oxide layer and a Poly layer with a thickness of 1.0 nm on the front side of the silicon wafer; then loading the silicon wafer into a tubular phosphorus diffusion furnace, using POCl3 diffusion to diffuse phosphorus on the back side of the silicon wafer and annealing, so that a phosphorus-doped Poly silicon layer with a thickness of 20 nm is formed on the back side, and the phosphorus doping concentration in the phosphorus-doped Poly layer is 0.1E21, ensuring that a good poly-Si / SiO2 passivation contact structure is formed on the front side of the silicon wafer;

[0044] S5: Remove the PSG layer on the front side of the silicon wafer to avoid its interference with subsequent processes and battery performance;

[0045] S6: Use PECVD technology to deposit mask SiO on the front side of the silicon wafer x layer, the deposition temperature was set at 500°C, the deposition time was 20 min, and the mask SiO x The layer thickness is 100nm; by adjusting the deposition parameters, a suitable mask SiO x layer quality and thickness;

[0046] Since laser texturing is difficult to control, if the poly-Si / SiO2 passivation contact structure is directly textured, the laser will inevitably burn through the poly-Si layer. Considering that the phosphorus-doped poly-Si layer is thin, a passivation and easy-to-clean film layer, the mask SiO2, needs to be deposited on its surface. x The layer is used to protect the phosphorus-doped poly silicon layer during the laser preparation of the array hole texture surface.

[0047] S7: Picosecond laser was used to prepare the array hole texture surface, the hole pitch was controlled at 0μm, the reflectivity reached 5%, the single pulse energy was 80uJ, the pulse frequency was 1000kHz, the scanning speed was 50000mm / s, and the number of scans was 1, forming an effective light trapping structure to improve the light absorption efficiency;

[0048] S8: Using isotropic etching, using an etching solution with a mass fraction of HF of 10wt% and a mass fraction of HNO3 of 20wt%, remove the mask SiO2 remaining after laser treatment within 2 minutes. x The molten layer and damage on the surface of the phosphorus-doped poly silicon layer are removed, and the PSG layer on the back side is removed to improve the surface quality;

[0049] Among them, the depth of the concave structure formed by laser texturing is between the mask SiO x The thickness of the layer is between the sum of the thickness of the film layer and the thickness of the phosphorus-doped poly silicon layer, that is, the thickness of the poly silicon layer removed by laser texturing is 110nm, so as to ensure that after removing the molten layer and damage left by the laser, a light trapping structure can appear on the phosphorus-doped poly silicon layer;

[0050] S9: Remove the N-poly and BSG layers on the back of the silicon wafer to further optimize the battery structure;

[0051] S10: Deposition of AlO on the back side x Passivation film and SiN x Anti-reflection film to improve the stability and optical performance of the battery;

[0052] S11: Print the back electrode and sinter it to make the electrode form a good ohmic contact with the silicon wafer to ensure the electrical performance of the battery.

[0053] Example 2

[0054] This embodiment provides a method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell. Figure 1 As shown, the preparation method comprises the following steps:

[0055] S1: The selected resistivity is 5Ω / cm 2 2. N-type single crystal silicon wafers with a thickness of 200 μm are treated with double-sided alkaline polishing using NaOH to remove the damaged layer and impurities on the surface of the silicon wafer, making the surface of the silicon wafer smooth and clean, providing a good foundation for subsequent processes;

[0056] S2: Using BCl3 as a boron diffusion source, a diffusion deposition process is performed at 1000°C for 60 minutes to diffuse boron atoms into the silicon wafer, forming a boron-doped single-crystalline silicon layer and a PN junction with the N-type silicon wafer. In this process, the flow rate, pressure and other parameters of the boron diffusion source are precisely controlled to ensure that the square resistance of the boron-doped single-crystalline silicon layer reaches 200Ω / cm 2 , with a thickness of 1.5μm, thus achieving good electrical properties;

[0057] S3: removing the boron-doped single crystal silicon layer and the BSG layer that are extended on the front and side surfaces of the silicon wafer;

[0058] S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front side of the silicon wafer; firstly, using the LPCVD (low pressure chemical vapor deposition) method, growing a tunneling oxide layer and a Poly layer with a thickness of 2.0 nm on the front side of the silicon wafer; then loading the silicon wafer into a tubular phosphorus diffusion furnace, using POCl3 diffusion to diffuse phosphorus on the back side of the silicon wafer and annealing, so that a phosphorus-doped Poly silicon layer with a thickness of 100 nm is formed on the back side, and the phosphorus doping concentration in the phosphorus-doped Poly layer is 2.0E21, ensuring that a good poly-Si / SiO2 passivation contact structure is formed on the front side of the silicon wafer;

[0059] S5: Remove the PSG layer on the front side of the silicon wafer to avoid its interference with subsequent processes and battery performance;

[0060] S6: Use PECVD technology to deposit mask SiO on the front side of the silicon wafer x layer, the deposition temperature was set at 600°C, the deposition time was 60 min, and the mask SiO x The layer thickness is 300nm; by adjusting the deposition parameters, a suitable mask SiO x layer quality and thickness;

[0061] S7: Picosecond laser was used to prepare the array hole texture surface, the hole pitch was controlled at 60μm, the reflectivity reached 15%, the single pulse energy was 100uJ, the pulse frequency was 3000kHz, the scanning speed was 30000mm / s, and the number of scans was 1, forming an effective light trapping structure to improve the light absorption efficiency;

[0062] S8: Using isotropic etching, using an etching solution with a mass fraction of HF of 60wt% and a mass fraction of HNO3 of 80wt%, remove the mask SiO2 remaining after laser treatment within 5 minutes. x The molten layer and damage on the surface of the phosphorus-doped poly silicon layer are removed, and the PSG layer on the back side is removed to improve the surface quality;

[0063] The depth of the concave structure formed by laser texturing is between the thickness of the mask layer deposited on the surface and the sum of the thickness of the film layer and the thickness of the phosphorus-doped poly silicon layer, that is, the thickness of the poly silicon layer removed by laser texturing is 350nm, so as to ensure that after removing the molten layer and damage left by the laser, a light trapping structure can appear on the phosphorus-doped poly silicon layer;

[0064] S9: Remove the N-poly and BSG layers on the back of the silicon wafer to further optimize the battery structure;

[0065] S10: Deposition of SiN on the back side x Passivation film and SiO x Anti-reflection film to improve the stability and optical performance of the battery;

[0066] S11: Print the back electrode and sinter it to make the electrode form a good ohmic contact with the silicon wafer to ensure the electrical performance of the battery.

[0067] Example 3

[0068] This embodiment provides a method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell. Figure 1 As shown, the preparation method comprises the following steps:

[0069] S1: The selected resistivity is 2Ω / cm 2 , N-type single crystal silicon wafers with a thickness of 150μm are double-sided alkaline polished using TMAH to remove the damaged layer and impurities on the surface of the silicon wafer, making the surface of the silicon wafer flat and smooth, providing a good foundation for subsequent processes;

[0070] S2: Using BCl3 as a boron diffusion source, a diffusion deposition process is performed at 900°C for 40 minutes to diffuse boron atoms into the silicon wafer, forming a boron-doped single-crystalline silicon layer and a PN junction with the N-type silicon wafer. In this process, the flow rate, pressure and other parameters of the boron diffusion source are precisely controlled to ensure that the square resistance of the boron-doped single-crystalline silicon layer reaches 300Ω / cm 2 , with a thickness of 1.0 μm, thus achieving good electrical properties;

[0071] S3: removing the boron-doped single crystal silicon layer and the BSG layer that are extended on the front and side surfaces of the silicon wafer;

[0072] S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front side of the silicon wafer; firstly, using a PVD (physical vapor deposition) method, growing a tunneling oxide layer and a Poly layer with a thickness of 1.5 nm on the front side of the silicon wafer; then loading the silicon wafer into a tubular phosphorus diffusion furnace, using POCl3 diffusion to diffuse phosphorus on the back side of the silicon wafer and annealing, so that a phosphorus-doped Poly silicon layer with a thickness of 60 nm is formed on the back side, and the phosphorus doping concentration in the phosphorus-doped Poly layer is 1.0E21, ensuring that a good poly-Si / SiO2 passivation contact structure is formed on the front side of the silicon wafer;

[0073] S5: Remove the PSG layer on the front side of the silicon wafer to avoid its interference with subsequent processes and battery performance;

[0074] S6: Use PECVD technology to deposit mask SiO on the front side of the silicon wafer x layer, the deposition temperature was set at 550°C, the deposition time was 40 min, and the mask SiO x The layer thickness is 200nm; by adjusting the deposition parameters, a suitable mask SiO x layer quality and thickness;

[0075] S7: Picosecond laser was used to prepare the array hole texture surface, the hole pitch was controlled at 30μm, the reflectivity reached 10%, the single pulse energy was 90uJ, the pulse frequency was 2000kHz, the scanning speed was 40000mm / s, and the number of scans was 1, forming an effective light trapping structure to improve the light absorption efficiency;

[0076] S8: Using isotropic etching, using an etching solution with a mass fraction of HF of 35wt% and a mass fraction of HNO3 of 50wt%, remove the mask SiO2 remaining after laser treatment within 3min. x The molten layer and damage on the surface of the phosphorus-doped poly silicon layer are removed, and the PSG layer on the back side is removed to improve the surface quality;

[0077] Among them, the depth of the concave structure formed by laser texturing is between the mask SiO x The thickness of the layer is between the sum of the thickness of the film layer and the thickness of the phosphorus-doped poly silicon layer, that is, the thickness of the poly silicon layer removed by laser texturing is 230nm, so as to ensure that after removing the molten layer and damage left by the laser, a light trapping structure can appear on the phosphorus-doped poly silicon layer;

[0078] S9: Remove the N-poly and BSG layers on the back side to further optimize the battery structure;

[0079] S10: Deposition of SiO on the back side x Passivation film and SiN x Anti-reflection film to improve the stability and optical performance of the battery;

[0080] S11: Print the back electrode and sinter it to make the electrode form a good ohmic contact with the silicon wafer to ensure the electrical performance of the battery.

[0081] Example 4

[0082] This embodiment provides a method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell, the preparation method comprising the following steps:

[0083] S1: The resistivity is 5Ω / cm 2 2. N-type single crystal silicon wafers with a thickness of 200 μm are treated with double-sided alkaline polishing using NaOH to remove the damaged layer and impurities on the surface of the silicon wafer, making the surface of the silicon wafer smooth and clean, providing a good foundation for subsequent processes;

[0084] S2: Using BCl3 as a boron diffusion source, a diffusion deposition process is performed at 1000°C for 60 minutes to diffuse boron atoms into the silicon wafer, forming a boron-doped single-crystalline silicon layer and a PN junction with the N-type silicon wafer. In this process, the flow rate, pressure and other parameters of the boron diffusion source are precisely controlled to ensure that the square resistance of the boron-doped single-crystalline silicon layer reaches 200Ω / cm 2 , with a thickness of 1.5μm, thus achieving good electrical properties;

[0085] S3: removing the boron-doped single crystal silicon layer and the BSG layer that are extended on the front and side surfaces of the silicon wafer;

[0086] S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front side of the silicon wafer; firstly, using the PECVD (plasma enhanced chemical vapor deposition) method, growing a tunneling oxide layer and a Poly layer with a thickness of 2.0 nm on the front side of the silicon wafer; then loading the silicon wafer into a tubular phosphorus diffusion furnace, using POCl3 diffusion to diffuse phosphorus on the back side of the silicon wafer and annealing, so that a phosphorus-doped Poly silicon layer with a thickness of 100 nm is formed on the back side, and the phosphorus doping concentration in the phosphorus-doped Poly layer is 2.0E21, ensuring that a good poly-Si / SiO2 passivation contact structure is formed on the front side of the silicon wafer;

[0087] S5: Remove the PSG layer on the front side of the silicon wafer to avoid its interference with subsequent processes and battery performance;

[0088] S6: Use PECVD technology to deposit mask SiO on the front side of the silicon wafer x layer, the deposition temperature was set at 600°C, the deposition time was 60 min, and the mask SiO x The layer thickness is 300nm; by adjusting the deposition parameters, a suitable mask SiO x layer quality and thickness;

[0089] S7: Picosecond laser was used to prepare the array hole texture surface, the hole pitch was controlled at 60μm, the reflectivity reached 15%, the single pulse energy was 100uJ, the pulse frequency was 3000kHz, the scanning speed was 30000mm / s, and the number of scans was 1, forming an effective light trapping structure to improve the light absorption efficiency;

[0090] S8: Using isotropic etching, using an etching solution with a mass fraction of HF of 60wt% and a mass fraction of HNO3 of 80wt%, remove the mask SiO2 remaining after laser treatment within 5 minutes. x The molten layer and damage on the surface of the phosphorus-doped poly silicon layer are removed, and the PSG layer on the back side is removed to improve the surface quality;

[0091] Among them, the thickness of the poly silicon layer removed during the laser texturing process is 410nm;

[0092] S9: Remove the N-poly and BSG layers on the back of the silicon wafer to further optimize the battery structure;

[0093] S10: Deposition of SiN on the back side x Passivation film and SiO x Anti-reflection film to improve the stability and optical performance of the battery;

[0094] S11: Print the back electrode and sinter it to make the electrode form a good ohmic contact with the silicon wafer to ensure the electrical performance of the battery.

[0095] Example 5

[0096] This embodiment provides a method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell, the preparation method comprising the following steps:

[0097] S1: The selected resistivity is 0.5Ω / cm 2 , N-type single crystal silicon wafers with a thickness of 100μm are treated with double-sided alkaline polishing using KOH to remove the damaged layer and impurities on the surface of the silicon wafer, making the surface of the silicon wafer smooth and clean, providing a good foundation for subsequent processes;

[0098] S2: Using BCl3 as a boron diffusion source, a diffusion deposition process is performed at 800°C for 20 minutes to diffuse boron atoms into the silicon wafer, forming a boron-doped single-crystalline silicon layer and a PN junction with the N-type silicon wafer. In this process, the flow rate, pressure and other parameters of the boron diffusion source are precisely controlled to ensure that the square resistance of the boron-doped single-crystalline silicon layer reaches 400Ω / cm 2 , with a thickness of 0.5μm, thus achieving good electrical properties;

[0099] S3: removing the boron-doped single crystal silicon layer and the BSG layer that are extended on the front and side surfaces of the silicon wafer;

[0100] S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front side of the silicon wafer; firstly, using the LPCVD (low pressure chemical vapor deposition) method, growing a tunneling oxide layer and a Poly layer with a thickness of 1.0 nm on the front side of the silicon wafer; then loading the silicon wafer into a tubular phosphorus diffusion furnace, using POCl3 diffusion to diffuse phosphorus on the back side of the silicon wafer and annealing, so that a phosphorus-doped Poly silicon layer with a thickness of 20 nm is formed on the back side, and the phosphorus doping concentration in the phosphorus-doped Poly layer is 0.5E21, ensuring that a good poly-Si / SiO2 passivation contact structure is formed on the front side of the silicon wafer;

[0101] S5: Remove the PSG layer on the front side of the silicon wafer to avoid its interference with subsequent processes and battery performance;

[0102] S6: Use LPCVD technology to deposit mask SiO on the front side of the silicon wafer x layer, the deposition temperature was set at 500°C, the deposition time was 20 min, and the mask SiO x The layer thickness is 100nm; by adjusting the deposition parameters, a suitable mask SiO x layer quality and thickness;

[0103] S7: Picosecond laser was used to prepare the array hole texture surface, the hole pitch was controlled at 0μm, the reflectivity reached 5%, the single pulse energy was 80uJ, the pulse frequency was 1000kHz, the scanning speed was 50000mm / s, and the number of scans was 1, forming an effective light trapping structure to improve the light absorption efficiency;

[0104] S8: Using isotropic etching, using an etching solution with a mass fraction of HF of 10wt% and a mass fraction of HNO3 of 20wt%, remove the mask SiO2 remaining after laser treatment within 2 minutes. x The molten layer and damage on the surface of the phosphorus-doped poly silicon layer are removed, and the PSG layer on the back side is removed to improve the surface quality;

[0105] The thickness of the poly silicon layer removed during the laser texturing process is 90nm;

[0106] S9: Remove the N-poly and BSG layers on the back of the silicon wafer to further optimize the battery structure;

[0107] S10: Deposition of AlO on the back side x Passivation film and SiN x Anti-reflection film to improve the stability and optical performance of the battery;

[0108] S11: Print the back electrode and sinter it to make the electrode form a good ohmic contact with the silicon wafer to ensure the electrical performance of the battery.

[0109] Comparative Example 1

[0110] The difference between this comparative example and Example 1 is that there is no S6 front deposition mask SiO x The laser texturing process of S7 is directly performed, and the other preparation methods and parameters are consistent with those in Example 1.

[0111] Comparative Example 2

[0112] The difference between this comparative example and Example 1 is that S7 adopts chemical etching texturing process instead of laser texturing, and the other preparation methods and parameters are consistent with Example 1.

[0113] Comparative Example 3

[0114] The difference between this comparative example and Example 1 is that the laser texturing process of S7 is performed first, and then the process of forming a poly-Si / SiO2 passivation contact structure of S4 is performed. The rest of the preparation methods and parameters are consistent with Example 1.

[0115] Performance Testing

[0116] The electrical performance of the crystalline silicon bottom cells of the perovskite crystalline silicon tandem solar cells prepared in Examples 1-5 and Comparative Examples 1-3 was tested.

[0117] The test method is: using an IV tester to measure various parameters of the solar cell, and the results are shown in Table 1.

[0118] Table 1 Test results of battery of embodiment and comparative example

[0119]

[0120] Performance test data conclusion analysis:

[0121] As can be seen from the above table, the present invention first prepares a poly-Si / SiO2 passivation contact structure and deposits a mask SiO2 of a certain thickness on the surface of the passivation contact structure. x After the layer is formed, a laser texturing process is performed, which effectively solves the problems of optical parasitic absorption and current loss caused by the thick poly silicon layer in the prior art. In addition, the silicon bottom cell prepared by the preparation method provided by the present invention has excellent conversion efficiency.

[0122] First, compared with Example 4, the surface N-poly of Examples 1-3 has a good passivation effect, and the battery opening voltage and conversion efficiency are higher; compared with Example 5, the surface velvet structure of Example 1 has a lower reflectivity, and the short-circuit current of the battery is higher.

[0123] Secondly, comparing Example 1 with Comparative Examples 1-3, Comparative Example 1 does not have the front deposition mask SiO xThe velvet structure prepared by laser may cause deep damage to the N-poly structure, reduce the passivation effect of N-poly, and the battery opening voltage is low; in comparative example 2, S7 adopts chemical corrosion texturing process instead of laser texturing process. Since the chemical process for preparing the velvet structure has a fast reaction speed and is difficult to control, the passivation layer may be destroyed, resulting in a very low opening voltage; in comparative example 3, the passivation contact structure is prepared after texturing, which causes too much damage to the silicon wafer surface and the battery opening voltage is low.

[0124] The present invention prepares a poly-Si / SiO2 passivation contact structure on the polished surface first, thereby reducing the composite of the front surface to a minimum. At the same time, the phosphorus-doped poly silicon layer has a very thin film thickness, which greatly reduces the parasitic absorption of the long-wave band. Then, a laser is used to prepare a light-trapping structure based on the poly-Si / SiO2 passivation contact structure, thereby avoiding the composite problem caused by first making a texture and then preparing the passivation structure. At the same time, a laser is used to prepare the array hole texture light-trapping structure, so that the surface morphology of the silicon wafer is very uniform, which is more conducive to the subsequent deposition of a perovskite layer on its surface. In addition, considering the problem of the thin film thickness of the phosphorus-doped poly silicon layer, the present invention deposits a layer of a mask SiO2 film on its surface that has a passivation effect and is easy to clean. x During the laser preparation of the array hole texture surface, the phosphorus-doped poly silicon layer is protected to prevent the laser from burning through the poly silicon layer and reduce the reflectivity of sunlight. The depth of the concave structure formed after laser texture preparation needs to be between the mask SiO deposited on the surface. x The layer thickness and the sum of the layer thickness and the phosphorus-doped poly silicon layer thickness are between to ensure that after removing the molten layer and damage left by the laser, a light trapping structure can appear on the phosphorus-doped poly silicon layer to increase the light incidence rate.

[0125] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description here should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in the field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell, characterized in that: The steps include: S1: Double-sided polishing of N-type silicon wafer; S2: Diffusing boron on the back side of the silicon wafer to form a boron-doped single crystal silicon layer; S3: removing the BSG layer on the front side of the silicon wafer; S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front side of the silicon wafer; S5: removing the PSG layer on the front side of the silicon wafer; S6: Deposit mask SiO on the front side of the silicon wafer x layer; S7: On the mask SiO x The surface of the layer is subjected to laser texturing; S8: Remove the remaining mask SiO after laser removal x The melt layer and damage on the surface of the layer and phosphorus-doped poly silicon layer, as well as the PSG layer on the back side; S9: remove the N-poly and BSG layers plated on the back of the silicon wafer; S10: backside deposition of passivation and anti-reflection film; S11: Printing the back electrode and sintering.

2. The preparation method according to claim 1, characterized in that: The depth of the recessed structure formed by laser texturing in S7 is greater than that of the mask SiO x The thickness of the layer is less than that of the SiO mask in S6 x The sum of the thickness of the layer and the poly silicon layer doped with phosphorus in S4.

3. The preparation method according to claim 1, characterized in that: The resistivity of the N-type silicon wafer in S1 is 0.5-5Ω / cm 2 , thickness is 100-200μm.

4. The preparation method according to claim 1, characterized in that: The temperature of the boron diffusion deposition in S2 is 800-1000°C, the time is 20-60 minutes, and the square resistance of the boron-doped single crystal silicon layer is 200-400Ω / cm 2 The thickness of the boron-doped single crystal silicon layer is 0.5 to 1.5 μm.

5. The preparation method according to claim 1, characterized in that: The thickness of the tunneling oxide layer in S4 is 1-2 nm; the thickness of the phosphorus-doped poly silicon layer is 20-100 nm, and the phosphorus doping concentration ranges from (0.1-2.0)E21.

6. The preparation method according to claim 1, characterized in that: In S6, the deposition temperature is 500-600°C, the deposition time is 20-60 minutes, and the mask SiO x The thickness of the layer is 100 to 300 nm.

7. The preparation method according to claim 1, characterized in that: The single pulse energy of the laser in S7 is 80-100uJ, the pulse frequency is 1000-3000kHz, the scanning speed is 30000-50000mm / s, and the number of scanning times is 1 time.

8. The preparation method according to claim 1, characterized in that: The S8 is an isotropic etching method, using an etching solution with a HF mass fraction of 10-60wt% and a HNO3 mass fraction of 20-80wt%, to remove the mask SiO2 remaining after the laser within 2-5 minutes. x The melted layer and damage on the surface of the phosphorus-doped poly silicon layer are removed, and the back-side plated PSG layer is removed at the same time.

9. A crystalline silicon bottom cell, characterized in that: The crystalline silicon bottom cell is prepared by the preparation method according to any one of claims 1 to 8 and is applied to perovskite crystalline silicon stacked solar cells.

10. The crystalline silicon bottom cell according to claim 9, characterized in that: The crystalline silicon bottom cell comprises: N-type silicon wafer, the front side of the N-type silicon wafer includes a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer in sequence, and the back side of the N-type silicon wafer includes a boron-doped single crystal silicon layer, a passivation and anti-reflection film layer, and a back electrode in sequence; a light trapping structure appears on the surface of the phosphorus-doped poly silicon layer.

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