Three-dimensional vertical co-spiral inductor

Abstract

One or more aspects include devices, systems, and methods for making the devices, systems that include co-spiral inductors. In at least one aspect, a co-spiral inductor includes a plurality of turns, each turn of the plurality of turns being vertically and horizontally shifted from a next successive turn. The plurality of turns is formed from traces formed on different metal layers on the substrate. The co-spiral inductor includes a plurality of insulators configured to electrically insulate each of the plurality of turns. The co-spiral inductor includes a plurality of interconnects configured to couple each turn of the plurality of turns to at least one other turn.

Description

[0001] Public domain

[0002] The present disclosure relates generally to semiconductor devices, including electronic devices incorporating semiconductor devices, and more particularly, but not exclusively, to inductors, three-dimensional (3D) inductors, related devices, and manufacturing techniques thereof.

[0003] background

[0004] Integrated circuit (IC) technology has made great strides in increasing computing power through the miniaturization of active components. Various packaging technologies (such as flip-chip devices) can be found in many electronic devices, including processors, servers, radio frequency (RF), RF front end (RFFE), and other integrated circuits. Advanced packaging and processing technologies allow system-on-chip (SOC) devices that may include multiple functional blocks, each of which is designed to perform a specific function, such as, for example, microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., 5G, LTE, Wi-Fi, Bluetooth, and other communications), etc.

[0005] Additionally, passive components can have a significant impact on the integrated circuit and / or packaging technology. For example, high-density inductors can be used to reduce the design footprint of RFFE applications and increase inductor density. The IC / packaging technology will have many metal layers for inductor routing. However, higher density inductors can have the key disadvantage of reduced self-resonant frequency (SRF), which can affect the inductor and overall IC performance.

[0006] Accordingly, a need exists for systems, apparatus, and methods, including those provided by the disclosure below, that overcome the deficiencies of conventional inductor designs.

[0007] Overview

[0008] A simplified overview of one or more aspects and / or examples associated with each device and method disclosed herein is given below. As such, the following overview should neither be considered an exhaustive overview of all conceived aspects and / or examples, nor should the following overview be considered to identify key or decisive elements associated with all conceived aspects and / or examples or to delineate the scope associated with any particular aspect and / or example. Accordingly, the sole purpose of the following overview is to present certain concepts related to one or more aspects and / or examples of the device and method disclosed herein in a simplified form prior to the detailed description given below.

[0009] In one aspect, a device comprising a co-spiral inductor includes: a plurality of turns, each turn of the plurality of turns being vertically and horizontally displaced from a next successive turn, wherein the plurality of turns are formed by traces formed on different metal layers on a substrate; a plurality of insulators configured to electrically insulate each turn of the plurality of turns; and a plurality of interconnects configured to couple each turn of the plurality of turns to at least one other turn.

[0010] In one aspect, a method for manufacturing a device including a co-spiral inductor includes: forming a plurality of turns, each turn of the plurality of turns being vertically and horizontally displaced from a next successive turn, wherein the plurality of turns are formed by traces formed on different metal layers on a substrate; forming a plurality of insulators configured to electrically insulate each turn of the plurality of turns; and forming a plurality of interconnects configured to couple each turn of the plurality of turns to at least one other turn.

[0011] Other features and advantages associated with the various devices and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A more complete appreciation of the various aspects of the present disclosure and many of its attendant advantages will be readily obtained as the same becomes better understood by reference to the following detailed description considered in conjunction with the accompanying drawings, which are presented for purposes of illustration only and do not constitute a limitation of the present disclosure in any way.

[0014] Figure 1 A partial cross-sectional view of an apparatus in accordance with one or more aspects of the present disclosure is illustrated.

[0015] Figure 2 A perspective view of a co-spiral inductor is illustrated in accordance with one or more aspects of the present disclosure.

[0016] Figure 3 Illustrated is a graph comparing the self-resonant frequency (SRF) and quality factor (Q) of various inductor designs in accordance with one or more aspects of the present disclosure.

[0017] Figure 4 A perspective view of a co-spiral inductor is illustrated in accordance with one or more aspects of the present disclosure.

[0018] Figure 5 Explained the comparison Figure 2 and Figure 4 A graph of the self-resonant frequency (SRF) and quality factor (Q) of an inductor design.

[0019] Figure 6 A partial cross-sectional view of an apparatus in accordance with one or more aspects of the present disclosure is illustrated.

[0020] Figure 7 An apparatus including a co-spiral inductor in accordance with one or more aspects of the present disclosure is illustrated.

[0021] Fig. 8A -D illustrates a partial cross-sectional view and a perspective view of an apparatus according to one or more aspects of the present disclosure.

[0022] Fig. 9 Components of an integrated device in accordance with one or more aspects of the present disclosure are illustrated.

[0023] Fig.10 A flow chart illustrating a method in accordance with one or more aspects of the present disclosure.

[0024] Fig.11 An exemplary mobile device in accordance with one or more aspects of the present disclosure is illustrated.

[0025] Fig.12 Various electronic devices are illustrated that may be integrated with any of the aforementioned devices according to one or more aspects of the present disclosure.

[0026] As a matter of practice, the features depicted in the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily enlarged or reduced for clarity. As a matter of practice, certain drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular device or method. In addition, similar reference numerals are used throughout the specification and drawings to indicate similar features.

[0027] Detailed Description

[0028] Various aspects of the present disclosure are illustrated in the following description and related drawings for specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of the present teachings. Additionally, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted so as not to obscure the relevant details taught in the present disclosure.

[0029] In some of the described example implementations, the following examples are identified where various component structures and portions of operations may be obtained from known conventional techniques and then arranged according to one or more exemplary embodiments. In such examples, internal details of portions of known conventional component structures and / or operations may be omitted to help avoid potential confusion of the concepts illustrated in the illustrative embodiments disclosed herein.

[0030] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms of "a", "a", and "the" are intended to also include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "having", "including" and / or "containing" when used herein indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0031] According to at least some of the various aspects disclosed, a 3D tapered vertical co-spiral inductor design for mitigating / solving SRF improvements at high density inductors. The requirements for implementing the present invention are (1) high-Q / high density inductors with higher SRF and smaller form factor, (2) more inductor routing layers (e.g., four thick metal layers) for higher density, and (3) small design footprint driven by high density inductors.

[0032] In accordance with at least some of the various aspects disclosed, designs for high density / high Q inductors with high SRF are provided. A 3D vertical co-spiral inductor is designed to obtain a high density inductor. A 3D tapered vertical co-spiral inductor is designed to increase the SRF. The outer metal trace thickness (outside the co-spiral aperture) is increased by the disclosed metal stack and associated manufacturing methods. In accordance with at least some of the various aspects disclosed, improvements include an inductor Q factor of more than 11% and a tolerable SRF reduction (4%) and inductance reduction (2%).

[0033] Figure 1A partial cross-sectional view of a device 100 according to one or more aspects of the present disclosure is illustrated. As illustrated, the device 100 may include a substrate 110 (e.g., a die, a filter die, an integrated passive device) and a co-spiral inductor 200, which in some aspects may be formed as part of the substrate (e.g., in a flip-chip configuration). Additional details will be discussed in the following disclosure. A first set of connectors 120 may be die bumps, copper pillars, or any suitable connectors configured to couple the substrate 110 to a packaging substrate 130, which in some aspects may include a laminate substrate. The packaging substrate 130 is coupled to a printed circuit board (PCB) 150 via a second set of connectors 140, which may be solder balls or any suitable connectors. In some aspects, the substrate 110 may be configured as an RFFE or other RF circuit including the co-spiral inductor 200. In some aspects, the packaging substrate 130 is configured to couple the substrate (e.g., fan out, change spacing, etc.) to the PCB 150 to form part of a larger device (e.g., a cellular phone, a tablet device, other mobile devices, etc.), as is known in the art. It will be appreciated that the illustration of the device 100 is provided solely to aid in the discussion of the various aspects disclosed and should not be construed as limiting the various aspects disclosed. For example, in some aspects, the device 100 may not have a PCB 150 or may have multiple PCBs 150, and / or packaging substrates 130 and / or substrates 110. The packaging substrate 130 may include additional active or passive components and may provide routing between elements of the substrate 110. Further, in some aspects, the device 100 may not have a packaging substrate 130, and the first set of connectors 120 may be directly coupled to the PCB 150. Accordingly, the various aspects disclosed are not limited to Figure 1 Examples explained.

[0034] Figure 2A perspective view of a co-spiral inductor 200 according to one or more aspects of the present disclosure is illustrated. In the illustrated configuration, the co-spiral inductor 200 has a first terminal 201 and a second terminal 202 that form a coupling point for the co-spiral inductor 200. The first terminal is part of a first turn 210 of the co-spiral inductor 200, which, as illustrated, is formed by a first trace in a first metal layer. As illustrated, a second turn 220 of the co-spiral inductor 200 is formed by a second trace in a second metal layer. As illustrated, a third turn 230 of the co-spiral inductor 200 is formed by a third trace in a third metal layer. As illustrated, a fourth turn 240 of the co-spiral inductor 200 is formed by a fourth trace in a fourth metal layer and terminates at the second terminal 202. The first turn 210 is coupled in series with the second turn 220 through a first interconnect 215. The second turn 220 is coupled in series with the third turn 230 through a second interconnect 225. The fourth turn 240 is coupled in series with the third turn 230 through the third interconnect 235. Accordingly, as illustrated, the co-spiral inductor 200 has four turns coupled in series. Additionally, it will be understood that each turn of the co-spiral inductor 200 is vertically and horizontally displaced from the next successive turn, so that the turn has a generally conical or stepped 3D form. Further, the traces are generally concentric in form, so that the co-spiral inductor 200 has generally conical and concentric turns. In some aspects, this configuration may be referred to as a vertical 3D co-spiral inductor or generally referred to as a co-spiral inductor. However, it will be understood that the various aspects disclosed are not limited to the illustrated configuration. For example, various aspects may include more or fewer traces / turns. The traces / turns may be hexagonal, circular, square, rectangular, or any other geometric shape. In some aspects, the co-spiral inductor 200 may have different geometries for different traces / turns. In some aspects, one or more traces / turns may be aligned vertically and / or horizontally. In some aspects, two or more traces / turns may be coupled in parallel. Accordingly, the various aspects disclosed are not limited to Figure 2 The illustrated examples provided in .

[0035] Figure 3A graph comparing the self-resonant frequency (SRF) and quality factor (Q) of various inductor designs according to one or more aspects of the present disclosure is illustrated. As discussed above, the various co-spiral inductor configurations disclosed herein provide increased SRF and high-Q inductors. Graph 310 illustrates a comparison of two conventional spiral inductors (Inductor 1 and Inductor 2) with Inductor 3, which is a co-spiral inductor design (e.g., co-spiral inductor 200). In graph 310, lines 311, 312, and 313 illustrate the change in inductance of Inductors 1, 2, and 3 with respect to frequency, respectively. As can be seen from graph 310, the SFR inductance peaks of Inductors 1 and Inductor 2 are significantly lower than the SFR inductance peak of Inductor 3. In graph 320, lines 321, 322, and 323 illustrate the change in Q of Inductors 1, 2, and 3 with respect to frequency, respectively. As can be seen from graph 320, as frequency increases, the quality factor (Q) of Inductor 1 and Inductor 2 is lower than that of Inductor 3. Specifically, the co-spiral inductor design of Inductor 3 can provide Q>30 over a much larger frequency range than conventional spiral Inductors 1 and 2.

[0036] Figure 4A perspective view of a co-spiral inductor 400 in accordance with one or more aspects of the present disclosure is illustrated. In the illustrated configuration, the co-spiral inductor 400 has a first terminal 401 and a second terminal 402 that form a coupling point for the co-spiral inductor 400. The first terminal is a portion of a first turn 410 of the co-spiral inductor 400, which, as illustrated, is formed by a first trace in a first metal layer. A second turn 420 of the co-spiral inductor 400 is formed by a second trace in a second metal layer. A turn 430 of the co-spiral inductor 400 is at least partially formed by a third trace in a third metal layer. A fourth turn 440 of the co-spiral inductor 400 is at least partially formed by a fourth trace in a fourth metal layer and terminates at the second terminal 402. The first turn 410 is coupled in series with the second turn 420 through a first interconnect 415. The second turn 420 is coupled in series with the third turn 430 through a second interconnect 425. Fourth turn 440 is coupled in series with third turn 430 through third interconnect 435. Accordingly, as illustrated, co-spiral inductor 400 has four turns coupled in series. Further, it will be appreciated that at least two turns of co-spiral inductor 400 are vertically and horizontally displaced from the next successive trace, and the traces have a generally conical or stepped 3D form. However, co-spiral inductor 400 has one or more turns (e.g., turn 440 and turn 430) comprising multiple metal layers coupled together. For example, as illustrated in detail section 450, third turn 430 may include trace 432 on the second metal layer and trace 436 on the third metal layer, which are coupled through trace 434 (e.g., via bar) on a first via layer disposed between the second metal layer and the third metal layer. Additionally, as illustrated in detail section 450, fourth turn 440 may include trace 442 on the third metal layer and trace 446 on the fourth metal layer, which are coupled by trace 444 (e.g., via bar) on the second via layer disposed between the third metal layer and the fourth metal layer. Accordingly, in some aspects, at least one turn (e.g., third turn 430 and fourth turn 440 as illustrated) is partially formed by the same metal layer as at least one other turn (e.g., 436 and 442). Even though a portion of the turns are formed by stacked metal layers, the traces are generally concentric in form and still have vertical (at least for a portion of each turn) and horizontal offsets, so that co-spiral inductor 400 has generally conical and concentric turns. In some aspects, this configuration may be referred to as a vertical 3D co-spiral inductor or generally referred to as a co-spiral inductor. However, it will be understood that the disclosed aspects are not limited to the illustrated configuration. For example, the various aspects may include more or fewer traces / turns. The traces / turns may be hexagonal, circular, square, rectangular, or any other geometric shape. In some aspects, co-spiral inductor 400 may have different geometries for different traces / turns. In some aspects, one or more traces / turns may be aligned vertically and / or horizontally.In some aspects, two or more traces / turns may be coupled in parallel. Further, there may be more or fewer stacked metal layers in the outer turns than in the illustrated example. Accordingly, the disclosed aspects are not limited. Figure 4 The illustrated examples provided in .

[0037] Figure 5 Illustrate a comparison of one or more aspects of the present disclosure Figure 2 Inductor 3 and Figure 4 Graph of self-resonant frequency (SRF) and quality factor (Q) of inductor design for inductor 4. As discussed above, the various co-spiral inductor configurations disclosed herein provide increased SRF and high-Q inductors. Graph 510 illustrates a comparison of two co-spiral inductors, inductor 3 (e.g., co-spiral inductor 200) and inductor 4 (e.g., co-spiral inductor 400). In graph 510, lines 513 and 514 illustrate the change in inductance of inductors 3 and 4 with respect to frequency, respectively. As can be seen from graph 510, the SFR inductance peak of inductor 4 is slightly lower than the SFR inductance peak of inductor 3, however, both are significantly higher than the conventional inductors discussed previously. Graph 515 illustrates the spread curve of inductance versus frequency for inductors 3 and 4 around the frequency of interest (e.g., 2 GHz to 4 GHz). As can be seen from lines 513 and 514, the inductance difference is relatively small over the illustrated frequency range, which is well below the SFR inductance peak. In graph 520, lines 523 and 524 illustrate the change in Q of inductors 3 and 4 with respect to frequency, respectively. As can be seen from graph 520, inductor 4 has a slightly higher quality factor (Q) at lower frequencies, while inductor 3 has a slightly higher quality factor (Q) at higher frequencies. However, it will be understood that both inductor 3 and inductor 4 can provide Q>30 over a much larger frequency range than the aforementioned conventional spiral inductors 1 and 2. Graph 525 illustrates the extended curve of Q versus frequency for inductors 3 and 4 around the frequency of interest (e.g., 2 GHz to 4 GHz). As can be seen from lines 523 and 524, the quality factor (Q) of inductor 4 is improved over the illustrated frequency range. Table 1 below provides a comparison of inductors 3 and 4 according to one or more aspects of the present disclosure. As can be seen from the following table, and with Figure 5 , the SFR of inductor 4 decreases slightly (-4%), and the inductance also decreases slightly (-2%), however, the Q of inductor 4 increases by 11%.

[0038] Inductor 3 Inductor 4 Difference SRF 11.1 10.65 -4％ Inductance(nH) 5.683 5.567 -2％ Q 39.3 43.9 +11％

[0039] Table 1

[0040] It will be understood that the foregoing graphs and values ​​are provided only for illustration and discussion of the various aspects disclosed, and should not be construed as limiting the various aspects to the illustrated values ​​or configurations. These comparisons are used to generally show that the design of the co-spiral inductor 200 has an increased SFR, while the design of the co-spiral inductor 400 has an increased Q. Those skilled in the art may make changes to the design to obtain the desired results noting the trade-off of SFR for Q, as discussed herein.

[0041] Figure 6 A partial cross-sectional view of an apparatus 600 according to one or more aspects of the present disclosure is illustrated. As illustrated, the apparatus 600 may include a hybrid integrated passive (HIP) device 601 including a substrate 602 and various metal layers 612 (e.g., a back end of line (BEOL) stack or a BEOL stack and one or more redistribution layers (RDL)). The various metal layers 612 may be used to form one or more co-spiral inductors as disclosed herein. Additionally, the apparatus 600 may be coupled to a device including an active component (e.g., a CMOS IC) integrated with the HIP device 601, the HIP device 601 including the substrate 602 and various metal layers 612 that may be used to form one or more co-spiral inductors as disclosed herein. It should be understood that in various aspects, one or more HIP devices 601 may be mounted to a packaging substrate 630 via a connector 620. One or more HIP devices 601 (including SoC devices in some aspects) may be interconnected via the packaging substrate 630 to allow for increased functionality. The packaging substrate 630 (which in some aspects may include a laminate substrate) includes a connector 640 that can be used to fan out connections from one or more HIP devices 601 and allow connection to further external components and / or devices (e.g., PCBs, etc.) as known in the art. However, it will be understood that the various aspects disclosed are not limited to these illustrated components, devices, and / or arrangements. For example, according to some aspects of the present disclosure, the device can be a radio frequency (RF) filter, an RF front end (RFFE) circuit, a power combiner, a duplexer, combinations thereof, and similar components that may use one or more co-spiral inductors as disclosed herein. It will be appreciated that the illustration of the device 600 is provided solely to aid in the discussion of the various aspects disclosed and should not be construed as limiting the various aspects disclosed. For example, in some aspects, the device 600 may include additional active and / or passive components / devices or may be limited to a single component / device. Accordingly, the various aspects disclosed are not limited to Figure 6 Examples explained.

[0042] Figure 7An apparatus 700 including a co-spiral inductor according to one or more aspects of the present disclosure is illustrated. As illustrated, the apparatus 700 is configured as a duplex multiplexer having a common port P1 and two frequency specific ports P2 and P3. In the illustrated example, inductors L1, L2, L3, L4, and L5 together with capacitors C1 to C11 are configured to form a high pass filter. Inductors L1 to L5 may be low density high Q 2D spiral inductors, each of which may be formed on a separate metal layer of the apparatus 700 and may have a relatively low inductance (e.g., on the order of 0.6 nH to 1.1 nH) and Q>40. Inductors L6 and L7 together with capacitors C12 to C14 are configured to form a low pass filter. Inductors L6 to L7 may be high density high Q 3D co-spiral inductors, which may be formed on multiple metal layers of the apparatus 700, as disclosed herein. Inductors L6 to L7 may have relatively high inductance (e.g., on the order of 5 nH to 11 nH) and Q>30. Various design details and configurations of duplexer circuits are known, so further discussion will be limited. It will be understood that the example configuration of device 700 is provided merely as an example of an implementation of a co-spiral inductor as disclosed herein along with standard components and circuit designs. Accordingly, the various aspects disclosed are not limited to this example configuration.

[0043] In order to fully illustrate the various aspects of the design of the present disclosure, a manufacturing method is proposed. Other manufacturing methods are also possible, and the manufacturing method discussed is presented only to help understand the concepts disclosed herein.

[0044] Figures 8A to 8D Various partial cross-sectional and perspective views of devices according to one or more aspects of the present disclosure are illustrated. Fig. 8A, device 800 illustrates a cross-sectional inductor structure view of a co-spiral inductor 802 according to one or more aspects of the present disclosure. In the illustrated configuration, the co-spiral inductor 802 has a first turn 810, a second turn 820, a third turn 830, and a fourth turn 840 of the co-spiral inductor 802, as illustrated, the first turn 810, the second turn 820, the third turn 830, and the fourth turn 840 are each formed in a different metal layer (e.g., M1-M4, formed in BEOL only or BEOL+RDL). It will be understood that, as illustrated, the device 800 can be reversed for manufacturing to allow for the deposition of successive metal layers and insulating layers on the substrate 805 to form the co-spiral inductor 802. Accordingly, in some aspects, the co-spiral inductor 802 can be formed of a plurality of turns (e.g., 810, 820, 830, 840), wherein each turn of the plurality of turns is vertically and horizontally displaced from the next successive turn. The deposited insulating layer forms a plurality of insulators (e.g., 812, 822, 832) configured to electrically insulate each of the plurality of turns. Additionally, the manufacturing process includes forming a plurality of interconnects (e.g., 815, 825, and 835) configured to couple each of the plurality of turns to at least one other turn, the plurality of interconnects being at least partially formed by vias V1-V3, respectively. In one or more aspects, the plurality of turns (e.g., 810, 820, 830, 840) and the plurality of interconnects (e.g., 815, 825, and 835) can be formed of any suitable conductor, and in some aspects can be formed of one or more of the following: copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (Pl), aluminum (Al), titanium (Ti), tin (Sn), and alloys or combinations thereof. In one or more aspects, a plurality of insulators (e.g., 812, 822, 832) are formed of one or more of the following: silicon dioxide (SiO2), an organic polymer dielectric, a polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or a silicone-based polymer dielectric. In one or more aspects, substrate 805 is formed of one or more of the following: silicon (Si), high resistivity silicon (HRSi), glass, aluminum oxide (alumina), a mixture or combination thereof. The various materials provided herein are merely examples of suitable materials, rather than an exhaustive list of all suitable materials. Accordingly, the various aspects disclosed are not limited to the example materials provided herein, and those skilled in the art may substitute other materials having the same function, such as conductors, insulators, etc.

[0045] Figure 8BA cross-sectional inductor structure view and corresponding perspective view of a co-spiral inductor 802 according to one or more aspects of the present disclosure are illustrated. In the illustrated configuration, the device 800 has been flipped to allow for subsequent processing, connection to additional components (e.g., a package substrate, a PCB, etc.). Accordingly, in some aspects, the co-spiral inductor 802 includes a plurality of turns (e.g., 810, 820, 830, 840), a plurality of insulators (e.g., 812, 822, 832), and a plurality of interconnects (e.g., 815, 825, 835), as described with respect to Fig. 8A As discussed. As illustrated in the perspective view, in the co-spiral inductor 802, the first turn 810 is coupled in series with the second turn 820 through the first interconnect 815. The second turn 820 is coupled in series with the third turn 830 through the second interconnect 825. The fourth turn 840 is coupled in series with the third turn 830 through the third interconnect 835. Accordingly, as illustrated, the co-spiral inductor 802 has four turns coupled in series. Additionally, it will be understood that each turn of the co-spiral inductor 802 is vertically and horizontally displaced from the next successive turn, so that the turn has a generally conical or stepped 3D form. Further, the traces are generally concentric in form, so that the co-spiral inductor 802 has generally conical and concentric turns. However, it will be understood that the various aspects disclosed are not limited to the illustrated configuration. For example, various aspects may include more or fewer traces / turns. The traces / turns may be hexagonal, circular, square, rectangular, or any other geometric shape. In some aspects, the co-spiral inductor 802 can have different geometries for different traces / turns. In some aspects, one or more traces / turns can be aligned vertically and / or horizontally. In some aspects, two or more traces / turns can be coupled in parallel. Accordingly, the various aspects disclosed are not limited to Fig. 8A and 8B The illustrated examples provided in .

[0046] Figure 8CThe device 850 in a cross-sectional inductor structure view of a co-spiral inductor 852 according to one or more aspects of the present disclosure is illustrated. In the illustrated configuration, the co-spiral inductor 852 has a first turn 860, a second turn 870, a third turn 880, and a fourth turn 890 of the co-spiral inductor 852, as illustrated, the first turn 860, the second turn 870, the third turn 880, and the fourth turn 890 are each formed in a different metal layer (e.g., M1-M4, formed in BEOL only or BEOL+RDL). It will be understood that, as illustrated, the device 850 can be reversed for manufacturing to allow for the deposition of successive metal layers and insulating layers on the substrate 855 to form the co-spiral inductor 852. Accordingly, in some aspects, the co-spiral inductor 852 can be formed of a plurality of turns (e.g., 860, 870, 880, 890), wherein each turn of the plurality of turns is vertically and horizontally displaced from the next successive turn. The deposited insulating layer forms a plurality of insulators (e.g., 862, 872, 882) configured to electrically insulate each of the plurality of turns. Additionally, the manufacturing process includes forming a plurality of interconnects (e.g., 865, 875, and 885) configured to couple each of the plurality of turns to at least one other turn, which may be formed at least in part by vias V1-V3, respectively. It will be appreciated that one or more interconnects may be formed in part by via bars (e.g., V2 and V3) that may be used to couple stacked metal layers / multi-layer turns. In one or more aspects, the plurality of turns (e.g., 860, 870, 880, 890) and the plurality of interconnects (e.g., 865, 875, and 885) can be formed of any suitable conductor, and in some aspects can be formed of one or more of the following: copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (PI), aluminum (Al), titanium (Ti), tin (Sn), and alloys or combinations thereof. In one or more aspects, the plurality of insulators (e.g., 862, 872, 882) are formed of one or more of the following: silicon dioxide (SiO2), an organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or a silicone-based polymer dielectric. In one or more aspects, the substrate 855 is formed of one or more of the following: silicon (Si), high resistivity silicon (HRSi), glass, aluminum oxide (alumina), mixtures or combinations thereof.

[0047] Fig.8DA cross-sectional inductor structure view and corresponding perspective view of a co-spiral inductor 852 according to one or more aspects of the present disclosure are illustrated. In the illustrated configuration, the device 850 has been flipped to allow for subsequent processing, connection to additional components (e.g., a package substrate, a PCB, etc.). Accordingly, in some aspects, the co-spiral inductor 852 includes a plurality of turns (e.g., 860, 870, 880, 890), a plurality of insulators (e.g., 852, 872, 882), and a plurality of interconnects (e.g., 865, 875, 885), as described with respect to FIG. Figure 8C As discussed. As illustrated in the perspective view, in the co-spiral inductor 852, the first turn 860 is coupled in series with the second turn 870 through the first interconnect 865. The second turn 870 is coupled in series with the third turn 880 through the second interconnect 875. The fourth turn 890 is coupled in series with the third turn 880 through the third interconnect 885. Accordingly, as illustrated, the co-spiral inductor 852 has four turns coupled in series. Further, it will be understood that at least two turns of the co-spiral inductor 852 are vertically and horizontally displaced from the next successive trace, and the trace has a generally conical or stepped 3D form. However, the co-spiral inductor 852 has one or more turns (e.g., turn 890 and turn 880) including multiple metal layers coupled together. For example, as illustrated in the Details section, the third turn 880 may include a trace 884 on the second metal layer and a trace 886 on the third metal layer, which are coupled through a via bar V2 (e.g., via / metal layer) disposed between the second metal layer M2 and the third metal layer M3. Additionally, as illustrated in the Details section, the fourth turn 890 may include a trace 894 on the third metal layer and a trace 896 on the fourth metal layer, which are coupled through a via bar V3 (e.g., via / metal layer) disposed between the third metal layer M3 and the fourth metal layer M4. Accordingly, in some aspects, at least one turn (e.g., the third turn 880 and the fourth turn 890 as illustrated) is partially formed by the same metal layer as at least one other turn (e.g., 886 and 894). Even though a portion of the turns are formed by stacked metal layers, the traces are generally concentric in form and still have vertical (at least for a portion of each turn) and horizontal offsets so that the co-spiral inductor 852 has generally conical and concentric turns. However, it will be understood that the various aspects disclosed are not limited to the illustrated configurations. For example, the various aspects may include more or fewer traces / turns. The traces / turns may be hexagonal, circular, square, rectangular, or any other geometric shape. In some aspects, the co-spiral inductor 852 may have different geometries for different traces / turns. In some aspects, one or more traces / turns may be aligned vertically and / or horizontally. In some aspects, two or more traces / turns may be coupled in parallel. Accordingly, the various aspects disclosed are not limited to Figure 8C and 8D The illustrated examples provided in .

[0048] It should be appreciated that the foregoing discussion of example manufacturing processes is provided only as a general illustration of some aspects of the present disclosure and is not intended to limit the present disclosure or the appended claims. Further, many details of manufacturing processes known to those skilled in the art may be omitted or combined in each summary process section to facilitate understanding of the various aspects disclosed without having to present every detail and / or all possible process variations in detail.

[0049] Fig. 9 Components of an apparatus 900 according to one or more aspects of the present disclosure are illustrated. Regardless of the various configurations of the various aspects discussed herein, it will be understood that the package 930 can be configured to couple the device 910 including at least one co-spiral inductor to the PCB 990. For example, the device 910 can be similar to any device / combination (e.g., 100 and 200, 600, 700, 800, 850) including at least one co-spiral inductor (e.g., 200, 400, 802, 852). The PCB 990 is also coupled to a power source 980 (e.g., a power management integrated circuit (PMIC)), which allows the package 930 and the device 910 to be electrically coupled to the PMIC 980. Specifically, one or more power (VDD) lines 991 and one or more ground (GND) lines 992 may be coupled to the PMIC 980 to distribute power to the PCB 990, to the package 930 via the VDD BGA pins 935 and the GND BGA pins 937, and to the device 910 via the connector 920 (which may be a plated UBM of various sizes and pitches coupled to the top metal layer / M1 layer 936 and other metal layers (such as the intermetallic layer 934 and the bottom metal layer 932) of the package 930, as discussed above). The VDD line 991 and the GND line 992 may each be formed by a trace, shape, or pattern in one or more metal layers (e.g., layers 1-6) of the PCB 990, which are coupled by one or more vias through insulating layers that separate the metal layers 1-6 in the PCB 990. The PCB 990 may have one or more PCB capacitors 995 (PCB caps) that may be used to condition power signals, as known to those skilled in the art. Additional connections and devices may be coupled to package 930 via one or more additional BGA balls / pins (not shown) on package 930 and / or through PCB 990 to package 930. It will be understood that the illustrated configurations and descriptions are provided merely to help illustrate the various aspects disclosed herein. For example, PCB 990 may have more or fewer metal layers and insulating layers, there may be multiple lines to power various components, etc. Accordingly, the above illustrative examples and associated drawings should not be read as limiting the various aspects disclosed and claimed herein.

[0050] From the foregoing it will be appreciated that there are various methods for making an apparatus including the co-spiral inductors disclosed herein. Fig.10 A flow chart illustrating a method 1000 for manufacturing a device including a co-spiral inductor. The method 1000 may include forming a plurality of turns in block 1002, each turn in the plurality of turns being vertically and horizontally displaced from a next successive turn, wherein the plurality of turns are formed from traces formed on different metal layers on a substrate. The method 1000 may include forming a plurality of insulators in block 1004, the plurality of insulators being configured to electrically insulate each turn in the plurality of turns. The method 1000 may include forming a plurality of interconnects in block 1006, the plurality of interconnects being configured to couple each turn in the plurality of turns to at least one other turn.

[0051] Accordingly, it will be appreciated from the above disclosure that additional processes for manufacturing the various aspects disclosed herein will be apparent to those skilled in the art, and a literal reproduction of the processes discussed above will not be provided or illustrated in the included figures. It will be understood that the sequence of manufacturing processes is not necessarily in any order, and that later processes may be discussed earlier to provide an example of the breadth of the various aspects disclosed.

[0052] According to various aspects disclosed herein, at least one aspect includes a method for manufacturing a device (e.g., 100, 600, 700, and 910) including a co-spiral inductor (e.g., 200, 400), the co-spiral inductor comprising: a plurality of turns (e.g., 210, 220, 230, 240, 410, 420, 430, and 440), each turn of the plurality of turns being vertically and horizontally displaced from the next successive turn (e.g., forming a tapered concentric 3D co-spiral configuration). Additionally, the plurality of turns may be formed from traces formed on different metal layers on a substrate (e.g., 100). A plurality of insulators (e.g., Figures 8A to 8D The insulating layer illustrated in FIG. 2 is configured to electrically insulate each of the plurality of turns, and the plurality of interconnects (e.g., 215, 225, 235, 415, 425, and 435) are configured to couple each of the plurality of turns to at least one other turn.

[0053] Among various technical advantages, the various aspects disclosed provide in at least some aspects that the characteristic tapered concentric 3D co-spiral configuration(s) provided by each of the plurality of turns being vertically and horizontally displaced from the next successive turn allows for increased inductor density and increased SRF with high Q value. It will be appreciated that the tapered 3D co-spiral inductors disclosed herein simultaneously optimize key inductor performance metrics (e.g., inductor density, SRF, and Q factor) because in conventional inductor designs inductor density is inversely proportional to SRF. Other technical advantages will be recognized from the various aspects disclosed herein, and these technical advantages are provided merely as examples and should not be construed as limiting any of the various aspects disclosed herein.

[0054] Other aspects may include one or more of the following features discussed in the various example aspects. In one or more aspects, the plurality of interconnects are configured to couple each of the plurality of turns in series. In one or more aspects, at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel. In one or more aspects, the plurality of turns are roughly hexagonal, circular, square, or rectangular in shape. In one or more aspects, the plurality of turns are roughly conical, wherein the first turn of the plurality of turns has a minimum length and the last turn of the plurality of turns has a maximum length. In one or more aspects, each of the plurality of turns is formed on a layer separate from any other turn of the plurality of turns.

[0055] In one or more aspects, the substrate is part of a flip chip. In one or more aspects, the apparatus includes a packaging substrate coupled to the substrate on a first side of the packaging substrate facing the co-spiral inductor. In one or more aspects, the apparatus includes a printed circuit board coupled to the packaging substrate on a second side of the packaging substrate opposite the first side.

[0056] In one or more aspects, at least two turns of the plurality of turns have different thicknesses. In one or more aspects, a first turn closest to the substrate has a smaller thickness than a last turn farthest from the substrate. In one or more aspects, at least one outer turn is formed by at least two stacked metal layers of different metal layers. In one or more aspects, at least one outer turn has at least one via layer coupling the at least two stacked metal layers. In one or more aspects, at least two stacked metal layers are on the same metal layer as at least one other turn of the plurality of turns.

[0057] In one or more aspects, the plurality of insulators are formed of one or more of silicon dioxide (SiO2), an organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or a silicone-based polymer dielectric. In one or more aspects, the plurality of turns are formed of one or more of copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (PI), aluminum (Al), titanium (Ti), tin (Sn), alloys thereof, or combinations thereof. In one or more aspects, the substrate is formed of one or more of silicon (Si), high resistivity silicon (HRSi), glass, aluminum oxide (alumina), mixtures thereof, or combinations thereof.

[0058] In one or more aspects, the apparatus comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with the HIP, a radio frequency (RF) filter, an RF front end (RFFE) circuit, a power combiner, or a duplexer. In one or more aspects, the co-spiral inductor is formed in a back end of line (BEOL) stack or a BEOL stack and one or more redistribution layers (RDL). In one or more aspects, the apparatus is selected from the group comprising at least one of the following: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, or a device in a motor vehicle.

[0059] The devices and functionality disclosed above may be designed and stored in computer files (e.g., register transfer level (RTL), geometry data flow (GDS) Gerber, etc.) stored on a computer readable medium. Some or all of such files may be provided to a manufacturing processor that manufactures devices based on such files. The resulting products may include various components including semiconductor wafers, which are then cut into semiconductor dies and packaged into semiconductor packages, integrated devices, package-on-package devices, system-on-chip devices, etc., which may then be used in the various devices described herein.

[0060] It will be appreciated that the various aspects disclosed herein may be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, a device may include means for performing the various functionalities discussed above. It will be appreciated that the foregoing aspects are provided only as examples, and the claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0061] Fig.11 An exemplary mobile device according to some examples of the present disclosure is illustrated. Fig.11 , a block diagram of a mobile device configured according to exemplary aspects is depicted and generally designated as mobile device 1100. In some aspects, mobile device 1100 can be configured as a wireless communication device. As shown, mobile device 1100 includes processor 1101. Processor 1101 can be communicatively coupled to memory 1132 over a link, which can be a die-to-die or chip-to-chip link. Mobile device 1100 also includes a display 1128 and a display controller 1126, wherein display controller 1126 is coupled to processor 1101 and display 1128.

[0062] In some respects, Fig.11 It may include: a coder / decoder (CODEC) 1134 (e.g., an audio and / or voice CODEC) coupled to the processor 1101; a speaker 1136 and a microphone 1138 coupled to the CODEC 1134; and a wireless circuit 1140 (which may include a modem, RF circuitry, filters, etc., which may be implemented using one or more co-spiral inductors as disclosed herein) coupled to a wireless antenna 1142 and the processor 1101.

[0063] In certain aspects, where one or more of the above blocks are present, the processor 1101, display controller 1126, memory 1132, CODEC 1134, and wireless circuit 1140 may be included in a system-level package or system-on-chip device 1122, which may be implemented in whole or in part using the techniques disclosed herein. Input device 1130 (e.g., a physical or virtual keyboard), power supply 1144 (e.g., a battery), display 1128, input device 1130, speaker 1136, microphone 1138, wireless antenna 1142, and power supply 1144 may be located external to the system-on-chip device 1122 and may be coupled to components of the system-on-chip device 1122 (such as an interface or controller).

[0064] It should be noted that although Fig.11 A mobile device 1100 is depicted, but the processor 1101 and memory 1132 may also be integrated into a set-top box, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop, tablet device, communication device, mobile phone, or other similar device.

[0065] Fig.12Various electronic devices that may be integrated with any of the aforementioned integrated devices or semiconductor devices according to various examples of the present disclosure are illustrated. For example, a mobile phone device 1202, a laptop device 1204, and a fixed location terminal device 1206 may each be generally considered as a user equipment (UE) and may include the co-spiral inductor 1200 described herein. The co-spiral inductor 1200 may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and stacked package devices described herein. Fig.12 The devices 1202, 1204, 1206 illustrated in the figure are merely exemplary. Other electronic devices can also feature the co-spiral inductor 1200, including but not limited to a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0066] The devices and functionality disclosed above may be designed and configured in computer files (e.g., register transfer level (RTL), geometry data flow (GDS) Gerber, etc.) stored on a computer readable medium. Some or all of such files may be provided to a manufacturing processor that manufactures devices based on such files. The resulting products may include semiconductor wafers that are subsequently cut into semiconductor dies and packaged into semiconductor packages, integrated devices, system-on-chip devices, etc., which may then be used in the various devices described herein.

[0067] It will be appreciated that the various aspects disclosed herein may be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, a device may include means for performing the various functionalities discussed above. It will be appreciated that the foregoing aspects are provided only as examples, and the claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0068] Figure 1-12One or more of the components, processes, features, and / or functions described herein may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1-12 and its corresponding description in this disclosure are not limited to die and / or IC. In some implementations, Figure 1-12 The invention and the corresponding description may be used to manufacture, create, provide and / or produce an integrated device. In some implementations, the device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a system-in-package (SiP), a system-on-chip (SoC), a package-on-package (PoP) device, and the like.

[0069] As used herein, the terms "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal" and variations thereof may interchangeably refer to any suitable mobile or stationary device capable of receiving wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smart phones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, onboard devices in motor vehicles, and / or other types of portable electronic devices typically carried by an individual and / or having communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include a device that communicates with another device that is capable of receiving wireless communications and / or navigation signals (such as through a short-range wireless, infrared, wired connection, or other connection), regardless of whether satellite signal reception, assistance data reception, and / or positioning-related processing occurs at the device or at the other device. A UE can be implemented by any of several types of devices including, but not limited to, a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smart phone, a tablet device, a consumer tracking device, an asset tag, etc.

[0070] Wireless communications between electronic devices may be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiplexing (OFDM), global system for mobile communications (GSM), 3GPP long term evolution (LTE), 5G new radio, (BT), Low Energy (BLE), IEEE 802.11 (WiFi) and IEEE802.15.4 ( / Thread), or other protocols that can be used in wireless communication networks or data communication networks. Low power consumption (also known as LE, BLE, and intelligent).

[0071] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" is not to be construed as trumping other examples. Likewise, the term "example" does not imply that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0072] It should be noted that the terms "connected", "coupled" or any variations thereof mean any connection or coupling, direct or indirect, between elements, and may encompass the presence of intermediate elements between two elements via which the two elements are "connected" or "coupled" together, unless the connection is explicitly disclosed as a direct connection.

[0073] Any reference to an element using designations such as "first," "second," etc. herein does not limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing two or more elements and / or element instances. Likewise, unless otherwise stated, a set of elements may include one or more elements.

[0074] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0075] Nothing described or illustrated in this application is intended to confer any component, act, feature, benefit, advantage, or equivalent to the public, regardless of whether the component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0076] In addition, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic actions described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and actions are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The technician can implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0077] Although some aspects have been described in conjunction with the device, it is undoubted that these aspects also constitute the description of the corresponding method, and therefore the block or assembly of the device should also be understood as the corresponding method action or the feature of the method action. Similarly, the description of the corresponding block or details or features of the corresponding device is also constituted in conjunction with or as the various aspects described in the method action. Some or all of the method actions can be performed by hardware devices (or using hardware devices), such as, for example, microprocessors, programmable computers or electronic circuits. In some examples, some or more of the most important method actions can be performed by such devices.

[0078] In the above detailed description, it can be seen that different features are grouped together in each example. This disclosure should not be understood as an intention that the example clauses have more features than the features explicitly mentioned in each clause. On the contrary, various aspects of the present disclosure may include less than all the features of the disclosed individual example clauses. Therefore, the attached clauses should be considered to be incorporated into the description, wherein each clause itself may be a separate example. Although each subordinate clause can be cited in each clause with a specific combination of one of the other clauses, the (all) aspects of the subordinate clause are not limited to the specific combination. It will be appreciated that other example clauses may also include a combination of the (all) aspects of the subordinate clause with the subject matter of any other subordinate clause or independent clause or any feature with other subordinate and independent clauses. The various aspects disclosed herein explicitly include these combinations, unless explicitly expressed or can be easily inferred that it is not intended to be a specific combination (e.g., contradictory aspects, such as defining an element as an insulator and a conductor at the same time). In addition, it is also intended that the various aspects of the clause can be included in any other independent clause, even if the clause is not directly subordinate to the independent clause.

[0079] Implementation examples are described in the following numbered clauses:

[0080] Item 1. A device comprising a co-spiral inductor, comprising: a plurality of turns, each of the plurality of turns being vertically and horizontally displaced from the next successive turn, wherein the plurality of turns are formed by traces formed on different metal layers on a substrate; a plurality of insulators configured to electrically insulate each of the plurality of turns; and a plurality of interconnects configured to couple each of the plurality of turns to at least one other turn.

[0081] Clause 2. The apparatus of clause 1, wherein the plurality of interconnects are configured to couple each turn of the plurality of turns in series.

[0082] Clause 3. The apparatus of any of Clauses 1 to 2, wherein at least one interconnect of the plurality of interconnects is configured to couple at least two turns of the plurality of turns in parallel.

[0083] Clause 4. The device of any of Clauses 1 to 3, wherein the plurality of turns are hexagonal, circular, square, or rectangular in shape.

[0084] Clause 5. The device of any of Clauses 1 to 4, wherein the plurality of turns are generally conical, wherein a first turn in the plurality of turns has a smallest length and a last turn in the plurality of turns has a largest length.

[0085] Clause 6. The device of any of Clauses 1 to 5, wherein each turn of the plurality of turns is formed on a separate layer from any other turn of the plurality of turns.

[0086] Clause 7. The device of Clause 6, wherein the substrate is part of a flip chip.

[0087] Clause 8. The apparatus of Clause 7, further comprising a packaging substrate coupled to the substrate on a first side of the packaging substrate facing the co-spiral inductor.

[0088] Clause 9. The apparatus of Clause 8, further comprising a printed circuit board coupled to the packaging substrate on a second side of the packaging substrate opposite the first side.

[0089] Clause 10. The device of any of Clauses 1 to 9, wherein at least two turns of the plurality of turns have different thicknesses.

[0090] Clause 11. The device of Clause 10, wherein a first turn closest to the substrate has a smaller thickness than a last turn farthest from the substrate.

[0091] Clause 12. The device of any of Clauses 10 to 11, wherein at least one outer turn is formed by at least two stacked metal layers of different metal layers.

[0092] Clause 13. The device of Clause 12, wherein the at least one outer turn has at least one via layer coupling at least two stacked metal layers.

[0093] Clause 14. The device of any of Clauses 12-13, wherein at least one of the at least two stacked metal layers is on the same metal layer as at least one other turn of the plurality of turns.

[0094] Item 15. A device as in any of items 1 to 14, wherein the plurality of insulators are formed of one or more of the following: silicon dioxide (SiO2), an organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or a silicone-based polymer dielectric.

[0095] Item 16. A device as in any of items 1 to 15, wherein the plurality of turns are formed from one or more of the following: copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (Pl), aluminum (Al), titanium (Ti), tin (Sn), alloys thereof, or combinations thereof.

[0096] Item 17. The device of any one of Items 1 to 16, wherein the substrate is formed of one or more of: silicon (Si), high resistivity silicon (HRSi), glass, aluminum oxide (alumina), mixtures or combinations thereof.

[0097] Clause 18. The device of any of clauses 1 to 17, wherein the device comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with the HIP, a radio frequency (RF) filter, an RF front end (RFFE) circuit, a power combiner, or a duplexer.

[0098] Item 19. The device of any one of Items 1 to 18, wherein the co-spiral inductor is formed in a back end of line (BEOL) stack or a BEOL stack and one or more redistribution layers (RDLs).

[0099] Clause 20. An apparatus as in any of clauses 1 to 19, wherein the apparatus is selected from a group comprising at least one of the following: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, or a device in a motor vehicle.

[0100] Item 21. A method for manufacturing a device including a co-spiral inductor, the method comprising: forming a plurality of turns, each of the plurality of turns being vertically and horizontally displaced from the next successive turn, wherein the plurality of turns are formed by traces formed on different metal layers on a substrate; forming a plurality of insulators, the plurality of insulators being configured to electrically insulate each of the plurality of turns; and forming a plurality of interconnects, the plurality of interconnects being configured to couple each of the plurality of turns to at least one other turn.

[0101] Clause 22. The method of Clause 21, wherein the plurality of interconnects are configured to couple each turn of the plurality of turns in series.

[0102] Clause 23. The method of any of Clauses 21 to 22, wherein at least one interconnect of the plurality of interconnects is configured to couple at least two turns of the plurality of turns in parallel.

[0103] Clause 24. The method of any one of Clauses 21 to 23, wherein the plurality of turns are hexagonal, circular, square, or rectangular in shape.

[0104] Clause 25. The method of any of Clauses 21 to 24, wherein the plurality of turns are generally conical, wherein a first turn in the plurality of turns has a smallest length and a last turn in the plurality of turns has a largest length.

[0105] Clause 26. The method of any of Clauses 21 to 25, further comprising forming each of the plurality of turns on a separate layer from any other of the plurality of turns.

[0106] Clause 27. The method of any one of Clauses 21 to 26, wherein the substrate is part of a flip chip.

[0107] Clause 28. The method of clauses 21 to 27, further comprising coupling the packaging substrate to the substrate on a first side of the packaging substrate facing the co-spiral inductor.

[0108] Clause 29. The method of Clause 28, further comprising coupling a printed circuit board to the packaging substrate on a second side of the packaging substrate opposite the first side.

[0109] Clause 30. The method of any of Clauses 21 to 29, wherein at least two turns of the plurality of turns have different thicknesses.

[0110] Clause 31. The method of Clause 30, wherein a first turn closest to the substrate has a smaller thickness than a last turn farthest from the substrate.

[0111] Clause 32. The method of any of Clauses 30 to 31, wherein the at least one outer turn is formed from at least two stacked metal layers of different metal layers.

[0112] Clause 33. The method of Clause 32, wherein the at least one outer turn has at least one via layer coupling at least two stacked metal layers.

[0113] Clause 34. The method of any of Clauses 32-33, wherein at least one of the at least two stacked metal layers is on the same metal layer as at least one other turn of the plurality of turns.

[0114] Item 35. A method as described in any of Items 21 to 34, wherein the plurality of insulators are formed from one or more of the following: silicon dioxide (SiO2), an organic polymer dielectric, a polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or a silicone-based polymer dielectric.

[0115] Item 36. A method as in any of items 21 to 35, wherein the plurality of turns are formed from one or more of the following: copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (Pl), aluminum (Al), titanium (Ti), tin (Sn), alloys thereof, or combinations thereof.

[0116] Item 37. The method of any one of Items 21 to 36, wherein the substrate is formed of one or more of: silicon (Si), high resistivity silicon (HRSi), glass, aluminum oxide (alumina), mixtures or combinations thereof.

[0117] Clause 38. A method as in any of clauses 21 to 37, wherein the device comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with the HIP, a radio frequency (RF) filter, an RF front end (RFFE) circuit, a power combiner, or a duplexer.

[0118] Item 39. The method of any one of Items 21 to 38, further comprising forming a co-spiral inductor in a back end of line (BEOL) stack or a BEOL stack and one or more redistribution layers (RDLs).

[0119] Clause 40. A method as in any of clauses 21 to 39, wherein the device is selected from a group comprising at least one of the following: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, or a device in a motor vehicle.

[0120] It should also be noted that the methods, systems and devices disclosed in the description or claims may be implemented by a device including means for performing the corresponding actions and / or functionalities of the disclosed methods.

[0121] In addition, in some examples, an individual action may be subdivided into or include multiple sub-actions. Such sub-actions may be included in and may be part of the disclosure of the individual action.

[0122] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made therein without departing from the scope of the present disclosure as defined in the appended claims. The functions and / or actions in the method claims of each example of the present disclosure described herein do not necessarily have to be performed in any particular order. In addition, well-known elements will not be described in detail or may be omitted to avoid blurring the relevant details of the various aspects and examples disclosed herein. In addition, although the elements of the present disclosure may be described or claimed in the singular, the plural number is also contemplated unless it is explicitly stated to be limited to the singular.

Claims

1. A device comprising a co-spiral inductor, comprising: a plurality of turns, each turn of the plurality of turns being vertically and horizontally displaced from a next successive turn, wherein the plurality of turns are formed by traces formed on different metal layers on a substrate; a plurality of insulators configured to electrically insulate each of the plurality of turns; as well as A plurality of interconnects are configured to couple each turn of the plurality of turns to at least one other turn. 2 . The apparatus of claim 1 , wherein the plurality of interconnects are configured to couple each of the plurality of turns in series. 3 . The apparatus of claim 1 , wherein at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel.

4. The device of claim 1, wherein the plurality of turns are hexagonal, circular, square, or rectangular in shape.

5. The apparatus of claim 1, wherein the plurality of turns are generally conical, wherein a first turn of the plurality of turns has a smallest length and a last turn of the plurality of turns has a largest length.

6. The apparatus of claim 1, wherein each turn of the plurality of turns is formed on a separate layer from any other turn of the plurality of turns.

7. The device of claim 6, wherein the substrate is part of a flip chip. 8 . The apparatus of claim 7 , further comprising a packaging substrate coupled to the substrate on a first side of the packaging substrate facing the co-spiral inductor. 9 . The apparatus of claim 8 , further comprising a printed circuit board coupled to the packaging substrate on a second side of the packaging substrate opposite the first side.

10. The device of claim 1, wherein at least two turns of the plurality of turns have different thicknesses.

11. The apparatus of claim 10, wherein a first turn closest to the substrate has a smaller thickness than a last turn farthest from the substrate.

12. The device of claim 10, wherein at least one outer turn is formed by at least two stacked metal layers of different metal layers.

13. The apparatus of claim 12, wherein the at least one outer turn has at least one via layer coupling the at least two stacked metal layers.

14. The apparatus of claim 12, wherein at least one of the at least two stacked metal layers is on a same metal layer as at least one other turn of the plurality of turns.

15. The device of claim 1, wherein the plurality of insulators are formed of one or more of: silicon dioxide (SiO2), an organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or a silicone-based polymer dielectric.

16. The device of claim 1, wherein the plurality of turns are formed of one or more of: copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (Pl), aluminum (Al), titanium (Ti), tin (Sn), alloys thereof, or combinations thereof.

17. The device of claim 1, wherein the substrate is formed of one or more of: silicon (Si), high resistivity silicon (HRSi), glass, aluminum oxide (alumina), mixtures or combinations thereof.

18. The apparatus of claim 1, wherein the apparatus comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with a HIP, a radio frequency (RF) filter, an RF front end (RFFE) circuit, a power combiner, or a duplexer.

19. The apparatus of claim 1, wherein the co-spiral inductor is formed in a back-end of line (BEOL) stack or the BEOL stack and one or more redistribution layers (RDLs).

20. The device of claim 1, wherein the device is selected from a group comprising at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, or a device in a motor vehicle.

21. A method for manufacturing a device including a co-spiral inductor, the method comprising: forming a plurality of turns, each turn of the plurality of turns being vertically and horizontally displaced from a next successive turn, wherein the plurality of turns are formed from traces formed on different metal layers on a substrate; forming a plurality of insulators configured to electrically insulate each of the plurality of turns; as well as A plurality of interconnects are formed, the plurality of interconnects configured to couple each turn of the plurality of turns to at least one other turn.

22. The method of claim 21, wherein the plurality of interconnects are configured to couple each of the plurality of turns in series.

23. The method of claim 21, wherein at least one interconnect of the plurality of interconnects is configured to couple at least two turns of the plurality of turns in parallel.

24. The method of claim 21, wherein the plurality of turns are hexagonal, circular, square, or rectangular in shape.

25. The method of claim 21, wherein the plurality of turns are generally conical, wherein a first turn of the plurality of turns has a smallest length and a last turn of the plurality of turns has a largest length.

26. The method of claim 21, further comprising forming each of the plurality of turns on a separate layer from any other of the plurality of turns.

27. The method of claim 21, wherein the substrate is part of a flip chip.

28. The method of claim 21, further comprising coupling the packaging substrate to the substrate on a first side of the packaging substrate facing the co-spiral inductor.

29. The method of claim 28, further comprising coupling a printed circuit board to the packaging substrate on a second side of the packaging substrate opposite the first side.

30. The method of claim 21, wherein at least two turns of the plurality of turns have different thicknesses.

31. The method of claim 30, wherein a first turn closest to the substrate has a smaller thickness than a last turn farthest from the substrate.

32. The method of claim 30, wherein at least one outer turn is formed from at least two stacked metal layers of different metal layers.

33. The method of claim 32, wherein the at least one outer turn has at least one via layer coupling the at least two stacked metal layers.

34. The method of claim 32, wherein at least one of the at least two stacked metal layers is on the same metal layer as at least one other turn of the plurality of turns.

35. The method of claim 21, wherein the plurality of insulators are formed of one or more of: silicon dioxide (SiO2), an organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or a silicone-based polymer dielectric.

36. The method of claim 21, wherein the plurality of turns are formed of one or more of: copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (Pl), aluminum (Al), titanium (Ti), tin (Sn), alloys thereof, or combinations thereof.

37. The method of claim 21, wherein the substrate is formed of one or more of: silicon (Si), high resistivity silicon (HRSi), glass, aluminum oxide (alumina), mixtures or combinations thereof.

38. The method of claim 21, wherein the device comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with a HIP, a radio frequency (RF) filter, an RF front end (RFFE) circuit, a power combiner, or a duplexer.

39. The method of claim 21, further comprising forming the co-spiral inductor in a back end of line (BEOL) stack or the BEOL stack and one or more redistribution layers (RDLs).

40. The method of claim 21, wherein the device is selected from a group comprising at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, or a device in a motor vehicle.

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