Display substrate, preparation method thereof and display device

Abstract

The invention provides a display substrate, a preparation method thereof and a display device, and belongs to the technical field of display. An array substrate in the display substrate comprises a substrate body, a plurality of pixels located on one side of the substrate body and spaced from one another, and shading layers located in reflecting layer spacing areas of every two adjacent pixels. Wherein the orthographic projection of the shading layer on the substrate covers the orthographic projection of the spacer region on the substrate, and the orthographic projection of the reflecting layer on the substrate is overlapped with the orthographic projection of the shading layer on the substrate. In this way, the shading structure can be formed in the spacer region to achieve shading, and light leakage is avoided. On the basis, a black matrix does not need to be arranged at the position, corresponding to the spacer region, of one side of the opposite substrate opposite to the array substrate. In this way, it can be ensured that the reflection aperture ratio is large, and therefore it can be ensured that the display effect is good.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] With the advancement of display technology, semi-transmissive liquid crystal display (LCD) panels with both reflective and transmissive functions have come into being. They can emit light using a reflective mode in a high-brightness environment and a transmissive mode in a low-brightness environment, ensuring clear display in different scenarios.

[0003] In the related art, a transflective LCD panel generally includes: an array substrate and a color filter (CF) substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the CF substrate. The liquid crystal molecules in the liquid crystal layer can be deflected under the drive of the array substrate and the CF substrate, thereby realizing reflective or transmissive display. In addition, a black matrix (BM) is also arranged on one side of the CF substrate as a light shielding layer to prevent light leakage during display.

[0004] However, providing a BM on one side of the CF substrate will result in a decrease in the reflective aperture ratio, which in turn leads to poor display brightness of the semi-transmissive and semi-reflective LCD panel, resulting in poor display effects. Summary of the invention

[0005] Provided are a display substrate and a preparation method thereof, and a display device, which can solve the problem in the related art that the reflective aperture ratio is reduced due to the arrangement of a BM on one side of a CF substrate, resulting in a poor display effect.

[0006] The technical solution is as follows:

[0007] In one aspect, a display substrate is provided, the display substrate comprising: an array substrate and an opposing substrate arranged opposite to each other; the opposing substrate comprising: a first common electrode; the array substrate comprising:

[0008] substrate;

[0009] A plurality of pixels arranged at intervals are located on a side of the substrate close to the counter substrate; wherein the pixel comprises a reflection area and a transmission area adjacent to each other; in the reflection area and the transmission area, the pixel comprises: a transparent conductive layer located on one side of the substrate; in the reflection area, the pixel further comprises: a gate conductive layer and a source-drain conductive layer located between the transparent conductive layer and the substrate and stacked in sequence, and a reflection layer located on a side of the transparent conductive layer away from the substrate;

[0010] At least one light-shielding layer is located in the interval area between the reflective layers of two adjacent pixels; wherein the orthographic projection of the at least one light-shielding layer on the substrate covers the orthographic projection of the interval area on the substrate, and the orthographic projection of the reflective layer on the substrate overlaps with the orthographic projection of the at least one light-shielding layer on the substrate to form a light-shielding structure in the interval area; and when displayed in a black state, the light-shielding layer close to the opposing substrate in the at least one light-shielding layer has the same potential as the first common electrode.

[0011] Optionally, the at least one light-shielding layer is shared with a conductive layer included in the pixel.

[0012] Optionally, the gate conductive layer included in the pixel is used to form: a gate line, and the transparent conductive layer included in the pixel is used to form: a second common electrode;

[0013] Wherein, the array substrate comprises two light shielding layers, and the two light shielding layers are respectively shared with the gate line and the second common electrode.

[0014] Optionally, the gate conductive layer included in the pixel is used to form: a second common electrode;

[0015] Wherein, the array substrate includes a light shielding layer, and the light shielding layer is shared with the second common electrode.

[0016] Optionally, the array substrate includes a light shielding layer, and the light shielding layer is shared with a source-drain conductive layer included in the pixel.

[0017] Optionally, the gate conductive layer included in the pixel is also used to form: a gate line;

[0018] The orthographic projection of the reflective layer on the substrate covers the orthographic projection of the gate line on the substrate.

[0019] Optionally, the line width of the gate line is smaller than a line width threshold, so that the orthographic projection of the reflective layer on the substrate covers the orthographic projection of the gate line on the substrate.

[0020] Optionally, the line width threshold is 5 microns.

[0021] Optionally, the display substrate further includes:

[0022] A supporting column, located between the display substrate and the counter substrate;

[0023] A black matrix is ​​located between the support pillars and the array substrate, and an orthographic projection of the black matrix on the substrate overlaps with an orthographic projection of the gate line formed by the gate conductive layer on the substrate.

[0024] Optionally, the pixel further includes a pixel circuit area, and the pixel circuit area, the reflective area and the transmissive area are adjacent to each other in sequence; the opposing substrate includes: a plurality of filter parts arranged at intervals corresponding to the plurality of pixels arranged at intervals one by one;

[0025] Wherein, the filter section includes: a first portion corresponding to the transmission area, a second portion corresponding to the reflection area, and a third portion corresponding to the pixel circuit area;

[0026] Furthermore, the orthographic projection of the first part on the substrate covers the orthographic projection of the transmission area of ​​the pixel on the substrate, the orthographic projection of the second part on the substrate is located within the orthographic projection of the reflection area of ​​the pixel on the substrate, and the orthographic projection of the third part on the substrate is located within the orthographic projection of the pixel circuit area of ​​the pixel on the substrate.

[0027] Optionally, the size of the first part is larger than the size of the third part, and the size of the third part is larger than the size of the second part.

[0028] Optionally, in the reflective region and the transmissive region, the pixel further comprises: a gate insulating layer and a passivation layer located between the transparent conductive layer and the substrate and stacked in sequence; in the reflective region, the gate insulating layer is located between the gate conductive layer and the source-drain conductive layer, the passivation layer is located between the source-drain conductive layer and the transparent conductive layer, and the pixel further comprises: a concave-convex layer located between the transparent conductive layer and the reflective layer;

[0029] Among them, the reflective layer and the concave-convex layer both have openings exposing the transmission area, so that the transparent conductive layer is exposed in the transmission area, and the reflective layer overlaps with the transparent conductive layer along the opening, and the transparent conductive layer is also overlapped with the source-drain conductive layer through a via hole penetrating the passivation layer.

[0030] Optionally, the material of the concave-convex layer includes: acrylic; the material of the reflective layer includes: at least one of aluminum and silver; and the material of the transparent conductive layer includes: indium tin oxide.

[0031] In another aspect, a method for preparing a display substrate is provided, for preparing the display substrate as described in the above aspect; the method comprises:

[0032] forming an opposing substrate, the opposing substrate comprising: a first common electrode;

[0033] forming a substrate on a side opposite to the counter substrate;

[0034] A plurality of pixels are formed at intervals on a side of the substrate close to the counter substrate, and the formed pixels include adjacent reflective areas and transmissive areas; in the reflective area and the transmissive area, the pixels include: a transparent conductive layer located on one side of the substrate; in the reflective area, the pixels also include: a gate conductive layer and a source-drain conductive layer located between the transparent conductive layer and the substrate and stacked in sequence, and a reflective layer located on a side of the transparent conductive layer away from the substrate;

[0035] At least one light-shielding layer is formed in the interval area of ​​the reflective layers of two adjacent pixels, and the orthographic projection of the at least one light-shielding layer formed on the substrate covers the orthographic projection of the interval area on the substrate, and the orthographic projection of the reflective layer on the substrate overlaps with the orthographic projection of the at least one light-shielding layer on the substrate to form a light-shielding structure in the interval area; and when displayed in a black state, the light-shielding layer close to the opposing substrate has the same potential as the first common electrode.

[0036] In another aspect, a display device is provided, the display device comprising: a power supply component, and the display substrate as described in the above aspect;

[0037] Wherein, the power supply component is coupled to the display substrate and is used to supply power to the display substrate.

[0038] In summary, the beneficial effects brought about by the technical solution provided by the present disclosure include at least:

[0039] A display substrate and a preparation method thereof, and a display device are provided. The array substrate in the display substrate includes: a substrate, a plurality of pixels located on one side of the substrate and spaced from each other, and a light shielding layer located in the reflective layer spacing area between each two adjacent pixels. The orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the spacing area on the substrate, and the orthographic projection of the reflective layer on the substrate overlaps the orthographic projection of the light shielding layer on the substrate. In this way, a light shielding structure can be formed in the spacing area to achieve light shielding and avoid light leakage. On this basis, a black matrix does not need to be set at the position corresponding to the spacing area on the side of the opposing substrate opposite to the array substrate. In this way, a large reflective aperture ratio can be ensured, thereby ensuring a better display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0042] Figure 2 is a structural schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0043] Figure 3 is a cross-sectional view of an array substrate provided by an embodiment of the present disclosure;

[0044] Figure 4 is a cross-sectional view of a spacer region in an array substrate provided by an embodiment of the present disclosure;

[0045] Figure 5 is a cross-sectional view of a spacer region in another array substrate provided by an embodiment of the present disclosure;

[0046] Figure 6 is a cross-sectional view of a spacer region in another array substrate provided by an embodiment of the present disclosure;

[0047] Figure 7 is a top view of a display substrate provided by an embodiment of the present disclosure;

[0048] Figure 8 is a top view of a local structure of a display substrate provided by an embodiment of the present disclosure;

[0049] Fig. 9 is a top view of another display substrate provided by an embodiment of the present disclosure;

[0050] Fig.10 is a flow chart of a method for preparing a display substrate provided by an embodiment of the present disclosure;

[0051] Fig.11 So Figure 4 Taking the structure shown as an example, a top view of the overall film layer of an array substrate is shown;

[0052] Fig.12 So Figure 4 Taking the structure shown as an example, a top view of an array substrate in the DD' direction is shown;

[0053] Fig.13 So Fig.11 Taking the structure shown as an example, a cross-sectional view of an array substrate in the AA' direction is shown;

[0054] Fig.14 So Fig.11 Taking the structure shown as an example, a cross-sectional view of an array substrate in the BB' direction is shown;

[0055] Fig.15 So Fig.11 Taking the structure shown as an example, a cross-sectional view of an array substrate in the CC' direction is shown;

[0056] Fig.16 So Figure 5 Taking the structure shown as an example, a top view of an array substrate in the DD' direction is shown;

[0057] Fig.17 So Figure 6 Taking the structure shown as an example, a top view of an array substrate in the DD' direction is shown;

[0058] Fig.18 So Figure 8 Taking the structure shown as an example, a top view of the overall film layer of an array substrate is shown;

[0059] Fig.19 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0061] Figure 1 Schematic diagram of a display substrate provided by an embodiment of the present disclosure. Figure 1 As shown, the display substrate includes: an array substrate 0 and an opposing substrate 1 which are arranged opposite to each other.

[0062] In some embodiments, continue to refer to Figure 1 The display substrate further includes: a liquid crystal layer 2 located between the array substrate 0 and the counter substrate 1, the liquid crystal layer including liquid crystal molecules. Under the driving action of the array substrate 0 and the counter substrate 1, the liquid crystal molecules in the liquid crystal layer 2 can be deflected, so that light can be transmitted or not transmitted, that is, light can be transmitted or not transmitted. And, the counter substrate 1 includes: a first common electrode. Figure 1 Based on this, continue to refer to Figure 2 It can be seen that the array substrate 0 includes:

[0063] Substrate 01.

[0064] The plurality of pixels 02 are arranged at intervals. The plurality of pixels 02 are located on a side of the substrate 01 close to the counter substrate 1, that is, Figure 1 , a plurality of pixels 02 may be located between the counter substrate 1 and the substrate 01 .

[0065] Each pixel 02 includes a reflective area A1 and a transmissive area A2 adjacent to each other. That is, the pixel 02 described in the embodiment of the present disclosure may be a semi-transmissive pixel, which is applied to a semi-transmissive LCD panel to achieve clear display in different scenes. Figure 1 and Figure 2 Based on this, continue to refer to Figure 3It can be seen from the array substrate shown that in the reflective area A1 and the transmissive area A2, the pixel 02 includes: a transparent conductive layer 021 located on one side of the substrate 01. In the reflective area A1, the pixel 02 also includes: a gate conductive layer GATE and a source & drain (SD) conductive layer SD located between the transparent conductive layer 021 and the substrate 01 and stacked in sequence, and a reflector (REF) layer REF located on the side of the transparent conductive layer 021 away from the substrate 01. Optionally, as Figure 2 As shown, the gate conductive layer GATE and the source-drain conductive layer SD are sequentially stacked in a direction away from the substrate 01. Of course, in some other embodiments, the gate conductive layer GATE and the source-drain conductive layer SD can also be sequentially stacked in a direction close to the substrate 01. Figure 3 In the reflective area A1 , the reflective layer REF is farthest from the substrate 01 , so that reflective display can be achieved through the reflective layer REF. In the transmissive area A2 , the transparent conductive layer 021 is farthest from the substrate 01 , so that transmissive display can be achieved through the transparent conductive layer 021 .

[0066] It should be noted that, since the plurality of pixels 02 are spaced apart from each other, Figure 3 As shown, the reflective layers REF of two adjacent pixels 02 are spaced apart from each other. In the embodiment of the present disclosure, the space between the reflective layers REF of two adjacent pixels 02 is divided into a spacer area B1. Figure 3 It can be seen that the array substrate 0 described in the embodiment of the present disclosure further includes:

[0067] At least one light shielding layer 03. The at least one light shielding layer 03 is located in the interval B1 of the reflective layer REF of two adjacent pixels 02. Among them, the orthographic projection of at least one light shielding layer 03 on the substrate 01 covers the orthographic projection of the interval B1 on the substrate 01, and the orthographic projection of the reflective layer REF on the substrate 01 overlaps with the orthographic projection of at least one light shielding layer 03 on the substrate 01, so as to form a light shielding structure in the interval B1. In this way, the light shielding structure can be used to effectively block light, avoid light leakage during reflective display, and ensure a better display effect. In addition, on the basis of setting a light shielding structure on one side of the array substrate 0, for the side of the opposing substrate 1, there is no need to set a light shielding layer (such as a black matrix BM) at the corresponding position of the interval B1 to block light and prevent light leakage. In this way, it is also possible to avoid a reduction in the reflective aperture ratio due to the setting of BM on one side of the opposing substrate 1, that is, to ensure a larger reflective aperture ratio, thereby avoiding poor display brightness, and further ensuring a better display effect.

[0068] Furthermore, in the disclosed embodiment, when the black state is displayed (that is, a black screen is displayed), the light shielding layer 03 close to the counter substrate 1 in at least one light shielding layer 03 has the same potential as the first common electrode in the counter substrate 1. In this way, it is possible to avoid the light shielding structure on one side of the array substrate 0 and the common electrode on one side of the counter substrate 1 forming a vertical electric field, thereby preventing the liquid crystal molecules in the liquid crystal layer 2 from being mis-deflected and causing light leakage, thereby further ensuring a better display effect.

[0069] In summary, the embodiments of the present disclosure provide a display substrate. The array substrate in the display substrate includes: a substrate, a plurality of pixels located on one side of the substrate and spaced from each other, and a shading layer located in the reflective layer spacing area between every two adjacent pixels. The orthographic projection of the shading layer on the substrate covers the orthographic projection of the spacing area on the substrate, and the orthographic projection of the reflective layer on the substrate overlaps with the orthographic projection of the shading layer on the substrate. In this way, a shading structure can be formed in the spacing area to achieve shading and avoid light leakage. On this basis, a black matrix does not need to be set at the position corresponding to the spacing area on the side of the opposing substrate opposite to the array substrate. In this way, a large reflective aperture ratio can be ensured, thereby ensuring a better display effect.

[0070] In addition, in the embodiment of the present disclosure, when the black state is displayed, the potential of the shading layer close to the opposing substrate is the same as that of the common electrode in the opposing substrate. This can avoid the shading layer in the array substrate and the common electrode in the opposing substrate from forming a vertical electric field, which may cause the liquid crystal molecules to be mis-deflected and cause light leakage, thereby further ensuring a better display effect.

[0071] Optional, continue to refer to Figure 3 It can be seen that in the embodiment of the present disclosure, in the reflective area A1 and the transmissive area A2, the pixel 02 may further include: a gate insulator (GI) layer GI and a passivation (PVX) layer PVX, which are located between the transparent conductive layer 021 and the substrate 01 and are sequentially stacked. In addition, in the reflective area A1, the gate insulating layer GI may be located between the gate conductive layer GATE and the source-drain conductive layer SD, and the passivation layer PVX may be located between the source-drain conductive layer SD and the transparent conductive layer 021.

[0072] And, the pixel 02 may also include: a concave-convex layer 022 located between the transparent conductive layer 021 and the reflective layer REF. Among them, the reflective layer REF and the concave-convex layer 022 may both have an opening K0, so that the transparent conductive layer 021 is exposed in the transmission area A2 to ensure the transmission display. In addition, the reflective layer REF may overlap with the transparent conductive layer 021 along the opening K0, and the transparent conductive layer 021 may also overlap with the source-drain conductive layer SD through a via penetrating the passivation layer PVX. Here, the reflective layer REF may be used as a metal pixel electrode, and the transparent conductive layer 021 may be used as a transparent pixel electrode, that is, the metal pixel electrode and the transparent pixel electrode may be coupled to serve as a pixel electrode. A pixel voltage may be provided to the pixel electrode via the source-drain conductive layer SD.

[0073] Optional, continue to refer to Figure 3 It can also be seen that in the reflective area A1, the pixel 02 may also include: an active (ACT) layer ACT located between the gate insulating layer GI and the source-drain conductive layer SD, and the source-drain conductive layer SD overlaps the active layer ACT. In some embodiments, the portion including the active layer ACT may be divided into a pixel circuit region, also called a channel region. On this basis, refer to Figure 3 It can be seen that due to the presence of the concavo-convex layer 022, the number of film layers included in the pixel 02 in the reflective area A1 and the transmissive area A2 is different. Accordingly, the film thickness of the reflective area A1 and the transmissive area A2 is different, which can be considered as a double-box thickness design.

[0074] Optionally, in some embodiments, the material of the concave-convex layer 022 may include: acrylic (ACR), and accordingly, the concave-convex layer 022 may also be referred to as an ACR layer, and the opening K0 of the ACR layer may also be referred to as an ACR macropore. The material of the reflective layer REF may include: at least one of aluminum Al and silver Ag, or may also be a molybdenum aluminum alloy MoAl. The material of the transparent conductive layer 021 includes: indium tin oxide (ITO), and accordingly, the transparent conductive layer 021 may also be referred to as an ITO layer. Of course, the materials here are only schematic illustrations and do not limit the embodiments of the present disclosure.

[0075] Optionally, at least one light shielding layer 03 described in the embodiment of the present disclosure and the conductive layer included in the pixel 02 may be shared, or may be considered to be located in the same layer, thereby simplifying the process and saving costs.

[0076] An optional implementation: Reference Figure 4 It can be seen from the partial structure of another array substrate shown that, in the embodiment of the present disclosure, the gate conductive layer GATE included in the pixel 02 can be used to form: a gate line Gate1, and the transparent conductive layer 021 included in the pixel 02 can be used to form: a second common electrode COM.

[0077] The array substrate 0 may include two light shielding layers 03 , and the two light shielding layers 03 may be shared with the gate line Gate1 and the second common electrode COM respectively.

[0078] That is, for example, the gate line Gate1 formed by the gate conductive layer GATE can be set as a part of the light shielding layer 02 of the spacer B1, that is, the gate line Gate1 can cover the spacer B1, and the reflective layer REF can overlap with the gate line Gate1 to form a light shielding structure. On this basis, considering that the gate line Gate1 covers the spacer B1 and the part that does not overlap with the reflective layer REF is leaked, it is easy to form a vertical electric field with the common electrode in the opposing substrate 1, which causes the liquid crystal molecules to be mis-deflected, causing light leakage, the embodiment of the present disclosure further uses a transparent conductive layer 021 (such as an ITO layer) located between the gate conductive layer GATE and the reflective layer REF to form a second common electrode COM in the array substrate 0, that is, based on this embodiment, the transparent conductive layer 021 can be used as the transparent pixel electrode recorded in the above embodiment, and can also be used as the common electrode in the array substrate 0. In addition, the transparent conductive layer 021 is also set as another light shielding layer 02, covering the spacer B1, and covering the part where the gate line Gate1 does not overlap with the reflective layer REF, that is, covering the part of the gate line Gate1 exposed to the outside. In this way, the structure in the spacer B1 close to the counter substrate 1 can be the common electrode in the array substrate 0. Since the common electrode in the array substrate 0 and the common electrode in the counter substrate 1 do not form a vertical electric field, the potentials of the two are the same when the black state is displayed, so while achieving the purpose of light shielding, light leakage due to erroneous deflection of liquid crystal molecules can also be avoided.

[0079] Based on the above records, it can be known that this optional implementation method can be considered as follows: the gate line Gate1 formed by the gate conductive layer GATE is not completely covered by the reflective layer REF, and is partially exposed to the spacer B1 and overlaps with the reflective layer REF to form a light shielding structure. On this basis, considering the existence of electric field leakage of the gate line Gate1, an additional transparent conductive layer 021 is provided to form a common electrode, and the common electrode is provided to cover the non-overlapping portion of the gate line Gate1 and the reflective layer REF, that is, the leaking portion of the gate line Gate1, so as to shield the electric field generated by the gate line Gate1.

[0080] Another optional implementation: refer to Figure 5 It can be seen from the partial structure of another array substrate shown that, in the embodiment of the present disclosure, the gate conductive layer GATE included in the pixel 02 can be used to form: a second common electrode COM.

[0081] The array substrate 0 may include a light shielding layer 03 , and the light shielding layer 03 may be shared with the second common electrode COM.

[0082] That is, for example, different from the above-mentioned optional implementation, in this other implementation, the gate conductive layer GATE can be used to form the common electrode in the array substrate 0. In addition, the common electrode formed by the gate conductive layer GATE can be set as the light shielding layer 03, that is, the common electrode formed by the gate conductive layer GATE can cover the spacing area B1, and the reflective layer REF can overlap with the common electrode formed by the gate conductive layer GATE to form a light shielding structure. On this basis, since the common electrode in the array substrate 0 and the common electrode in the opposing substrate 1 will not form a vertical electric field, the potentials of the two are the same when the black state is displayed, so while achieving the purpose of light shielding, it can also avoid light leakage due to the mis-deflection of liquid crystal molecules.

[0083] Another optional implementation: Reference Figure 6 It can be seen from the partial structure of another array substrate that the array substrate 0 may include a light shielding layer 03 , and the light shielding layer 03 may be shared with the source-drain conductive layer SD included in the pixel 02 .

[0084] That is, for example, different from the above one and another optional implementation, in this other optional implementation, the source-drain conductive layer SD can be directly set instead of the gate conductive layer GATE as the light shielding layer 03. That is, the source-drain conductive layer SD can cover the spacer B1, and the reflective layer REF can overlap with the source-drain conductive layer SD to form a light shielding structure. On this basis, because the source-drain conductive layer SD in the array substrate 0 and the common electrode in the opposing substrate 1 are generally at the same potential when the black state is displayed, while achieving the purpose of light shielding, it can also avoid light leakage due to the mis-deflection of liquid crystal molecules.

[0085] Based on the above description, it can be known that in this other optional implementation and yet another optional implementation, the gate line Gate1 formed by the gate conductive layer GATE can be completely covered by the reflective layer REF, that is, the orthographic projection of the reflective layer REF on the substrate 01 can cover the orthographic projection of the gate line Gate1 on the substrate 01. In this way, the electric field generated by the gate line Gate1 will not leak out. And, in the above one optional implementation, a light-shielding structure is formed by arranging a common electrode formed by the reflective layer REF and the gate conductive layer GATE to overlap; in the above another optional implementation, a light-shielding structure is formed by arranging a common electrode formed by the reflective layer REF and the source-drain conductive layer SD to overlap.

[0086] Optionally, for the above-mentioned another optional implementation method and yet another optional implementation method, the line width of the gate line Gate1 can also be reduced, that is, the line width of the gate line Gate1 is set to be smaller than the line width threshold, so that the orthographic projection of the reflective layer REF on the substrate 01 covers the orthographic projection of the gate line Gate1 on the substrate 01.

[0087] It should be noted that, on the basis of reducing the line width of the gate line Gate1, the coupling capacitance on the gate line Gate1 can also be reduced, thereby further ensuring a better display effect.

[0088] For example, in some embodiments, the line width threshold may be 5 micrometers (μm). That is, the line width of the traditional gate line Gate1 of about 10 μm can be reduced to 5 μm. Of course, the setting of the line width of the gate line Gate1 also needs to take into account factors such as resistance, capacitance, and broken wires, so the line width of the gate line Gate1 can usually be set to be greater than or equal to 3.5 μm. That is, in the embodiment of the present disclosure, the line width of the gate line Gate1 can be set to be greater than or equal to 3.5 μm and less than or equal to 5 μm.

[0089] Optionally, similar to the gate line Gate1, for the Source line formed by the source-drain conductive layer SD, the line width of the Source line can also be reduced to reduce the coupling capacitance on the Source line, for example, the line width of the traditional Source line of about 10 μm can be reduced to 3 μm. Of course, reducing the line width of the Source line here is mostly applied to one of the above optional implementations, so that the Source line can be completely covered by the reflective layer REF.

[0090] It should be noted that the above line width values ​​are only for illustrative purposes and do not limit the embodiments of the present disclosure.

[0091] Optional, in Figure 1 Based on Figure 7 It can be seen from the top view of a display substrate that the display substrate described in the embodiment of the present disclosure may also include:

[0092] Point supporting (PS) column PS. The point supporting column PS may be located between the array substrate 0 and the counter substrate 1. There are no liquid crystal molecules at the PS position.

[0093] And, black matrix BM. The black matrix BM can be located between the support pillar PS and the array substrate 0, and the orthographic projection of the black matrix BM on the substrate 01 can overlap with the orthographic projection of the gate line Gate1 formed by the gate conductive layer GATE on the substrate 01. That is, at the PS position, the black matrix BM can be added to shield the leakage light generated by the leakage of the electric field of the gate line Gate1.

[0094] Of course, in another optional implementation, refer to Figure 8It can be seen from the other display substrate shown that in the embodiment of the present disclosure, a black matrix BM can also be set on the side where all gate lines Gate1 leak to achieve light leakage. However, this will lead to a decrease in the reflective aperture ratio. Therefore, as described in the above embodiment, the embodiment of the present disclosure forms a light shielding structure on one side of the array substrate 0 to replace the black matrix BM to achieve light shielding, so that the other parts except the PS position do not need to be provided with a black matrix BM, thereby improving the reflective aperture ratio and ensuring a better reflection effect.

[0095] It should be noted that the black matrix BM is a choice of the light shielding layer. In some embodiments, a black pixel defining layer can be provided to replace the black matrix BM as the light shielding layer. The light shielding structure formed on one side of the array substrate 0 in the embodiment of the present disclosure can also be considered as a black matrix BM.

[0096] That is, on the one hand, the embodiment of the present disclosure can block the light leakage caused by the leakage of the electric field of the gate line Gate1 by setting a black matrix BM on one side of the opposing substrate 1. On the other hand, the embodiment of the present disclosure can form a BM by setting a reflective layer REF on one side of the array substrate 0 to overlap with the gate line Gate1, and at the same time setting a common electrode formed by a transparent conductive layer 021 to cover the non-overlapping position of the reflective layer REF and the gate line Gate1, so as to shield the electric field leaked from the gate line Gate1, so that the electric field of the gate line Gate1 does not leak out. On the other hand, the embodiment of the present disclosure can shrink the gate line Gate1, and at the same time set the reflective layer REF to overlap with the common electrode to form a BM, so that the electric field of the gate line Gate1 does not leak out. On the other hand, the embodiment of the present disclosure can shrink the gate line Gate1, and at the same time set the reflective layer REF to overlap with the source and drain conductive layer SD to form a BM, so that the electric field of the gate line Gate1 does not leak out. The purpose of preventing light leakage is achieved.

[0097] Optional, reference Figure 7 and Fig. 9 It can be seen from the top view of another display substrate that the pixel 02 can also include a pixel circuit area A3, and the pixel circuit area A3, the reflective area A1 and the transmissive area A2 can be adjacent to each other in sequence. That is, the reflective area A1 can be located between the pixel circuit area A3 and the transmissive area A2, and the pixel circuit area A3 and the transmissive area A2 can both be adjacent to the reflective area A1. In addition, the opposing substrate 1 described in the embodiment of the present disclosure may include: a plurality of filter portions 10 arranged at intervals corresponding to the plurality of pixels 02 arranged at intervals, and the structure including the plurality of filter portions 10 may also be called a color filter. Accordingly, the opposing substrate 1 may be called a color filter substrate. For example, Figure 7 and Fig. 9 The plurality of pixels 02 shown include a red pixel 02R, a green pixel 02G, and a blue pixel 02B.

[0098] The filter section 10 may include: a first portion 101 corresponding to the transmission area A2, a second portion 102 corresponding to the reflection area A1, and a third portion 103 corresponding to the pixel circuit area A3. Moreover, the orthographic projection of the first portion 101 on the substrate 01 may cover the orthographic projection of the transmission area A2 of the pixel 02 on the substrate 01, the orthographic projection of the second portion 102 on the substrate 01 may be located within the orthographic projection of the reflection area A1 of the pixel 02 on the substrate 01, and the orthographic projection of the third portion 103 on the substrate 01 may be located within the orthographic projection of the pixel circuit area A3 of the pixel 02 on the substrate 01. That is, the filter section 10 may cover the transmission area A2 to ensure a better transmission effect. Moreover, in the reflection area A1 and the pixel circuit area A3, the filter section 10 may be partially dug, that is, the filter section 10 may be covered by the reflection area A1, so that the filter sections 10 corresponding to the pixels 02 of different colors are spaced apart, thereby improving the reflectivity and ensuring a better reflection effect. For the hole-punched area, ambient light will not directly enter the human eye through the filter 10. It should be noted that the filter 10 corresponding to pixels 02 of different colors may also have different designs. Figure 7 and Fig. 9 The difference is: Figure 7 BM was set only at the PS position; Fig. 9 BM is set at the light leakage position of the gate line Gate1.

[0099] Optionally, in some embodiments, continue to refer to Figure 7 and Fig. 9 It can be seen that the size of the first portion 101 of the filter unit 10 can be larger than the size of the third portion 103, and the size of the third portion 103 can be larger than the size of the second portion 102. That is, the size of the portion of the filter unit 101 located in the transmission area A2 can be the largest, the size of the portion located in the pixel circuit area A3 is the second largest, and the size of the portion located in the reflection area A1 is the smallest. The size here can refer to: the area of ​​the positive projection of the filter unit 10 on the substrate 01.

[0100] Optionally, in some embodiments, continue to refer to Figure 7 and Fig. 9 It can be seen that the orthographic projection of the filter unit 10 on the substrate 01 may be in the shape of a stripe. This can facilitate the setting of the position of the filter unit 10. Of course, the shape here is only a schematic illustration and does not limit the embodiment of the present disclosure.

[0101] In summary, the embodiments of the present disclosure provide a display substrate. The array substrate in the display substrate includes: a substrate, a plurality of pixels located on one side of the substrate and spaced from each other, and a shading layer located in the reflective layer spacing area between every two adjacent pixels. The orthographic projection of the shading layer on the substrate covers the orthographic projection of the spacing area on the substrate, and the orthographic projection of the reflective layer on the substrate overlaps with the orthographic projection of the shading layer on the substrate. In this way, a shading structure can be formed in the spacing area to achieve shading and avoid light leakage. On this basis, a black matrix does not need to be set at the position corresponding to the spacing area on the side of the opposing substrate opposite to the array substrate. In this way, a large reflective aperture ratio can be ensured, thereby ensuring a better display effect.

[0102] In addition, in the embodiment of the present disclosure, when the black state is displayed, the potential of the shading layer close to the opposing substrate is the same as that of the common electrode in the opposing substrate. This can avoid the shading layer in the array substrate and the common electrode in the opposing substrate from forming a vertical electric field, which may cause the liquid crystal molecules to be mis-deflected and cause light leakage, thereby further ensuring a better display effect.

[0103] Fig.10 1 is a flow chart of a method for preparing a display substrate provided in an embodiment of the present disclosure, which is used to prepare the display substrate described in the above embodiment. Fig.10 As shown, the method includes:

[0104] Step 1001: forming an opposing substrate.

[0105] Optionally, as described in the above embodiment, the formed opposing substrate 1 includes: a first common electrode.

[0106] Step 1002: forming a substrate on the opposite side of the counter substrate.

[0107] Optionally, the formed substrate 01 may include a glass substrate or a flexible substrate.

[0108] Step 1003: forming a plurality of pixels spaced apart from each other on a side of the substrate close to the counter substrate.

[0109] Optional, such as Figure 2 and Figure 3 As shown, the formed pixel 02 includes adjacent reflective region A1 and transmissive region A2. Moreover, in both the reflective region A1 and the transmissive region A2, the pixel 02 includes: a transparent conductive layer 021 located on one side of the substrate 01. In the reflective region A1, the pixel 02 also includes: a gate conductive layer GATE and a source-drain conductive layer SD located between the transparent conductive layer 021 and the substrate 01 and stacked in sequence, and a reflective layer REF located on the side of the transparent conductive layer 021 away from the substrate 01.

[0110] Step 1004 , forming at least one light shielding layer in the interval area between the reflective layers of two adjacent pixels.

[0111] Optional, such as Figure 3 As shown, the orthographic projection of at least one light-shielding layer 03 formed on the substrate 01 covers the orthographic projection of the spacing area B1 on the substrate 01, and the orthographic projection of the reflective layer on the REF substrate 01 overlaps with the orthographic projection of at least one light-shielding layer 03 on the substrate 01 to form a light-shielding structure in the spacing area B1; and, when displayed in a black state, the light-shielding layer 03 close to the opposing substrate 1 has the same potential as the first common electrode.

[0112] As an optional implementation, Figure 4 Taking the display substrate shown in FIG. 1 as an example, the preparation process of the array substrate is described as follows:

[0113] (1) First, a gate metal material may be deposited on one side of a provided substrate 01 (eg, a glass substrate), and the gate metal material may be processed using a GateMask to form a gate conductive layer GATE, and the formed gate conductive layer GATE may include a gate line Gate1.

[0114] (2) Then, a gate insulating material may be deposited on the side of the gate conductive layer GATE away from the substrate 01 to form a gate insulating layer GI; then, an Active material may be deposited on the side of the gate insulating layer GI away from the substrate 01, and the active material may be processed using an Active Mask to form an active layer ACT.

[0115] (3) Then, source-drain metal materials can be deposited on the side of the active layer ACT away from the substrate 01, and the source-drain metal materials can be processed using SDMask to form a source-drain conductive layer SD, and the formed source-drain conductive layer SD includes a Source line (such as a data line) and a source-drain conductive pattern.

[0116] (4) Then, a passivation material may be deposited on the side of the source-drain conductive layer SD away from the substrate 01 to form a passivation layer PVX, and holes may be punched on the passivation layer PVX to form via holes penetrating the passivation layer PVX to expose the source-drain conductive layer SD.

[0117] (5) Then, a transparent conductive material (such as indium tin oxide ITO) can be deposited on the side of the passivation layer PVX away from the substrate 01, and the transparent conductive material can be processed with an ITO Mask to form a transparent conductive layer 021, that is, an ITO layer. The ITO layer can be overlapped with the exposed source and drain conductive layer SD through the above-mentioned vias penetrating the passivation layer PVX. It should be noted that in this implementation, the formed ITO layer can be used as a transparent pixel electrode and a common electrode in the array substrate 0, that is, the second common electrode COM described in the above-mentioned embodiment.

[0118] (6) Then, a concave-convex layer 022 (e.g., an ACR layer) can be formed on the side of the ITO layer away from the substrate 01, and the portion of the ACR layer located in the transmission area A2 can be removed to form an ACR macrohole to expose the portion of the transparent conductive layer 021 located in the transmission area A2. In this way, the position of the ACR macrohole can be divided into the transmission area A2, and the other position can be divided into the reflection area A1. Of course, the portion of the reflection area A1 including the active layer ACT can be further divided into the channel area. It can be seen from here that due to the existence of the ACR layer, the film thickness of the reflection area A1 and the transmission area A2 is different, forming a double-box thick display substrate.

[0119] (7) Then, a reflective metal material (such as metal Al, molybdenum aluminum alloy MoAl or metal Ag) can be deposited on the side of the ACR layer away from the substrate 01 to form a reflective layer REF. Moreover, at the position of the ACR macrohole, the reflective layer REF can be overlapped with the ITO layer along the ACR macrohole, so that the reflective layer REF as a metal pixel electrode is coupled with the ITO layer as a transparent pixel electrode. It should be noted that in this implementation, the orthographic projection of the gate line Gate1 formed by the gate conductive layer GATE on the substrate 01 covers the spacing area B1 between the reflective layer REF in two adjacent pixels 02, that is, it is not completely covered by the reflective layer REF. In addition, in the spacing area B1, the orthographic projection of the reflective layer REF on the substrate 01 also overlaps with the orthographic projection of the gate line Gate1 on the substrate 01, so as to form a shading structure on one side of the array substrate 0 to achieve shading. Moreover, the orthographic projection of the common electrode formed by the ITO layer on the substrate 01 also covers the spacer area B1, that is, between the portion of the gate line Gate1 not covered by the reflective layer REF and the reflective layer REF, so as to shield the electric field leaked from the gate line Gate1, thereby avoiding the problem of mis-deflection of liquid crystal molecules due to the leakage of the electric field of the gate line Gate1 and the formation of a vertical electric field with the common electrode on the side of the opposing substrate 1 when the reflective layer REF and the gate line Gate1 overlap to form a shading structure, thereby further ensuring a better shading effect.

[0120] Optionally, for one of the above optional implementations, Fig.11 A top view of the overall film layer including the gate conductive layer GATE+active layer ACT+source-drain conductive layer SD+ITO layer+ACR layer+reflective layer REF is shown. Fig.12 Shows Fig.11 The structure shown is a partial enlarged top view in the DD' direction. Fig.11 Based on the top view of the overall film layer, Fig.13 shows a cross-sectional view of the array substrate in the AA' direction;

[0121] Fig.14 shows a cross-sectional view of the array substrate in the BB' direction; Fig.15 FIG. 4 shows a cross-sectional view of the array substrate in the CC' direction. Figure 4 The cross-sectional view of the array substrate in the DD' direction is shown, which is not illustrated here. Fig.12 It can be further seen that for Figure 4 As for the structure shown, a reflective layer REF is specifically set in the interval area B1 to overlap the gate line Gate1 formed by the gate conductive layer GATE to form a light-shielding structure, and on this basis, a transparent conductive layer 021 is additionally set between the gate line Gate1 formed by the gate conductive layer GATE and the reflective layer REF to form a common electrode COM, so that the common electrode COM covers the non-overlapping part of the gate line Gate1 and the reflective layer REF, that is, the leaking part of the gate line Gate1, so as to shield the electric field generated by the gate line Gate1. It can be considered that the formed light-shielding structure includes: the gate line Gate1 formed by the gate conductive layer GATE stacked in sequence, the common electrode COM formed by the transparent conductive layer 021, and the reflective layer REF. In addition, Fig.12 The source-drain conductive layer SD is also schematically indicated.

[0122] As another optional implementation, Figure 5 Taking the display substrate shown in FIG. 1 as an example, the preparation process of the array substrate is described as follows:

[0123] (1) First, a gate metal material may be deposited on one side of the provided substrate 01, and the gate metal material may be processed by using a Gate Mask to form a gate conductive layer GATE, and the formed gate conductive layer GATE includes a gate line Gate1 and a second common electrode COM, that is, in this implementation, the gate conductive layer GATE may be used as a common electrode on one side of the array substrate 0. Optionally, in this embodiment, the line width of the gate line Gate1 may be reduced to reduce the coupling capacitance on the gate line Gate1.

[0124] (2) Then, a gate insulating material may be deposited on the side of the gate conductive layer GATE away from the substrate 01 to form a gate insulating layer GI; then, an Active material may be deposited on the side of the gate insulating layer GI away from the substrate 01, and the active material may be processed using an Active Mask to form an active layer ACT.

[0125] (3) Then, a source-drain metal material may be deposited on the side of the active layer ACT away from the substrate 01, and the source-drain metal material may be processed by SDMask to form a source-drain conductive layer SD, and the formed source-drain conductive layer SD includes a Source line and a source-drain conductive pattern. Optionally, in this embodiment, the line width of the Source line may be reduced to reduce the coupling capacitance on the Source line.

[0126] (4) Then, a passivation material may be deposited on the side of the source-drain conductive layer SD away from the substrate 01 to form a passivation layer PVX, and holes may be punched on the passivation layer PVX to form via holes penetrating the passivation layer PVX to expose the source-drain conductive layer SD.

[0127] (5) Then, a transparent conductive material (such as indium tin oxide ITO) can be deposited on the side of the passivation layer PVX away from the substrate 01, and the transparent conductive material can be processed with an ITO Mask to form a transparent conductive layer 021, i.e., an ITO layer. The ITO layer can be overlapped with the exposed source and drain conductive layer SD through the above-mentioned vias penetrating the passivation layer PVX. It should be noted that in this implementation, the formed ITO layer can be used as a transparent pixel electrode.

[0128] (6) Then, a concave-convex layer 022 (e.g., an ACR layer) can be formed on the side of the ITO layer away from the substrate 01, and the portion of the ACR layer located in the transmission area A2 can be removed to form an ACR macrohole to expose the portion of the transparent conductive layer 021 located in the transmission area A2. In this way, the position of the ACR macrohole can be divided into the transmission area A2, and the other position can be divided into the reflection area A1. Of course, as described in the above embodiment, the portion of the reflection area A1 including the active layer ACT can be further divided into the channel area.

[0129] (7) Then, a reflective metal material can be deposited on the side of the ACR layer away from the substrate 01 to form a reflective layer REF. In addition, at the position of the ACR large hole, the reflective layer REF can be overlapped with the ITO layer along the ACR large hole, so that the reflective layer REF as a metal pixel electrode is coupled with the ITO layer as a transparent pixel electrode. It should be noted that in this implementation, the gate line Gate1 formed by the gate conductive layer GATE is located within the positive projection of the reflective layer REF on the substrate 01, and there is no electric field leakage; the positive projection of the common electrode (i.e., the second common electrode COM) formed by the gate conductive layer GATE on the substrate 01 covers the spacing area B1 between the reflective layer REF in two adjacent pixels 02. In addition, in the spacing area B1, the positive projection of the reflective layer REF on the substrate 01 also overlaps with the positive projection of the common electrode formed by the gate conductive layer GATE on the substrate 01, so as to form a shading structure on one side of the array substrate 0 to achieve shading.

[0130] Optionally, for another optional implementation of the above, Fig.16 A top view of a local film layer of the array substrate in the spacing area B1 is shown. Figure 5 The structure shown can be considered as Fig.16 The cross-section of the top view in the DD' direction is shown. Fig.16 It can be further seen that for Figure 5As for the structure shown, the reflective layer REF is specifically arranged in the spacer B1 to overlap the common electrode COM formed by the gate conductive layer GATE to form a light shielding structure. It can be considered that the formed light shielding structure includes: the common electrode COM formed by the gate conductive layer GATE and the reflective layer REF stacked in sequence. In addition, Fig.16 The gate line Gate1 and the source-drain conductive layer SD formed by the gate conductive layer GATE at other positions are also schematically indicated.

[0131] As another optional implementation, Figure 6 Taking the display substrate shown in FIG. 1 as an example, the preparation process of the array substrate is described as follows:

[0132] (1) First, a gate metal material may be deposited on one side of the provided substrate 01, and the gate metal material may be processed by using a Gate Mask to form a gate conductive layer GATE, and the formed gate conductive layer GATE includes a gate line Gate1 and a second common electrode COM, that is, in this implementation, the gate conductive layer GATE may be used as a common electrode on one side of the array substrate 0. Optionally, in this embodiment, the line width of the gate line Gate1 may be reduced to reduce the coupling capacitance on the gate line Gate1.

[0133] (2) Then, a gate insulating material may be deposited on the side of the gate conductive layer GATE away from the substrate 01 to form a gate insulating layer GI; then, an Active material may be deposited on the side of the gate insulating layer GI away from the substrate 01, and the active material may be processed using an Active Mask to form an active layer ACT.

[0134] (3) Then, source-drain metal materials may be deposited on the side of the active layer ACT away from the substrate 01, and the source-drain metal materials may be processed by SDMask to form a source-drain conductive layer SD, and the formed source-drain conductive layer SD includes Source lines and source-drain conductive patterns.

[0135] (4) Then, a passivation material may be deposited on the side of the source-drain conductive layer SD away from the substrate 01 to form a passivation layer PVX, and holes may be punched on the passivation layer PVX to form via holes penetrating the passivation layer PVX to expose the source-drain conductive layer SD.

[0136] (5) Then, a transparent conductive material (such as indium tin oxide ITO) can be deposited on the side of the passivation layer PVX away from the substrate 01, and the transparent conductive material can be processed with an ITO Mask to form a transparent conductive layer 021, i.e., an ITO layer. The ITO layer can be overlapped with the exposed source and drain conductive layer SD through the above-mentioned vias penetrating the passivation layer PVX. It should be noted that in this implementation, the formed ITO layer can be used as a transparent pixel electrode.

[0137] (6) Then, a concave-convex layer 022 (e.g., an ACR layer) can be formed on the side of the ITO layer away from the substrate 01, and the portion of the ACR layer located in the transmission area A2 can be removed to form an ACR macrohole to expose the portion of the transparent conductive layer 021 located in the transmission area A2. In this way, the position of the ACR macrohole can be divided into the transmission area A2, and the other position can be divided into the reflection area A1. Of course, as described in the above embodiment, the portion of the reflection area A1 including the active layer ACT can be further divided into the channel area.

[0138] (7) Then, a reflective metal material can be deposited on the side of the ACR layer away from the substrate 01 to form a reflective layer REF. Moreover, at the position of the ACR large hole, the reflective layer REF can be overlapped with the ITO layer along the ACR large hole, so that the reflective layer REF as a metal pixel electrode is coupled with the ITO layer as a transparent pixel electrode. It should be noted that in this implementation, the gate line Gate1 formed by the gate conductive layer GATE is located within the orthographic projection of the reflective layer REF on the substrate 01 by the orthographic projection on the substrate 01, and there is no electric field leakage; the orthographic projection of the source and drain conductive layer SD on the substrate 01 covers the spacing area B1 between the reflective layer REF in two adjacent pixels 02. In addition, in the spacing area B1, the orthographic projection of the reflective layer REF on the substrate 01 also overlaps with the orthographic projection of the source and drain conductive layer SD on the substrate 01, so as to form a shading structure on one side of the array substrate 0 to achieve shading.

[0139] Optionally, for another optional implementation of the above, Fig.17 A top view of a local film layer of the array substrate in the spacing area B1 is shown. Figure 6 The structure shown can be considered as Fig.17 The cross-section of the top view in the DD' direction is shown. Fig.17 It can be further seen that for Figure 6 As for the structure shown, a reflective layer REF is specifically arranged in the spacer region B1 to overlap with the source-drain conductive layer SD to form a light shielding structure. It can be considered that the formed light shielding structure includes: the source-drain conductive layer SD and the reflective layer REF stacked in sequence. In addition, Fig.17 The gate line Gate1 formed by the gate conductive layer GATE at other positions is also schematically indicated.

[0140] Optional, for the above Figures 4 to 6 In terms of the corresponding implementation method, at the end, if Figure 7 As shown, a black matrix BM can be set at the PS position on one side of the counter substrate 1 to block the light leakage caused by the gate line Gate1 at the position without liquid crystal molecules. However, there is no need to set a black matrix BM at the position corresponding to the spacer B1 on one side of the counter substrate 1 to achieve light shielding. In this way, a large reflective aperture ratio can be ensured.

[0141] Of course, reference Figure 8 and Fig. 9 It can be seen from the other display substrate shown that in some other implementations, a black matrix BM can be directly arranged on one side of the counter substrate 1 to block the leaked portion of the gate line Gate1 on one side of the array substrate 0, thereby preventing the electric field of the gate line Gate1 from leaking. That is, the preparation process is as follows:

[0142] (1) First, a gate metal material can be deposited on one side of the provided substrate 01, and the gate metal material can be processed using a Gate Mask to form a gate conductive layer GATE, and the formed gate conductive layer GATE includes a gate line Gate1 and a second common electrode COM, that is, in this implementation, the gate conductive layer GATE can be used as the common electrode on one side of the array substrate 0.

[0143] (2) Then, a gate insulating material may be deposited on the side of the gate conductive layer GATE away from the substrate 01 to form a gate insulating layer GI; then, an Active material may be deposited on the side of the gate insulating layer GI away from the substrate 01, and the active material may be processed using an Active Mask to form an active layer ACT.

[0144] (3) Then, source-drain metal materials may be deposited on the side of the active layer ACT away from the substrate 01, and the source-drain metal materials may be processed by SDMask to form a source-drain conductive layer SD, and the formed source-drain conductive layer SD includes Source lines and source-drain conductive patterns.

[0145] (4) Then, a passivation material may be deposited on the side of the source-drain conductive layer SD away from the substrate 01 to form a passivation layer PVX, and holes may be punched on the passivation layer PVX to form via holes penetrating the passivation layer PVX to expose the source-drain conductive layer SD.

[0146] (5) Then, a transparent conductive material (such as indium tin oxide ITO) can be deposited on the side of the passivation layer PVX away from the substrate 01, and the transparent conductive material can be processed with an ITO Mask to form a transparent conductive layer 021, i.e., an ITO layer. The ITO layer can be overlapped with the exposed source and drain conductive layer SD through the above-mentioned vias penetrating the passivation layer PVX. It should be noted that in this implementation, the formed ITO layer can be used as a transparent pixel electrode.

[0147] (6) Then, a concave-convex layer 022 (e.g., an ACR layer) can be formed on the side of the ITO layer away from the substrate 01, and the portion of the ACR layer located in the transmission area A2 can be removed to form an ACR macrohole to expose the portion of the transparent conductive layer 021 located in the transmission area A2. In this way, the position of the ACR macrohole can be divided into the transmission area A2, and the other position can be divided into the reflection area A1. Of course, as described in the above embodiment, the portion of the reflection area A1 including the active layer ACT can be further divided into the channel area.

[0148] (7) Then, a reflective metal material may be deposited on the side of the ACR layer away from the substrate 01 to form a reflective layer REF. Furthermore, at the location of the ACR macrohole, the reflective layer REF may be overlapped with the ITO layer along the ACR macrohole, so that the reflective layer REF as a metal pixel electrode is coupled with the ITO layer as a transparent pixel electrode.

[0149] (8) Finally, a black matrix BM may be provided on the external leakage side of the gate line Gate1 formed by the gate conductive layer GATE to shield light leakage and prevent the occurrence of light leakage.

[0150] Optionally, for another implementation manner above, Fig.18 FIG. 1 shows a top view of a display substrate. Fig.18 It can also be seen that the black matrix BM covers the light-leaking portion of the gate line Gate1 formed by the gate conductive layer GATE, thereby effectively shielding the electric field of the gate line Gate1 from leaking outward and preventing the occurrence of light leakage.

[0151] It should be noted that the above-mentioned mask processing process may include a one-time patterning process, which includes: coating, exposure and development.

[0152] In summary, the embodiments of the present disclosure provide a method for preparing a display substrate. In this method, a plurality of pixels spaced apart from each other can be formed on one side of the substrate, and a light-shielding layer can be formed in the reflective layer spacing area between every two adjacent pixels. The orthographic projection of the formed light-shielding layer on the substrate covers the orthographic projection of the spacing area on the substrate, and the orthographic projection of the reflective layer on the substrate overlaps the orthographic projection of the light-shielding layer on the substrate. In this way, a light-shielding structure can be formed in the spacing area to achieve light shielding and avoid light leakage. On this basis, a black matrix does not need to be set at the position corresponding to the spacing area on one side of the opposing substrate. In this way, a large reflective aperture ratio can be ensured, thereby ensuring a better display effect.

[0153] In addition, in the embodiment of the present disclosure, when the black state is displayed, the potential of the shading layer close to the opposing substrate is the same as that of the common electrode in the opposing substrate. This can avoid the shading layer in the array substrate and the common electrode in the opposing substrate from forming a vertical electric field, which may cause the liquid crystal molecules to be mis-deflected and cause light leakage, thereby further ensuring a better display effect.

[0154] Fig.19 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. Fig.19 As shown, the display device includes: a power supply component J1, and a display substrate 00 as described in the above embodiment.

[0155] The power supply component J1 is coupled to the display substrate 00 and is used to supply power to the display substrate 00 .

[0156] Optionally, the display device may be an LCD display device, and the display device may be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, e-books, and any other products or components with display functions.

[0157] Since the display device can have substantially the same technical effects as the display substrate described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0158] It should be noted that the terms used in the embodiments of the present disclosure are only used to explain the embodiments and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0159] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish different components.

[0160] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0161] Words such as “include” or “comprising” and the like mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0162] "Up", "down", "left" or "right" etc. are only used to indicate relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly. "Connected" or "coupled" refers to electrical connection.

[0163] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display substrate, characterized in that: The display substrate comprises: an array substrate and an opposing substrate arranged opposite to each other; the opposing substrate comprises: a first common electrode; the array substrate comprises: substrate; A plurality of pixels arranged at intervals are located on a side of the substrate close to the counter substrate; wherein the pixel comprises a reflection area and a transmission area adjacent to each other; in the reflection area and the transmission area, the pixel comprises: a transparent conductive layer located on one side of the substrate; in the reflection area, the pixel further comprises: a gate conductive layer and a source-drain conductive layer located between the transparent conductive layer and the substrate and stacked in sequence, and a reflection layer located on a side of the transparent conductive layer away from the substrate; At least one light-shielding layer is located in the interval area between the reflective layers of two adjacent pixels; wherein the orthographic projection of the at least one light-shielding layer on the substrate covers the orthographic projection of the interval area on the substrate, and the orthographic projection of the reflective layer on the substrate overlaps with the orthographic projection of the at least one light-shielding layer on the substrate to form a light-shielding structure in the interval area; and when displayed in a black state, the light-shielding layer close to the opposing substrate in the at least one light-shielding layer has the same potential as the first common electrode.

2. The display substrate according to claim 1, characterized in that: The at least one light shielding layer is shared with the conductive layer included in the pixel.

3. The display substrate according to claim 2, characterized in that: The gate conductive layer included in the pixel is used to form: a gate line, and the transparent conductive layer included in the pixel is used to form: a second common electrode; Wherein, the array substrate comprises two light shielding layers, and the two light shielding layers are respectively shared with the gate line and the second common electrode.

4. The display substrate according to claim 2, characterized in that: The pixel includes a gate conductive layer for forming: a second common electrode; Wherein, the array substrate includes a light shielding layer, and the light shielding layer is shared with the second common electrode.

5. The display substrate according to claim 2, characterized in that: The array substrate includes a light shielding layer, and the light shielding layer is shared with the source-drain conductive layer included in the pixel.

6. The display substrate according to claim 4 or 5, characterized in that: The gate conductive layer included in the pixel is also used to form: a gate line; The orthographic projection of the reflective layer on the substrate covers the orthographic projection of the gate line on the substrate.

7. The display substrate according to claim 6, characterized in that: The line width of the gate line is smaller than a line width threshold, so that the orthographic projection of the reflective layer on the substrate covers the orthographic projection of the gate line on the substrate.

8. The display substrate according to claim 7, characterized in that: The line width threshold is 5 microns.

9. The display substrate according to any one of claims 1 to 4, characterized in that: The display substrate further comprises: A supporting column, located between the display substrate and the counter substrate; A black matrix is ​​located between the support pillars and the array substrate, and an orthographic projection of the black matrix on the substrate overlaps with an orthographic projection of the gate line formed by the gate conductive layer on the substrate.

10. The display substrate according to any one of claims 1 to 4, characterized in that: The pixel further comprises a pixel circuit area, wherein the pixel circuit area, the reflection area and the transmission area are adjacent to each other in sequence; the opposing substrate comprises: a plurality of filter parts arranged at intervals corresponding to the plurality of pixels arranged at intervals; Wherein, the filter section includes: a first portion corresponding to the transmission area, a second portion corresponding to the reflection area, and a third portion corresponding to the pixel circuit area; Furthermore, the orthographic projection of the first part on the substrate covers the orthographic projection of the transmission area of ​​the pixel on the substrate, the orthographic projection of the second part on the substrate is located within the orthographic projection of the reflection area of ​​the pixel on the substrate, and the orthographic projection of the third part on the substrate is located within the orthographic projection of the pixel circuit area of ​​the pixel on the substrate.

11. The display substrate according to claim 10, characterized in that: The size of the first portion is larger than that of the third portion, and the size of the third portion is larger than that of the second portion.

12. The display substrate according to any one of claims 1 to 4, characterized in that: In the reflective region and the transmissive region, the pixel further comprises: a gate insulating layer and a passivation layer located between the transparent conductive layer and the substrate and stacked in sequence; in the reflective region, the gate insulating layer is located between the gate conductive layer and the source-drain conductive layer, the passivation layer is located between the source-drain conductive layer and the transparent conductive layer, and the pixel further comprises: a concave-convex layer located between the transparent conductive layer and the reflective layer; Among them, the reflective layer and the concave-convex layer both have openings exposing the transmission area, so that the transparent conductive layer is exposed in the transmission area, and the reflective layer overlaps with the transparent conductive layer along the opening, and the transparent conductive layer is also overlapped with the source-drain conductive layer through a via hole penetrating the passivation layer.

13. The display substrate according to claim 12, characterized in that: The material of the concavo-convex layer includes: acrylic; the material of the reflective layer includes: at least one of aluminum and silver; the material of the transparent conductive layer includes: indium tin oxide.

14. A method for preparing a display substrate, characterized in that: Used for preparing a display substrate as claimed in any one of claims 1 to 13; the method comprises: forming an opposing substrate, the opposing substrate comprising: a first common electrode; forming a substrate on a side opposite to the counter substrate; A plurality of pixels are formed at intervals on a side of the substrate close to the counter substrate, and the formed pixels include adjacent reflective areas and transmissive areas; in the reflective area and the transmissive area, the pixels include: a transparent conductive layer located on one side of the substrate; in the reflective area, the pixels also include: a gate conductive layer and a source-drain conductive layer located between the transparent conductive layer and the substrate and stacked in sequence, and a reflective layer located on a side of the transparent conductive layer away from the substrate; At least one light-shielding layer is formed in the interval area of ​​the reflective layers of two adjacent pixels, and the orthographic projection of the at least one light-shielding layer formed on the substrate covers the orthographic projection of the interval area on the substrate, and the orthographic projection of the reflective layer on the substrate overlaps with the orthographic projection of the at least one light-shielding layer on the substrate to form a light-shielding structure in the interval area; and when displayed in a black state, the light-shielding layer close to the opposing substrate has the same potential as the first common electrode.

15. A display device, characterized in that: The display device comprises: a power supply component, and a display substrate as claimed in any one of claims 1 to 13; Wherein, the power supply component is coupled to the display substrate and is used to supply power to the display substrate.

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