Cholesteric liquid crystal display panel and driving method thereof
By introducing storage capacitors into the cholesteric liquid crystal display panel and combining specific driving methods, the problem of limited cross-voltage range of existing cholesteric liquid crystal display modules is solved, achieving a wider cross-voltage range and higher compatibility.
Patent Information
- Application Number
- CN202411879275.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-03-04
AI Technical Summary
The existing cholesteric liquid crystal display modules have the problem of limited cross-pressure range in the driving mode, resulting in limited compatibility.
By introducing storage capacitors into the cholesteric liquid crystal display panel and combining a specific driving method, a high-span voltage display effect is achieved. The specific method includes applying a variable first potential to the TFT substrate through the first common end, applying a variable second potential to the CF substrate through the second common end, and providing a gate driving signal to the gate line through the gate driver until the pixel unit enters the P state.
The cross-voltage range of cholesteric LCD displays is expanded, the compatibility of the display is improved, and the limitation of conventional source driving voltages is avoided.
Smart Images
Figure CN119556509A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of display panel driving, and in particular to a cholesteric liquid crystal display panel and a driving method thereof. Background Art
[0002] Liquid crystal display modules are widely used in various display devices, and their performance directly affects the display effect. Cholesteric liquid crystal has unique optical properties and can provide a wider viewing angle and higher contrast. However, existing cholesteric liquid crystal display modules have certain limitations in driving methods. Figure 1 As shown in the figure, the conventional cholesteric LCD single pixel driving architecture mainly consists of gate line, source line, common line, TFT transistor and pixel unit, where the source line is used to send data to the drain of TFT, the gate line controls the gate of TFT to control the TFT on or off, and the pixel unit is connected to the source of TFT to receive and store data signal and form an electric field with the common electrode to control the deflection of liquid crystal. Figure 2 As shown in the figure, the image display is completed through three stages: power-on / normal Xon / scanning. Because the driver IC supports limited voltage, generally only (6-15V), it is difficult to achieve a clamping voltage of more than 50V. As a result, the compatibility of the active drive solution of the liquid crystal is limited. Summary of the invention
[0003] In order to solve the technical problems existing in the background technology, the present invention provides a cholesteric liquid crystal display panel and a driving method thereof.
[0004] A cholesteric liquid crystal display panel proposed by the present invention comprises: a TFT substrate, a CF substrate, M pixel units, M storage capacitors, M gate lines, a first common terminal, and a second common terminal. The M gate lines, the M pixel units, and the M storage capacitors are all packaged between the TFT substrate and the CF substrate arranged in parallel. The M pixel units and the M storage capacitors are arranged relatively in a one-to-one correspondence. One end of any pixel unit is connected to one end of a storage capacitor in a one-to-one correspondence. The other end of the storage capacitor is connected to one end of a gate line. The other end of the gate line is connected to a gate driver. One end of any pixel unit is connected to the first common terminal through the TFT substrate, and the other end is connected to the second common terminal through the storage capacitor and the CF substrate.
[0005] Preferably, it further comprises: M TFT transistors, one end of any pixel unit is connected to the source of a TFT transistor in a one-to-one correspondence, and the gate of any TFT transistor is connected to one end of a storage capacitor in a one-to-one correspondence.
[0006] Preferably, one end of any pixel unit is connected to one end of a storage capacitor in a one-to-one correspondence, and one end of the storage capacitor is connected to the second common end through the CF substrate.
[0007] Preferably, it further comprises: M source lines, the drain of any TFT transistor is connected to one end of a source line in a one-to-one correspondence, and the other end of the source line is connected to a source driver.
[0008] Preferably, the M gate lines and the M storage capacitors are arranged in rows with equal spacing, and the M source lines are arranged in columns with equal spacing.
[0009] A driving method proposed in the present invention is applied to drive any of the above-mentioned cholesteric liquid crystal display panels, comprising:
[0010] Power on the LCD module;
[0011] A variable first potential is applied to the TFT substrate through the first common terminal, a variable second potential is synchronously applied to the CF substrate through the second common terminal, and a gate drive signal is provided to the gate line through the gate driver until the pixel unit corresponding to the storage capacitor position enters the P state, wherein the absolute value of the difference between the first potential and the second potential is greater than zero; when all M pixel units enter the P state, a refresh scan is performed.
[0012] Preferably, the variable first potential and the variable second potential at the same time have the same absolute value and opposite polarity.
[0013] Preferably, before the display panel enters the P state, the variable first potential and the gate driving signal timing are the same at the same time.
[0014] Preferably, before the display panel enters the P state, the timing cycle of the variable first potential and the variable second potential includes at least one complete timing cycle.
[0015] In the present invention, the proposed cholesteric liquid crystal display panel and its driving method are to power on the liquid crystal display module; apply a variable first potential to the TFT substrate through the first common terminal, apply a variable second potential to the CF substrate synchronously through the second common terminal, and provide a gate drive signal to the gate line through the gate driver until the pixel unit corresponding to the storage capacitor position enters the P state. The storage capacitor added on the basis of the original LCD architecture and the timing are used to achieve high cross-voltage, which gets rid of the conventional source drive voltage limitation. The cross-voltage range of the cholesteric liquid crystal display screen is expanded, and the compatibility of the cholesteric liquid crystal display screen is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A schematic diagram of a prior art cholesteric LCD pixel architecture;
[0017] Figure 2 for Figure 1 The driving timing diagram;
[0018] Figure 3A schematic diagram of a cholesteric LCD pixel architecture of a cholesteric liquid crystal display module proposed by the present invention;
[0019] Figure 4 A common end driving schematic diagram of a driving method proposed by the present invention;
[0020] Figure 5 A driving timing diagram of a driving method proposed by the present invention.
[0021] Legend: 1. Common line; 2. Gate line; 3. TFT transistor; 4. Source line; 5. Pixel unit; 6. Storage capacitor. DETAILED DESCRIPTION
[0022] Reference Figure 3-5 A cholesteric liquid crystal display panel proposed by the present invention comprises: a TFT substrate, a CF substrate, M pixel units, M storage capacitors, M gate lines, a first common terminal, and a second common terminal. The M gate lines, the M pixel units, and the M storage capacitors are all packaged between the TFT substrate and the CF substrate arranged in parallel. The M pixel units and the M storage capacitors are arranged one-to-one in a relatively corresponding manner. One end of any pixel unit is connected to one end of a storage capacitor in a one-to-one corresponding manner. The other end of the storage capacitor is connected to one end of a gate line. The other end of the gate line is connected to a gate driver. One end of any pixel unit is connected to the first common terminal through the TFT substrate, and the other end is connected to the second common terminal through the storage capacitor and the CF substrate.
[0023] Specifically, it also includes: M TFT transistors, one end of any pixel unit is connected to the source of a TFT transistor in a one-to-one correspondence, and the gate of any TFT transistor is connected to one end of a storage capacitor in a one-to-one correspondence.
[0024] Specifically, one end of any pixel unit is connected to one end of a storage capacitor in a one-to-one correspondence, and one end of the storage capacitor is connected to the second common end through the CF substrate.
[0025] Specifically, it also includes: M source lines, the drain of any TFT transistor is connected to one end of a source line in a one-to-one correspondence, and the other end of the source line is connected to a source driver.
[0026] In this embodiment, the M gate lines and the M storage capacitors are arranged in rows with equal spacing, and the M source lines are arranged in columns with equal spacing.
[0027] Reference Figure 3-5 The present invention provides a driving method for driving a cholesteric liquid crystal display panel as described above, comprising:
[0028] Power on the LCD module;
[0029] A variable first potential is applied to the TFT substrate through the first common terminal, a variable second potential is synchronously applied to the CF substrate through the second common terminal, and a gate drive signal is provided to the gate line through the gate driver until the pixel unit corresponding to the storage capacitor position enters the P state, wherein the absolute value of the difference between the first potential and the second potential is greater than zero; when all M pixel units enter the P state, a refresh scan is performed.
[0030] In this embodiment, the variable first potential and the variable second potential at the same time have the same absolute value and opposite polarity.
[0031] In this embodiment, before the display panel enters the P state, the variable first potential and the gate driving signal timing are the same at the same time.
[0032] In this embodiment, if Figure 5 As shown, Acvcom1 is a variable first potential, Acvcom2 is a variable second potential, Gate is a gate drive signal, and before the display panel enters the P state, the gate drive signal and the variable second potential Acvcom2 have the same voltage at the same time.
[0033] like Figure 2 As shown, the common solution is to realize the voltage difference electric field between LC through the avcom on the Cf substrate side and the source line of the TFT substrate. Because the voltage of the source line is output by the IC, the existing IC process for this application is only 32V. If you want to make more than 50V, you need to invest a lot of cost and time to do process design verification. Figure 5 As shown, since the voltage can be output without going through the IC, there is no limitation of the 32V process, and an external DCDC chip (±30V) can be used to achieve a 60V cross-voltage.
[0034] In this embodiment, before the display panel enters the P state, the timing cycle of the variable first potential and the variable second potential at least includes one complete timing cycle.
[0035] In this embodiment, the storage capacitor is connected through the gate line, and before the display panel enters the P state, the gate drive signal is the same as the variable second potential timing voltage. After entering the P state, the gate drive signal resumes the normal shift timing for progressive scanning, and this timing can achieve dual-channel Acvcom high cross-voltage and retain the progressive scanning function.
[0036] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.
Claims
1. A cholesteric liquid crystal display panel, characterized in that: include: A TFT substrate, a CF substrate, M pixel units, M storage capacitors, M gate lines, a first common terminal, and a second common terminal. The M gate lines, the M pixel units, and the M storage capacitors are all encapsulated between the TFT substrate and the CF substrate that are arranged in parallel. The M pixel units and the M storage capacitors are arranged relatively in a one-to-one correspondence. One end of any pixel unit is connected to one end of a storage capacitor in a one-to-one correspondence. The other end of the storage capacitor is connected to one end of a gate line. The other end of the gate line is connected to a gate driver. One end of any pixel unit is connected to the first common terminal through the TFT substrate, and the other end is connected to the second common terminal through the storage capacitor and the CF substrate.
2. The cholesteric liquid crystal display panel according to claim 1, characterized in that: It also includes: M TFT transistors, one end of any pixel unit is connected to the source of a TFT transistor in a one-to-one correspondence, and the gate of any TFT transistor is connected to one end of a storage capacitor in a one-to-one correspondence.
3. The cholesteric liquid crystal display panel according to claim 2, characterized in that: One end of any pixel unit is connected to one end of a storage capacitor in a one-to-one correspondence, and one end of the storage capacitor is connected to the second common end through the CF substrate.
4. The cholesteric liquid crystal display panel according to claim 3, characterized in that: Also includes: There are M source lines, and the drain of any TFT transistor is connected to one end of a source line in a one-to-one correspondence, and the other end of the source line is connected to a source driver.
5. The cholesteric liquid crystal display panel according to claim 4, characterized in that: The M gate lines and the M storage capacitors are arranged in rows with equal spacing, and the M source lines are arranged in columns with equal spacing.
6. A driving method, characterized in that: The method is applied to drive a cholesteric liquid crystal display panel according to any one of claims 1 to 5, comprising: Power on the LCD module; A variable first potential is applied to the TFT substrate through the first common terminal, a variable second potential is synchronously applied to the CF substrate through the second common terminal, and a gate drive signal is provided to the gate line through the gate driver until the pixel unit corresponding to the storage capacitor position enters the P state, wherein the absolute value of the difference between the first potential and the second potential is greater than zero; when all M pixel units enter the P state, a refresh scan is performed.
7. The driving method according to claim 6, characterized in that: At the same time, the variable first potential and the variable second potential have the same absolute value and opposite polarity.
8. The driving method according to claim 6, characterized in that: Before the display panel enters the P state, the variable first potential and the gate driving signal timing are the same at the same time.
9. The driving method according to claim 6, characterized in that: Before the display panel enters the P state, the timing cycle of the variable first potential and the variable second potential at least includes one complete timing cycle.