Heterogeneous control system composed of MCU and FPGA and application program updating method

Abstract

The invention provides a heterogeneous control system composed of an MCU (Microprogrammed Control Unit) and an FPGA (Field Programmable Gate Array) and an application program updating method, which can be applied to the technical field of rail transit vehicle-mounted equipment. The vehicle-mounted controller provided by the invention comprises a micro-control unit which is connected with a CAN bus, and the CAN bus is connected with an upper computer through an interface conversion card; the field programmable gate array is connected with the micro-control unit; and the FLASH memory is connected with the field programmable gate array. According to the heterogeneous control system composed of the MCU and the FPGA and the application program updating method, the FPGA program and the MCU program can be remotely upgraded through the CAN bus under the condition that a controller shell is not opened, the program upgrading efficiency is greatly improved, the upgrading cost is reduced, and the upgrading time is shortened; and multiple same board card programs can be upgraded at the same time, so that the upgrading time is shortened.

Description

Technical Field

[0001] The present application relates to the technical field of rail transit on-board equipment, and in particular to a heterogeneous control system composed of an MCU and an FPGA and an application program update method. Background Art

[0002] In rail transit, the onboard controller plays a vital role in controlling the vehicle's traction, braking, energy configuration, etc. The operation of the onboard controller is mainly realized by executing programs through FPGA (Field Programmable Gate Array) and MCU (Microcontroller Unit). Therefore, the FPGA and MCU programs need to be updated frequently. Therefore, it is necessary to improve the speed and efficiency of updating FPGA and MCU.

[0003] The FPGA configuration mode in the existing vehicle controller is generally the master mode, where the FPGA is the master and is connected to a PROM (programmable read-only memory) or FLASH (flash memory) storage chip. After the controller is powered on, the FPGA actively reads the program from the PROM or FLASH and then runs the program. The MCU program in the existing vehicle controller is in the MCU's own FLASH memory. After the controller is powered on, the MCU actively runs the application program in its own FLASH memory.

[0004] The program update and upgrade of FPGA and MCU needs to be performed through the JTAG (Joint Test Action Group) interface using a dedicated emulator. The disadvantages are: 1. A dedicated emulator must be used; 2. The JTAG interface on the controller must be connected. The existing subway and EMU traction converter controllers are installed under the car body and in a closed chassis, which makes it very inconvenient to upgrade the FPGA and MCU programs or impossible to upgrade on site due to structural and space limitations. The controller can only be removed and upgraded in a special environment, and the controller must be installed back after the program is upgraded, which is very troublesome. 3. The program can only be updated one board at a time, and the program cannot be updated at the same time for the same board. Summary of the invention

[0005] In response to the problems in the prior art, the embodiments of the present application provide a heterogeneous control system composed of an MCU and an FPGA and an application program update method, which can at least partially solve the problems in the prior art.

[0006] On the one hand, an embodiment of the present application provides a vehicle controller composed of an MCU and an FPGA, including:

[0007] A micro control unit is connected to the CAN bus, wherein the CAN bus is connected to the host computer via an interface conversion card;

[0008] A field programmable gate array connected to the micro control unit;

[0009] The FLASH memory is connected to the field programmable gate array.

[0010] In some embodiments, the host computer establishes a communication connection with the micro control unit via the CAN bus using the UDS protocol.

[0011] In some embodiments, the micro control unit is connected to the SSPI interface of the field programmable gate array through the SPI interface, and is connected to the mode pin and the reload configuration pin of the field programmable gate array through the IO interface.

[0012] In some embodiments, the FLASH memory of the micro control unit includes a boot loader area, a micro control unit application area, a micro control unit application backup area, and a field programmable gate array program backup area.

[0013] On the other hand, an embodiment of the present application provides a heterogeneous control system composed of an MCU and an FPGA, including the vehicle-mounted controller described in any of the above embodiments, and further including:

[0014] CAN bus is connected to the host computer through an interface conversion card.

[0015] On the other hand, an embodiment of the present application provides an application updating method, which is applied to the vehicle controller described in any of the above embodiments or the heterogeneous control system composed of the MCU and FPGA described in any of the above embodiments, and the method includes:

[0016] Get the update program sent by the host computer through the CAN bus;

[0017] If the update program is a micro control unit program, the update program is stored in a FLASH memory of the micro control unit, and a boot loader in the FLASH memory is run, and the update program is run by the boot loader;

[0018] If the update program is a field programmable gate array program, the field programmable gate array is controlled to burn the update program into a FLASH memory connected to the field programmable gate array.

[0019] In some embodiments, obtaining the update program sent by the host computer via the CAN bus includes:

[0020] Entering a program download mode according to a program download request sent by the host computer, wherein the program download request includes the type of the update program;

[0021] Obtain the size of the update program sent by the host computer, determine whether the size of the update program exceeds the size of the corresponding storage area of ​​the FLASH memory of the microcontroller unit, and if not, reply a positive response to the host computer;

[0022] According to the program erase request sent by the host computer, the micro control unit program backup area or the field programmable gate array backup area inside the micro control unit is erased, and after the erasure is successful, a positive response of the erasure success is returned to the host computer;

[0023] The host computer obtains data packets sent by the update program in a multi-frame transmission mode after segmenting and packaging the update program until the update program is completely downloaded.

[0024] In some embodiments, if the update program is a micro control unit program, the update program is stored in a FLASH memory of the micro control unit, and a boot loader in the FLASH memory is run, and the boot loader runs the update program, including:

[0025] If the update program is a microcontroller program, then according to the program update diagnostic instruction sent by the host computer, it jumps to the starting address of the internal FLASH memory and starts running the boot loader. The boot loader copies the update program in the microcontroller application backup area to the microcontroller application area and runs the update program.

[0026] In some embodiments, if the update program is a field programmable gate array program, controlling the field programmable gate array to burn the update program into a FLASH memory connected to the field programmable gate array includes:

[0027] If the update program is a field programmable gate array program, then modifying the mode pin level of the field programmable gate array through the IO interface of the micro control unit so that the mode pin level is consistent with the configuration level of the field programmable gate array SSPI working mode;

[0028] Outputting a low level pulse to the reload configuration pin of the field programmable gate array through the IO interface, so that the field programmable gate array enters the SSPI working mode;

[0029] Control the FLASH memory connected to the field programmable gate array through the SSPI interface of the field programmable gate array and erase the data in the FLASH memory;

[0030] Write the field programmable gate array program into the FLASH memory via the SSPI interface;

[0031] Read back the FPGA program in the external FLASH memory through the SSPI interface and compare it with the FPGA program in the microcontroller unit;

[0032] If they are consistent, the microcontroller unit modifies the mode pin level of the field programmable gate array through the IO interface so that the mode pin level is consistent with the configuration level of the program loaded from the external Flash memory;

[0033] A low level pulse is output to the reload configuration pin through the IO interface of the micro control unit, so that the field programmable gate array loads the update program from the FLASH memory and runs it.

[0034] In some embodiments, when it is necessary to update the program for at least two vehicle controllers at the same time, the upper computer sends a data packet via the CAN bus each time, and then waits for a response from each of the vehicle controllers. If the upper computer receives an affirmative response from one of the vehicle controllers within the specified time, it continues to send the next data packet via the CAN bus.

[0035] The heterogeneous control system composed of MCU and FPGA and the application updating method provided in the present application, when it is necessary to download the FPGA program or the MCU program, the host computer establishes a communication connection with the MCU through the CAN bus using the UDS protocol (Road vehicle-unified diagnostic services). After the communication is established, the host computer informs the MCU that the program needs to be updated, and informs whether to update the FPGA program or the MCU program. After that, the MCU enters the program download mode, the host computer divides the program into packets, and calculates the CRC check value of each packet of data. The host computer downloads each packet of data and the check value to the MCU through the CAN bus and the UDS protocol. After the MCU verifies that it is correct, the MCU saves the reported data to its own FLASH storage (backup area). If the MCU receives the FPGA program, then after the program is received, the MCU downloads the FPGA program to the FLASH memory outside the FPGA through the SSPI configuration interface of the FPGA; if the MCU receives the MCU program, the MCU will jump to the Bootloader program, and the Bootloader will copy the MCU program to the application storage area and run it. In this way, the FPGA program and MCU program can be remotely upgraded through the CAN bus without opening the controller casing, which greatly improves the program upgrade efficiency, reduces the upgrade cost, and shortens the upgrade time; and multiple identical board programs can be upgraded at the same time, shortening the upgrade time; in addition, since the MCU storage is used for temporary program storage, the risk of the controller not being able to operate normally due to program download failure is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0037] Figure 1 It is a structural diagram of a vehicle controller composed of an MCU and an FPGA provided in an embodiment of the present application.

[0038] Figure 2 It is a structural schematic diagram of a heterogeneous control system composed of an MCU and an FPGA provided in an embodiment of the present application.

[0039] Figure 3 This is a schematic diagram of the internal storage area division of a micro control unit provided in an embodiment of the present application.

[0040] Figure 4 It is a flowchart of an application updating method provided in one embodiment of the present application.

[0041] Figure 5 It is a partial flow chart of an application updating method provided in one embodiment of the present application.

[0042] Figure 6 It is a partial flow chart of an application updating method provided in one embodiment of the present application.

[0043] Figure 7 It is a flowchart of an application updating method provided in one embodiment of the present application.

[0044] Figure 8 It is a flowchart of an application updating method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Here, the illustrative embodiments of the present application and their descriptions are used to explain the present application, but are not intended to limit the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be arbitrarily arranged with each other.

[0046] The terms “first”, “second”, etc. used in this document do not specifically refer to an order or sequence, nor are they used to limit this application. They are only used to distinguish elements or operations described with the same technical terms.

[0047] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0048] As used herein, "and / or" includes any and all permutations of the items described.

[0049] Figure 1 FIG. 1 is a schematic diagram of a vehicle controller composed of an MCU and an FPGA provided in an embodiment of the present application. Figure 1 As shown, the vehicle-mounted controller provided in the embodiment of the present application includes:

[0050] The microcontroller unit is connected to the CAN bus, wherein the CAN bus is connected to the host computer via an interface conversion card (see Figure 2 );

[0051] A field programmable gate array connected to the micro control unit;

[0052] The FLASH memory is connected to the field programmable gate array.

[0053] The vehicle controller composed of MCU and FPGA provided in the embodiment of the present application, when it is necessary to download the FPGA program or the MCU program, the host computer establishes a communication connection with the MCU through the CAN bus using the UDS protocol (Road Vehicle-Unified Diagnostic Services). After the communication is established, the host computer informs the MCU that the program needs to be updated, and informs whether to update the FPGA program or the MCU program. After that, the MCU enters the program download mode, the host computer divides the program into packets, and calculates the CRC check value of each packet of data. The host computer downloads each packet of data and the check value to the MCU through the CAN bus and the UDS protocol. After the MCU verifies that there is no error, the MCU saves the reported data to its own FLASH storage (backup area). If the MCU receives the FPGA program, then after the program is received, the MCU downloads the FPGA program to the FLASH memory outside the FPGA through the SSPI configuration interface of the FPGA; if the MCU receives the MCU program, the MCU will jump to the Bootloader program, and the Bootloader will copy the MCU program to the application storage area and run it. In this way, the FPGA program and MCU program can be remotely upgraded through the CAN bus without opening the controller casing, which greatly improves the program upgrade efficiency, reduces the upgrade cost, and shortens the upgrade time; and multiple identical board programs can be upgraded at the same time, shortening the upgrade time; in addition, since the MCU storage is used for temporary program storage, the risk of the controller not being able to operate normally due to program download failure is avoided.

[0054] like Figure 1 As shown, in some embodiments, the host computer establishes a communication connection with the micro control unit via the CAN bus using the UDS protocol.

[0055] like Figure 1 As shown, in some embodiments, the micro control unit is connected to the SSPI interface of the field programmable gate array through the SPI interface, and is connected to the mode pin and the reload configuration pin of the field programmable gate array through the IO interface.

[0056] like Figure 3 As shown, in some embodiments, the FLASH memory of the micro control unit includes a boot loader area, a micro control unit application area, a micro control unit application backup area, and a field programmable gate array program backup area.

[0057] Based on the same inventive concept, the embodiment of the present application also provides a heterogeneous control system composed of an MCU and an FPGA, such as Figure 2 As shown, the heterogeneous control system composed of MCU and FPGA provided in the embodiment of the present application includes the vehicle-mounted controller described in any of the above embodiments, and also includes:

[0058] CAN bus is connected to the host computer through an interface conversion card.

[0059] Based on the same inventive concept, the embodiment of the present application also provides an application updating method, which is applied to the vehicle controller described in any of the above embodiments or the heterogeneous control system composed of the MCU and FPGA described in any of the above embodiments, such as Figure 4 As shown, the method includes:

[0060] S100, obtaining the update program sent by the host computer via the CAN bus;

[0061] S200, if the update program is a micro control unit program, the update program is stored in the FLASH memory of the micro control unit, and the boot loader in the FLASH memory is run, and the boot loader runs the update program;

[0062] S300: If the update program is a field programmable gate array program, control the field programmable gate array to burn the update program into a FLASH memory connected to the field programmable gate array.

[0063] The application update method provided in the embodiment of the present application can remotely upgrade the FPGA program and the MCU program through the CAN bus without opening the controller housing, thereby greatly improving the program upgrade efficiency, reducing the upgrade cost, and shortening the upgrade time; and can simultaneously upgrade multiple identical board programs to shorten the upgrade time; in addition, since the MCU storage is used for temporary storage of the program, the risk of the controller failing to operate normally due to program download failure is avoided.

[0064] like Figure 5 As shown, in some embodiments, obtaining the update program sent by the host computer through the CAN bus includes:

[0065] S101, entering a program download mode according to a program download request sent by a host computer, wherein the program download request includes a type of an update program;

[0066] S102, obtaining the size of the update program sent by the host computer, determining whether the size of the update program exceeds the size of the corresponding storage area of ​​the FLASH memory of the microcontroller unit, and if not, replying an affirmative response to the host computer;

[0067] S103, according to the program erase request sent by the host computer, the micro control unit program backup area or the field programmable gate array backup area inside the micro control unit is erased, and after the erasure is successful, a positive response of the erasure success is returned to the host computer;

[0068] S104, obtaining data packets sent by the host computer in a multi-frame transmission mode after segmenting and packaging the update program, until the update program is completely downloaded.

[0069] In some embodiments, if the update program is a microcontroller program, the update program is saved in the FLASH memory of the microcontroller, and the boot loader in the FLASH memory is run, and the update program is run by the boot loader, including: if the update program is a microcontroller program, then according to the program update diagnostic instruction sent by the host computer, jump to the starting address of the internal FLASH memory, start running the boot loader, and the boot loader copies the update program in the microcontroller application backup area to the microcontroller application area and runs the update program.

[0070] like Figure 6 As shown, in some embodiments, if the update program is a field programmable gate array program, controlling the field programmable gate array to burn the update program into a FLASH memory connected to the field programmable gate array includes:

[0071] S301, if the update program is a field programmable gate array program, modifying the mode pin level of the field programmable gate array through the IO interface of the micro control unit so that the mode pin level is consistent with the configuration level of the field programmable gate array SSPI working mode;

[0072] S302, outputting a low level pulse to the reload configuration pin of the field programmable gate array through the IO interface, so that the field programmable gate array enters the SSPI working mode;

[0073] S303, controlling the FLASH memory connected to the field programmable gate array through the SSPI interface of the field programmable gate array and erasing the data in the FLASH memory;

[0074] S304, writing the field programmable gate array program into the FLASH memory through the SSPI interface;

[0075] S305, reading back the FPGA program in the external FLASH storage through the SSPI interface and comparing it with the FPGA program in the microcontroller unit;

[0076] S306, if they are consistent, the micro control unit modifies the mode pin level of the field programmable gate array through the IO interface so that the mode pin level is consistent with the configuration level of the program loaded from the external Flash memory;

[0077] S307, outputting a low level pulse to the reload configuration pin through the IO interface of the micro control unit, so that the field programmable gate array loads the update program from the FLASH memory and runs it.

[0078] In some embodiments, when it is necessary to update the program for at least two vehicle controllers at the same time, the upper computer sends a data packet via the CAN bus each time, and then waits for a response from each of the vehicle controllers. If the upper computer receives an affirmative response from one of the vehicle controllers within the specified time, it continues to send the next data packet via the CAN bus.

[0079] Specifically, when there are multiple identical boards in the controller that need to update the program, the board identifies the ID value of its own slot and uses different CAN ID values ​​to communicate with the host computer. When the host computer downloads the FPGA program or MCU program, it does not send a data packet to each board separately, but sends a data packet once and waits for the response of each board. To ensure that the program is downloaded within the specified time, the host computer will continue to send the next packet of data as long as it receives a positive response from a board before the specified time arrives.

[0080] In order to better understand the present application, the application updating method provided by the present application is described in detail below through a specific embodiment.

[0081] MCU is the core of the whole system. FPGA and MCU program reception, storage and FPGA program download are all implemented by the MCU application. A part of the MCU internal FLASH area is used to save the FPGA program and MCU program sent by the host computer. When the MCU downloads the FPGA program, it first modifies the FPGA's working mode, and then controls the FPGA's reload configuration pin to make the FPGA work in SSPI mode. After that, the MCU controls the FPGA's SSPI interface to realize the burning of the FPGA's external FLASH. After the burning is completed, the MCU modifies the FPGA's working mode to read the program mode from the external FLASH, and then controls the reload configuration pin to make the FPGA reload the program from the external FLASH and run it.

[0082] Figure 1 A connection relationship diagram of the MCU and FPGA inside the controller board in a heterogeneous control system composed of an MCU and an FPGA provided in an embodiment of the present application. In the embodiment of the present application, the MCU is connected to the SSPI interface of the FPGA via the SPI bus interface, the MCU is connected to the mode interface (MODE IO) and the reload configuration interface (RECONF IO) of the FPGA via the IO interface, and the FPGA is connected to the external SPI FLASH storage chip via the program loading pin.

[0083] Figure 2 This is a schematic diagram of the structure of the heterogeneous control system composed of MCU and FPGA provided in this application. In the heterogeneous control system composed of MCU and FPGA, each controller board is connected through the CAN bus, and the host computer can communicate with the entire CAN bus through the interface card. The main control chip inside the board is MCU and FPGA.

[0084] Figure 3 Schematic diagram of the division of MCU internal FLASH storage area provided for the embodiment of the present application. In the embodiment of the present application, the storage area of ​​the MCU is divided into Bootloader (a program that starts loading the application), MCU application area, MCU application backup area, and FPGA program backup area, wherein the MCU application area, MCU application backup area, and FPGA program backup area contain information of the corresponding program.

[0085] Figure 7 The FPGA and MCU program upgrade process provided by the embodiment of the present application. During the entire program download process, the UDS protocol is used between the host computer and the MCU for service request and data transmission.

[0086] The host computer is connected to the CAN bus inside the controller through the interface card. The host computer uses the UDS protocol to establish a communication connection with the board that needs to upgrade the program. Then the host computer sends a download program request to the board to inform the MCU whether to update the MCU program or the FPGA program next, and puts the board MCU application into program download mode. After that, the host computer calculates the size of the downloaded program (both the MCU and FPGA programs are binary files.bin) and sends the value to the board. The board MCU program determines whether the size of the downloaded program exceeds the size of its own FLASH storage area. If it does not exceed the range, it will reply to the host computer with a positive response. After that, the host computer sends an erase program request to the board. The MCU erases the internal MCU program backup area or FPGA backup area. After the MCU is successfully erased, it will reply to the host computer with a positive response of "erase successful". After that, the host computer starts to pack the data in segments and send each packet of data in a multi-frame transmission mode. After each packet of data is sent, the check code of this packet of data will be sent immediately. After receiving this packet of data, the lower computer calculates the check code and compares it with the check code sent by the upper computer. If they are consistent, the packet of data will be burned into the backup area and a positive response will be sent to the upper computer. After receiving the positive response, the upper computer will continue to send the next packet of data. This process continues until the upper computer has downloaded the program. After that, the upper computer will send the relevant information of the program, such as version, size, compilation date, check code, etc. to the MCU, and the MCU will save this information in the information area of ​​the program in the program backup area.After the program is downloaded, the host computer sends a "program update" diagnostic command to the MCU. If the MCU program was downloaded before, the MCU program will jump to the starting address of the internal FLASH and start running the Bootloader. The Bootloader will copy the program in the backup area to the program running area and run the latest program. After the latest program is running, the host computer obtains the relevant information of the program through the UDS protocol to confirm that the program has been updated. If the FPGA program was downloaded before, the MCU program will burn the program to the FPGA by controlling the SSPI interface of the FPGA. In FLASH, the specific steps are that MCU modifies the MODE pin level of FPGA through the IO interface. The pin level is consistent with the configuration level of FPGA "SSPI mode". A low-level pulse is output to the "reload configuration pin" through the IO interface to make FPGA enter SSPI working mode. After that, MCU controls the external FLASH of FPGA through the SSPI interface of FPGA and erases the external FLASH content. Then, the FPGA program is written to the external FLASH through the SSPI interface. Both erasing and programming are operated according to the page byte size of FLASH. Then, the external FLASH content is read back through the SSPI interface and compared with the FPGA program in the MCU. If they are consistent, the MCU modifies the MODE pin level of FPGA through the IO interface. The pin level is consistent with the configuration level of "loading program from external Flash". A low-level pulse is output to the "reload configuration pin" through the IO interface to make FPGA load the program from FLASH and run it. Then, MCU sends a "program update" affirmative response to the host computer, indicating that the program update is complete. After receiving the affirmative response, the host computer will print a prompt of successful configuration. At this point, the FPGA program is burned.

[0087] like Figure 8As shown in the figure, when it is necessary to update the program for multiple identical boards at the same time, the operation of the host computer is similar to upgrading a single board. Each time the host computer sends a command, it only needs to send it once, and then wait for the response of each board. After receiving the diagnostic command, each board will respond separately. Each board application recognizes the ID value of its own board (the ID value is determined by the board hardware, and the ID value of boards in different positions is different), and will use different CAN ID values ​​to communicate with the host computer, thereby avoiding CANID conflicts. When the host computer transmits the program, it also sends a packet of data at a time, and waits for the response of each board after sending a packet of data. After the host computer sends a packet of data, if some boards do not reply to the host computer or send a negative reply to the host computer within the specified time, the host computer will record the ID of the board that did not reply or sent a negative reply and display the failure of the board program download on the interface. At the same time, in order to download the program normally, the host computer will continue to send the next packet of data; if the host computer does not receive a reply from any board or the received replies are all negative within the specified time, the host computer will repeat the packet of data; if the host computer does not receive a reply from any board or the received replies are all negative for more than three times, the host computer believes that there is a problem with the communication with the board, and the host computer will no longer send the program and raise the sending failure. One-to-many data transmission is realized between the host computer and each board, which improves the transmission efficiency.

[0088] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0089] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A vehicle controller composed of MCU and FPGA, characterized in that: include: A micro control unit is connected to the CAN bus, wherein the CAN bus is connected to the host computer via an interface conversion card; A field programmable gate array connected to the micro control unit; The FLASH memory is connected to the field programmable gate array.

2. The vehicle-mounted controller according to claim 1, characterized in that: The host computer establishes a communication connection with the micro control unit via the CAN bus using the UDS protocol.

3. The vehicle-mounted controller according to claim 1, characterized in that: The micro control unit is connected to the SSPI interface of the field programmable gate array through the SPI interface, and is connected to the mode pin and the reload configuration pin of the field programmable gate array through the IO interface.

4. The vehicle-mounted controller according to claim 1, characterized in that: The FLASH memory of the micro control unit includes a boot loader area, a micro control unit application area, a micro control unit application backup area, and a field programmable gate array program backup area.

5. A heterogeneous control system composed of MCU and FPGA, characterized in that: The vehicle controller comprises at least one of claims 1 to 4, and further comprises: CAN bus is connected to the host computer through an interface conversion card.

6. A method for updating an application, characterized in that: Applied to the vehicle controller according to any one of claims 1 to 4 or the heterogeneous control system composed of the MCU and FPGA according to claim 5, the method comprises: Get the update program sent by the host computer through the CAN bus; If the update program is a micro control unit program, the update program is stored in a FLASH memory of the micro control unit, and a boot loader in the FLASH memory is run, and the update program is run by the boot loader; If the update program is a field programmable gate array program, the field programmable gate array is controlled to burn the update program into a FLASH memory connected to the field programmable gate array.

7. The method according to claim 6, characterized in that Get the update program sent by the host computer through the CAN bus, including: Entering a program download mode according to a program download request sent by the host computer, wherein the program download request includes the type of the update program; Obtain the size of the update program sent by the host computer, determine whether the size of the update program exceeds the size of the corresponding storage area of ​​the FLASH memory of the microcontroller unit, and if not, reply a positive response to the host computer; According to the program erase request sent by the host computer, the micro control unit program backup area or the field programmable gate array backup area inside the micro control unit is erased, and after the erasure is successful, a positive response of the erasure success is returned to the host computer; The host computer obtains data packets sent by the update program in a multi-frame transmission mode after segmenting and packaging the update program until the update program is completely downloaded.

8. The method according to claim 6, characterized in that If the update program is a micro control unit program, the update program is stored in a FLASH memory of the micro control unit, and a boot loader in the FLASH memory is run, and the boot loader runs the update program, including: If the update program is a microcontroller program, then according to the program update diagnostic instruction sent by the host computer, it jumps to the starting address of the internal FLASH memory and starts running the boot loader. The boot loader copies the update program in the microcontroller application backup area to the microcontroller application area and runs the update program.

9. The method according to claim 6, characterized in that If the update program is a field programmable gate array program, controlling the field programmable gate array to burn the update program into a FLASH memory connected to the field programmable gate array includes: If the update program is a field programmable gate array program, then modifying the mode pin level of the field programmable gate array through the IO interface of the micro control unit so that the mode pin level is consistent with the configuration level of the field programmable gate array SSPI working mode; Outputting a low level pulse to the reload configuration pin of the field programmable gate array through the IO interface, so that the field programmable gate array enters the SSPI working mode; Control the FLASH memory connected to the field programmable gate array through the SSPI interface of the field programmable gate array and erase the data in the FLASH memory; Write a field programmable gate array program into the FLASH memory via an SSPI interface; Read back the FPGA program in the external FLASH memory through the SSPI interface and compare it with the FPGA program in the microcontroller unit; If they are consistent, the microcontroller unit modifies the mode pin level of the field programmable gate array through the IO interface so that the mode pin level is consistent with the configuration level of the program loaded from the external Flash memory; A low level pulse is output to the reload configuration pin through the IO interface of the micro control unit, so that the field programmable gate array loads the update program from the FLASH memory and runs it.

10. The method according to claim 7, characterized in that When it is necessary to update the program for at least two vehicle controllers at the same time, the host computer sends a data packet via the CAN bus each time, and then waits for the response of each of the vehicle controllers. If the host computer receives an affirmative response from one of the vehicle controllers within the specified time, it continues to send the next data packet via the CAN bus.

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