Modeling method, system and equipment for communication between CPU (Central Processing Unit) core particles and readable storage medium

Abstract

The invention relates to the technical field of computer structure simulation, in particular to a modeling method, system and device for communication between CPU core grains and a readable storage medium, an Ariel simulator is configured for each CPU core grain, and the Ariel simulator comprises a first SST Link communicating with a cache and a memory and a second SST Link communicating with other CPU core grains; each Ariel simulator carries out SST component instantiation based on an SST structure simulation toolkit; wherein each CPU core simulator is internally provided with a second SST Link port, a CPU communication event type and an event processing function, the second SST Link port is used for communicating with other CPU cores, and the event processing function packages a corresponding event and externally provides an API (Application Program Interface). According to the invention, x86 instruction set message passing type analog simulation of the multi-CPU core particle integrated system can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of computer structure simulation, and in particular to a CPU inter-chip communication modeling method, system, device and readable storage medium. Background Art

[0002] With the development of computers, the computing scale of software programs is getting larger and larger, but due to the limitations of chip manufacturing technology, the scale of a single chip has an upper limit. Therefore, more and more servers use multi-way CPU technology, that is, systems containing multiple CPUs. Compared with the computing speed of the CPU, the transmission efficiency between CPUs is relatively low. When the computing task involves a scenario with communication between CPUs, the system performance will be significantly reduced. At present, CPU simulators commonly used in the industry, such as Gem5 and sniper, can simulate the functions and performance of the CPU, but can only model and simulate a single CPU. It is impossible to simulate the communication behavior between multiple CPUs in a system with multiple CPUs, and cannot reflect the impact of communication between CPUs on the performance of the entire system. In the SST framework, although the x86 CPU simulator Ariel is also integrated, and the SST framework itself also supports communication between multiple components, the communication between Ariel and other components only realizes the simulation of communication with the memory component, and cannot simulate the communication behavior between CPUs. For this reason, there is an urgent need for a CPU simulator that can simulate the communication behavior between multiple CPUs in a multi-CPU system to improve the overall performance of the system. Summary of the invention

[0003] To this end, the present invention provides a CPU inter-chip communication modeling method, system, device and readable storage medium, based on an improved Ariel simulator and using an SST framework to implement x86 instruction set message passing simulation of a multi-CPU chip integration system.

[0004] According to the design scheme provided by the present invention, on the one hand, a CPU inter-chip communication modeling method is provided, comprising: An Ariel simulator is configured for each CPU core so that each CPU core is implemented in an independent Ariel simulator, wherein the Ariel simulator includes: a first SST Link for communicating with a cache and a memory and a second SST Link for communicating with other CPU cores; Each Ariel simulator instantiates SST components based on the SST structural simulation toolkit to perform interconnect simulation of multi-CPU chiplet communication behaviors by instantiating SST components; Among them, each CPU chip simulator is equipped with a second SST Link port for communicating with other CPU chips, a CPU communication event type and an event processing function. The event processing function encapsulates the corresponding event and provides an API interface to the outside to simulate the corresponding event function through API interface calls.

[0005] As a CPU inter-chip communication modeling method of the present invention, further, each Ariel simulator instantiates the SST component based on the SST structure simulation toolkit, including: Register an inter-CPU communication event processing function for the second SST Link and set a virtual communication address, wherein the inter-CPU communication event type is set in the event processing function, and the virtual communication address is used to provide an API function interface externally.

[0006] As a CPU chiplet communication modeling method of the present invention, further, interconnection simulation of multiple CPU chiplet communication behaviors is performed by instantiating SST components, including: In response to the data requirements of multi-CPU communication, the data is encapsulated as an inter-CPU communication event function, and the virtual communication address of the opposite CPU is obtained by parsing the data, so as to use the second SST Link to send the inter-CPU communication event to the opposite CPU.

[0007] In another aspect, the present invention further provides a CPU inter-chiplet communication modeling system, comprising: a chiplet simulation configuration module and a component instantiation module, wherein: A chiplet simulation configuration module, configured to configure an Ariel simulator for each CPU chiplet so that each CPU chiplet is implemented in an independent Ariel simulator, the Ariel simulator comprising: a first SST Link for communicating with a cache and a memory and a second SST Link for communicating with other CPU chips; The component instantiation module is used by each Ariel simulator to instantiate SST components based on the SST structural simulation toolkit, so as to interconnect and simulate the communication behavior of multiple CPU core particles by instantiating SST components; Among them, each CPU chip simulator is equipped with a second SST Link port for communicating with other CPU chips, a CPU communication event type and an event processing function. The event processing function encapsulates the corresponding event and provides an API interface to the outside to simulate the corresponding event function through API interface calls.

[0008] In another aspect, the present invention further provides an electronic device, comprising: at least one processor, and a memory coupled to the at least one processor; The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method as described above.

[0009] In yet another aspect, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed, the method described above can be implemented.

[0010] Beneficial effects of the present invention: The present invention increases the communication channel of the Ariel simulator backend and provides the user with an API interface for calling the backend communication function. Based on the Ariel and SST framework, the communication behavior between CPU chips in a multi-CPU chip integrated system can be simulated more realistically and accurately without affecting the original CPU calculation simulation function. This allows chip designers to simulate and model a system with multiple CPUs during the chip design phase to test and verify the performance of the multi-chip system, thereby accelerating the system design time and reducing the system verification cost. The present invention has good application prospects in the field of system chip front-end design and verification testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a schematic diagram of the CPU inter-chip communication modeling process in the embodiment; Figure 2 This is a schematic diagram of the external interface of the original Ariel simulator in the embodiment; Figure 3 This is a schematic diagram of the external interface of the improved Ariel simulator in the embodiment; Figure 4 The figure is a schematic diagram of the process of Ariel simulator processing user function calls in the embodiment. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solutions and advantages of the present invention clearer and more understandable, the present invention is further described in detail below in conjunction with the accompanying drawings and technical solutions.

[0013] In wafer-level system design, multiple CPU cores are designed for the system, so the communication consumption between CPU cores is an important indicator in wafer-level system design. In order to simulate and model the communication behavior between CPU cores, the embodiment of the present invention, see Figure 1 As shown, a CPU inter-chip communication modeling method is provided, including: S101, configuring an Ariel simulator for each CPU core, so that each CPU core is implemented in an independent Ariel simulator, wherein the Ariel simulator includes: a first SST Link for communicating with a cache and a memory and a second SST Link for communicating with other CPU cores; S102, each Ariel simulator instantiates an SST component based on an SST structural simulation toolkit, so as to perform interconnection simulation on communication behaviors of multiple CPU core particles by instantiating the SST component; Among them, each CPU chip simulator is equipped with a second SST Link port for communicating with other CPU chips, a CPU communication event type and an event processing function. The event processing function encapsulates the corresponding event and provides an API interface to the outside world to simulate the corresponding event function through API interface calls.

[0014] In the embodiment of this case, an Ariel simulator of multiple Ariel x86 CPUs is run based on the SST framework, and a function for calling communication functions between Ariel simulators is provided to the user to simulate the communication behavior between multiple CPU cores.

[0015] In the SST framework, each individual simulator is abstracted as an SST component. SST components are connected through SSTLinks, and SST components can send SST events to the peer SST components through SST Links. Figure 2 As shown, there is a dedicated SST link that communicates with the memory simulator to handle memory simulation events, thereby accurately simulating the kernel's calls to cache and memory.

[0016] In this embodiment, Figure 3 As shown in the figure, a new SSTLink port for processing communication with other CPUs, a new CPU communication event type, and a corresponding event processing function are added in the Ariel simulator. Each Link is assigned an address, and the event is sent to the specified CPU by setting the address of the event dest.

[0017] Specifically, each Ariel simulator instantiates SST components based on the SST structural simulation toolkit and can be designed to include: Register an inter-CPU communication event processing function for the second SST Link and set a virtual communication address, wherein the inter-CPU communication event type is set in the event processing function, and the virtual communication address is used to provide an API function interface externally.

[0018] Among them, the interconnection simulation of multi-CPU chip communication behavior is carried out by instantiating SST components, which may include: In response to the data requirements of multi-CPU communication, the data is encapsulated as an inter-CPU communication event function, and the virtual communication address of the opposite CPU is obtained by parsing the data, so as to use the second SST Link to send the inter-CPU communication event to the opposite CPU.

[0019] The Ariel simulator is developed based on Intel's pin tool. The pin tool's instrumentation function can detect which functions are called in the user program. Based on the principle of this tool, when the Ariel simulator provides a custom interface to the user, it only needs to provide a fake API function interface, and no operation needs to be performed inside the function.

[0020] like Figure 4 As shown in the figure, in the front-end code of the Ariel simulator, the pin tool is used to detect the function interface. When the function call is detected, it is replaced with a function that implements the function. In the actual function, the input data is encapsulated as a corresponding event, and then the event is thrown to the simulator backend, which simulates it.

[0021] Furthermore, based on the above method, an embodiment of the present invention also provides a CPU inter-chiplet communication modeling system, comprising: a chiplet simulation configuration module and a component instantiation module, wherein: A chiplet simulation configuration module, configured to configure an Ariel simulator for each CPU chiplet so that each CPU chiplet is implemented in an independent Ariel simulator, the Ariel simulator comprising: a first SST Link for communicating with a cache and a memory and a second SST Link for communicating with other CPU chips; The component instantiation module is used by each Ariel simulator to instantiate SST components based on the SST structural simulation toolkit, so as to interconnect and simulate the communication behavior of multiple CPU core particles by instantiating SST components; Among them, each CPU chip simulator is equipped with a second SST Link port for communicating with other CPU chips, a CPU communication event type and an event processing function. The event processing function encapsulates the corresponding event and provides an API interface to the outside to simulate the corresponding event function through API interface calls.

[0022] like Figure 3 As shown, a link is added for each core to communicate with other CPUs at the link that Ariel creates to communicate with the cache and memory. An event handling function is registered for the newly created link, a virtual communication address is set for the newly created link, and the newly created link is bound to each core. In the event handling function, a new inter-CPU communication event type is added. An inter-CPU communication event handling function is created, the event is unpacked in the function, and the operation to be simulated is performed. An inter-CPU communication event creation function is created, the user input received from the front end is encapsulated into the corresponding event, and the event is sent to the peer end through the newly added inter-CPU communication link.

[0023] To provide users with an API interface for calling backend communication functions, you can add API interface functions in the arielapi.c / .h files for external programs to use. In these two files, you only need to provide the function name, and the function inside is an empty function; then, recompile it in the api folder and generate a .so file for users to compile programs. Ariel's pin3 tool will identify the name of the empty function in the api file and replace it with the actual operation function in ariel. In the actual operation function, encapsulate the data to be transmitted as ArielCommand. Send ArielCommand to the ariel backend through tunnel->writeMessage. The tick function in the arielcore.cc file will imitate the CPU clock and periodically enter this function. In the tick function, the processNextEvent() function is called to process the events in the queue. In the processNextEvent() function, if the queue is empty, the event queue will be replenished through the refillQueue() function. In refillQueue, the ArielCommand sent in the previous step through tunnel->writeMessage will be read out through tunnel->readMessageNB. Through the CPU communication event type enumeration in ArielCommand, enter the corresponding case and enter the createCpuEvent function. ArielCpuEvent will be created in createCpuEvent. After the event is created, it will be placed in the queue through coreQ->push. Continue to return to the processNextEvent function, coreQ->front processes the event at the head of the queue. Enter the corresponding handle function through the event type to send the event through the new CPU Link.

[0024] For systems containing multiple CPUs, the embodiments of this case simulate and model the communication behavior between CPUs based on the improved Ariel simulator and SST framework to reflect the impact of communication consumption on the performance of multi-CPU systems. It can quickly and effectively evaluate the design during the chip design phase, speed up system design time, and reduce system verification costs.

[0025] Furthermore, an embodiment of the present invention further provides an electronic device, including: at least one processor, and a memory coupled to the at least one processor; The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method as described above.

[0026] Furthermore, an embodiment of the present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed, the method described above can be implemented.

[0027] Unless otherwise specifically stated, the relative steps, numerical expressions and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0028] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0029] The units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation is not considered to be beyond the scope of the present invention.

[0030] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits, and accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software function modules. The present invention is not limited to any specific form of combination of hardware and software.

[0031] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A CPU inter-chip communication modeling method, characterized in that: Include: An Ariel simulator is configured for each CPU core so that each CPU core is implemented in an independent Ariel simulator, wherein the Ariel simulator includes: a first SST Link for communicating with a cache and a memory and a second SST Link for communicating with other CPU cores; Each Ariel simulator instantiates SST components based on the SST structural simulation toolkit to perform interconnect simulation of multi-CPU chiplet communication behaviors by instantiating SST components; Among them, each CPU chip simulator is equipped with a second SST Link port for communicating with other CPU chips, a CPU communication event type and an event processing function. The event processing function encapsulates the corresponding event and provides an API interface to the outside to simulate the corresponding event function through API interface calls.

2. The CPU inter-chiplet communication modeling method according to claim 1, characterized in that: Each Ariel simulator instantiates SST components based on the SST Structural Simulation Toolkit, including: Register an inter-CPU communication event processing function for the second SST Link and set a virtual communication address, wherein the inter-CPU communication event type is set in the event processing function, and the virtual communication address is used to provide an API function interface externally.

3. The CPU inter-chiplet communication modeling method according to claim 1 or 2, characterized in that: By instantiating SST components, the communication behavior of multiple CPU chips is interconnected and simulated, including: In response to the data requirements of multi-CPU communication, the data is encapsulated as an inter-CPU communication event function, and the virtual communication address of the opposite CPU is obtained by parsing the data, so as to use the second SST Link to send the inter-CPU communication event to the opposite CPU.

4. A CPU inter-chip communication modeling system, characterized in that: Contains: core particle simulation configuration module and component instantiation module, among which, A chiplet simulation configuration module, configured to configure an Ariel simulator for each CPU chiplet so that each CPU chiplet is implemented in an independent Ariel simulator, wherein the Ariel simulator includes: a first SST Link for communicating with a cache and a memory and a second SST Link for communicating with other CPU chips; The component instantiation module is used by each Ariel simulator to instantiate SST components based on the SST structural simulation toolkit, so as to interconnect and simulate the communication behavior of multiple CPU core particles by instantiating SST components; Among them, each CPU chip simulator is equipped with a second SST Link port for communicating with other CPU chips, a CPU communication event type and an event processing function. The event processing function encapsulates the corresponding event and provides an API interface to the outside to simulate the corresponding event function through API interface calls.

5. An electronic device, characterized in that: include: at least one processor, and a memory coupled to the at least one processor; The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method according to any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the method according to any one of claims 1 to 3 can be implemented.

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