Chip design verification system and method

Abstract

The embodiments of the present application provide a chip design verification system and method, in which different computing nodes communicate data through RDMA technology, which speeds up data interaction between different computing nodes and improves communication efficiency between computing nodes. The chip design to be verified is divided into different DUTs, and different computing nodes are used to implement different services of the chip design to be verified, avoiding the use of one computing node to implement different services of the chip design to be verified. Implementing different services of the chip design to be verified by different computing nodes can improve the efficiency of verifying the chip design to be verified.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a chip design verification system and method. Background Art

[0002] The current chip design complexity and scale are increasing, and the time to market is becoming increasingly tight. How to efficiently verify and ensure the quality of chip design has become a core issue that urgently needs to be solved in the chip research and development field. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a chip design verification system and method to improve the efficiency of chip verification. The specific technical solution is as follows:

[0004] In a first aspect, the present application provides a chip design verification system, the system comprising:

[0005] A plurality of computing nodes and an RDMA communication component corresponding to each of the computing nodes;

[0006] The computing node is used to receive the TB code sent to itself by the control node, wherein the TB code includes the code of the DUT instantiation module, the acquisition component and the assignment component, and the DUT instantiation module of the TB code of different computing nodes is used to implement different businesses of the chip design to be verified; run the received TB code to generate the DUT instantiation module, the acquisition component and the assignment component corresponding to itself; when its own DUT instantiation module is not the DUT instantiation module of the first-level business, use the assignment component to obtain the business data of the previous-level business received by the RDMA communication component corresponding to the current computing node; use its own DUT instantiation module to process the business data of the previous-level business to obtain the current business data; when its own DUT instantiation module is not the DUT instantiation module of the last-level business, use the acquisition component to call the RDMA communication component corresponding to the current computing node to send the current business data to the RDMA communication component corresponding to the computing node of the next-level business; when its own DUT instantiation module is the DUT instantiation module of the last-level business, use the current business data as the output result of the chip design to be verified;

[0007] The RDMA communication component is used to send business data to other RDMA communication components, or receive business data sent by other RDMA communication components.

[0008] In an optional implementation, the computing node is also used to: receive an Agent component sent to itself by the control node, and use the Agent component to generate an excitation signal; when its own DUT instantiation module is a DUT instantiation module for the first-level business, use its own DUT instantiation module to process the excitation signal to obtain current business data.

[0009] In an optional implementation, the computing node is specifically used to use its own assignment component to call the application program interface of the RDMA communication component corresponding to the current computing node after its corresponding RDMA communication component receives the business data, and store the received business data into the first data queue; use its own assignment component to read the business data from the first data queue based on the DUT clock signal and send it to its own DUT instantiation module for processing.

[0010] In an optional implementation, the computing node is specifically used to store the business data output by its own DUT instantiation module into a second data queue based on the DUT clock signal; use the acquisition component to read the business data from the second data queue, call the application interface of the RDMA communication component corresponding to the current computing node, and input the read business data as a payload.

[0011] In an optional implementation, the system further includes: a control node;

[0012] The control node is used to obtain the Partition configuration file of the chip design to be verified, and generate multiple TB codes of the chip design to be verified according to the Partition configuration file. The TB code includes a DUT instantiation module, an acquisition component and an assignment component. The DUT instantiation modules of different TB codes are used to implement different services of the chip design to be verified; different computing nodes are assigned to each TB code, and each TB code is sent to the corresponding computing node.

[0013] In an optional implementation, the Partition configuration file includes the number of DUTs, each DUT instantiation module, a DUT RTL file list, and DUT port grouping information;

[0014] The control node is specifically used to query the DUT port grouping information for each DUT instantiation module to determine the external port of the DUT instantiation module; query the DUT RTL file list to determine the clock signal of the external port of the DUT instantiation module; generate the acquisition component and assignment component of the DUT instantiation module based on the clock signal of the external port of the DUT instantiation module; and generate TB code according to the DUT instantiation module, the acquisition component and the assignment component of the DUT instantiation module.

[0015] In a second aspect, the present application provides a chip design verification method, which is applied to a chip design verification system, wherein the chip design verification system includes a plurality of computing nodes and an RDMA communication component corresponding to each of the computing nodes; the method includes:

[0016] The computing node receives the TB code sent to itself by the control node, wherein the TB code includes the codes of the DUT instantiation module, the acquisition component and the assignment component, and the DUT instantiation module of the TB code of different computing nodes is used to implement different businesses of the chip design to be verified; runs the received TB code to generate the DUT instantiation module, the acquisition component and the assignment component corresponding to itself; when its own DUT instantiation module is not the DUT instantiation module of the first-level business, uses the assignment component to obtain the business data of the previous-level business received by the RDMA communication component corresponding to the current computing node; uses its own DUT instantiation module to process the business data of the previous-level business to obtain the current business data; when its own DUT instantiation module is not the DUT instantiation module of the last-level business, uses the acquisition component to call the RDMA communication component corresponding to the current computing node to send the current business data to the RDMA communication component corresponding to the computing node of the next-level business; when its own DUT instantiation module is the DUT instantiation module of the last-level business, uses the current business data as the output result of the chip design to be verified;

[0017] The RDMA communication component sends service data to other RDMA communication components, or receives service data sent by other RDMA communication components.

[0018] In an optional implementation, the method further includes:

[0019] The computing node receives the Agent component sent to itself by the control node, and uses the Agent component to generate an excitation signal; when its own DUT instantiation module is the DUT instantiation module of the first-level business, it uses its own DUT instantiation module to process the excitation signal to obtain current business data.

[0020] In an optional implementation, the chip design verification system further includes: a control node, and the method further includes:

[0021] The control node obtains a Partition configuration file of the chip design to be verified, and generates multiple TB codes of the chip design to be verified according to the Partition configuration file, wherein the TB code includes a DUT instantiation module, an acquisition component and an assignment component, and the DUT instantiation modules of different TB codes are used to implement different services of the chip design to be verified; a different computing node is assigned to each TB code, and each TB code is sent to a corresponding computing node.

[0022] In an optional implementation, the Partition configuration file includes the number of DUTs, each DUT instantiation module, a DUT RTL file list, and DUT port grouping information;

[0023] The control node obtains a Partition configuration file of the chip design to be verified, and generates a plurality of TB codes of the chip design to be verified according to the Partition configuration file, including:

[0024] The control node queries the DUT port grouping information for each DUT instantiation module to determine the external port of the DUT instantiation module; queries the DUT RTL file list to determine the clock signal of the external port of the DUT instantiation module; generates the acquisition component and the assignment component of the DUT instantiation module based on the clock signal of the external port of the DUT instantiation module; and generates TB code according to the DUT instantiation module, the acquisition component and the assignment component of the DUT instantiation module.

[0025] In another aspect of the embodiments of the present application, the embodiments of the present application provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0026] The memory is used to store computer programs;

[0027] The processor is used to implement any simulation verification method described in the second aspect when executing the computer program stored in the memory.

[0028] In another aspect of the implementation of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the simulation verification method described in any one of the first aspects is implemented.

[0029] In another aspect of the implementation of the present application, a computer program product comprising instructions is also provided, which, when executed on a computer, enables the computer to execute any simulation verification method described in the first aspect.

[0030] Beneficial effects of the embodiments of the present application:

[0031] The chip design verification system and method provided in the embodiments of the present application use RDMA technology to perform data communication between different computing nodes, which speeds up data interaction between different computing nodes and improves communication efficiency between computing nodes. In addition, the chip design to be verified is divided into different DUTs, and different computing nodes are used to implement different services of the chip design to be verified, avoiding the use of one computing node to implement different services of the chip design to be verified. Implementing different services of the chip design to be verified by different computing nodes can improve the efficiency of verifying the chip design to be verified.

[0032] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0034] Figure 1 A first structural schematic diagram of a chip design verification system provided in this application;

[0035] Figure 2 A second structural schematic diagram of a chip design verification system provided by this application;

[0036] Figure 3 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0038] Terminology explanation:

[0039] EDA: Electronic design automation, refers to the design method that uses computer-aided design software to complete the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of very large-scale integrated circuit (VLSI) chips;

[0040] DUT instantiation module: Design Under Test, i.e. the design to be verified;

[0041] TB: Test Bench, which is the EDA verification platform;

[0042] RDMA: RDMA, the full name of which is Remote Direct Memory Access, is a high-performance network communication technology.

[0043] like Figure 1 As shown, the present application provides a chip design verification system, the system comprising:

[0044] A plurality of computing nodes (including computing node 101, computing node 102, ..., computing node 10n) and an RDMA communication component corresponding to each of the computing nodes (including RDMA communication component 201, RDMA communication component 202, ..., RDMA communication component 20n);

[0045] The computing node is used to receive the TB code sent to itself by the control node, wherein the TB code includes the code of the DUT instantiation module, the acquisition component and the assignment component, and the DUT instantiation module of the TB code of different computing nodes is used to implement different businesses of the chip design to be verified; run the received TB code to generate the DUT instantiation module, the acquisition component and the assignment component corresponding to itself; when its own DUT instantiation module is not the DUT instantiation module of the first-level business, use the assignment component to obtain the business data of the previous-level business received by the RDMA communication component corresponding to the current computing node; use its own DUT instantiation module to process the business data of the previous-level business to obtain the current business data; when its own DUT instantiation module is not the DUT instantiation module of the last-level business, use the acquisition component to call the RDMA communication component corresponding to the current computing node to send the current business data to the RDMA communication component corresponding to the computing node of the next-level business; when its own DUT instantiation module is the DUT instantiation module of the last-level business, use the current business data as the output result of the chip design to be verified;

[0046] The RDMA communication component is used to send business data to other RDMA communication components, or receive business data sent by other RDMA communication components.

[0047] The computing node is an EDA verification platform used to verify the chip design, such as functional verification, performance verification, stress verification or other complex scenario verification of the chip design. The RDMA communication component is used to enable different computing nodes to communicate through RDMA. The RDMA communication component is used to send business data to other RDMA communication components, or receive business data sent by other RDMA communication components.

[0048] The chip design to be verified can be divided into multiple DUTs. Exemplarily, the control node can divide the chip design to be verified into multiple DUTs based on the cohesion of the chip design to be verified. In one example, after the control node obtains the design information of the chip design to be verified, it can obtain the number of DUTs, the DUT instantiation modules specified according to the cohesion of each business implemented by the chip design to be verified, the DUT RTL (Register Transfer Level) file list and the DUT port grouping information, and divide the chip design to be verified into multiple DUTs based on the number of DUTs, the DUT instantiation modules, the DUT RTL file list and the DUT port grouping information. The TB code includes the code of the DUT instantiation module, the acquisition component and the assignment component. The control node sends each TB code to the computing node corresponding to the TB code.

[0049] After obtaining the TB code, the computing node can run the TB code to generate its own corresponding DUT instantiation module, acquisition component and assignment component.

[0050] For each computing node, when its own DUT instantiation module is not the DUT instantiation module of the first-level business, it means that the DUT instantiation module corresponding to the computing node needs to be processed based on the business data of its upper-level business. In this way, the computing node uses the assignment component to obtain the business data of the upper-level business received by the RDMA communication component corresponding to the current computing node, and then uses its own DUT instantiation module to process the business data of the upper-level business to obtain the current business data.

[0051] When its own DUT instantiation module is not the DUT instantiation module of the last level of business, it means that the business processing result of the DUT instantiation module corresponding to the computing node needs to be given to its next level of business. In this way, the computing node uses the acquisition component to call the RDMA communication component corresponding to the current computing node to send the current business data to the RDMA communication component corresponding to the computing node of the next level of business.

[0052] When the DUT instantiation module itself is the DUT instantiation module of the last-level service, the current service data is used as the output result of the chip design to be verified.

[0053] Different computing nodes communicate data through RDMA technology, which speeds up data interaction between different computing nodes and improves communication efficiency between computing nodes. In addition, the chip design to be verified is divided into different DUTs, and different computing nodes are used to implement different businesses of the chip design to be verified, avoiding the use of one computing node to implement different businesses of the chip design to be verified. Implementing different businesses of the chip design to be verified through different computing nodes can improve the efficiency of verifying the chip design to be verified.

[0054] In an optional implementation, the computing node is also used to: receive an Agent component sent to itself by the control node, and use the Agent component to generate an excitation signal; when its own DUT instantiation module is a DUT instantiation module for the first-level business, use its own DUT instantiation module to process the excitation signal to obtain current business data.

[0055] When the DUT instantiation module is a DUT instantiation module of a first-level business, the Agent component generates a stimulus signal, and the DUT instantiation module processes the stimulus signal to obtain current business data.

[0056] In an optional implementation, the computing node is specifically used to call the application program interface of the RDMA communication component corresponding to the current computing node using its own assignment component after its corresponding RDMA communication component receives the business data, and store the received business data into a first data queue; use its own assignment component to read the business data from the first data queue based on the DUT clock signal and send it to its own DUT instantiation module for processing.

[0057] The first data queue can be a first-in-first-out queue. After the corresponding RDMA communication component of the computing node receives the business data, it can use its own assignment component to call the application interface of the RDMA communication component corresponding to the current computing node, store the received business data into the first data queue, and then use its own assignment component to read the business data from the first data queue based on the DUT clock signal and send it to its own DUT instantiation module for processing.

[0058] In an optional implementation, the computing node is specifically used to store the business data output by its own DUT instantiation module into a second data queue based on the DUT clock signal; use the acquisition component to read the business data from the second data queue, call the application interface of the RDMA communication component corresponding to the current computing node, and input the read business data as a payload.

[0059] The second data queue can be a first-in-first-out queue. The computing node can store the business data output by its own DUT instantiation module in the second data queue based on the DUT clock signal. Then the acquisition component can read the business data from the second data queue, call the application interface of the RDMA communication component corresponding to the current computing node, and input the read business data as a payload.

[0060] In an optional implementation, the system further includes: a control node;

[0061] The control node is used to obtain a Partition configuration file of the chip design to be verified, and generate multiple TB codes of the chip design to be verified according to the Partition configuration file. The TB codes include a DUT instantiation module, an acquisition component and an assignment component. The DUT instantiation modules of different TB codes are used to implement different services of the chip design to be verified; different computing nodes are assigned to each TB code, and each TB code is sent to a corresponding computing node.

[0062] The control node is a device used to generate multiple TB codes for the chip design to be verified according to the different services to be implemented by the chip design to be verified. The DUT instantiation modules of different TB codes are used to implement different services of the chip design to be verified. The control file can obtain the Partition configuration file, and generate multiple TB codes of the chip design to be verified according to the Partition configuration file. After the TB code is generated, the control node allocates different computing nodes to each TB code, and sends each TB code to the corresponding computing node. Exemplarily, after the control node obtains each TB code, for the TB code to be allocated, the control node obtains each computing node, and randomly selects a computing node from each computing node and allocates it to the TB code to be allocated, so as to use the allocated computing node to run the TB code to be allocated. The TB code to be allocated is the TB code of the unallocated computing node in each TB code.

[0063] In an optional implementation, the Partition configuration file includes the number of DUTs, each DUT instantiation module, a DUT RTL file list, and DUT port grouping information;

[0064] The control node is specifically used to query the DUT port grouping information for each DUT instantiation module to determine the external port of the DUT instantiation module; query the DUT RTL file list to determine the clock signal of the external port of the DUT instantiation module; generate the acquisition component and assignment component of the DUT instantiation module based on the clock signal of the external port of the DUT instantiation module; and generate TB code according to the DUT instantiation module, the acquisition component and the assignment component of the DUT instantiation module.

[0065] Based on the above embodiments, Figure 2 As shown, the chip design to be verified can be divided into n DUTs (including DUT1, DUT2, ..., DUTn), and the DUT ports (DUT ports) connected to the outside of each DUT are determined according to the hierarchical structure after the DUT is divided. The DUT ports are grouped according to different clock domains according to the DUT ports and the DUT RTL file list in the DUT. That is to say, for each DUT instantiation module, the DUT port grouping information is queried to determine the external port of the DUT instantiation module, the DUT RTL file list is queried to determine the clock signal of the external port of the DUT instantiation module, and based on the clock signal of the external port of the DUT instantiation module, the acquisition component and the assignment component of the DUT instantiation module are generated, and TB code is generated according to the DUT instantiation module, the acquisition component and the assignment component of the DUT instantiation module.

[0066] During simulation, when DUT1 is the DUT instantiation module of the first-level business, the Agent generates an excitation signal, and the DUT instantiation module processes the excitation signal to obtain the current business data. Then DUT1 uses the acquisition component to call the RDMA communication component corresponding to the current computing node to send the current business data to the RDMA communication component corresponding to the computing node of the next-level business.

[0067] Different computing nodes communicate data through RDMA communication technology, which speeds up data interaction between different computing nodes and improves communication efficiency between computing nodes. In addition, the chip design to be verified is divided into different DUTs, and different computing nodes are used to implement different businesses of the chip design to be verified, avoiding the use of one computing node to implement different businesses of the chip design to be verified. Implementing different businesses of the chip design to be verified through different computing nodes can improve the efficiency of verifying the chip design to be verified.

[0068] The present application provides a chip design verification method, which is applied to a chip design verification system, wherein the chip design verification system includes a plurality of computing nodes and an RDMA communication component corresponding to each of the computing nodes; the method includes:

[0069] The computing node receives the TB code sent to itself by the control node, wherein the TB code includes the codes of the DUT instantiation module, the acquisition component and the assignment component, and the DUT instantiation module of the TB code of different computing nodes is used to implement different businesses of the chip design to be verified; runs the received TB code to generate the DUT instantiation module, the acquisition component and the assignment component corresponding to itself; when its own DUT instantiation module is not the DUT instantiation module of the first-level business, uses the assignment component to obtain the business data of the previous-level business received by the RDMA communication component corresponding to the current computing node; uses its own DUT instantiation module to process the business data of the previous-level business to obtain the current business data; when its own DUT instantiation module is not the DUT instantiation module of the last-level business, uses the acquisition component to call the RDMA communication component corresponding to the current computing node to send the current business data to the RDMA communication component corresponding to the computing node of the next-level business; when its own DUT instantiation module is the DUT instantiation module of the last-level business, uses the current business data as the output result of the chip design to be verified;

[0070] The RDMA communication component sends service data to other RDMA communication components, or receives service data sent by other RDMA communication components.

[0071] In an optional implementation, the method further includes:

[0072] The computing node receives the Agent component sent to itself by the control node, and uses the Agent component to generate an excitation signal; when its own DUT instantiation module is the DUT instantiation module of the first-level business, it uses its own DUT instantiation module to process the excitation signal to obtain current business data.

[0073] In an optional implementation, the chip design verification system further includes: a control node, and the method further includes:

[0074] The control node obtains a Partition configuration file of the chip design to be verified, and generates multiple TB codes of the chip design to be verified according to the Partition configuration file, wherein the TB code includes a DUT instantiation module, an acquisition component and an assignment component, and the DUT instantiation modules of different TB codes are used to implement different services of the chip design to be verified; a different computing node is assigned to each TB code, and each TB code is sent to a corresponding computing node.

[0075] In an optional implementation, the Partition configuration file includes the number of DUTs, each DUT instantiation module, a DUT RTL file list, and DUT port grouping information;

[0076] The control node obtains a Partition configuration file of the chip design to be verified, and generates a plurality of TB codes of the chip design to be verified according to the Partition configuration file, including:

[0077] The control node queries the DUT port grouping information for each DUT instantiation module to determine the external port of the DUT instantiation module; queries the DUT RTL file list to determine the clock signal of the external port of the DUT instantiation module; generates the acquisition component and the assignment component of the DUT instantiation module based on the clock signal of the external port of the DUT instantiation module; and generates TB code according to the DUT instantiation module, the acquisition component and the assignment component of the DUT instantiation module.

[0078] The present application also provides an electronic device, such as Figure 3 As shown, it includes a processor 301 , a communication interface 302 , a memory 303 and a communication bus 304 , wherein the processor 301 , the communication interface 302 , and the memory 303 communicate with each other via the communication bus 304 .

[0079] Memory 303, used for storing computer programs;

[0080] The processor 301 is used to execute the program stored in the memory 303 to implement the following steps:

[0081] The computing node receives the TB code sent to itself by the control node, wherein the TB code includes the codes of the DUT instantiation module, the acquisition component and the assignment component, and the DUT instantiation module of the TB code of different computing nodes is used to implement different businesses of the chip design to be verified; runs the received TB code to generate the DUT instantiation module, the acquisition component and the assignment component corresponding to itself; when its own DUT instantiation module is not the DUT instantiation module of the first-level business, uses the assignment component to obtain the business data of the previous-level business received by the RDMA communication component corresponding to the current computing node; uses its own DUT instantiation module to process the business data of the previous-level business to obtain the current business data; when its own DUT instantiation module is not the DUT instantiation module of the last-level business, uses the acquisition component to call the RDMA communication component corresponding to the current computing node to send the current business data to the RDMA communication component corresponding to the computing node of the next-level business; when its own DUT instantiation module is the DUT instantiation module of the last-level business, uses the current business data as the output result of the chip design to be verified;

[0082] The RDMA communication component sends service data to other RDMA communication components, or receives service data sent by other RDMA communication components.

[0083] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0084] The communication interface is used for communication between the above electronic device and other devices.

[0085] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0086] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0087] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned simulation verification methods are implemented.

[0088] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any simulation verification method in the above embodiments.

[0089] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0090] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0091] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0092] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A chip design verification system, characterized in that: The system comprises: A plurality of computing nodes and an RDMA communication component corresponding to each of the computing nodes; The computing node is used to receive the TB code sent to itself by the control node, wherein the TB code includes the code of the DUT instantiation module, the acquisition component and the assignment component, and the DUT instantiation module of the TB code of different computing nodes is used to implement different businesses of the chip design to be verified; run the received TB code to generate the DUT instantiation module, the acquisition component and the assignment component corresponding to itself; when its own DUT instantiation module is not the DUT instantiation module of the first-level business, use the assignment component to obtain the business data of the previous-level business received by the RDMA communication component corresponding to the current computing node; use its own DUT instantiation module to process the business data of the previous-level business to obtain the current business data; when its own DUT instantiation module is not the DUT instantiation module of the last-level business, use the acquisition component to call the RDMA communication component corresponding to the current computing node to send the current business data to the RDMA communication component corresponding to the computing node of the next-level business; when its own DUT instantiation module is the DUT instantiation module of the last-level business, use the current business data as the output result of the chip design to be verified; The RDMA communication component is used to send business data to other RDMA communication components, or receive business data sent by other RDMA communication components.

2. The chip design verification system according to claim 1, characterized in that: The computing node is also used to: receive the Agent component sent to itself by the control node, and use the Agent component to generate an excitation signal; when its own DUT instantiation module is the DUT instantiation module of the first-level business, use its own DUT instantiation module to process the excitation signal to obtain current business data.

3. The chip design verification system according to claim 1, characterized in that: The computing node is specifically used to use its own assignment component to call the application program interface of the RDMA communication component corresponding to the current computing node after its corresponding RDMA communication component receives the business data, and store the received business data into the first data queue; use its own assignment component to read the business data from the first data queue based on the DUT clock signal and send it to its own DUT instantiation module for processing.

4. The chip design verification system according to claim 1, characterized in that: The computing node is specifically used to store the business data output by its own DUT instantiation module into the second data queue based on the DUT clock signal; use the acquisition component to read the business data from the second data queue, call the application interface of the RDMA communication component corresponding to the current computing node, and input the read business data as a payload.

5. The chip design verification system according to claim 1, characterized in that: The system further comprises: a control node; The control node is used to obtain the Partition configuration file of the chip design to be verified, and generate multiple TB codes of the chip design to be verified according to the Partition configuration file. The TB code includes a DUT instantiation module, an acquisition component and an assignment component. The DUT instantiation modules of different TB codes are used to implement different services of the chip design to be verified; different computing nodes are assigned to each TB code, and each TB code is sent to the corresponding computing node.

6. The chip design verification system according to claim 5, characterized in that: The Partition configuration file includes the number of DUTs, each DUT instantiation module, a DUT RTL file list, and DUT port grouping information; The control node is specifically used to query the DUT port grouping information for each DUT instantiation module to determine the external port of the DUT instantiation module; query the DUT RTL file list to determine the clock signal of the external port of the DUT instantiation module; Based on the clock signal of the external port of the DUT instantiation module, the acquisition component and the assignment component of the DUT instantiation module are generated; and the TB code is generated according to the DUT instantiation module, the acquisition component and the assignment component of the DUT instantiation module.

7. A chip design verification method, characterized in that: Applied to a chip design verification system, the chip design verification system includes a plurality of computing nodes and an RDMA communication component corresponding to each of the computing nodes; the method includes: The computing node receives the TB code sent to itself by the control node, wherein the TB code includes the codes of the DUT instantiation module, the acquisition component and the assignment component, and the DUT instantiation module of the TB code of different computing nodes is used to implement different businesses of the chip design to be verified; runs the received TB code to generate the DUT instantiation module, the acquisition component and the assignment component corresponding to itself; when its own DUT instantiation module is not the DUT instantiation module of the first-level business, uses the assignment component to obtain the business data of the previous-level business received by the RDMA communication component corresponding to the current computing node; uses its own DUT instantiation module to process the business data of the previous-level business to obtain the current business data; when its own DUT instantiation module is not the DUT instantiation module of the last-level business, uses the acquisition component to call the RDMA communication component corresponding to the current computing node to send the current business data to the RDMA communication component corresponding to the computing node of the next-level business; when its own DUT instantiation module is the DUT instantiation module of the last-level business, uses the current business data as the output result of the chip design to be verified; The RDMA communication component sends service data to other RDMA communication components, or receives service data sent by other RDMA communication components.

8. The chip design verification method according to claim 7, characterized in that: The method further comprises: The computing node receives the Agent component sent to itself by the control node, and uses the Agent component to generate an excitation signal; when its own DUT instantiation module is the DUT instantiation module of the first-level business, it uses its own DUT instantiation module to process the excitation signal to obtain current business data.

9. The chip design verification method according to claim 7, characterized in that: The chip design verification system further includes: a control node, and the method further includes: The control node obtains a Partition configuration file of the chip design to be verified, and generates multiple TB codes of the chip design to be verified according to the Partition configuration file, wherein the TB code includes a DUT instantiation module, an acquisition component and an assignment component, and the DUT instantiation modules of different TB codes are used to implement different services of the chip design to be verified; a different computing node is assigned to each TB code, and each TB code is sent to a corresponding computing node.

10. The chip design verification method according to claim 9, characterized in that: The Partition configuration file includes the number of DUTs, each DUT instantiation module, a DUT RTL file list, and DUT port grouping information; The control node obtains a Partition configuration file of the chip design to be verified, and generates a plurality of TB codes of the chip design to be verified according to the Partition configuration file, including: The control node queries the DUT port grouping information for each DUT instantiation module to determine the external port of the DUT instantiation module; queries the DUT RTL file list to determine the clock signal of the external port of the DUT instantiation module; generates the acquisition component and the assignment component of the DUT instantiation module based on the clock signal of the external port of the DUT instantiation module; and generates TB code according to the DUT instantiation module, the acquisition component and the assignment component of the DUT instantiation module.

Images