Memory and working method
By using multiple transistors and logic circuits in the memory to generate output signals based on current and input voltage, the problems of complex memory structure and large area occupancy are solved, structure simplification and area reduction are achieved, and R&D costs and time are saved.
Patent Information
- Application Number
- CN202411651218.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-03-04
AI Technical Summary
Due to the existence of a large number of logic gates, memory has complex structure and large area, making it difficult to effectively simplify.
A memory is designed that includes a plurality of transistors and logic circuits through which output signals are generated based on current and input voltages flowing through the transistors, simplifying the structure of the memory and reducing the area occupied.
The state of the output signal can be controlled through multiple transistors and logic circuits, simplifying the memory structure, reducing the area occupied, and saving the cost and time of process development.
Smart Images
Figure CN119559987A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of storage technology, and in particular to a memory and a working method. Background Art
[0002] The memory usually includes a large number of logic gates. When an input signal enters the memory, these logic gates control the state of the output signal according to the state of the input signal.
[0003] However, these large numbers of logic gates result in a complex memory structure and a large occupied area. Summary of the invention
[0004] The present application provides a memory and a working method to alleviate the technical problem that the memory has a relatively complex structure and occupies a large area.
[0005] In a first aspect, the present application provides a memory comprising multiple transistors and a logic circuit, wherein the first electrodes of the multiple transistors are all connected to a power supply terminal, the control electrodes of the multiple transistors are all connected to an input voltage, and the logic circuit is connected to the second electrodes of the multiple transistors, for generating corresponding output signals according to the current flowing through the multiple transistors and the input voltage.
[0006] In a second aspect, the present application provides a memory operating method, which is applied to the above-mentioned memory, and the operating method includes: manufacturing transistors; and selecting multiple transistors according to conversion states.
[0007] The memory and working method provided in the present application can control the state of the output signal through multiple transistors and logic circuits, simplifying the structure of the memory and reducing the occupied area.
[0008] Furthermore, a plurality of transistors can be selected from transistors formed by existing processes without the need for special process development, which saves the cost and time of process development. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.
[0010] Figure 1 A first circuit diagram of a memory provided in an embodiment of the present application.
[0011] Figure 2 A second circuit diagram of the memory provided in an embodiment of the present application.
[0012] Figure 3 A third circuit diagram of the memory provided in an embodiment of the present application.
[0013] Figure 4A schematic diagram of the change between Id and Vg of the transistor provided in an embodiment of the present application.
[0014] Figure 5 A schematic diagram of a first conversion mode of a memory provided in an embodiment of the present application.
[0015] Figure 6 A schematic diagram of a second conversion mode of a memory provided in an embodiment of the present application.
[0016] Figure 7 A schematic diagram of a third conversion mode of the memory provided in an embodiment of the present application.
[0017] Figure 8 A schematic diagram of a fourth conversion mode of the memory provided in an embodiment of the present application.
[0018] Fig. 9 A schematic diagram of the fifth conversion mode of the memory provided in an embodiment of the present application.
[0019] Fig.10 A schematic diagram of the sixth conversion mode of the memory provided in an embodiment of the present application.
[0020] Fig.11 A schematic diagram of the seventh conversion mode of the memory provided in an embodiment of the present application.
[0021] Fig.12 A schematic diagram of the conversion state of the memory provided in an embodiment of the present application.
[0022] Fig.13 A schematic diagram of the structure of a first transistor provided in an embodiment of the present application.
[0023] Fig.14 A schematic diagram of the structure of a second transistor provided in an embodiment of the present application.
[0024] Fig.15 A schematic diagram of the structure of the third transistor provided in an embodiment of the present application.
[0025] Fig.16 A schematic diagram of the first structure of multiple transistors provided in an embodiment of the present application.
[0026] Fig.17 A second structural schematic diagram of multiple transistors provided in an embodiment of the present application.
[0027] Fig.18 A third structural schematic diagram of multiple transistors provided in an embodiment of the present application. DETAILED DESCRIPTION
[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0029] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.
[0030] This embodiment provides a memory, see Figures 1 to 12 ,like Figure 1 As shown, the memory includes multiple transistors MOS and a logic circuit 100, the first electrodes of the multiple transistors MOS are all connected to the power supply terminal VDD, the control electrodes of the multiple transistors MOS are all connected to the input voltage V, and the logic circuit 100 is connected to the second electrodes of the multiple transistors MOS, and is used to generate corresponding output signals according to the current flowing through the multiple transistors MOS and the input voltage V.
[0031] It can be understood that the memory provided in this embodiment can control the state of the output signal through multiple MOS transistors and the logic circuit 100, which simplifies the structure of the memory and reduces the occupied area.
[0032] Furthermore, a plurality of MOS transistors can be selected from MOS transistors formed by existing processes without the need for special process development, which saves the cost and time of process development.
[0033] It should be noted that the channel types of multiple MOS transistors may be the same, for example, all are P-channel field effect transistors, or all are N-channel field effect transistors. In some embodiments, the channel types of multiple MOS transistors may also be different. The first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or, when the first electrode is the drain, the second electrode is the source. The control electrode may be a gate or a base.
[0034] Exemplarily, the above-mentioned memory may be, but is not limited to, a mask read-only memory (Mask Rom), and may also be other memory chips applicable to the present application.
[0035] The power supply terminal VDD is used to connect to the high level. The input terminal is used to connect to the input voltage V.
[0036] In some embodiments, the input voltage V includes a first input voltage, and the first input voltage is applied to the memory to generate a corresponding output signal according to a current flowing through the plurality of transistors MOS.
[0037] In some of the embodiments, the input voltage V includes a second input voltage, the second input voltage is applied to the memory, and a corresponding output signal is generated according to a current flowing through the plurality of transistors MOS.
[0038] In some embodiments, the input voltage V includes a first input voltage and a second input voltage; the first input voltage is applied to the memory, and a corresponding output signal is generated according to the current flowing through multiple transistors MOS; the second input voltage is applied to the memory, and a corresponding output signal is generated according to the current flowing through multiple transistors MOS.
[0039] It should be noted that the first input voltage may be illustratively greater than the second input voltage. In some other embodiments, the first input voltage may also be less than the second input voltage.
[0040] In some embodiments, such as Figure 2 , Figure 3 As shown, the logic circuit 100 includes a current determination unit 10, a voltage determination unit 20 and a signal processing unit 30. The current determination unit 10 is connected to the second electrodes of multiple transistors MOS, and is used to determine the total current I according to the sum of the currents flowing through the multiple transistors MOS; the voltage determination unit 20 is used to determine the voltage comparison result according to the input voltage V and the threshold voltages of multiple transistors MOS; the signal processing unit 30 is connected to the current determination unit 10 and the voltage determination unit 20, and is used to generate an output signal according to the total current I and the voltage comparison result. In some embodiments, the above-mentioned units are not completely independent circuit structures, for example, the current determination unit 10 and the voltage determination unit 20 can be implemented by the same circuit structure.
[0041] In some embodiments, such as Figure 2 , Figure 3 As shown, the current determination unit 10 includes a current acquisition circuit 11 and a current summing circuit 12. The current acquisition circuit 11 is connected to the second electrodes of multiple transistors MOS and is used to acquire the current flowing through each transistor MOS; the current summing circuit 12 is connected to the current acquisition circuit 11 and is used to obtain the total current I according to the sum of the currents flowing through each transistor MOS.
[0042] It should be noted that the current acquisition circuit 11 can be implemented by a resistor or a Hall sensor, for example.
[0043] In some embodiments, such as Figure 2 , Figure 3 As shown, the voltage determination unit 20 includes a register 21 and a voltage comparison circuit 22. The register 21 is used to store the threshold voltage and input voltage V of each transistor MOS; the voltage comparison circuit 22 is connected to the register 21 and is used to determine the voltage comparison result according to the magnitude relationship between the input voltage V and each threshold voltage.
[0044] It should be noted that the threshold voltage of the transistor MOS may be known in advance, for example, obtained by pre-measurement or pre-estimation. The input voltage V in the register 21 may be updated in real time, and in some other embodiments, the input voltage V may also be cached by a buffer.
[0045] In some embodiments, such as Figure 2 , Figure 3 As shown, the signal processing unit 30 includes a first mapping table 31 and a second mapping table 32. The first mapping table 31 is used to determine the conversion state of the memory according to the total current I and the voltage comparison result; the second mapping table 32 is used to determine the output signal according to the conversion state.
[0046] In some embodiments, such as Figure 3 As shown, the multiple transistors MOS include a first transistor MOS1, a second transistor MOS2 and a third transistor MOS3. The first electrode of the first transistor MOS1 is connected to the power supply terminal VDD, the control electrode of the first transistor MOS1 is connected to the input voltage V, and the second electrode of the first transistor MOS1 is connected to the logic circuit 100; the first electrode of the second transistor MOS2 is connected to the first electrode of the first transistor MOS1, the control electrode of the second transistor MOS2 is connected to the control electrode of the first transistor MOS1, and the second electrode of the second transistor MOS2 is connected to the logic circuit 100; the first electrode of the third transistor MOS3 is connected to the first electrode of the first transistor MOS1, the control electrode of the third transistor MOS3 is connected to the control electrode of the first transistor MOS1, and the second electrode of the third transistor MOS3 is connected to the logic circuit 100.
[0047] In some embodiments, when the output signal exemplarily has three code values, namely, the first code value, the second code value, and the third code value, the number of the plurality of transistors MOS may be three. The first code value may be data on the low bit of the output signal, the second code value may be data on the second lowest bit of the output signal, and the third code value may be data on the high bit of the output signal. Alternatively, in some other embodiments, the first code value may be data on the high bit of the output signal, the second code value may be data on the second lowest bit of the output signal, and the third code value may be data on the low bit of the output signal.
[0048] In some other embodiments, the number of the plurality of MOS transistors may also be two, four, five or more integers, and each MOS transistor outputs a corresponding code value to meet the requirements of output signals with different bit widths.
[0049] Figure 4 A schematic diagram of the change between Id and Vg of the MOS transistor provided in an embodiment of the present application.
[0050] Wherein, Id represents the drain current, i.e., the current flowing between the drain and source of the transistor MOS. Vg represents the gate potential of the transistor MOS. MOS-1 represents a transistor MOS with a first threshold voltage Vt1, MOS-2 represents a transistor MOS with a second threshold voltage Vt2, and MOS-3 represents a transistor MOS with a third threshold voltage Vt3. The first threshold voltage Vt1 is less than the second threshold voltage Vt2, and the second threshold voltage Vt2 is less than the third threshold voltage Vt3.
[0051] See also Figures 5 to 12 , the first transistor MOS1, the second transistor MOS2 and the third transistor MOS3 are all N-channel transistor MOS for example. Id1 represents the drain current of MOS-1, Id2 represents the drain current of MOS-2, Id3 represents the drain current of MOS-3, and the total current I represents the sum of Id1, Id2 and Id3. The first code value is the data on the low bit of the output signal, the second code value is the data on the second low bit of the output signal, and the third code value is the data on the high bit of the output signal for example.
[0052] like Figure 5 and Fig.12 As shown, the first transistor MOS1, the second transistor MOS2 and the third transistor MOS3 are all transistor MOS with a third threshold voltage Vt3, the voltage comparison result is that the input voltage V is less than the third threshold voltage Vt3, and the total current I is approximately equal to 0. The first mapping table 31 determines that the conversion state is the first conversion mode according to the voltage comparison result and the total current I is approximately equal to 0; the second mapping table 32 determines that the output signal is 000 according to the conversion state being the first conversion mode.
[0053] like Figure 6 and Fig.12As shown, the first transistor MOS1 is a transistor MOS with a first threshold voltage Vt1, the second transistor MOS2 and the third transistor MOS3 are both transistor MOS with a third threshold voltage Vt3, the voltage comparison result is that the input voltage V is greater than the first threshold voltage Vt1 and less than the second threshold voltage Vt2, the total current I is equal to the current Id1 of the transistor MOS with the first threshold voltage Vt1, the first mapping table 31 determines that the conversion state is the second conversion mode according to the voltage comparison result and the total current I; the second mapping table 32 determines that the output signal is 001 according to the conversion state being the second conversion mode.
[0054] like Figure 7 and Fig.12 As shown, the first transistor MOS1 and the second transistor MOS2 are both transistor MOS with a first threshold voltage Vt1, the third transistor MOS3 is a transistor MOS with a third threshold voltage Vt3, the voltage comparison result is that the input voltage V is greater than the first threshold voltage Vt1 and less than the second threshold voltage Vt2, the total current I is equal to twice the current of the transistor MOS with the first threshold voltage Vt1, that is, 2Id1, the first mapping table 31 determines that the conversion state is the third conversion mode according to the voltage comparison result and the total current I; the second mapping table 32 determines that the output signal is 010 according to the conversion state being the third conversion mode.
[0055] like Figure 8 and Fig.12 As shown, the first transistor MOS1, the second transistor MOS2 and the third transistor MOS3 are all transistor MOS with a first threshold voltage Vt1, the voltage comparison result is that the input voltage V is greater than the first threshold voltage Vt1 and less than the second threshold voltage Vt2, the total current I is equal to three times the current of the transistor MOS with the first threshold voltage Vt1, that is, 3Id1, the first mapping table 31 determines that the conversion state is the fourth conversion mode according to the voltage comparison result and the total current I; the second mapping table 32 determines that the output signal is 011 according to the conversion state being the fourth conversion mode.
[0056] like Fig. 9 and Fig.12 As shown, the first transistor MOS1 is a transistor MOS with a second threshold voltage Vt2, the second transistor MOS2 and the third transistor MOS3 are both transistor MOS with a third threshold voltage Vt3, the voltage comparison result is that the input voltage V is greater than the second threshold voltage Vt2 and less than the third threshold voltage Vt3, the total current I is equal to the current Id2 of the transistor MOS with the second threshold voltage Vt2, the first mapping table 31 determines that the conversion state is the fifth conversion mode according to the voltage comparison result and the total current I; the second mapping table 32 determines that the output signal is 100 according to the conversion state being the fifth conversion mode.
[0057] like Fig.10 and Fig.12 As shown, the first transistor MOS1 and the second transistor MOS2 are both transistor MOS with a second threshold voltage Vt2, the third transistor MOS3 is a transistor MOS with a third threshold voltage Vt3, the voltage comparison result is that the input voltage V is greater than the second threshold voltage Vt2 and less than the third threshold voltage Vt3, the total current I is equal to twice the current of the transistor MOS with the second threshold voltage Vt2, that is, 2Id2, the first mapping table 31 determines that the conversion state is the sixth conversion mode according to the voltage comparison result and the total current I; the second mapping table 32 determines that the output signal is 101 according to the conversion state being the sixth conversion mode.
[0058] like Fig.11 and Fig.12 As shown, the first transistor MOS1, the second transistor MOS2 and the third transistor MOS3 are all transistor MOS with a second threshold voltage Vt2, the voltage comparison result is that the input voltage V is greater than the second threshold voltage Vt2 and less than the third threshold voltage Vt3, the total current I is equal to three times the current of the transistor MOS with the second threshold voltage Vt2, that is, 3Id2, the first mapping table 31 determines that the conversion state is the seventh conversion mode according to the voltage comparison result and the total current I; the second mapping table 32 determines that the output signal is 110 according to the conversion state being the seventh conversion mode.
[0059] In one embodiment, the logic circuit 100 includes a current determination unit 10 and a signal determination unit. The current determination unit 10 is connected to the second electrodes of multiple transistors MOS and is used to determine the total current I according to the sum of the currents flowing through the multiple transistors MOS; the signal determination unit is connected to the current determination unit and is used to determine the output signal according to the total current I.
[0060] For example Fig.12 As shown, when the total current I is approximately equal to 0, the output signal is 000; or, when the total current I is Id1, the output signal is 001; and so on, when the total current I is 3Id2, the output signal is 110. Compared with the aforementioned method for determining the output signal, this embodiment requires less hardware circuits and the determination process is simpler.
[0061] The structure of the first transistor MOS1 is as follows Fig.13 As shown, it includes a first source S1, a first gate G1 and a first drain D1, the first gate G1 is layered with the first source S1 and the first drain D1, and the projection of the first gate G1 is located between the first source S1 and the first drain D1. At least one contact hole CV can be set on the first source S1, the first gate G1 and the first drain D1.
[0062] The structure of the second transistor MOS2 is as follows Fig.14As shown, it includes a second source S2, a second gate G2 and a second drain D2, the second gate G2 is layered with the second source S2 and the second drain D2, and the projection of the second gate G2 is located between the second source S2 and the second drain D2. At least one contact hole CV can be set on the second source S2, the second gate G2 and the second drain D2.
[0063] The structure of the third transistor MOS3 is as follows Fig.15 As shown, it includes a third source S3, a third gate G3 and a third drain D3, the third gate G3 and the third source S3 and the third drain D3 are layered, and the projection of the third gate G3 is located between the third source S3 and the third drain D3. At least one contact hole CV can be set on the third source S3, the third gate G3 and the third drain D3.
[0064] from Figures 13 to 15 It can be seen that the width of the source and drain of the first transistor MOS1, the width of the source and drain of the second transistor MOS2, and the width of the source and drain of the third transistor MOS3 decrease in sequence.
[0065] Fig.16 The combined design of three third transistors MOS3 is shown. The three third transistors MOS3 share the same gate, so they can be formed through a one-time process, simplifying the manufacturing process.
[0066] If each of the third transistors MOS3 is a transistor MOS with a third threshold voltage Vt3, when the input voltage V is less than the third threshold voltage Vt3, the output signal is 000.
[0067] Fig.17 The combined design of two first transistors MOS1 and one third transistor MOS3 is shown. The two first transistors MOS1 and one third transistor MOS3 share the same gate, so they can be formed through a one-time process, simplifying the manufacturing process.
[0068] If the two first transistors MOS1 are both transistors MOS with a first threshold voltage Vt1, and the one third transistor MOS3 is a transistor MOS with a third threshold voltage Vt3, when the input voltage V is greater than the first threshold voltage Vt1 and less than the second threshold voltage Vt2, the output signal is 010.
[0069] Fig.18 The combined design of two second transistors MOS2 and one third transistor MOS3 is shown. The two second transistors MOS2 and one third transistor MOS3 share the same gate, so they can be formed through a one-time process, simplifying the manufacturing process.
[0070] If the two second transistors MOS2 are both transistors MOS with a second threshold voltage Vt2, and the one third transistor MOS3 is a transistor MOS with a third threshold voltage Vt3, the input voltage V is greater than the second threshold voltage Vt2 and less than the third threshold voltage Vt3, the output signal is 101.
[0071] Other combinations of MOS transistors can also be Figures 16 to 18 The contents shown are implemented and will not be repeated here.
[0072] In one of the embodiments, this embodiment provides a memory operation method, which is applied to the above-mentioned memory, and includes: manufacturing a transistor MOS; and selecting a plurality of transistor MOS according to a conversion state.
[0073] It can be understood that since the working method provided in this embodiment is applied to the above-mentioned memory, the state of the output signal can also be controlled by multiple MOS transistors and the logic circuit 100, which simplifies the structure of the memory and reduces the occupied area.
[0074] Furthermore, a plurality of MOS transistors can be selected from MOS transistors formed by existing processes without the need for special process development, which saves the cost and time of process development.
[0075] In some embodiments, selecting a plurality of MOS transistors according to a conversion state includes: configuring the conversion state to include at least one conversion mode; and selecting a plurality of MOS transistors according to each conversion mode.
[0076] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0077] The above is a detailed introduction to the memory and working method provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A memory, characterized in that: The memory comprises: A plurality of transistors, wherein the first electrodes of the plurality of transistors are all connected to a power supply terminal, and the control electrodes of the plurality of transistors are all connected to an input voltage; A logic circuit is connected to the second electrodes of the plurality of transistors and is used to generate corresponding output signals according to the currents flowing through the plurality of transistors and the input voltage.
2. The memory according to claim 1, characterized in that: The input voltage includes a first input voltage and / or a second input voltage; Applying a first input voltage to the memory and generating a corresponding output signal according to currents flowing through the plurality of transistors; and / or, A second input voltage is applied to the memory, and a corresponding output signal is generated according to currents flowing through the plurality of transistors.
3. The memory according to claim 1, characterized in that: The logic circuit comprises: a current determining unit, the current determining unit being connected to the second electrodes of the plurality of transistors and configured to determine a total current according to a sum of currents flowing through the plurality of transistors; a voltage determination unit, configured to determine a voltage comparison result according to the input voltage and the threshold voltages of the plurality of transistors; A signal processing unit, the signal processing unit is connected to the current determination unit and the voltage determination unit, and is used to generate the output signal according to the comparison result of the total current and the voltage.
4. The memory according to claim 3, characterized in that: The current determination unit comprises: A current acquisition circuit, connected to the second electrodes of the plurality of transistors, and configured to acquire a current flowing through each of the transistors; A current summing circuit is connected to the current acquisition circuit and is used to obtain the total current according to the sum of the currents flowing through each of the transistors.
5. The memory according to claim 4, characterized in that: The voltage determination unit comprises: A register, the register being used to store a threshold voltage of each of the transistors and the input voltage; A voltage comparison circuit is connected to the register and is used to determine the voltage comparison result according to the magnitude relationship between the input voltage and each of the threshold voltages.
6. The memory according to claim 5, characterized in that: The signal processing unit comprises: a first mapping table, wherein the first mapping table is used to determine a conversion state of the memory according to a comparison result between the total current and the voltage; A second mapping table, wherein the second mapping table is used to determine the output signal according to the conversion state.
7. The memory according to claim 1, characterized in that: The logic circuit comprises: a current determining unit, the current determining unit being connected to the second electrodes of the plurality of transistors and configured to determine a total current according to a sum of currents flowing through the plurality of transistors; A signal determination unit is connected to the current determination unit and is used to determine the output signal according to the total current.
8. The memory according to any one of claims 1 to 7, characterized in that: The output signal includes a first code value, a second code value, and a third code value, and the plurality of transistors include: a first transistor, wherein a first electrode of the first transistor is connected to the power supply terminal, a control electrode of the first transistor is connected to an input voltage, and a second electrode of the first transistor is connected to the logic circuit; a second transistor, wherein a first electrode of the second transistor is connected to a first electrode of the first transistor, a control electrode of the second transistor is connected to a control electrode of the first transistor, and a second electrode of the second transistor is used to be connected to the logic circuit; A third transistor, wherein a first electrode of the third transistor is connected to the first electrode of the first transistor, a control electrode of the third transistor is connected to the control electrode of the first transistor, and a second electrode of the third transistor is connected to the logic circuit.
9. The memory according to claim 8, characterized in that: The first threshold voltage is less than the second threshold voltage, and the second threshold voltage is less than the third threshold voltage; The first transistor, the second transistor and the third transistor are all transistors of the third threshold voltage; Alternatively, the first transistor is a transistor of the first threshold voltage, and the second transistor and the third transistor are both transistors of the third threshold voltage; Alternatively, the first transistor and the second transistor are both transistors of the first threshold voltage, and the third transistor is a transistor of the third threshold voltage; Alternatively, the first transistor, the second transistor and the third transistor are all transistors of the first threshold voltage; Alternatively, the first transistor is a transistor of the second threshold voltage, and the second transistor and the third transistor are both transistors of the third threshold voltage; Alternatively, the first transistor and the second transistor are both transistors of the second threshold voltage, and the third transistor is a transistor of the third threshold voltage; Alternatively, the first transistor, the second transistor and the third transistor are all transistors of the second threshold voltage.
10. A memory operating method, characterized in that: The working method is applied to the memory according to any one of claims 1 to 9, and the working method comprises: Making transistors; The plurality of transistors are selected according to the switching state.
11. The working method according to claim 10, characterized in that: The selecting the plurality of transistors according to the conversion state comprises: Configuring the conversion state to include at least one conversion mode; The plurality of transistors are selected according to each of the switching modes.
12. The working method according to claim 11, characterized in that: The plurality of transistors include a first transistor, a second transistor, and a third transistor, the first threshold voltage is less than the second threshold voltage, and the second threshold voltage is less than the third threshold voltage; the selecting the plurality of transistors according to each of the conversion modes includes: When the conversion mode is in the first conversion mode where the output signal is 000, determining that the first transistor, the second transistor, and the third transistor are all transistors with the third threshold voltage; When the conversion mode is in the second conversion mode where the output signal is 001, determining that the first transistor is a transistor of the first threshold voltage, and the second transistor and the third transistor are both transistors of the third threshold voltage; When the conversion mode is in the third conversion mode where the output signal is 010, determining that the first transistor and the second transistor are both transistors of the first threshold voltage, and the third transistor is a transistor of the third threshold voltage; When the conversion mode is in a fourth conversion mode in which the output signal is 011, determining that the first transistor, the second transistor, and the third transistor are all transistors of the first threshold voltage; When the conversion mode is in the fifth conversion mode in which the output signal is 100, determining that the first transistor is a transistor of the second threshold voltage, and the second transistor and the third transistor are both transistors of the third threshold voltage; When the conversion mode is in the sixth conversion mode in which the output signal is 101, it is determined that the first transistor and the second transistor are both transistors of the second threshold voltage, and the third transistor is a transistor of the third threshold voltage; When the conversion mode is in the seventh conversion mode in which the output signal is 110, it is determined that the first transistor, the second transistor, and the third transistor are all transistors of the second threshold voltage.