Test system and test method for memory chip

Abstract

The invention provides a test system and a test method for a memory chip. The test system comprises a host, a chip test seat, a first interface module, a second interface module and a bridging chip module, the chip testing seat is used for installing a chip to be tested. The first interface module and the second interface module are used for being connected with a host; the bridging chip module is used for acquiring a test data packet written by the host and performing protocol conversion on the test data packet between the data packet format of the chip to be tested and the data packet format of the first interface module or the second interface module; the bridge chip module is used for adjusting the read-write performance of the to-be-tested chip to different read-write speed levels so as to detect the read-write performance of the to-be-tested chip. According to the method, the integrity of the test data packet after being read and written by the storage chip is judged through the host, so that the read-write performance of the chip to be tested at the corresponding read-write speed is determined, and the problem that a traditional test platform cannot completely meet the read-write performance test requirement of the storage chip after iteration is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of memory chip testing, and in particular to a memory chip testing system and a testing method. Background Art

[0002] With the widespread application of UFS (Universal Flash Storage) storage chips in terminal products such as TVs, set-top boxes, tablets or mobile phones, the performance and reliability requirements of UFS storage chips are getting higher and higher. The most important thing is to ensure that the data stored in UFS is stable and reliable. UFS storage chips are composed of ARM CPU as a controller and NAND Flash. The ARM CPU runs the controller software, usually called firmware. The main function of the firmware is to manage the bad blocks, GC, early warning, improve the performance and life of NAND Flash, and ensure the reliable use of NAND Flash. With the large-scale application of UFS and other storage particles in mobile phones, tablets, and wearable devices, clients have higher and higher requirements for UFS storage performance. How to ensure that UFS can maintain performance stability in application scenarios is what every storage manufacturer needs to pay attention to.

[0003] With the evolution and iteration of the UFS protocol, the speeds of UFS2.1, UFS2.2, UFS3.1, UFS4.0, and UFS5.0 are getting faster and faster. The current card readers on the market basically only meet the test requirements of UFS2.1 and UFS2.2 speeds, and lack support for higher speeds of UFS3.1, UFS4.0, and UFS5.0. For module manufacturers, there is a lack of high-speed testing tools. Based on the actual product testing needs, this paper proposes an overall testing system solution that can solve the current dilemma and meet the needs of UFS storage manufacturers for high-speed testing tools.

[0004] With the widespread use of UFS storage chips in terminal products, storage chip manufacturers need testing tools that can test UFS storage performance. Traditional platforms cannot fully meet the performance testing requirements of iterative storage chips.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention and does not constitute any limitation to the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the present invention provides a test system and a test method for a memory chip to solve the problem that the traditional test platform cannot fully meet the requirements for the read and write performance test of the iterative memory chip.

[0007] The present invention provides a memory chip testing system, comprising: Host; Chip test socket, used to install the chip to be tested; The first interface module and the second interface module are connected to the host and the bridge chip module respectively; A bridge chip module, the bridge chip module is connected to the chip under test by connecting to the chip test socket, the bridge chip module obtains a test data packet sent by the host, performs protocol conversion on the test data packet between the data packet format of the chip under test and the data packet format of the first interface module or the second interface module, and then writes the converted test data packet to the chip under test, then reads the test data packet in the chip under test, converts its data packet format and sends it to the host; Among them, the host determines whether the test data packet written by the host to the chip under test through the first interface module or the second interface module is consistent with the test data packet sent to the host by the chip under test through the first interface module or the second interface module, so as to detect the read and write performance of the chip under test; the bridge chip module adjusts the read and write performance of the chip under test to different read and write speed levels, and converts the data packet format between the test data packet written from the host to the chip under test and the test data packet sent from the chip under test to the host.

[0008] In one embodiment of the present invention, the bridge chip module identifies the first interface module or the second interface module connected to the host, and adjusts the read and write performance of the first interface module or the second interface module to the highest read and write speed through the host according to the read and write performance adjustment command of the host.

[0009] In one embodiment of the present invention, the bridge chip module includes: Central processing unit; A memory access unit, used to read the test data packet of the chip under test and write the test data packets of the first interface module and the second interface module into the chip under test; A memory buffer unit, used to receive and store the test data packets read and written by the memory access unit; The protocol conversion unit is used to convert the data packet format of the chip under test into the data packet format of the first interface module or the second interface module, and convert the data packet format of the first interface module or the second interface module into the data packet format of the chip under test.

[0010] In one embodiment of the present invention, the central processing unit performs an initialization operation on the chip to be tested that is loaded into the chip test socket, and determines a corresponding read / write speed level according to the specification of the chip to be tested.

[0011] In one embodiment of the present invention, the memory access unit includes a remote direct memory access unit and a write data memory access unit. The remote direct memory access unit reads a test data packet of the chip under test and writes the read test data packet of the chip under test into the memory buffer unit. The write data memory access unit writes the test data packets of the first interface module and the second interface module into the memory buffer unit.

[0012] In one embodiment of the present invention, the protocol conversion unit removes the protocol field from the test data packet in the memory buffer unit and retains its original data field, and then packages the original data field to form a new data packet format, so that the test data packet can be converted between the data packet format of the chip to be tested and the data packet format of the first interface module or the second interface module.

[0013] In one embodiment of the present invention, the central processing unit is used to write the test data packet of the first interface module or the second interface module into the memory buffer unit through the write data memory access unit, and convert the test data packet in the data packet format of the first interface module or the second interface module into the data packet format of the chip to be tested through the protocol conversion unit.

[0014] In one embodiment of the present invention, the central processing unit is used to read the test data packet of the chip under test into the memory buffer unit through the remote direct memory access unit, and convert the data packet format of the chip under test into the data packet format of the first interface module or the second interface module through the protocol conversion unit. The present invention also provides a method for testing a memory chip, comprising: Detecting whether the first interface module or the second interface module is connected to the host through the bridge chip module, and detecting the chip to be tested loaded into the chip test socket; Obtain a test data packet sent by the host, convert the test data packet between the data packet format of the first interface module or the second interface module and the data packet format of the chip to be tested through the bridge chip module, write the converted test data packet into the chip to be tested, then read out the test data packet written into the chip to be tested, convert its data packet format and send it to the host; Determining by the host whether the test data packet written by the host to the chip under test through the first interface module or the second interface module is consistent with the test data packet sent by the chip under test to the host through the first interface module or the second interface module, so as to detect the read and write performance of the chip under test; The read and write performance of the chip under test is adjusted to different read and write speed levels through the bridge chip module, and the data packet format conversion is performed between the test data packet written from the host to the chip under test and the test data packet sent from the chip under test to the host.

[0015] The beneficial effects of the present invention are as follows: through the provided memory chip test system and test method, the host controls the read and write speed of the memory chip read and write performance, and increases the read and write speed to a higher speed, and the host determines the integrity of the test data packet after reading and writing the memory chip, thereby determining the read and write performance of the chip to be tested corresponding to the read and write speed. The read and write performance of multiple storage products can be quickly detected in different test environments, thereby improving the test efficiency.

[0016] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 This is an architecture diagram of the storage chip testing system of the present invention; Figure 2 is a schematic diagram of the bridge chip module of the present invention; Figure 3 A schematic diagram of the data packet format of the USB protocol data packet in the present invention; Figure 4 A schematic diagram of the data packet format of the PCIE protocol data packet in the present invention; Figure 5 A schematic diagram of the data packet format of the UFS protocol data packet in the present invention; Figure 6 The flowchart of the storage chip testing method in the present invention.

[0018] In the figure: 10, host; 20, chip test socket; 30, first interface module; 40, second interface module; 50, bridge chip module; 60, indication module; 51, central processing unit; 52, memory access unit; 53, memory buffer unit; 54, protocol conversion unit; 55, interface unit; 56, power management unit; 57, serial interface unit; 58, speed indication unit. DETAILED DESCRIPTION

[0019] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied by other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the features in the following embodiments and embodiments can be combined with each other without conflict. It should also be understood that the terms used in the embodiments of the present invention are to describe specific specific embodiments, rather than to limit the scope of protection of the present invention.

[0020] See also Figures 1 to 6 . It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention. At the same time, the terms such as position and quantitative relationship cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0021] See also Figure 1The present invention provides a memory chip test system, comprising a host 10, a chip test socket 20, a first interface module 30, a second interface module 40 and a bridge chip module 50; the chip test socket 20 is used to install a chip to be tested; the first interface module 30 and the second interface module 40 are connected to the host 10 and the bridge chip module 50 respectively; the bridge chip module 50 is connected to the chip to be tested by connecting to the chip test socket 20, and the bridge chip module 50 obtains a test data packet sent by the host 10, performs protocol conversion on the test data packet between the data packet format of the chip to be tested and the data packet format of the first interface module 30 or the second interface module 40, and then converts the converted test data packet into a test data packet format; The test data packet is written into the chip under test, and then the test data packet in the chip under test is read out, and the data packet format is converted and sent to the host 10; wherein, the host 10 determines whether the test data packet sent by the host 10 to the chip under test through the first interface module 30 or the second interface module 40 is consistent with the test data packet sent by the chip under test to the host 10 through the first interface module 30 or the second interface module 40, so as to detect the read and write performance of the chip under test; the bridge chip module 50 adjusts the read and write performance of the chip under test to different read and write speed levels, and performs data packet format conversion between the test data packet sent from the host 10 to the chip under test and the test data packet sent from the chip under test to the host 10.

[0022] Specifically, in an embodiment of the present invention, the host 10, such as a computer, serves as an interactive terminal for operating the test system, and forms a connection with the bridge chip module 50 through a first interface module 30, such as a high-speed serial computer expansion bus standard PCIE (Peripheral Component Interconnect Express) interface or a second interface module 40, such as a universal serial bus USB (Universal SerialBus) interface, to write and read test data packets. Similarly, the number of multi-channel threads of the multi-core CPU in the host 10 can also be used to meet the multi-channel queue MCQ (Multi-Channel Queue) test of the universal flash memory UFS (Univeral Flash Storage) to improve its storage performance and concurrent processing capabilities, and ensure that the UFS storage particles, that is, the extreme performance of the chip to be tested, are tested. The chip test socket 20 is used to install the storage chip to be tested, such as UFS, to test the read and write performance. As shown in the attached Figure 1-2As shown, in some embodiments, the chip test socket 20 can be expanded to a four-way UFS Socket channel. In other embodiments, there can be four UFS chip test sockets 20 connected to the bridge chip module 50. These four chip test sockets 20 can simultaneously connect 1 to 4 USF chips to be tested for testing to meet the testing requirements of different storage chip particle quantities and capacities. The corresponding interfaces of the first interface module 30 and the second interface module 40, such as PCIE 4.0 and USB 4.0, have higher read and write speeds than UFS 4.0, which serves as read and write performance redundancy for the chips to be tested, such as UFS 4.0 storage chips. The bridge chip module 50, that is, the bridge conversion chip, can be customized to be a chip MULTI BRIDGE that integrates multiple bridging functions, and can connect different types of buses and interfaces in a computer system to realize data transmission and protocol conversion. It is used to realize the mutual conversion between different high-speed interface protocols in the bridge conversion chip of UFS to PCIE or USB with high read and write speed after iteration.

[0023] Please refer to the attached Figure 1 As shown, in one embodiment of the present invention, the test system also includes an indication module 60, which can be an indication ratio light G1-G5, indicating the current UFS read and write performance adjustment Tuning speed level, which is used to intuitively feedback the read and write speed level of the chip under test.

[0024] That is to say, in an embodiment of the present invention, the test system of the storage chip can be understood as a UFS / USB / PCIE protocol adapter card device, which sets the read and write speeds of different protocols and converts the test data packet written by the host 10 between the data packet formats of different interface protocols and storage protocols. After the test data packet has passed the read and write process between the UFS / USB / PCIE protocols, the integrity of the data content in the test data packet is still maintained, which indicates the performance reliability of the storage chip at the current read and write speed. The host 10 controls the read and write speed of the storage chip's read and write performance to increase it to a higher read and write speed, and the host 10 determines the integrity of the test data packet after reading and writing the storage chip, thereby determining the read and write performance of the chip to be tested at the corresponding read and write speed.

[0025] In one embodiment, the host 10 is used to send a read / write performance adjustment instruction of the first interface module 30, and the maximum read / write speed of the first interface module 30 is greater than the maximum read / write speed of the second interface module 40. When the first interface module 30 and the second interface module 40 exist at the same time, that is, when the PCIE interface and the USB interface exist at the same time, the speed of the PCIE interface is usually adjusted first, because the PCIE interface usually provides higher bandwidth and lower latency. In this way, for high-performance applications such as hardware with high data transmission rates such as chips to be tested, by adjusting the speed of the PCIE interface, the performance components in the test system can be ensured to be in the best operating state, while the priority of the read / write speed requirement of the USB interface in the test system application scenario is placed after the PCIE interface. In this way, the highest read / write speed performance requirement of the test system is ensured. The bridge chip module 50 identifies the first interface module 30 or the second interface module 40 connected to the host 10, and adjusts the read / write performance of the first interface module 30 or the second interface module 40 to the highest read / write speed through the host 10 according to the read / write performance adjustment command of the host 10. During the reading and writing process of the test data packet between the host 10 and the chip to be tested, for example, the first interface module 30 and the second interface module 40 correspond to two interface protocol types, PCIE and USB, respectively, and utilize their higher read and write performance than the chip to be tested, such as the UFS storage chip. After the connection is achieved through the host 10, the read and write performance of the two interface protocols needs to be adjusted to the highest read and write speed accordingly. For example, the host 10 identifies the hardware versions of the two interface protocols, adapts the driver and firmware updates, and performs corresponding configuration optimization to meet the read and write speed performance test requirements of the chip to be tested.

[0026] See also Figure 2In one embodiment, the bridge chip module 50 includes a central processing unit 51, a memory access unit 52, a memory buffer unit 53 and a protocol conversion unit 54. The memory access unit 52 is used to read the test data packet of the chip under test and write the test data packet of the first interface module 30 and the second interface module 40 to the chip under test; the memory buffer unit 53 is used to receive and store the test data packet read by the memory access unit 52 and the test data packet written; the protocol conversion unit 54 is used to convert the data packet format of the chip under test into the data packet format of the first interface module 30 or the second interface module 40, and convert the data packet format of the first interface module 30 or the second interface module 40 into the data packet format of the chip under test. The central processing unit 51 performs initialization operations on the chip under test loaded in the chip test socket 20, and determines the corresponding read and write speed level according to the specifications of the chip under test. The memory access unit 52 includes a remote direct memory access unit and a write data memory access unit. The remote direct memory access unit reads the test data packet of the chip under test and writes the read test data packet of the chip under test into the memory buffer unit 53. The write data memory access unit writes the test data packet of the first interface module 30 and the second interface module 40 into the memory buffer unit 53.

[0027] Specifically, in an embodiment of the present invention, the central processing unit 51 may be a processor chip using the RISC-V (Reduced Instruction Set Computer - Five, fifth generation simplified instruction set computer) instruction set architecture, which is responsible for the internal configuration management of the entire bridge chip module 50. By using a processor chip using the RISC-V instruction set architecture to manage the data flow of the test system, perform protocol conversion and process control tasks, it can be customized according to the needs of the test system, add or remove instruction set extensions, thereby optimizing performance and power consumption. At the same time, the open source nature of the RISC-V instruction set architecture eliminates the need to pay high license fees, thereby reducing chip costs; it can also be modified and optimized according to the specific needs of the test system, and quickly iterate the design; and it can be compatible with various interfaces and protocols, supporting a variety of application scenarios.

[0028] More specifically, the central processing unit 51 initializes the read and write performance adjustment Tuning for the UFS storage chip identified to be installed on the chip test socket 20, and according to the different specifications SPEC of the storage particles stored in the UFS storage chip, the chip to be tested, that is, the storage chip, can be adjusted and set from its read and write speed level Gear1 to Gear2, Gear3, Gear4 or Gear5, that is, the read and write performance corresponding to the Gear1-Gear5 (gear 1-gear 5) read and write speed levels can be tested respectively.

[0029] In the embodiment of the present invention, the memory access unit 52 implements the read and write operations of the test data packet in the bridge chip module 50 between the first interface module 30 or the second interface module 40 and the chip to be tested through the remote direct memory access unit (RDMA) and the write-data memory access unit (WDMA), and sends the final read and written test data packet to the memory buffer unit 53 (SRAM Buffer). Similarly, the use of the memory buffer unit 53 can make the memory access unit 52 convert different protocols faster, ensuring that the read and write speed can reach the highest speed of the protocol, meeting the test system's requirements for read and write performance testing.

[0030] See also Figure 2 As shown, in an embodiment of the present invention, the bridge chip module 50 also includes a power management unit 56, a serial interface unit 57, a speed indication unit 58 and multiple interface units 55; the power management unit 56 is used for power management of the bridge chip module 50, the serial interface unit 57 is used to output debug log information, the speed indication unit 58 is used to detect the speed of the chip under test after performance adjustment, and the corresponding indication module 60, and the multiple interface units 55 are used to connect to the first interface module 30, the second interface module 40 and the chip test socket 20 respectively.

[0031] See also Figures 1 to 5 In one embodiment, the protocol conversion unit 54 removes the protocol field from the test data packet in the memory buffer unit 53 and retains its original data field, and then packages the original data field to form a new data packet format, so that the test data packet is converted between the data packet format of the chip under test and the data packet format of the first interface module 30 or the second interface module 40. The central processing unit 51 is used to write the test data packet of the first interface module 30 or the second interface module 40 into the memory buffer unit 53 through the write data memory access unit, and convert the test data packet in the data packet format of the first interface module 30 or the second interface module 40 into the data packet format of the chip under test through the protocol conversion unit 54. The central processing unit 51 is used to read the test data packet of the chip under test into the memory buffer unit 53 through the remote direct memory access unit, and convert the data packet format of the chip under test into the data packet format of the first interface module 30 or the second interface module 40 through the protocol conversion unit 54.

[0032] Specifically, in the embodiment of the present invention, the protocol conversion unit 54 (Protocol Conversion-1 / ProtocolConversion-2) includes two parts for bidirectionally converting the test data packet between the data packet format of the first interface module 30 such as the PCIE protocol data packet or the second interface module 40 such as the USB protocol data packet and the data packet format of the chip to be tested such as the UFS protocol data packet. Figures 1 to 5 As shown, the main difference between the data packet formats of the first interface module 30 such as the PCIE protocol data packet, the second interface module 40 such as the USB protocol data packet and the chip under test such as the UFS protocol data packet is that they follow different protocol specifications.

[0033] More specifically, in the attached Figure 3 In the USB protocol data packet format, the data packet format content of the USB protocol data packet may include: packet start SOP (Start - Of - Packet), synchronization SYNC (Synchronization), packet content Packet Content, packet end EOP (End - Of - Packet), packet identifier PID (Packet Identifier), address, frame number, data and cyclic redundancy check CRC (Cyclic Redundancy Check), among which some packet identifiers PID carry addresses, some packet identifiers PID carry frame numbers, and some packet identifiers PID carry data, and their addresses / frame numbers / data do not appear at the same time.

[0034] In the attached Figure 4 In the data packet format of the PCIE protocol data packet, the data packet format content may include: transaction layer data packet TLP (Transaction Layer Packet), start Start, sequence Sequence, header Header, data load DataPayload, end-to-end cyclic redundancy check ECRC (End-to-End Cyclic Redundancy Check), link layer cyclic redundancy check LCRC (Link-layer Cyclic Redundancy Check) and end End. In the field of the transaction layer data packet TLP, the digital unit corresponding to each part of the field is double word DW (Double Word) and byte B (Byte); double word DW usually refers to two adjacent words (Word) in the computer field. It is a data storage unit. The number of bytes is different under different architectures. In a common 32-bit system, 1 double word is 4 bytes (Byte); Byte B is a unit of measurement used by computer information technology to measure storage capacity, and 1 byte is equal to 8 bits (bit).

[0035] In the attached Figure 5 In the data packet format of the UFS protocol data packet, the data packet format content may include: Bit, Byte, Operation Code, Read Protection RDPROTECT, Disable Page Out DPO (Disable Page Out), Force Unit Access FUA (Force Unit Access), Read Attributes Response Command RARC (Read Attributes Response Command), Obsolete, Most Significant Bit MSB (Most Significant Bit), Logical Block Address LOGICAL BLOCK ADDRESS, Least Significant Bit LSB (Least Significant Bit), Reserved, Group Number GROUP NUMBER, Transfer Length TRANSFER LENGTH, and Control CONTROL.

[0036] By combining different definitions of different fields such as the start, address, data, checksum, end, and attributes of these protocol data packets, that is, in the embodiment of the present invention, the test data packets can be understood as the same test data packets between different modules, and whether there are differences in the test data packets needs to be detected and judged by the host 10. In other words, the protocol conversion unit 54 (Protocol Conversion-1) removes the protocol field of the UFS protocol data packet stored in the memory buffer unit 53, retains the original data (DATA), and then packages the corresponding original data into a PCIE protocol data packet or a USB protocol data packet. The protocol conversion unit 54 (Protocol Conversion-2) removes the protocol field of the PCIE protocol data packet or the USB protocol data packet stored in the memory buffer unit 53, retains the original data, and then packages the corresponding original data into a UFS protocol data packet.

[0037] See also Figure 6 The present invention also provides a method for testing a memory chip, comprising: S10, detecting through the bridge chip module 50 whether the first interface module 30 or the second interface module 40 is connected to the host 10, and detecting the chip to be tested loaded into the chip test socket 20; S20, obtaining a test data packet sent by the host 10, converting the test data packet between the data packet format of the first interface module 30 or the second interface module 40 and the data packet format of the chip to be tested through the bridge chip module 50, then writing the converted test data packet to the chip to be tested, then reading out the test data packet written in the chip to be tested, and sending it to the host 10 after converting its data packet format; S30, judging by the host 10 whether the test data packet written by the host 10 to the chip under test through the first interface module 30 or the second interface module 40 and the test data packet sent by the chip under test to the host through the first interface module 30 or the second interface module 40 are consistent with the test data packet written by the host 10, so as to detect the read and write performance of the chip under test; S40, adjusting the read and write performance of the chip under test to different read and write speed levels through the bridge chip module 50, and performing data packet format conversion between the test data packets written from the host 10 to the chip under test and the test data packets sent from the chip under test to the host 10.

[0038] Specifically, in an embodiment of the present invention, the test method of the storage chip is mainly for conversion of different high-speed interface protocols of UFS / USB / PCIE, so as to facilitate the UFS product to use PC-side multi-threading for extreme speed testing. The bridge chip module 50, as the operation and control core in the storage chip test method, is the execution unit for test data packet read and write processing and program running. The bridge chip module 50 can adjust the read and write speed performance of the chip to be tested on the chip test socket 20 and the first interface module 30 and the second interface module 40 according to the instructions of the host 10, and collect the correct rate of data packet format conversion of the test data packet of the chip to be tested under the set read and write speed performance by comparing the written test data packet with the read test data packet. The bridge chip module 50 can be used to detect the read and write performance of the chip to be tested.

[0039] More specifically, in one embodiment of the present invention, step S10 may include a two-part test process. In the first part of the test process, the test system using the test method, namely, a UFS / USB / PCIE protocol adapter card device, corresponds to steps (1)-(3) respectively. Step (1) may be represented as four chip test sockets 20UFS Socket in the UFS / USB / PCIE protocol adapter card device, in which 1 / 2 / 3 / 4 chips to be tested in different combinations, namely, UFS storage particles, can be placed. Step (2) may be represented as the UFS / USB / PCIE protocol adapter card device being inserted into the gold finger interface of the host 10PC end through the first interface module 30, namely, the PCIE interface. Step (3) may be represented as the host 10PC-UI sending a PCIE Tuning command for read / write performance adjustment of the first interface module 30, and after identifying the UFS / USB / PCIE protocol adapter card device, tuning the PCIE to the highest speed, and then jumping to step (9). In the test process of the second part, corresponding to steps (9)-(10), step (9) can be represented as the bridge chip module 50Bridge IC checking whether the first interface module 30 such as PCIE or the second interface module 40 such as USB is inserted into the host 10PC end, and performing tuning with the host 10PC end until the highest speed of PCIE or USB. Step (10) can be represented as the bridge chip module 50Bridge IC power-on initialization, and the central processing unit 51 of the RISC-V instruction set architecture is used to configure the internal module, and send a command to check whether there is a chip to be tested, that is, a UFS storage particle, in the UFS Socket.

[0040] In one embodiment of the present invention, step S20 may include two parts of the test process. In the first part of the test process, the steps (4)-(6) correspond to each other. Step (4) may be represented as the upper-layer software at the PC-UI end of the host 10 sends a write command for a large block of random data, and then the process may jump to step (12). Step (5) may be represented as the upper-layer software at the PC-UI end of the host 10 sends a read command for a large block of random data, and then the process may jump to step (14). Step (6) may be represented as the upper-layer software at the PC-UI end of the host 10 compares the read data with the write data. In the second part of the test process, the steps (12)-(15) correspond to each other. Step (12) may be represented as the test data packet of the host 10 PC-UI passes through the PCIE Interface interface, and then writes the data packet format of the PCIE or the data packet format of the USB into the memory buffer unit 53 SRAM Buffer through the write data memory access unit WDMA in the bridge chip module 50. Step (13) can be represented as the protocol conversion unit 54Protocol Conversion-2 parsing the PCIE data packet format or the USB data packet format, packaging to generate the UFS data packet format, and sending it to the corresponding chip to be tested, that is, the universal flash storage channels 1 / 2 / 3 / 4 (UFS-CH1 / UFS-CH2 / UFS-CH3 / UFS-CH4) installed in the four chip test sockets 20. Step (14) can be represented as the central processing unit 51 using the RISC-V instruction set architecture reading the test data packets stored in the UFS-CH1 / UFS-CH2 / UFS-CH3 / UFS-CH4 installed in the four chip test sockets 20 into the memory unit SRAM Buffer through the remote direct memory access unit RDMA in the bridge chip module 50. Step (15) can be represented as the protocol conversion unit 54Protocol Conversion-1 converting the data packet format of UFS-CH1 / UFS-CH2 / UFS-CH3 / UFS-CH4 installed in the four chip test sockets 20 into the data packet format of PCIE or the data packet format of USB.

[0041] In one embodiment of the present invention, step S30 may include two parts of the test process. In the first part of the test process, they correspond to steps (7)-(8) respectively. Step (7) can be represented as judging whether the comparison between the read data and the written data is consistent through the host 10. If so, it can jump to step (8), otherwise it can jump to step (16). Step (8) can be represented as inserting the UFS / USB / PCIE protocol adapter device into the USB interface of the PC via USB, and then jumping to step (9). In the second part of the test process, they correspond to steps (16)-(17) respectively. Step (16) can be represented as performing data analysis and checking on the comparison error between the read data and the written data in the host 10 as the root cause of the data error, and performing repair verification. Step (17) can be represented as judging whether the problem has been repaired. If so, it can jump to step (3), otherwise it can jump to step (16).

[0042] In one embodiment of the present invention, step S40 may include step (11), which is represented by the central processing unit 51 using the RISC-V instruction set architecture initializing Tuning for the inspected UFS storage chip, and according to the different SPEC specifications of the storage particles in the chip to be tested, the read and write speed level can be selected from Gear1 to Gear2 or Gear3 or Gear4 or Gear5 for adjustment.

[0043] In summary, the present invention provides a test system and test method for a memory chip, by setting the read and write speeds of different protocols, cooperating with the test data packet written by the host to be converted between the data packet formats of different interface protocols and storage protocols, when the test data packet is read and written between the UFS / USB / PCIE protocols, the integrity of the data content in the test data packet is still maintained, that is, the performance reliability of the memory chip under the current read and write speed is indicated, the read and write speed of the read and write performance of the memory chip is controlled by the host, and is increased to a higher read and write speed, and the integrity of the test data packet after reading and writing by the memory chip is judged by the host, thereby determining the read and write performance of the corresponding read and write speed of the chip to be tested. The present invention is simple to operate, highly reusable, and can quickly detect the read and write performance of multiple storage products in different test environments, thereby improving the test efficiency.

[0044] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A memory chip testing system, characterized in that: include: Host; Chip test socket, used to install the chip to be tested; The first interface module and the second interface module are connected to the host and the bridge chip module respectively; A bridge chip module, wherein the bridge chip module is connected to the chip to be tested by connecting to the chip test socket, the bridge chip module obtains a test data packet sent by the host, performs protocol conversion on the test data packet between a data packet format of the chip to be tested and a data packet format of the first interface module or the second interface module, and then writes the converted test data packet to the chip to be tested, and then reads the test data packet in the chip to be tested, converts the data packet format and sends it to the host; Among them, the host determines whether the test data packet sent by the host to the chip under test through the first interface module or the second interface module is consistent with the test data packet sent by the chip under test to the host through the first interface module or the second interface module, so as to detect the read and write performance of the chip under test; the bridge chip module adjusts the read and write performance of the chip under test to different read and write speed levels, and performs data packet format conversion between the test data packet sent from the host to the chip under test and the test data packet sent from the chip under test to the host.

2. The test system according to claim 1, characterized in that: The bridge chip module identifies the first interface module or the second interface module connected to the host, and adjusts the read and write performance of the first interface module or the second interface module to a maximum read and write speed through the host according to a read and write performance adjustment command of the host.

3. The test system according to claim 2, characterized in that: The bridge chip module includes: Central processing unit; A memory access unit, used for reading a test data packet of the chip under test and writing the test data packets of the first interface module and the second interface module into the chip under test; A memory buffer unit, used to receive and store the test data packets read and written by the memory access unit; The protocol conversion unit is used to convert the data packet format of the chip under test into the data packet format of the first interface module or the second interface module, and convert the data packet format of the first interface module or the second interface module into the data packet format of the chip under test.

4. The test system according to claim 3, characterized in that: The central processing unit performs initialization operation on the chip to be tested which is loaded into the chip test socket, and determines the corresponding reading and writing speed level according to the specification of the chip to be tested.

5. The test system according to claim 3, characterized in that: The memory access unit includes a remote direct memory access unit and a write data memory access unit. The remote direct memory access unit reads the test data packet of the chip under test and writes the read test data packet of the chip under test into the memory buffer unit. The write data memory access unit writes the test data packets of the first interface module and the second interface module into the memory buffer unit.

6. The test system according to claim 3, characterized in that: The protocol conversion unit removes the protocol field from the test data packet in the memory buffer unit and retains its original data field, and then packages the original data field to form a new data packet format, so that the test data packet can be converted between the data packet format of the chip under test and the data packet format of the first interface module or the second interface module.

7. The test system according to claim 5, characterized in that: The central processing unit is used to write the test data packet of the first interface module or the second interface module into the memory buffer unit through the write data memory access unit, and convert the data packet format of the first interface module or the second interface module into the data packet format of the chip under test through the protocol conversion unit.

8. The test system according to claim 5, characterized in that: The central processing unit is used to read the test data packet of the chip under test into the memory buffer unit through the remote direct memory access unit, and convert the data packet format of the chip under test into the data packet format of the first interface module or the second interface module through the protocol conversion unit.

9. A method for testing a memory chip, characterized in that: include: Detecting whether the first interface module or the second interface module is connected to the host through the bridge chip module, and detecting the chip to be tested loaded into the chip test socket; Obtaining a test data packet sent by the host, converting the test data packet between the data packet format of the first interface module or the second interface module and the data packet format of the chip to be tested through the bridge chip module, then writing the converted test data packet to the chip to be tested, then reading out the test data packet written to the chip to be tested, and sending it to the host after converting its data packet format; Determining by the host whether a test data packet written by the host to the chip under test through the first interface module or the second interface module is consistent with a test data packet sent by the chip under test to the host through the first interface module or the second interface module, so as to detect the read and write performance of the chip under test; The read and write performance of the chip under test is adjusted to different read and write speed levels through the bridge chip module, and data packet format conversion is performed between the test data packet written from the host to the chip under test and the test data packet sent from the chip under test to the host.

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