Semiconductor device and manufacturing method thereof
By introducing a shallow trench isolation structure and a back gate structure that penetrate the substrate into the semiconductor device, combined with an insulating layer and a contact structure, the problem of wiring path optimization under high integration is solved, achieving faster chip read/write speeds and higher area utilization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2026-04-14
AI Technical Summary
How to improve the speed of semiconductor chips, especially in the case of high integration, is difficult to achieve by effectively optimizing the wiring path to improve read and write speed using existing technologies.
By introducing a shallow trench isolation structure that penetrates the substrate in a semiconductor device and powering the device from the back side of the substrate, the substrate thickness is reduced, and a back gate structure is connected to the gate structure accordingly. Combined with an insulating layer and a contact structure, power can be supplied from the back side to shorten the wiring path.
It achieves shorter wiring paths, improves chip read/write speed and area utilization, and enhances the ability to regulate channel carrier concentration and electric field current.
Smart Images
Figure CN121865684A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] The peripheral circuits in semiconductor devices are formed on complementary metal-oxide-semiconductor (CMOS) wafers. With the development of semiconductor technology, chip integration is becoming increasingly higher. However, improving chip speed remains a key area of research. Summary of the Invention
[0003] The purpose of this disclosure is to provide a semiconductor device and a method for manufacturing the same, so as to improve the speed of a chip.
[0004] To achieve the above objectives, this disclosure provides a semiconductor device including a first semiconductor structure and a pad lead-out structure. The first semiconductor structure includes a substrate, a shallow trench isolation structure, and peripheral circuitry. The substrate has a first side and a second side opposite to each other. The shallow trench isolation structure penetrates the substrate. The peripheral circuitry is disposed on the first side of the substrate. The pad lead-out structure is located on the second side of the substrate.
[0005] In one embodiment of this disclosure, the peripheral circuit includes at least one transistor, the transistor including a gate structure extending from a first side of the substrate; the first semiconductor structure further includes a back gate structure disposed on a second side of the substrate and corresponding to the gate structure.
[0006] In one embodiment of this disclosure, the first semiconductor structure further includes a second contact portion, one end of which is connected to the back gate structure, and the other end of which is connected to the pad lead-out structure.
[0007] In one embodiment of this disclosure, the thickness of the substrate is on the nanometer scale.
[0008] In one embodiment of this disclosure, along a first direction of the substrate, the substrate includes a first sub-substrate and a second sub-substrate, the first sub-substrate and the second sub-substrate having different thicknesses.
[0009] In one embodiment of this disclosure, the first semiconductor structure further includes a first insulating layer, a second insulating layer, an insulating portion, a contact structure, and a first contact portion; the first insulating layer is located on a first side of the substrate, and the second insulating layer is located between the substrate and the pad lead-out structure; the insulating portion penetrates the substrate and extends to the second insulating layer; the contact structure is disposed on the first insulating layer; the first contact portion penetrates the insulating portion, one end of the first contact portion is connected to the pad lead-out structure, and the other end of the first contact portion is connected to the contact structure.
[0010] In one embodiment of this disclosure, a resistive layer is provided between the first contact portion and the contact structure.
[0011] In one embodiment of this disclosure, the shallow trench isolation structure extends to the second insulating layer; the dimensions of the shallow trench isolation structure are the same as the dimensions of the insulating portion along a direction perpendicular to the first side of the substrate.
[0012] In one embodiment of this disclosure, the peripheral circuit includes a first transistor, the first transistor including a gate structure, a first source and a first drain, the gate structure, the first source and the first drain all being led out from a first side of the substrate.
[0013] In one embodiment of this disclosure, the peripheral circuit further includes a second transistor, the second transistor including a gate structure, a second source and a second drain, the gate structure being led out from a first side of the substrate; at least one of the second source and the second drain being led out from a second side of the substrate to be connected to the pad lead-out structure.
[0014] In one embodiment of this disclosure, the peripheral circuitry includes a third transistor, which includes a gate structure, a third source, and a third drain. The gate structure extends from a first side of the substrate, and at least one of the third source and the third drain extends from a second side of the substrate and is connected to the pad lead-out structure.
[0015] In one embodiment of this disclosure, the semiconductor device further includes a second semiconductor structure comprising a memory array located on the side of the peripheral circuit away from the substrate.
[0016] In view of the above objectives, this disclosure also provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a shallow trench isolation structure on a first side of the substrate; forming a peripheral circuit on the first side of the substrate; removing a portion of the substrate to expose the shallow trench isolation structure; and forming a pad lead-out structure on a second side of the substrate.
[0017] In one embodiment of this disclosure, a peripheral circuit is formed on a first side of the substrate, including: a first transistor forming the peripheral circuit on the substrate, the first transistor including a gate structure, a first source, and a first drain; the gate structure, the first source, and the first drain are led out from the first side of the substrate.
[0018] In one embodiment of this disclosure, a peripheral circuit is formed on a first side of the substrate, and the method further includes: a second transistor formed on the substrate, the second transistor including a gate structure, a second source, and a second drain; the gate structure is led out from the first side of the substrate, and at least one of the second source and the second drain is led out from the second side of the substrate.
[0019] In one embodiment of this disclosure, a peripheral circuit is formed on a first side of the substrate, including: a third transistor of the peripheral circuit formed on the substrate, the third transistor including a gate structure, a third source, and a third drain; the gate structure is led out from the first side of the substrate, and at least one of the third source and the third drain is led out from a second side of the substrate.
[0020] In one embodiment of this disclosure, prior to removing a portion of the substrate to expose the shallow trench isolation structure, the method further includes providing a second semiconductor structure, the second semiconductor structure including a memory array, and bonding the memory array to the peripheral circuitry.
[0021] In one embodiment of this disclosure, in the process of removing a portion of the substrate to expose the shallow trench isolation structure, the thickness of the remaining substrate is on the nanometer scale.
[0022] In one embodiment of this disclosure, after removing a portion of the substrate to expose the shallow trench isolation structure, the method further includes forming a back gate structure on a second side of the substrate, the back gate structure corresponding to the gate structure of a transistor in the peripheral circuit.
[0023] In one embodiment of this disclosure, after forming a back gate structure on the second side of the substrate, the method further includes forming a second contact portion, one end of which is connected to the back gate structure, and the other end of which is connected to the pad lead-out structure.
[0024] In one embodiment of this disclosure, after providing the substrate, the method further includes: forming an insulating portion on a first side of the substrate; forming a first insulating layer on the first side of the substrate; and forming a contact structure, one end of which is located within the first insulating layer, and the other end of which extends through the first insulating layer to the side of the substrate away from the substrate.
[0025] In one embodiment of this disclosure, after removing a portion of the substrate to expose the shallow trench isolation structure, the method further includes: forming a second insulating layer on a second side of the retained substrate; forming a first contact portion that penetrates the second insulating layer and the insulating portion and extends to the first insulating layer to connect with the contact structure.
[0026] In one embodiment of this disclosure, after providing the substrate, the method further includes: thinning at least a portion of a region on a first side of the substrate along a first direction of the substrate, such that the substrate includes a first sub-substrate and a second sub-substrate, the first sub-substrate and the second sub-substrate having different thicknesses.
[0027] In one embodiment of this disclosure, after removing a portion of the substrate, the method further includes: thinning at least a portion of a region on a first side of the retained substrate along a first direction of the substrate, such that the substrate includes a first sub-substrate and a second sub-substrate, the first sub-substrate and the second sub-substrate having different thicknesses.
[0028] In one embodiment of this disclosure, before forming a shallow trench isolation structure on the first side of the substrate, the method further includes: injecting hydrogen ions into a plurality of regions within the substrate to form foamed layers in different regions, wherein the plurality of regions are arranged along a first direction of the substrate, and the distance between the foamed layers in two adjacent regions and the first side of the substrate is not equal.
[0029] In one embodiment of this disclosure, a peripheral circuit is formed on a first side of the substrate, including: a plurality of transistors formed on the substrate, at least two transistors being located in different regions of the substrate, the transistors including one or more combinations of a first transistor, a second transistor, and a third transistor.
[0030] In one embodiment of this disclosure, after bonding the memory array to the peripheral circuitry, the method further includes: etching a portion of the shallow trench isolation structure; removing a portion of the substrate to expose a foamed layer in different regions; and removing the foamed layer.
[0031] In one embodiment of this disclosure, after removing the foam layer, the method further includes forming a back gate structure on a second side of the substrate.
[0032] The main beneficial effects of this disclosure are:
[0033] The semiconductor device disclosed herein features a shallow trench isolation structure that penetrates the substrate, ensuring a thin substrate thickness. This enables power supply from the back of the first semiconductor structure, resulting in a short wiring path and improved chip read / write speed.
[0034] The semiconductor device manufacturing method disclosed herein removes part of the substrate to expose a shallow trench isolation structure while ensuring a thin substrate thickness, thereby enabling power supply from the back side of the first semiconductor structure. This results in a short wiring path and improves the chip's read / write speed. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0036] Figure 1 This is a schematic diagram of a first structure of a semiconductor device provided in an embodiment of the present disclosure;
[0037] Figure 2 A schematic diagram of a second structure of a semiconductor device provided in an embodiment of this disclosure (only the first semiconductor structure is shown);
[0038] Figure 3 A schematic diagram of a third structure of a semiconductor device provided in an embodiment of this disclosure (only the first semiconductor structure is shown);
[0039] Figure 4 A fourth structural schematic diagram of a semiconductor device provided in an embodiment of this disclosure (only the first semiconductor structure is shown);
[0040] Figure 5 A fifth structural schematic diagram of a semiconductor device provided in the embodiments of this disclosure (only the first semiconductor structure is shown);
[0041] Figure 6 A sixth structural schematic diagram of a semiconductor device provided in the embodiments of this disclosure (only the first semiconductor structure is shown);
[0042] Figure 7 A seventh structural schematic diagram of a semiconductor device provided in an embodiment of this disclosure;
[0043] Figure 8 A schematic diagram of an eighth structure of a semiconductor device provided in this disclosure (pad lead-out structure not shown);
[0044] Figure 9 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;
[0045] Figures 10 to 34 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation
[0046] The technical solutions of this disclosure will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0047] Generally, terms can be understood, at least in part, based on their use in context. For example, the term "one or more," depending at least in part on the context, can be used to describe any feature, structure, or characteristic in the singular, or in the plural, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a" or "described" in this document can also be understood, at least in part on the context, to convey either a singular or plural usage. Furthermore, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again, depending at least in part on the context.
[0048] It should be readily understood that, in the description of this disclosure, it is necessary to clarify that the meanings of “on,” “above,” and “above” should be interpreted in the broadest sense, such that “on” not only means “directly on” something, but also includes the meaning of being “on” something with an intermediate feature or layer between them. Furthermore, “above” or “above” not only means “on” or “above” something, but can also include it being “on” or “above” something without an intermediate feature or layer between them (i.e., directly on something).
[0049] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "below," "lower layer," "above," "upper layer," etc., to describe the relationship between one element or feature and another element or feature as shown in the figure. Spatially related terms are intended to include different orientations of the device in use or process steps (in addition to the orientation shown in the figure). The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted accordingly.
[0050] In the description of this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. A substrate includes a front side and a back side. The front side of the substrate is typically where a semiconductor device is formed; unless otherwise stated, the semiconductor device is formed on the front side of the substrate, and the back side is opposite to the front side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0051] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend integrally over the structure of a bottom or upper layer, or may have a range smaller than that of the bottom or upper layer. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect pathways are formed) and one or more dielectric layers.
[0052] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.
[0053] See Figures 1 to 8 As shown, this embodiment provides a semiconductor device, including a first semiconductor structure 10 and a pad lead-out structure 30. The first semiconductor structure 10 includes a substrate 11, a shallow trench isolation structure 17 and peripheral circuits. The substrate has a first side and a second side opposite to each other. The shallow trench isolation structure 17 penetrates the substrate, and the peripheral circuits are disposed on the first side of the substrate. The pad lead-out structure 30 is located on the second side of the substrate.
[0054] It should be understood that the first side of the substrate 11 can be the front side and the second side can be the back side.
[0055] The semiconductor device provided in this embodiment has a shallow trench isolation structure 17 that penetrates the substrate, ensuring that the substrate is relatively thin. This enables power supply from the back of the first semiconductor structure, resulting in a short wiring path, which is beneficial for improving the read / write speed of the chip and the area utilization of the semiconductor device.
[0056] The substrate 11 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or any other suitable material.
[0057] In some embodiments, the peripheral circuitry may include at least one of a row decoder, a column decoder, a control circuit, an input / output buffer, a state machine, and a static random access memory. For example, the peripheral circuitry may be a CMOS (Complementary Metal Oxide Semiconductor) circuit.
[0058] In this embodiment, the thickness of the substrate is on the nanometer scale. For example, the thickness of the substrate is less than 200 nm.
[0059] The nanoscale substrate in this embodiment has the excellent performance of silicon-on-insulator (SOI) devices, which helps to reduce the short-channel effect.
[0060] In one embodiment, the peripheral circuit includes at least one transistor, the transistor including a gate structure extending from a first side of the substrate; the first semiconductor structure 10 further includes a back gate structure 19 disposed on a second side of the substrate and corresponding to the gate structure.
[0061] In this embodiment, a horizontal transistor is used as an example. Each horizontal transistor has a shallow trench isolation structure 17 on both sides to separate adjacent transistors.
[0062] When the peripheral circuit includes multiple transistors, in order to clearly describe the technical solution of this embodiment, the different transistors are numbered sequentially, for example, the first transistor, the second transistor, and the third transistor.
[0063] Since the substrate thickness is on the nanometer scale, the channel carrier concentration and electric field current of the semiconductor device can be adjusted through the back gate structure 19. Furthermore, each transistor's gate structure corresponds to a back gate structure 19, enhancing independent control capability.
[0064] In some embodiments, see Figure 1 As shown, the peripheral circuit includes a first transistor 121, which includes a gate structure, a first source 1212 and a first drain 1213. The gate structure, the first source 1212 and the first drain 1213 are all led out from the first side of the substrate 11.
[0065] To clearly describe the technical solution of this embodiment, the gate structure in the first transistor 121 is named the first gate structure 1211.
[0066] For example, the first gate structure 1211 is located on the first side of the substrate, the first source 1212 and the first drain 1213 are both located inside the substrate 11, and the first source 1212 and the first drain 1213 are respectively located on both sides of the first gate structure 1211.
[0067] In one embodiment, see Figure 1 As shown, the first semiconductor structure 10 further includes a first insulating layer 131, a second insulating layer 132, an insulating portion 15, a contact structure 14, and a first contact portion 16; the first insulating layer 131 is located on a first side of the substrate, and the second insulating layer 132 is located between the substrate and the pad lead-out structure 30; the insulating portion 15 penetrates the substrate and extends to the second insulating layer 132; the contact structure 14 is disposed on the first insulating layer 131; the first contact portion 16 penetrates the insulating portion 15, one end of the first contact portion 16 is connected to the pad lead-out structure 30, and the other end of the first contact portion 16 is connected to the contact structure 14.
[0068] For example, see Figure 18 As shown, the first contact hole 160 and the third contact hole (not shown) can be formed using, for example, dry or wet etching processes. The third contact hole is formed within the first insulating layer 131, and the first contact hole 160 penetrates the second insulating layer 132 and a portion of the first insulating layer 131. Conductive material is filled into the third contact hole to form a contact structure 14, and conductive material is filled into the first contact hole to form a first contact portion 16. The conductive material can be, but is not limited to, copper, aluminum, and tungsten.
[0069] See Figure 1 As shown, the first insulating layer 131 includes Figure 1 The blank portion marked 131 and the portion filled with double diagonal lines above the blank portion are formed in different processes, and the materials are usually the same. For example, the material of the first insulating layer 131 can be silicon oxide.
[0070] The first semiconductor structure 10 also includes lead-out structures 104 and a first metal layer 101 located within the first insulating layer 131. Multiple lead-out structures 104 are included. A first gate structure 1211, a first source 1212, and a first drain 1213 are respectively connected to one end of each lead-out structure 104. The other end of each lead-out structure 104 is connected to the first metal layer 101. The first metal layer 101 is connected to a contact structure 14. Backside power supply is achieved through the connection of the pad lead-out structure 30, the first contact portion 16, the contact structure 14, and the first metal layer 101 to the first transistor 121, thereby controlling the first transistor. This structure features a short power supply path and fast chip read / write speed.
[0071] In one embodiment, a resistive layer 141 is provided between the first contact portion 16 and the contact structure 14. The presence of the resistive layer 141 ensures that the etching of the first contact hole 160 can proceed normally.
[0072] The resistive layer 141 is very thin, and it may be penetrated when fabricating the first contact hole corresponding to the first contact portion 16. However, whether or not the resistive layer 141 is penetrated, it will not affect the overall conductivity. For example, the material of the resistive layer 141 can be titanium nitride.
[0073] In one embodiment, see Figure 1 As shown, the first semiconductor structure 10 further includes a second contact portion 18, one end of which is connected to the back gate structure 19, and the other end of which is connected to the pad lead-out structure 30. The second contact portion 18 is formed on the second insulating layer 132.
[0074] For example, a dry or wet etching process can be used to form the second contact hole 180 within the second insulating layer 132, and a conductive material can be filled into the second contact hole 180 to form the second contact portion 18. For example, the conductive material can be, but is not limited to, copper, aluminum, tungsten, or other suitable conductive materials.
[0075] In some embodiments, the conductive materials in the first contact portion 16, the second contact portion 18, and the contact structure 14 may be the same.
[0076] In one embodiment, the shallow trench isolation structure 17 extends to the second insulating layer 132; the dimensions of the shallow trench isolation structure 17 are the same as the dimensions of the insulating portion 15 along a direction perpendicular to the first side of the substrate 11.
[0077] Shallow trenches 170 and grooves 150 are formed on the first side of the substrate. The depth of the shallow trenches 170 and the depth of the grooves 150 are equal, allowing for simultaneous etching and reducing production costs. Then, oxides are deposited into the shallow trenches 170 and the grooves 150 to form shallow trench isolation structures 17 and insulating portions 15, respectively.
[0078] In one embodiment, the semiconductor device further includes a second semiconductor structure 20, which includes a memory array 21 located on the side of the peripheral circuit away from the substrate.
[0079] The memory array and peripheral circuits are set on different chips. The peripheral circuits do not occupy the area of the chip on which the memory array is located. Therefore, the memory array can be set on the entire chip, which is beneficial to improve the efficiency of the memory array, that is, to increase the proportion of chip area occupied by the memory array.
[0080] In some embodiments, the peripheral circuitry further includes a second transistor 122, which includes a gate structure, a second source 1222, and a second drain 1223. The gate structure is led out from a first side of the substrate. At least one of the second source 1222 and the second drain 1223 is led out from a second side of the substrate to be connected to the pad lead-out structure 30.
[0081] To clearly describe the technical solution of this embodiment, the gate structure in the second transistor 122 is named the second gate structure 1221.
[0082] See Figure 2 As shown, the second source 1222 and the second drain 1223 are both led out from the second side of the substrate 11 to connect with the pad lead-out structure 30. Exemplarily, the second gate structure 1221 is located on the first side of the substrate, the second source 1222 and the second drain 1223 are both located within the substrate 11, and the second source 1222 and the second drain 1223 are respectively located on both sides of the second gate structure 1221.
[0083] When there are multiple first transistors and multiple second transistors, the multiple first transistors can be interconnected, and the multiple second transistors can be interconnected; the pad lead-out structure is directly connected to the device port. In this case, it is not necessary to provide the insulating part 15, the contact structure 14, and the first contact part 16. Of course, see [reference needed]. Figure 3 As shown, an insulating part 15, a contact structure 14, and a first contact part 16 can also be provided, depending on the circuit connection.
[0084] It should be noted that, Figure 2 and Figure 3 The second semiconductor structure and the pad lead-out structure are not shown in the diagram.
[0085] In some embodiments, see Figure 4 and Figure 5 As shown, the peripheral circuit includes a third transistor 123, which includes a gate structure, a third source 1232 and a third drain 1233. The gate structure is led out from the first side of the substrate, and at least one of the third source 1232 and the third drain 1233 is led out from the second side of the substrate and connected to the pad lead-out structure 30.
[0086] To clearly describe the technical solution of this embodiment, the gate structure in the third transistor 123 is named the third gate structure 1231.
[0087] In some embodiments, one of the third source 1232 and the third drain 1233 is led out from the second side of the substrate 11 to connect with the pad lead-out structure 30, and the other is led out from the first side of the substrate 11. See, for example... Figure 4As shown, the third source 1232 is led out from the second side of the substrate, and the third drain 1233 is led out from the first side of the substrate.
[0088] When there are multiple third transistors, they can be interconnected either on the front or the back. The pad lead-out structure is directly connected to the device port. In this case, it is not necessary to set up the insulating part 15, the contact structure 14, and the first contact part 16. Of course, see [reference needed]. Figure 5 As shown, an insulating part 15, a contact structure 14, and a first contact part 16 can also be provided, depending on the circuit connection.
[0089] It should be noted that, Figure 4 and Figure 5 The second semiconductor structure and the pad lead-out structure are not shown in the diagram.
[0090] In other embodiments, see Figure 6 As shown, the third source 1232 and the third drain 1233 are both led out from the second side of the substrate 11. The pad lead-out structure is directly connected to the device port. In this case, it is not necessary to set the insulating part 15, the contact structure 14 and the first contact part 16. Of course, the insulating part 15, the contact structure 14 and the first contact part 16 can also be set, depending on the circuit connection.
[0091] For example, Figure 6 Two third transistors 123 are shown in the figure.
[0092] In some embodiments, see Figure 7 and Figure 8 As shown, along a first direction of the substrate (indicated by arrow direction D1), the substrate includes a first sub-substrate 111 and a second sub-substrate 112. The first sub-substrate 111 and the second sub-substrate 112 have different thicknesses, which allows them to accommodate different operating voltages. For example, the thickness of the first sub-substrate 111 is less than the thickness of the second sub-substrate 112. When a voltage is applied to a transistor, a low voltage can be applied to the transistor on the first sub-substrate 111, and a high voltage can be applied to the transistor on the second sub-substrate 112. The thickness of the first sub-substrate 111 is the dimension of the first sub-substrate 111 along arrow direction D2, and the thickness of the second sub-substrate 112 is the dimension of the second sub-substrate 112 along arrow direction D2.
[0093] For example, there are several ways to achieve different thicknesses for the first sub-substrate 111 and the second sub-substrate 112. For instance, the original substrate with a larger thickness can be etched or photolithographically processed to form the first sub-substrate 111 and the second sub-substrate 112 with different thicknesses.
[0094] For example, after thinning the second side of the substrate, the thinned substrate can be etched or photolithographically processed to form a first sub-substrate 111 and a second sub-substrate 112 with different thicknesses.
[0095] For example, a first sub-substrate 111 and a second sub-substrate 112 with different thicknesses can also be formed by hydrogen ion implantation.
[0096] See Figure 9 As shown, this embodiment also provides a method for manufacturing a semiconductor device, which may include the following steps:
[0097] Step S902, provide a substrate;
[0098] Step S904: A shallow trench isolation structure 17 is formed on the first side of the substrate;
[0099] Step S906: Form a peripheral circuit on the first side of the substrate;
[0100] Step S908: Remove part of the substrate to expose the shallow trench isolation structure 17;
[0101] Step S9010: Form a pad lead-out structure 30 on the second side of the substrate.
[0102] The semiconductor device manufacturing method provided in this embodiment removes part of the substrate to expose the shallow trench isolation structure 17, and can ensure that the substrate thickness is relatively thin, thereby enabling power supply from the back of the first semiconductor structure. The wiring path is short, which is beneficial to improving the read and write speed of the chip and the area utilization of the semiconductor device.
[0103] It should be understood that, Figure 9 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 9 The steps shown can be adjusted in order according to actual needs. Figures 10 to 34 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. The following is in conjunction with... Figure 9 , Figures 10 to 34 The method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be described in detail.
[0104] In step S902, the provided substrate 11' may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or any other suitable material. The thickness of the substrate 11' is greater than the thickness of the substrate 11 in the ultimately formed semiconductor device.
[0105] The substrate 11' has a first side and a second side, the first side of which can be the front side and the second side can be the back side.
[0106] In step S904, a shallow trench isolation structure 17 is formed on the first side of the substrate 11'. (See also...) Figure 10 As shown, at least two shallow trenches 170 are formed on the first side of the substrate 11', and the two shallow trenches 170 have the same depth. See also Figure 11 As shown, oxides are deposited into the shallow trench 170 to form a shallow trench isolation structure 17.
[0107] For example, the oxide can be silicon oxide.
[0108] In some exemplary processes following step S902, an insulating portion 15 is also formed on a first side of the substrate 11'.
[0109] In some embodiments, to simplify the process and reduce costs, in solutions requiring the fabrication of the insulating portion 15, a groove 150 can be formed simultaneously on the first side of the substrate 11'. See also Figure 12 As shown, the depth of groove 150 is equal to the depth of shallow trench 170. See also Figure 13 As shown, oxide is deposited simultaneously in shallow trenches 170 and recesses 150. Exemplarily, the oxide in recesses 150 is the same as the oxide in shallow trenches 170, so that it can be formed using the same process.
[0110] In some exemplary processes following step S902, the process further includes forming a first insulating layer 131 on a first side of the substrate 11'.
[0111] For example, the method of forming the first insulating layer 131 may be one or a combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and electroplating processes.
[0112] See Figure 14 As shown, after the first insulating layer 131 is formed on the first side of the substrate 11', step S906 is performed.
[0113] In step S906, a peripheral circuit is formed on the first side of the substrate, including: a first transistor 121 on the substrate, the first transistor 121 including a first gate structure 1211, a first source 1212 and a first drain 1213; wherein the first gate structure 1211, the first source 1212 and the first drain 1213 are led out from the first side of the substrate.
[0114] For example, a doped region is first formed in the substrate 11'. Along the thickness direction of the substrate 11', the doped region extends from the first side of the substrate towards the direction closer to the second side. Along the thickness direction of the substrate 11', the size of the doped region is smaller than the size of the shallow trench isolation structure 17. The first gate structure 1211 is located in the first insulating layer 131. The first source 1212 and the first drain 1213 are both located in the doped region, and the first source 1212 and the first drain 1213 are respectively located on both sides of the first gate structure 1211.
[0115] A lead-out structure 104 is formed in the first insulating layer 131, such that the first gate structure 1211, the first source 1212 and the first drain 1213 are led out from the first side of the substrate.
[0116] Since the first gate structure 1211, the first source 1212 and the first drain 1213 are led out from the first side of the substrate, a contact structure 14 needs to be formed to facilitate the subsequent connection of the back-side power supply with the first transistor 121.
[0117] Specifically, a resistive layer 141 can be formed first, and the material of the resistive layer 141 can be titanium nitride. Then, a third contact hole is formed, which penetrates the side of the first insulating layer 131 away from the substrate and extends to the resistive layer 141. Conductive material is deposited into the third contact hole to form a contact structure 14.
[0118] In some exemplary processes following step S906, the process further includes forming a first metal layer 101 and a first bonding structure 103.
[0119] See Figure 15 As shown, the first gate structure 1211, the first source 1212, the first drain 1213, and the contact structure 14 of the first transistor 121 are all connected to the first metal layer 101, and the first bonding structure is connected to the first metal layer 101.
[0120] It should be understood that the wiring layout of the first metal layer 101 is arranged according to the actual situation.
[0121] In some exemplary processes following step S906, the process further includes: providing a second semiconductor structure 20, the second semiconductor structure 20 including a memory array 21, and bonding the memory array 21 to peripheral circuitry.
[0122] For example, see Figure 16As shown, the second semiconductor structure includes a second bonding structure 22, which is bonded to the first bonding structure 103. Exemplary bonding methods such as hybrid bonding, anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding can be used to bond the first semiconductor structure 10 and the second semiconductor structure 20.
[0123] In some embodiments, in the process of removing a portion of the substrate to expose the shallow trench isolation structure 17, the thickness of the remaining substrate is in the nanometer range.
[0124] Specifically, the thickness of the doped region can be controlled at the nanometer level, see [reference]. Figure 17 As shown, when removing part of the substrate, the undoped part can be removed, and the doped part forms substrate 11, which is the substrate that is retained.
[0125] For example, the thickness of substrate 11 is less than 200 nm.
[0126] The nanoscale substrate in this embodiment has the excellent performance of silicon-on-insulator (SOI) devices, which helps to reduce the short-channel effect.
[0127] See Figure 18 As shown, some exemplary processes after removing a portion of the substrate to expose the shallow trench isolation structure 17 also include forming a back gate structure 19 on a second side of the substrate 11, the back gate structure 19 corresponding to the gate structure of a transistor in the peripheral circuit.
[0128] Specifically, a second insulating layer 132 is first formed on the second side of the retained substrate 11. For example, an oxide layer is deposited on the second side of the retained substrate 11, and a dielectric layer is deposited on the oxide layer. The dielectric layer and the oxide layer together form the second insulating layer 132. A straight trench is formed in the dielectric layer, and electrode material is deposited in the straight trench to form a back gate structure 19.
[0129] For example, the method of forming the second insulating layer 132 may be one or a combination of CVD, PVD, ALD and electroplating processes.
[0130] The material of the dielectric layer can be, but is not limited to, tetraethyl orthosilicate (TEOS).
[0131] It should be understood that chemical mechanical polishing can be performed after the electrode material is deposited.
[0132] See also Figure 18As shown, some exemplary processes after forming the back gate structure 19 on the second side of the substrate 11 further include: forming a first contact portion 16, which penetrates the second insulating layer 132 and the insulating portion 15 and extends to the first insulating layer 131 to connect with the contact structure 14; forming a second contact portion 18, one end of which is connected to the back gate structure 19 and the other end of which is connected to the pad lead-out structure 30.
[0133] Specifically, after forming the back gate structure 19, a dielectric layer (e.g., TEOS) is deposited, which can also be understood as part of the second insulating layer. Then, a first contact hole 160 and a second contact hole 180 can be formed in the dielectric layer using, for example, a dry or wet etching process. The first contact hole 160 penetrates the second insulating layer 132 and the insulating portion 15, and extends to the first insulating layer 131. The second contact hole 180 penetrates the second insulating layer 132 and extends to the back gate structure 19.
[0134] See Figure 19 As shown, conductive material is deposited into the first contact hole 160 and the second contact hole 180 to form the first contact portion 16 and the second contact portion 18, respectively.
[0135] It should be noted that before depositing conductive material into the first contact hole 160 and the second contact hole 180, an adhesive layer (not shown in the figure) can be formed on the inner wall of the first contact hole 160 and the second contact hole 180. The adhesive layer can be made of materials such as titanium nitride to increase the adhesion between the conductive material and the second insulating layer 132 and the insulating part 15.
[0136] After the first contact portion 16 and the second contact portion 18 are formed, a second metal layer 102 is formed. The second metal layer 102 can be a single layer or multiple layers. For example, in this embodiment, the second metal layer 102 has two layers.
[0137] In step S9010, a pad lead-out structure 30 is formed on the second side of the substrate. The formed structure can be found in [reference needed]. Figure 1 .
[0138] Depending on the structure of the transistors in the peripheral circuit, an adaptive adjustment will be made in step S906.
[0139] For example, step S906 further includes: forming a second transistor 122 with peripheral circuitry on the substrate, see [reference]. Figure 3As shown, the second transistor 122 includes a second gate structure 1221, a second source 1222, and a second drain 1223; the second gate structure 1221 is led out from the first side of the substrate 11', and the second source 1222 and the second drain 1223 are both led out from the second side of the substrate 11'. Of course, it is also possible that only one of the second source 1222 and the second drain 1223 is led out from the second side of the substrate 11'.
[0140] It should be understood that the second source 1222 and / or the second drain 1223 extending from the second side of the substrate 11' are typically fabricated after the second insulating layer 132 is formed. For example, the second source 1222 and / or the second drain 1223 extending from the second side of the substrate 11' may be formed before the back gate structure is formed.
[0141] When the peripheral circuit includes the second transistor 122, the pad lead-out structure can be directly connected to the device port. See [link / reference needed]. Figure 2 As shown, at this time, the fabrication of the insulating part 15, the contact structure 14, and the first contact part 16 can be omitted. That is, in step S904, see... Figure 10 and Figure 11 As shown, it is not necessary to form the groove 150 at the same time, nor is it necessary to form the insulating part 15.
[0142] For example, step S906 includes: forming a third transistor 123 of the peripheral circuit on the substrate, see [reference]. Figure 5 As shown, the third transistor 123 includes a third gate structure 1231, a third source 1232 and a third drain 1233; the third gate structure is led out from the first side of the substrate 11', and at least one of the third source and the third drain is led out from the second side of the substrate 11'.
[0143] For example, the third source is led out from the second side of the substrate 11', and the third drain 1233 is led out from the first side of the substrate.
[0144] When the peripheral circuit includes the third transistor 123, the pad lead structure can be directly connected to the device port. See [link / reference] Figure 4 As shown, at this time, the fabrication of the insulating part 15, the contact structure 14 and the first contact part 16 can also be omitted.
[0145] When the peripheral circuit includes multiple transistors, the peripheral circuit is formed on the first side of the substrate, including: multiple transistors forming the peripheral circuit on the substrate, the transistors including one or more combinations of a first transistor 121, a second transistor 122 and a third transistor 123.
[0146] For example, the peripheral circuit may include a plurality of first transistors, or at least one first transistor and at least one second transistor, and may also include a plurality of third transistors.
[0147] When the peripheral circuit includes multiple transistors, regions of different thicknesses can be formed in the substrate along the first direction of the substrate 11' to accommodate different operating voltages. For example, along the first direction of the substrate 11, the substrate includes a first sub-substrate 111 and a second sub-substrate 112, where the thickness of the first sub-substrate 111 is less than the thickness of the second sub-substrate 112. When a voltage is applied to the transistors, a low voltage can be applied to the transistors on the first sub-substrate 111, and a high voltage can be applied to the transistors on the second sub-substrate 112.
[0148] For example, there are several ways to achieve different thicknesses for the first sub-substrate 111 and the second sub-substrate 112. Three of these methods will be described below.
[0149] In some implementations, see Figure 20 As shown, in some exemplary processes after providing substrate 11', the process further includes: thinning at least a portion of a region on a first side of substrate 11' along a first direction of substrate 11', such that substrate 11' includes a first sub-substrate 111 and a second sub-substrate 112, the first sub-substrate 111 and the second sub-substrate 112 having different thicknesses.
[0150] When fabricating transistors, at least two transistors are located in different regions of the substrate.
[0151] For example, see Figure 21 As shown, two first transistors 121 are shown, one of which is located on a first sub-substrate 111 and the other is located on a second sub-substrate 112.
[0152] For example, the thickness of the first sub-substrate 111 is less than the thickness of the second sub-substrate 112. When applying a voltage to the two first transistors, a low voltage can be applied to the first transistor on the first sub-substrate 111 and a high voltage can be applied to the first transistor on the second sub-substrate 112.
[0153] In some implementations, see Figure 22 As shown, after removing part of the substrate, the method further includes: thinning at least a portion of a region on the first side of the retained substrate along a first direction of the substrate, so that the substrate includes a first sub-substrate 111 and a second sub-substrate 112, the first sub-substrate 111 and the second sub-substrate 112 having different thicknesses.
[0154] In some implementations, see Figures 23 to 34 As shown, a first sub-substrate 111 and a second sub-substrate 112 with different thicknesses can also be formed by hydrogen ion implantation.
[0155] Specifically, some exemplary processes prior to forming the shallow trench isolation structure 17 on the first side of the substrate further include: injecting hydrogen ions into multiple regions within the substrate 11' to form foamed layers 113 in different regions, wherein the multiple regions are arranged along a first direction of the substrate and the distance between the foamed layers 113 in two adjacent regions and the first side of the substrate is not equal.
[0156] See Figure 23 As shown, before injecting hydrogen ions into multiple regions within the substrate 11', the method further includes depositing an oxide layer on a first side of the substrate 11'.
[0157] See Figure 24 As shown, hydrogen ions can be implanted into different regions of the substrate using an ion implantation process to form foamed layers 113 in different regions, and the distances between the foamed layers 113 in two adjacent regions and the first side of the substrate are not equal.
[0158] For example, the substrate includes two regions arranged along a first direction.
[0159] In some exemplary processes following the implantation of hydrogen ions into multiple regions within the substrate 11', the process further includes forming multiple shallow trench groups on a first side of the substrate, each shallow trench group including two shallow trenches 170. Grooves 150 may also be formed simultaneously, if desired.
[0160] Figure 25 for Figure 24 Top view, Figure 26 for Figure 25 A cross-sectional view along line AA. See, for example, [link to example]. Figure 25 and Figure 26 As shown, two shallow trench groups are formed on the first side of the substrate. Two shallow trenches in one shallow trench group penetrate the foam layer 113 in one region, and two shallow trenches in the other shallow trench group penetrate the foam layer 113 in another region.
[0161] See Figure 27 As shown, oxides are deposited into all the shallow trenches 170 and grooves 150 to form the shallow trench isolation structure 17 and the insulating portion 15.
[0162] A doped region is formed in the substrate along the thickness direction of the substrate 11'. The doped region extends from the first side of the substrate toward the direction closer to the second side. The size of the doped region along the thickness direction of the substrate 11' can be larger than the size of the shallow trench isolation structure 17.
[0163] See Figure 28 As shown, a first transistor 121 and a corresponding lead-out structure 104 are formed in two regions respectively.
[0164] See Figure 29 As shown, a first metal layer 101 and a first bonding structure 103 are formed.
[0165] See Figure 30 As shown, the peripheral circuit in the first semiconductor structure 10 is bonded to the memory array in the second semiconductor structure 20 through the first bonding structure 103 and the second bonding structure 22.
[0166] See Figure 31 As shown, some exemplary processes after bonding the memory array 21 to the peripheral circuitry also include: etching a portion of the shallow trench isolation structure 17; and removing a portion of the substrate to expose the foamed layer 113 in different areas.
[0167] Specifically, etching a portion of the shallow trench isolation structure 17 includes: removing undoped portions of the substrate 11', then performing chemical mechanical polishing to expose the surface of the shallow trench isolation structure 17, and then etching a portion of the shallow trench isolation structure 17. For example, along the thickness direction of the substrate, the size of the shallow trench isolation structure 17 retained after etching is smaller than the minimum distance between the foamed layer 113 and the first side of the substrate.
[0168] See Figure 32 As shown, the foam layer 113 can be removed by wet etching.
[0169] See Figure 33 As shown, some exemplary processes after removing the foam layer 113 also include forming a back gate structure 19 on a second side of the substrate.
[0170] In some exemplary processes following the formation of the back gate structure 19 on the second side of the substrate 11, the process further includes: forming a first contact portion 16, which penetrates the second insulating layer 132 and the insulating portion 15 and extends to the first insulating layer 131 to connect with the contact structure 14; and forming a second contact portion 18, one end of which is connected to the back gate structure 19.
[0171] It should be noted that the process of forming the back grid structure 19, the first contact portion 16 and the second contact portion 18 has been described previously and will not be repeated here.
[0172] See Figure 34 As shown, a pad lead-out structure 30 is formed on the second side of the substrate, and the pad lead-out structure 30 is connected to the other end of the second contact portion 18.
[0173] It should be noted that the semiconductor device provided in this embodiment can be manufactured using the semiconductor device manufacturing method provided in this embodiment.
[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A semiconductor device, characterized in that, include: A first semiconductor structure includes a substrate, a shallow trench isolation structure, and peripheral circuitry. The substrate has a first side and a second side opposite to each other. The shallow trench isolation structure penetrates the substrate, and the peripheral circuitry is disposed on the first side of the substrate. as well as A pad lead-out structure; the pad lead-out structure is located on the second side of the substrate.
2. The semiconductor device according to claim 1, characterized in that, The peripheral circuit includes at least one transistor, the transistor including a gate structure extending from a first side of the substrate; The first semiconductor structure further includes a back gate structure, which is disposed on the second side of the substrate and corresponds to the gate structure.
3. The semiconductor device according to claim 2, characterized in that, The first semiconductor structure further includes a second contact portion, one end of which is connected to the back gate structure, and the other end of which is connected to the pad lead-out structure.
4. The semiconductor device according to claim 1, characterized in that, The thickness of the substrate is in the nanometer range.
5. The semiconductor device according to claim 1, characterized in that, Along a first direction of the substrate, the substrate includes a first sub-substrate and a second sub-substrate, the first sub-substrate and the second sub-substrate having different thicknesses.
6. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes a first insulating layer, a second insulating layer, an insulating portion, a contact structure, and a first contact portion; the first insulating layer is located on a first side of the substrate, and the second insulating layer is located between the substrate and the pad lead-out structure; The insulating portion penetrates the substrate and extends to the second insulating layer; the contact structure is disposed on the first insulating layer; the first contact portion penetrates the insulating portion, one end of the first contact portion is connected to the pad lead-out structure, and the other end of the first contact portion is connected to the contact structure.
7. The semiconductor device according to claim 6, characterized in that, A resistive layer is provided between the first contact portion and the contact structure.
8. The semiconductor device according to claim 7, characterized in that, The shallow trench isolation structure extends to the second insulating layer; along a direction perpendicular to the first side of the substrate, the dimensions of the shallow trench isolation structure are the same as the dimensions of the insulating portion.
9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The peripheral circuit includes a first transistor, which includes a gate structure, a first source, and a first drain, all of which are led out from a first side of the substrate.
10. The semiconductor device according to claim 9, characterized in that, The peripheral circuit also includes a second transistor, which includes a gate structure, a second source, and a second drain. The gate structure is led out from a first side of the substrate. At least one of the second source and the second drain is led out from a second side of the substrate to connect to the pad lead-out structure.
11. The semiconductor device according to any one of claims 1 to 8, characterized in that, The peripheral circuit includes a third transistor, which includes a gate structure, a third source, and a third drain. The gate structure is led out from a first side of the substrate, and at least one of the third source and the third drain is led out from a second side of the substrate and connected to the pad lead-out structure.
12. The semiconductor device according to any one of claims 1 to 8, characterized in that, It also includes a second semiconductor structure, which includes a memory array located on the side of the peripheral circuit away from the substrate.
13. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; A shallow trench isolation structure is formed on the first side of the substrate; A peripheral circuit is formed on the first side of the substrate; Part of the substrate is removed to expose the shallow trench isolation structure; A pad lead-out structure is formed on the second side of the substrate.
14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, A peripheral circuit is formed on the first side of the substrate, including: A first transistor of the peripheral circuit is formed on the substrate, the first transistor including a gate structure, a first source and a first drain; The gate structure, the first source, and the first drain are led out from a first side of the substrate.
15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The peripheral circuit is formed on the first side of the substrate, and the circuit also includes: A second transistor of the peripheral circuit is formed on the substrate, the second transistor including a gate structure, a second source, and a second drain; The gate structure is led out from a first side of the substrate, and at least one of the second source and the second drain is led out from a second side of the substrate.
16. The method for manufacturing a semiconductor device according to claim 13, characterized in that, A peripheral circuit is formed on the first side of the substrate, including: A third transistor of the peripheral circuit is formed on the substrate, the third transistor including a gate structure, a third source, and a third drain; The gate structure is led out from a first side of the substrate, and at least one of the third source and the third drain is led out from a second side of the substrate.
17. The method for manufacturing a semiconductor device according to any one of claims 13 to 16, characterized in that, Before removing a portion of the substrate to expose the shallow trench isolation structure, the process also includes: A second semiconductor structure is provided, the second semiconductor structure including a memory array, and the memory array is bonded to the peripheral circuitry.
18. A method for manufacturing a semiconductor device according to any one of claims 13 to 16, characterized in that, In the process of removing part of the substrate to expose the shallow trench isolation structure, the thickness of the remaining substrate is on the nanometer scale.
19. A method for manufacturing a semiconductor device according to any one of claims 13 to 16, characterized in that, After removing part of the substrate to expose the shallow trench isolation structure, the process also includes: A back gate structure is formed on the second side of the substrate, the back gate structure corresponding to the gate structure of the transistor in the peripheral circuit.
20. The method for manufacturing a semiconductor device according to claim 19, characterized in that, After forming the back gate structure on the second side of the substrate, the method further includes: A second contact portion is formed, one end of which is connected to the back gate structure, and the other end of which is connected to the pad lead-out structure.
21. The method for manufacturing a semiconductor device according to claim 17, characterized in that, After providing the substrate, the following are also included: An insulating portion is formed on the first side of the substrate; A first insulating layer is formed on a first side of the substrate; A contact structure is formed, one end of which is located within the first insulating layer, and the other end of which penetrates the side of the first insulating layer away from the substrate.
22. The method for manufacturing a semiconductor device according to claim 21, characterized in that, After removing part of the substrate to expose the shallow trench isolation structure, the process also includes: A second insulating layer is formed on the second side of the retained substrate; A first contact portion is formed, which penetrates the second insulating layer and the insulating portion, and extends to the first insulating layer to connect with the contact structure.
23. The method for manufacturing a semiconductor device according to any one of claims 13 to 16, characterized in that, After providing the substrate, the following are also included: Along a first direction of the substrate, at least a portion of a region on a first side of the substrate is thinned to make the substrate include a first sub-substrate and a second sub-substrate, the first sub-substrate and the second sub-substrate having different thicknesses.
24. The method for manufacturing a semiconductor device according to claim 18, characterized in that, After removing part of the substrate, the process also includes: Along a first direction of the substrate, at least a portion of a region on a first side of the retained substrate is thinned so that the substrate includes a first sub-substrate and a second sub-substrate, the first sub-substrate and the second sub-substrate having different thicknesses.
25. The method for manufacturing a semiconductor device according to claim 17, characterized in that, Before forming the shallow trench isolation structure on the first side of the substrate, the method further includes: Hydrogen ions are injected into multiple regions within the substrate to form foamed layers in different regions, wherein the multiple regions are arranged along a first direction of the substrate, and the distance between the foamed layers in two adjacent regions and the first side of the substrate is not equal.
26. The method for manufacturing a semiconductor device according to claim 25, characterized in that, A peripheral circuit is formed on the first side of the substrate, including: A plurality of transistors of the peripheral circuit are formed on the substrate, at least two transistors being located in different regions of the substrate, the transistors including one or more combinations of a first transistor, a second transistor, and a third transistor.
27. The method for manufacturing a semiconductor device according to claim 25, characterized in that, After bonding the storage array to the peripheral circuitry, the process further includes: Etch a portion of the shallow trench isolation structure; Remove part of the substrate to expose the foamed layer in different areas; Remove the foam layer.
28. The method for manufacturing a semiconductor device according to claim 27, characterized in that, After removing the foamed layer, the process also includes: A back gate structure is formed on the second side of the substrate.