A packaging method and packaging structure for large wafer-level chips

Abstract

The present application provides a packaging method and packaging structure of a wafer-level large chip, which relates to the field of semiconductor technology. The method comprises: obtaining a wafer-level large chip; the wafer-level large chip refers to a chip structure composed of a plurality of different types of core particles or a plurality of single core particles; preparing a plurality of metal pillars on the first surface of the wafer-level large chip according to the bonding points between the wafer-level large chip and a substrate; preparing a glass transfer plate, the glass transfer plate comprising a plurality of glass through holes, the positions of the glass through holes corresponding one-to-one to the positions of the plurality of metal pillars; inserting the metal pillars on the first surface of the wafer-level large chip into the glass through holes of the glass transfer plate, so that the first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate; bonding the second surface of the glass transfer plate to the substrate to obtain the packaging structure of the wafer-level large chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a packaging method and packaging structure for a wafer-level large chip. Background Art

[0002] As chip size continues to increase and functional integration increases, wafer-level large chip packaging technology faces increasingly complex manufacturing processes and severe cost control challenges.

[0003] Specifically, the traditional packaging process requires multiple alignment and connection steps in the realization of multi-layer interconnection structures and high-density solder joints, which is prone to process errors and packaging defects. Especially in large chip packaging, the alignment and connection steps between the large chip and the substrate are complicated, and the alignment accuracy requirements are higher. Any slight alignment error may cause interconnection defects and affect the overall performance and reliability of the package. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a packaging method and packaging structure for a wafer-level large chip, so as to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect of an embodiment of the present application, a method for packaging a large wafer-level chip is provided, the method comprising:

[0006] Obtaining a wafer-level large chip; the wafer-level large chip refers to a chip structure composed of a plurality of different types of core particles or a plurality of single core particles;

[0007] According to the bonding points between the wafer-level large chip and the substrate, a plurality of metal pillars are prepared on the first surface of the wafer-level large chip;

[0008] Prepare a glass transfer plate, wherein the glass transfer plate comprises a plurality of through-glass holes, and positions of the through-glass holes correspond one-to-one to positions of the plurality of metal pillars;

[0009] Inserting the metal column on the first surface of the wafer-level large chip into the glass through hole of the glass transfer plate, so that the first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate;

[0010] The second surface of the glass transfer plate is bonded to the substrate to obtain the packaging structure of the wafer-level large chip.

[0011] In a possible implementation manner, the preparation of the glass transfer plate includes:

[0012] obtaining a glass substrate;

[0013] According to the bonding points between the wafer-level large chip and the substrate, preparing the through-glass holes on the glass substrate;

[0014] A first seed layer is prepared on the side wall of the through-glass hole by magnetron sputtering or evaporation process, and the metal material used in the first seed layer is the same as the metal material used in the metal column.

[0015] In a possible implementation manner, the step of preparing the through-glass via on the glass substrate includes:

[0016] The through-glass hole is prepared on the glass substrate by laser induced etching, and the diameter of the through-glass hole is greater than 300 um.

[0017] In a possible implementation, bonding the first surface of the wafer-level large chip to the first surface of the glass transfer plate includes:

[0018] On the second surface of the glass transfer plate, injecting solder balls into each of the through-glass holes;

[0019] The solder balls are melted by a thermal reflow process to fill the gap between the through glass via and the metal column.

[0020] In a possible implementation manner, after obtaining the wafer-level large chip, the method further includes:

[0021] Preparing a dielectric layer of the wafer-level large chip;

[0022] A rewiring RDL interconnection layer of the wafer-level large chip is prepared, and the RDL interconnection layer is used to realize the interconnection between the multiple core particles inside the wafer-level large chip.

[0023] In a possible implementation manner, preparing a plurality of metal pillars on the first surface of the wafer-level large chip includes:

[0024] sputtering a second seed layer on the first surface of the wafer-level large chip, wherein the metal material used in the second seed layer is the same as the metal material used in the metal column;

[0025] The second seed layer is photolithographically processed to obtain a plurality of metal pads according to the bonding points between the wafer-level large chip and the substrate;

[0026] The plurality of metal pads are electroplated to obtain the plurality of metal columns, wherein the height of the metal columns is greater than or equal to 2 / 3 of the depth of the through glass hole, and the diameter of the metal columns is smaller than the diameter of the through glass hole.

[0027] In a possible implementation manner, the metal material used for the metal column is copper.

[0028] In a possible implementation manner, bonding the second surface of the glass transfer plate to the substrate includes:

[0029] A ball planting process is adopted on the second surface of the glass transfer plate to perform flip-chip bonding on the second surface of the glass transfer plate and the substrate to obtain the packaging structure of the wafer-level large chip.

[0030] The second aspect of the embodiment of the present application further provides a packaging structure of a wafer-level large chip, wherein the packaging structure of the wafer-level large chip is prepared by the packaging method of the wafer-level large chip described in the first aspect;

[0031] The packaging structure comprises:

[0032] Wafer-level large chip; the wafer-level large chip refers to a chip structure composed of multiple different types of core particles or multiple single core particles;

[0033] The first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate;

[0034] The glass transfer plate includes a plurality of through-glass holes, each of which includes a metal column, one end of which is connected to a bonding point on the first surface of the wafer-level large chip, and the other end of which is connected to a bonding point on the substrate via a solder ball.

[0035] In a possible implementation manner, the height of the metal column is greater than or equal to 2 / 3 of the depth of the through glass via, and less than or equal to the depth of the through glass via.

[0036] An embodiment of the present application provides a packaging method for a wafer-level large chip, the method comprising: obtaining a wafer-level large chip; the wafer-level large chip refers to a chip structure composed of a plurality of different types of core particles or a plurality of single core particles; preparing a plurality of metal pillars on the first surface of the wafer-level large chip according to the bonding points between the wafer-level large chip and the substrate; preparing a glass transfer plate, the glass transfer plate comprising a plurality of glass through holes, the positions of the glass through holes corresponding one-to-one to the positions of the plurality of metal pillars; inserting the metal pillars on the first surface of the wafer-level large chip into the glass through holes of the glass transfer plate, so that the first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate; bonding the second surface of the glass transfer plate to the substrate to obtain the packaging structure of the wafer-level large chip.

[0037] The packaging method of a wafer-level large chip provided in the present application prepares a plurality of metal pillars on the wafer-level large chip, inserts the metal pillars into the glass through holes on the glass transfer plate, completes the bonding between the wafer-level large chip and the glass transfer plate, and then completes the bonding between the wafer-level large chip and the substrate by implanting solder balls, thereby simplifying the packaging process flow between the large chip and the substrate (especially the alignment and connection steps), and achieving high-precision alignment between the large chip and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0039] Figure 1 It is a flowchart of the steps of a wafer-level large chip packaging method provided in an embodiment of the present application;

[0040] Figure 2 is a schematic structural diagram of a metal column formed in a packaging method provided in an embodiment of the present application;

[0041] Figure 3 is a structural schematic diagram of a glass transfer plate formed in a packaging method provided in an embodiment of the present application;

[0042] Figure 4 is a schematic diagram of a preparation process of a glass transfer plate formed in a packaging method provided in an embodiment of the present application;

[0043] Figure 5 This is a schematic diagram of the structure after alignment of a wafer-level large chip and a glass transfer plate provided in an embodiment of the present application;

[0044] Figure 6 It is a schematic diagram of the structure after bonding a wafer-level large chip and a glass transfer plate formed by a packaging method provided in an embodiment of the present application;

[0045] Figure 7 This is a schematic structural diagram of a glass transfer board formed by a packaging method provided in an embodiment of the present application after ball planting;

[0046] Figure 8 It is a schematic diagram of a packaging structure of a wafer-level large chip provided in an embodiment of the present application;

[0047] Description of the drawings: wafer-level large chip 100, metal pillar 101;

[0048] Glass transfer plate 200, glass through hole 201, first seed layer 202, material after solder ball melts 203;

[0049] Substrate 300, solder balls 301. DETAILED DESCRIPTION

[0050] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully communicated to those skilled in the art.

[0051] Existing wafer-level packaging technologies mainly include: Flip Chip, Wafer-Level Ball Grid Array (WLBGA), Wafer-Level System-in-Package (WL-SiP), etc. These technologies have solved the problems of packaging density and performance to a certain extent, but there are still many shortcomings when dealing with large chip packaging.

[0052] Flip chip packaging is widely used in the packaging of high-performance chips due to its high-density solder joints and good electrical performance. However, as the chip size increases, flip chip packaging faces new challenges in interconnection density and thermal management. First, with the increase in the number and density of solder joints, the complexity of the manufacturing process has increased significantly, and higher requirements have been placed on the uniformity and reliability of the solder joints. Any tiny solder joint defect may cause the package to fail and affect the reliability of the entire system. In addition, the thermal management capability of flip chip packaging is limited at high power density, and it is difficult to effectively and quickly conduct the heat generated by the chip to the external heat dissipation structure, resulting in an increase in chip temperature, which in turn affects its performance and life.

[0053] As a mature wafer-level packaging technology, wafer-level ball grid array (WLBGA) packaging achieves high-density interconnection and good heat dissipation performance by directly forming a ball grid array at the wafer level. However, WLBGA still faces problems in material selection and thermal stress control when dealing with large chip packaging. Traditional BGA packaging materials have limitations in thermal conductivity and thermal expansion coefficient, making it difficult to achieve uniform heat conduction under high power density and large chip area, resulting in uneven thermal stress inside the package, which in turn causes warping and microcracks between the chip and the substrate. In addition, the process flow of WLBGA packaging is relatively complex and requires multiple welding and alignment steps, which increases the difficulty and cost of manufacturing and limits its application in large-scale production.

[0054] Wafer-level system packaging (WL-SiP), as a technology that integrates multiple chips and electronic components in one package, can achieve high integration and multi-functionality to a certain extent. However, the application of WL-SiP packaging in large chip packaging also faces the problems of interconnection complexity and thermal management difficulties. Multi-chip integration makes the internal interconnection lines of the package more complicated, increases the delay and crosstalk risk of signal transmission, and affects the signal integrity and stability of the system. At the same time, the high power density of multiple chips significantly increases the overall heat dissipation requirements of the package. Traditional heat dissipation solutions are difficult to meet the requirements of efficient heat conduction, resulting in uneven temperature inside the package, affecting the performance and reliability of the chip.

[0055] The above-mentioned wafer-level packaging technology has the following main problems when dealing with large chip packaging:

[0056] 1) The manufacturing process is complex and difficult to control: Especially in the realization of high-density interconnection and multi-layer structure, the traditional process has many steps and requires extremely high equipment precision and process control, which leads to a significant increase in manufacturing difficulty and cost. Large chip packaging requires processing more solder joints and interconnection lines. Any slight process error may lead to packaging defects, reducing packaging yield and reliability.

[0057] 2) Insufficient thermal management capabilities: Due to the limitations of thermal conductivity and thermal expansion coefficient of traditional packaging materials, it is difficult to achieve efficient heat conduction and uniform heat dissipation, resulting in increased temperature and concentrated thermal stress inside the package. Especially in large chip packaging, high power density and large area lead to uneven heat distribution, which is difficult to effectively deal with by traditional heat dissipation solutions, thus causing warping and microcracks between the chip and the substrate, affecting the mechanical stability and service life of the package.

[0058] 3) Material selection and processing limitations: Existing packaging technologies have difficulty in taking into account electrical conductivity, thermal conductivity and mechanical strength in material selection, which limits further improvements in packaging performance. High-performance packaging materials are usually expensive and have strict requirements on process conditions during processing, further increasing manufacturing costs. In addition, the mismatch in thermal expansion coefficients between the material and the substrate can easily cause mechanical stress and microcracks inside the package, affecting the reliability and life of the package.

[0059] 4) Complicated alignment and connection steps: Traditional packaging processes require multiple alignment and connection steps to achieve multi-layer interconnection structures and high-density solder joints, which are prone to process errors and packaging defects. Especially in large chip packaging, the alignment accuracy between the chip and the substrate is required to be higher. Any slight alignment error may cause interconnection defects and affect the overall performance and reliability of the package.

[0060] The existence of these problems mainly stems from the inherent limitations of existing wafer-level packaging technology when dealing with large chip packaging. First, with the increase in chip size and power density, traditional packaging processes are stretched to the limit in achieving high-density interconnections and multi-layer structures, and it is difficult to meet the requirements of high precision and high reliability. Secondly, traditional packaging materials have insufficient performance in thermal management and cannot effectively cope with the high power density and complex heat flow paths in large chip packaging, causing thermal management to become a bottleneck restricting packaging performance and reliability. In addition, the unreasonable process flow and material selection of existing packaging technology have led to a complex and costly manufacturing process, making it difficult to achieve large-scale commercial production. Finally, the multiple operations of the traditional packaging process in the alignment and connection steps are prone to cause process errors and packaging defects, affecting the overall quality and reliability of the package.

[0061] In view of the above problems, the present application embodiment proposes a packaging method and packaging structure for a wafer-level large chip, so as to simplify the packaging process (especially the alignment and connection steps) when preparing the packaging structure between the wafer-level large chip and the substrate, and achieve high-precision alignment between the large chip and the substrate. In conjunction with the accompanying drawings, the packaging method for a wafer-level large chip provided by the present application embodiment is described in detail through some embodiments and their application scenarios.

[0062] The first aspect of the present application provides a packaging method for a large wafer-level chip, referring to Figure 1 , Figure 1 A flowchart of a wafer-level large chip packaging method provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method includes:

[0063] Step S101, obtaining a wafer-level large chip; the wafer-level large chip refers to a chip structure composed of a plurality of different types of core particles or a plurality of single-type core particles.

[0064] Specifically, first prepare the chip, and select a wafer-level large chip according to the packaging requirements in the actual application process. The wafer-level large chip includes multiple core particles of the same type, which are integrated from multiple core particles. Among them, the multiple core particles can be different types of core particles or multiple core particles of the same type. It should be noted that the large chip in this embodiment refers to the type of chip obtained by integrating multiple core particles, and does not limit the specific data range of the area size of the chip. A large chip refers to a chip with an area larger than the maximum exposure area of ​​the current lithography machine. The large chip has two characteristics: first, the large chip has a large area, which breaks the area limit of the step-and-step lithography machine, and integrates a large number of transistors into one chip, which can exceed the number of transistors integrated on a single chip under the current manufacturing technology. Secondly, the large chip consists of multiple functional bare cores (i.e., core particles), and several emerging semiconductor manufacturing technologies are used to integrate prefabricated bare cores into the large chip.

[0065] In this embodiment, the specific structure of the wafer-level large chip is not limited. The wafer-level large chip may be a wafer-level chip obtained from a tape-out field, and the size is in the range of 2 to 12 inches.

[0066] In a possible implementation manner, after obtaining the wafer-level large chip, the method further includes:

[0067] Preparing a dielectric layer of the wafer-level large chip;

[0068] A rewiring RDL interconnection layer of the wafer-level large chip is prepared, and the RDL interconnection layer is used to realize the interconnection between the multiple core particles inside the wafer-level large chip.

[0069] In this embodiment, for the obtained wafer-level large chip, since it includes multiple core particles (equivalent to sub-chips with the same function), it is necessary to connect the multiple core particles through a certain process. Specifically, a dielectric layer can be prepared on the surface of the wafer-level large chip first, and then an RDL interconnection layer can be prepared. The RDL interconnection layer includes a metal interconnection structure, and the corresponding core particles are connected through the metal interconnection structure to achieve interconnection between multiple core particles. In this embodiment, since the internal structure of the wafer-level large chip is not limited, the structure of the prepared RDL interconnection layer is not limited accordingly, and can be set according to actual application requirements. In this embodiment, the wafer-level large chip and the related dielectric layer and RDL interconnection layer are regarded as a whole (the structure of the dielectric layer and the RDL interconnection layer is not described in the accompanying drawings), and subsequent steps are performed to complete the packaging of the wafer-level large chip and the substrate.

[0070] Step S102 : preparing a plurality of metal pillars on the first surface of the wafer-level large chip according to the bonding points between the wafer-level large chip and the substrate.

[0071] Reference Figure 2 , Figure 2 A schematic diagram of the structure of a metal column formed in a packaging method is shown. Figure 2 As shown, the upper and lower surfaces of the wafer-level large chip 100 are the first surface and the second surface respectively. In the subsequent process of preparing the packaging structure, the surface where the wafer-level large chip 100 is bonded to the substrate is used as the first surface of the wafer-level large chip.

[0072] There are multiple bonding points between the wafer-level large chip 100 and the substrate, and the connection between the wafer-level large chip and the substrate is achieved through multiple bonding points. The positions of the bonding points on the first surface of the wafer-level large chip can be predetermined, so that multiple metal pillars 101 are prepared at the positions of the bonding points to achieve subsequent bonding with the substrate through the metal pillars. The embodiment of the present application adopts a modular design concept and uses a complex multi-layer interconnection structure (i.e., a wafer-level large chip composed of multiple core particles) as a standardized module, which not only reduces the process steps and alignment difficulty, but also improves the flexibility and scalability of the process, so that the packaging process can better adapt to the changes in different chip sizes and functional requirements.

[0073] In a possible implementation manner, the metal material used for the metal column is copper.

[0074] In this embodiment, the position of the metal pillar 101 (ie, the position of the bonding point) can be determined according to actual process requirements, and the metal material used for the metal pillar can be copper metal with conductive properties.

[0075] In a possible implementation manner, the step S102, preparing a plurality of metal pillars on the first surface of the wafer-level large chip, includes:

[0076] Step S1021 , sputtering a second seed layer on the first surface of the wafer-level large chip, wherein the metal material used in the second seed layer is the same as the metal material used in the metal pillar.

[0077] Step S1022: Photolithography is used to prepare a plurality of metal pads on the second seed layer according to the bonding points between the wafer-level large chip and the substrate.

[0078] Step S1023, electroplating the plurality of metal pads to obtain the plurality of metal pillars, wherein the height of the metal pillars is greater than or equal to 2 / 3 of the depth of the through glass hole, and the diameter of the metal pillars is smaller than the diameter of the through glass hole.

[0079] The metal material used in the second seed layer may be copper. The height of the metal column is greater than or equal to 2 / 3 of the depth of the through-glass hole, and less than or equal to the depth of the through-glass hole. The diameter (i.e., width) of the metal column should be smaller than the diameter of the through-glass silicon hole, so that the metal column can be inserted into the through-glass hole after alignment.

[0080] Step S103 , preparing a glass transfer plate, wherein the glass transfer plate comprises a plurality of through-glass holes, and positions of the through-glass holes correspond one-to-one to positions of the plurality of metal pillars.

[0081] Among them, refer to Figure 3 , Figure 3A schematic diagram of the structure of a glass transfer plate formed in a packaging method is shown. Figure 3 As shown, a plurality of through-glass holes 201 are prepared in the glass transfer plate 200, so that the positions of the through-glass holes 201 are the same as the positions of the metal pillars 101, that is, the same as the positions of the bonding points. The thickness of the glass transfer plate can be set according to the actual process requirements. Among them, a seed layer can also be set on the side wall of the through-glass hole (at Figure 3 (not shown) so that it can be bonded with a large wafer-level chip later.

[0082] When dealing with large chip packaging, the relevant packaging process faces the problem of mismatching thermal expansion coefficients between the material (i.e., wafer-level large chip) and the substrate, which can easily cause mechanical stress and microcracks inside the package, affecting the reliability and life of the package. Specifically, in the process of wafer-level system large chip packaging, thermal management is one of the key factors to ensure stable operation of the chip and extend its service life. With the enhancement of chip functions and the increase of operating frequency, the heat generated by the chip during operation increases significantly, resulting in an increase in the temperature inside the package. When facing high power density and large chip area, the relevant packaging process often finds it difficult to achieve efficient heat conduction and heat dissipation, which in turn causes a series of thermal stress problems, the most notable of which is the warping phenomenon between the chip and the substrate. Warping is a structural deformation caused by mechanical stress generated by the mismatch of thermal expansion coefficients between the chip and the substrate during temperature changes. Different materials expand and contract at different rates during heating and cooling, especially in high power density and large chip packaging, where this mismatch in thermal expansion coefficients is more obvious. Warping not only affects the physical connection between the chip and the substrate, causing stress concentration and fracture of the interconnect structure, but may also cause microcracks and structural failure inside the package, seriously affecting the reliability and service life of the package. Traditional solutions mainly rely on thermal interface materials (TIM) and heat sinks for heat conduction and heat dissipation. However, these methods have many limitations in large chip packaging. First, as the chip area increases, the problem of uneven heat distribution becomes more prominent, and traditional heat dissipation solutions are difficult to meet the needs of global thermal management. Secondly, the thermal conductivity of the thermal interface material is limited, making it difficult to achieve efficient heat transfer, resulting in difficulty in effectively dissipating the chip hot spots. In addition, due to the problem of thermal expansion matching during the packaging process, it is still difficult to completely eliminate the warping phenomenon between the chip and the substrate, affecting the mechanical stability and reliability of the package.

[0083] In order to solve the above-mentioned heat conduction and heat dissipation problems, this embodiment uses a glass transfer plate to isolate the wafer-level large chip and the substrate, so that the two can be bonded and connected through the glass through-holes in the glass transfer plate while achieving thermal isolation. Specifically, the embodiment of the present application uses silicon glass bonding technology to reduce the warping phenomenon caused by the thermal stress mismatch between the chip and the substrate. Silicon glass bonding is an advanced packaging technology that introduces a silicon glass layer (i.e., a glass transfer plate) between the chip and the substrate to achieve efficient heat conduction and mechanical connection between the two. Silicon glass has excellent thermal conductivity and a low thermal expansion coefficient, can maintain good structural stability under high temperature conditions, and reduce thermal stress between the chip and the substrate. This embodiment effectively solves the warping problem caused by thermal stress mismatch in the large chip packaging process by using silicon glass bonding technology, and improves the mechanical stability and thermal management efficiency of the package. At the same time, the introduction of silicon glass bonding also provides the possibility for further optimization and innovation of the packaging process, and promotes the development of wafer-level system large chip packaging technology.

[0084] In a possible implementation manner, the step S103, preparing a glass transfer plate, includes:

[0085] Step S1031, obtaining a glass substrate;

[0086] Step S1032, preparing the through-glass via on the glass substrate according to the bonding points between the wafer-level large chip and the substrate;

[0087] In this embodiment, refer to Figure 4 , Figure 4 A schematic diagram of the preparation process of a glass transfer plate formed in a packaging method is shown, Figure 4 As shown, first Figure 4 As shown, a glass substrate 200 is obtained, and the material of the glass substrate can be silicon glass. Then, according to the positions corresponding to the bonding points, a glass through hole 201 is prepared so that the position of the glass through hole corresponds to the position of the metal column one by one, and the metal column can be inserted into the glass through hole later.

[0088] In a possible implementation manner, the step of preparing the through-glass via on the glass substrate includes:

[0089] The through-glass hole is prepared on the glass substrate by laser induced etching, and the diameter of the through-glass hole is greater than 300 um.

[0090] In this embodiment, if Figure 4As shown, a glass through hole is formed by laser induced etching or other glass-based processing techniques. The aperture of the glass through hole can be designed according to actual application needs. In order to facilitate the injection of solder balls in subsequent processes, the diameter of the glass through hole 201 should generally be controlled to be greater than 300um, so that the depth of the glass through hole 201 is consistent with the thickness of the glass adapter plate 200.

[0091] Step S1033, preparing a first seed layer on the sidewall of the through glass hole by magnetron sputtering or evaporation process, wherein the metal material used in the first seed layer is the same as the metal material used in the metal column.

[0092] like Figure 4 As shown, considering that the metal pillars of the wafer-level large chip need to be inserted into the glass through-holes of the glass transfer plate for bonding, it is also necessary to prepare a seed layer (first seed layer 202) on the side wall of the glass through-hole 201 by magnetron sputtering or evaporation process in advance. The metal material used in the first seed layer 202 can be metallic copper.

[0093] The selection and processing of packaging materials is also a major challenge in the packaging process. Large chip packaging needs to take into account multiple aspects of performance such as electrical conductivity, thermal conductivity and mechanical strength, which limits the diversity of materials and the flexibility of the process. High-performance packaging materials are usually expensive, and have strict requirements on process conditions during processing, which further increases the manufacturing cost. The embodiment of the present application optimizes the selection of packaging materials (using glass adapter plates as packaging materials) and processing technology (preparing glass through holes in glass adapter plates in advance), adopts cost-effective and high-performance materials, reduces the cost of packaging materials and processing difficulty, and ensures the economy and sustainability of the packaging process. Through these innovative process improvements, the manufacturing cost of large chip packaging is significantly reduced, and the production efficiency and yield are improved.

[0094] The embodiment of the present application optimizes the heat conduction path between the chip and the substrate by introducing a silicon glass layer into the packaging structure, significantly improves the overall thermal conductivity, and ensures efficient heat dissipation of the chip at high power density. At the same time, the mechanical properties of silicon glass enable it to effectively alleviate the stress concentration caused by the mismatch of thermal expansion coefficients, reducing the warping and microcrack generation of the packaging structure. In addition, the silicon glass bonding process has high process compatibility and reliability, can be seamlessly integrated with existing packaging processes, simplifies the overall manufacturing process, and reduces process complexity and cost. Therefore, this embodiment successfully overcomes the thermal stress mismatch and warping problems faced by traditional packaging technology in large chip packaging through innovative packaging structure design and advanced silicon glass bonding process, significantly improves the performance and reliability of the packaging system, ensures the stable operation and long life of large chips at high power density, and provides a solid technical guarantee for the reliability and performance of high-end electronic products.

[0095] Step S104 , inserting the metal pillars on the first surface of the wafer-level large chip into the through-glass holes of the glass transfer plate, so that the first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate.

[0096] Specifically, the metal pillars of the wafer-level large chip can be aligned one by one with the glass through holes on the glass transfer plate by using an alignment device, so that the metal pillars are inserted into the glass through holes, so that the first surface of the wafer-level large chip contacts the first surface of the glass transfer plate. The alignment device used in this embodiment can be any device that realizes the alignment function, and its type is not limited in this embodiment. Then, the bonding is completed by the ball planting process.

[0097] Silicon glass bonding technology can achieve high-precision alignment and connection between chips and substrates, reducing multiple alignment and connection steps in traditional packaging processes. The present application adopts silicon glass bonding technology, and through one-time bonding, it achieves high-precision alignment between chips and substrates, significantly simplifying the preparation process of interconnect structures. Not only does it reduce process steps and equipment requirements, it also reduces the incidence of process errors and packaging defects, and improves packaging yield. Therefore, the embodiment of the present application introduces high-precision wafer-level bonding equipment, improves the accuracy and consistency of the packaging process, and significantly improves the yield.

[0098] In a possible implementation manner, step S104, bonding the first surface of the wafer-level large chip to the first surface of the glass transfer plate, includes:

[0099] Step S1041 , injecting solder balls into each of the through-glass holes on the second surface of the glass transfer plate.

[0100] Step S1042 , melting the solder ball through a thermal reflow process to fill the gap between the through glass via and the metal column.

[0101] In this embodiment, refer to Figure 5 , Figure 5 A schematic diagram of the structure after a large wafer-level chip and a glass transfer plate are aligned is shown. Figure 5 As shown, first, insert the metal pillar 101 of the wafer-level large chip into the glass through hole 201 on the glass transfer board, so that the first surface of the wafer-level large chip contacts the first surface of the glass transfer board. Insert a solder ball into each glass through hole so that the solder ball contacts the top of the metal pillar. Figure 6 , Figure 6 The schematic diagram of the structure after the wafer-level large chip formed by a packaging method is bonded to the glass transfer plate is shown, Figure 6As shown, through the heat reflow process, the material 203 after the solder ball melts fills the gap between the metal column 101 and the glass through hole 201. The excess material after the solder ball melts on the second surface of the glass transfer plate is removed. Among them, the upper and lower surfaces of the glass transfer plate 200 are the first surface and the second surface respectively, and the surface where the wafer-level large chip 100 is bonded to the glass transfer plate 200 is used as the first surface of the glass transfer plate 200. The surface where the glass transfer plate 200 is bonded to the substrate is used as the second surface of the glass transfer plate 200.

[0102] Step S105 , bonding the second surface of the glass transfer plate to the substrate to obtain the packaging structure of the wafer-level large chip.

[0103] In a possible implementation manner, the step S105 of bonding the second surface of the glass transfer plate to the substrate includes:

[0104] A ball planting process is adopted on the second surface of the glass transfer plate to perform flip-chip bonding on the second surface of the glass transfer plate and the substrate to obtain the packaging structure of the wafer-level large chip.

[0105] Specifically, refer to Figure 7 , Figure 7 A schematic diagram of the structure after ball planting on a glass transfer board formed by a packaging method is shown, Figure 7 As shown, after the wafer-level large chip is bonded to the glass transfer board, multiple solder balls 301 are driven into each glass through hole on the second surface of the glass transfer board through the ball planting process, and then the glass transfer board after ball planting is flip-chip bonded to the substrate (PCB board) through the flip-chip bonding process to complete the packaging and obtain the packaging structure of the wafer-level large chip. Figure 8 , Figure 8 A schematic diagram of a wafer-level large chip packaging structure is shown. Figure 8 As shown, the wafer-level large chip 100 is inserted into the glass through hole 201 of the glass transfer plate 200 through the metal column 101 on the first surface, so that the wafer-level large chip 100 is bonded to the glass transfer plate 200, and then bonded to the substrate 300 through the solder ball 301.

[0106] The wafer-level large chip packaging process usually involves multiple complex processes, including chip cutting, interconnect layer stacking, material deposition, micromachining, and packaging integration. These process steps are not only complicated, but also have extremely high requirements for equipment accuracy and process control, resulting in a significant increase in the difficulty and cost of the manufacturing process. Specifically, with the increase in chip size, the increase in the number of interconnect layers and the interconnect density, the precision requirements for the packaging process also increase. The preparation process of multi-layer interconnection requires multiple steps such as exposure, development, and etching, and each step requires extremely high process control accuracy to ensure the accuracy of interlayer alignment. However, in actual production, any slight alignment error may cause interconnection defects and affect the overall performance and reliability of the package. In addition, the complex interlayer connection process not only increases the process steps, but also increases the difficulty of manufacturing, reduces production efficiency, and thus pushes up the packaging cost. In addition, the cleanliness and surface flatness requirements in the packaging process are extremely high. In the large chip packaging process, any slight contamination or surface unevenness may cause packaging defects and reduce the packaging yield. In order to achieve high cleanliness and high surface flatness, the packaging process requires a lot of investment in production environment and equipment costs, such as high-cleanliness production workshops, precision surface treatment equipment, etc. These investments not only increase production costs, but also limit the scale and economy of the packaging process.

[0107] The embodiment of the present application proposes an innovative wafer-level large chip packaging method, which completes the bonding between the wafer and the substrate by preparing high copper pillars on the wafer-level large chip, bonding with glass through holes and then implanting solder balls, thereby simplifying the process flow and improving the overall performance and reliability of the package. By simplifying the process flow, introducing silicon glass temporary bonding technology, optimizing the manufacturing steps, and introducing advanced materials and process technologies, the problems of manufacturing process complexity, insufficient thermal management and material performance limitations in the prior art are solved, thereby achieving high efficiency and low cost of large chip packaging.

[0108] Secondly, silicon glass bonding technology has excellent thermal conductivity and mechanical stability, which can ensure efficient thermal management and mechanical reliability of the package while simplifying the process flow. The silicon glass layer (i.e., glass adapter plate) can not only efficiently conduct heat, reduce the temperature difference between the chip and the substrate, and avoid warping caused by thermal stress mismatch, but also provide a strong mechanical connection and enhance the overall stability of the package structure. This makes the packaging process no longer need to rely on complex thermal interface materials and multi-layer heat dissipation structures, further simplifying the manufacturing process. In addition, silicon glass bonding technology has good process compatibility and can be seamlessly integrated with existing packaging processes and materials. When introducing new materials and new processes, traditional packaging processes often require a lot of process optimization and equipment transformation, which increases technical risks and costs. However, due to its process flexibility and compatibility, silicon glass bonding technology can be improved on the basis of existing packaging processes without large-scale process adjustments and equipment investment, reducing the complexity and cost of the packaging process. The embodiment of the present application successfully simplifies and optimizes the packaging process flow by applying silicon glass bonding technology to wafer-level large chip packaging structures. Specifically, the embodiments of the present application use silicon glass bonding technology to replace traditional multi-layer interconnects and thermal interface materials, reducing the alignment and connection steps in the packaging process, reducing process complexity and manufacturing costs. At the same time, the efficient thermal conduction and mechanical stability of silicon glass bonding technology ensure efficient thermal management and mechanical reliability of the package, and improve the overall performance and life of the packaging system. Through the above innovations, the present application not only solves the manufacturing process complexity and cost control problems faced in large chip packaging, but also simplifies and optimizes the packaging process through silicon glass bonding technology, significantly improving the production efficiency and yield of the package.

[0109] The second aspect of the embodiment of the present application further provides a packaging structure of a wafer-level large chip, wherein the packaging structure of the wafer-level large chip is prepared by the packaging method of the wafer-level large chip described in the first aspect;

[0110] The packaging structure comprises:

[0111] Wafer-level large chip; the wafer-level large chip refers to a chip structure composed of multiple different types of core particles or multiple single core particles;

[0112] The first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate;

[0113] The glass transfer plate includes a plurality of through-glass holes, each of which includes a metal column, one end of which is connected to a bonding point on the first surface of the wafer-level large chip, and the other end of which is connected to a bonding point on the substrate via a solder ball.

[0114] In a possible implementation manner, the height of the metal column is greater than or equal to 2 / 3 of the depth of the through glass via, and less than or equal to the depth of the through glass via.

[0115] In the embodiment of the present application, the packaging structure of the wafer-level large chip can be as follows: Figure 8 As shown, the packaging structure mainly includes three parts: a wafer-level large chip 100, a glass transfer plate 200 and a substrate 300. Among them, the first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate, and the metal column 101 on the first surface of the wafer-level large chip is inserted into the glass through hole 201 of the glass transfer plate. Solder balls are driven into the glass through hole and melted by a thermal reflow process, so that the melted solder ball material fills the gap between the glass through hole 201 and the metal column 101 to complete the bonding.

[0116] In a possible implementation manner, the metal material used for the metal column is copper, and the metal column is a copper column.

[0117] like Figure 8 As shown, the second surface of the glass transfer plate 200 is bonded to the substrate 300. Specifically, by using a ball planting process on the second surface of the glass transfer plate to prepare a plurality of solder balls 301, the second surface of the glass transfer plate is flip-chip bonded to the substrate through the solder balls 301 to obtain the packaging structure of the wafer-level large chip.

[0118] In a possible implementation manner, a first seed layer is prepared on the sidewall of the through glass hole, and the metal material used in the first seed layer is the same as the metal material used in the metal column.

[0119] In a possible implementation manner, the diameter of the through-glass hole is greater than 300 um.

[0120] In a possible implementation, the wafer-level large chip includes: a dielectric layer and a redistribution layer (RDL), and the RDL interconnection layer is used to realize the interconnection between the multiple core particles inside the wafer-level large chip.

[0121] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0122] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices, electronic devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0123] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0124] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0125] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0126] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0127] The above is a detailed introduction to the packaging method and packaging structure of a wafer-level large chip provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A packaging method for a large wafer-level chip, characterized in that: The method comprises: Obtaining a wafer-level large chip; the wafer-level large chip refers to a chip structure composed of a plurality of different types of core particles or a plurality of single core particles; According to the bonding points between the wafer-level large chip and the substrate, a plurality of metal pillars are prepared on the first surface of the wafer-level large chip; Prepare a glass transfer plate, wherein the glass transfer plate comprises a plurality of through-glass holes, and positions of the through-glass holes correspond one-to-one to positions of the plurality of metal pillars; Inserting the metal column on the first surface of the wafer-level large chip into the glass through hole of the glass transfer plate, so that the first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate; The second surface of the glass transfer plate is bonded to the substrate to obtain the packaging structure of the wafer-level large chip.

2. The packaging method according to claim 1, characterized in that: The method for preparing the glass transfer plate comprises: obtaining a glass substrate; According to the bonding points between the wafer-level large chip and the substrate, preparing the through-glass holes on the glass substrate; A first seed layer is prepared on the side wall of the through-glass hole by magnetron sputtering or evaporation process, and the metal material used in the first seed layer is the same as the metal material used in the metal column.

3. The packaging method according to claim 2, characterized in that: The step of preparing the through-glass hole on the glass substrate comprises: The through-glass hole is prepared on the glass substrate by laser induced etching, and the diameter of the through-glass hole is greater than 300 um.

4. The packaging method according to claim 1, characterized in that: Bonding the first surface of the wafer-level large chip to the first surface of the glass transfer plate comprises: On the second surface of the glass transfer plate, injecting solder balls into each of the through-glass holes; The solder balls are melted by a thermal reflow process to fill the gap between the through glass via and the metal column.

5. The packaging method according to claim 1, characterized in that: After obtaining the wafer-level large chip, the method further includes: Preparing a dielectric layer of the wafer-level large chip; A rewiring RDL interconnection layer of the wafer-level large chip is prepared, and the RDL interconnection layer is used to realize the interconnection between the multiple core particles inside the wafer-level large chip.

6. The packaging method according to claim 1, characterized in that: The step of preparing a plurality of metal pillars on the first surface of the wafer-level large chip comprises: sputtering a second seed layer on the first surface of the wafer-level large chip, wherein the metal material used in the second seed layer is the same as the metal material used in the metal column; The second seed layer is photolithographically processed to obtain a plurality of metal pads according to the bonding points between the wafer-level large chip and the substrate; The plurality of metal pads are electroplated to obtain the plurality of metal columns, wherein the height of the metal columns is greater than or equal to 2 / 3 of the depth of the through glass hole, and the diameter of the metal columns is smaller than the diameter of the through glass hole.

7. The packaging method according to claim 1, characterized in that: The metal material used for the metal column is copper.

8. The packaging method according to claim 1, characterized in that: The step of bonding the second surface of the glass transfer plate to the substrate comprises: A ball planting process is adopted on the second surface of the glass transfer plate to perform flip-chip bonding on the second surface of the glass transfer plate and the substrate to obtain the packaging structure of the wafer-level large chip.

9. A wafer-level large chip packaging structure, characterized in that: The wafer-level large chip packaging structure is prepared by the wafer-level large chip packaging method according to any one of claims 1 to 8; The packaging structure comprises: Wafer-level large chip; the wafer-level large chip refers to a chip structure composed of multiple different types of core particles or multiple single core particles; The first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate; The glass transfer plate includes a plurality of through-glass holes, each of which includes a metal column, one end of which is connected to a bonding point on the first surface of the wafer-level large chip, and the other end of which is connected to a bonding point on the substrate via a solder ball.

10. The packaging structure according to claim 9, characterized in that: The height of the metal column is greater than or equal to 2 / 3 of the depth of the through glass via, and less than or equal to the depth of the through glass via.

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