Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method thereof and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, and forming a first electrode, a first dielectric layer, a second electrode, a first etching stop layer and a second dielectric layer which are stacked in sequence on the substrate; respectively etching the second dielectric layer of the first region and the second dielectric layer of the second region to respectively form a first primary hole and a second primary hole; etching the second dielectric layer below the first primary hole and the second primary hole by adopting a first etching selection ratio so as to expose the first etching stop layer; and etching the first etching stop layer and the first dielectric layer above the transverse extension region by adopting different etching selection ratios so as to expose the first electrode and the second electrode. And etching to the first etching stop layer, and removing a step difference formed by different heights of the first electrode and the second electrode at the moment, so that the etching end point of the through hole can be determined.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to semiconductor structures and preparation methods thereof, and electronic devices. Background Art

[0002] In the semiconductor manufacturing process, the back-end process usually refers to the process of completing the metal interconnection of the chip. Usually, an interlayer capacitor structure is prepared between the metal layers of the metal interconnection layer of the chip to improve the efficiency of chip area utilization.

[0003] In conventional technology, the upper and lower metal plates constituting the interlayer capacitor are connected by etching a through hole. However, due to the different heights of the upper and lower metal plates, there is a step difference, and the etching endpoint of the through hole is difficult to control. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof, and an electronic device to address the problem that the etching endpoint of the through hole of the interlayer capacitor metal plate is difficult to control.

[0005] In a first aspect, the present application provides a method for preparing a semiconductor structure, the method comprising the following steps:

[0006] Providing a substrate, and forming a first electrode, a first dielectric layer, a second electrode, a first etch stop layer and a second dielectric layer stacked in sequence on the substrate, wherein the first electrode is longer than the second electrode and has a lateral extension region;

[0007] Etching the second dielectric layer in a first region and the second dielectric layer in a second region respectively to form a first primary hole and a second primary hole respectively, wherein the first region is a region of the second dielectric layer directly above the lateral extension region, and the second region is a region directly above the second electrode, wherein neither the first primary hole nor the second primary hole contacts the first etch stop layer;

[0008] Etching the second dielectric layer below the first primary hole and the second primary hole using a first etching selection ratio to expose the first etching stop layer;

[0009] The first etch stop layer and the first dielectric layer above the lateral extension region are etched using an etch selectivity different from the first etch selectivity to expose the first electrode and the second electrode.

[0010] In one embodiment, etching the second dielectric layer below the first primary hole and the second primary hole using a first etching selectivity ratio to expose the first etching stop layer includes:

[0011] Based on the first etch stop layer, the second dielectric layer below the first primary hole is etched to obtain a first through hole by adopting a first etch selectivity ratio, and the second dielectric layer below the second primary hole is etched to obtain a second through hole.

[0012] In one embodiment, etching the first etch stop layer and the first dielectric layer above the lateral extension region using an etch selectivity different from the first etch selectivity to expose the first electrode and the second electrode includes:

[0013] Along the first through hole and the second through hole, the first etch stop layer and the first dielectric layer located above the lateral extension region are etched using an etch selectivity different from the first etch selectivity to respectively form a first interconnection hole exposing the first electrode and a second interconnection hole exposing the second electrode.

[0014] In one embodiment, a second etch stop layer is further formed on the first electrode and the second electrode, and a material of the second etch stop layer is different from a material of the first etch stop layer;

[0015] The first etching stop layer and the first dielectric layer located above the lateral extension region are etched along the first through hole and the second through hole using an etching selectivity different from the first etching selectivity to form a first interconnection hole exposing the first electrode and a second interconnection hole exposing the second electrode, respectively, including:

[0016] Along the first through hole and the second through hole, based on the second etch stop layer, the first etch stop layer is etched with a second etch selectivity to form a first interconnection primary hole and a second interconnection primary hole;

[0017] The second etch stop layer and the first dielectric layer above the lateral extension region are etched along the first interconnection primary hole and the second interconnection primary hole using a third etch selectivity ratio to form the first interconnection hole and the second interconnection hole.

[0018] In one embodiment, the distance between the bottom surface of the first primary hole and the first electrode is less than 12% of the thickness of the original second dielectric layer;

[0019] The distance between the bottom surface of the second primary hole and the second electrode is less than 12% of the thickness of the original second dielectric layer.

[0020] In one embodiment, etching the second dielectric layer in the first region and the second dielectric layer in the second region respectively to form the first primary hole and the second primary hole respectively comprises:

[0021] forming a patterned photoresist on the second dielectric layer;

[0022] Based on the patterned photoresist, the second dielectric layer is pre-etched using a fourth etching selection ratio to form a first primary hole and a second primary hole, respectively.

[0023] In one embodiment, after pre-etching the second dielectric layer based on the patterned photoresist using a fourth etching selection ratio to form a first primary hole and a second primary hole, the method further includes:

[0024] The patterned photoresist is removed.

[0025] In one embodiment, the substrate includes a third dielectric layer, a preset routing line and a third etch stop layer, the preset routing line is located on the third dielectric layer, the third etch stop layer covers the preset routing line and the third dielectric layer, the first electrode is located on the third etch stop layer, and the material of the third etch stop layer is the same as that of the first etch stop layer;

[0026] Etching the second dielectric layer in the first region and the second dielectric layer in the second region to form a first primary hole and a second primary hole respectively, and also forming a third primary hole above the preset wiring;

[0027] Etching the second dielectric layer below the first primary hole and the second primary hole using a first etching selection ratio to expose the first etch stop layer and form a third through hole above the preset wiring;

[0028] The first etch stop layer and the first dielectric layer above the lateral extension region are etched using an etch selectivity different from the first etch selectivity to expose the first electrode and the second electrode while forming a third interconnect hole exposing the preset routing line.

[0029] In a second aspect, the present application further provides a semiconductor structure, which is prepared by the semiconductor structure preparation method.

[0030] In a third aspect, the present application also provides an electronic device, which includes the semiconductor structure.

[0031] In the method for preparing the semiconductor structure, a first electrode, a first dielectric layer and a second electrode are first formed on a substrate, the first electrode and the second electrode form a step structure, the first electrode has a lateral extension region relative to the second electrode, a first etch stop layer is formed to simultaneously cover the substrate, the first electrode, the first dielectric layer and the second electrode, and a second dielectric layer is formed on the first etch stop layer. In the etching process, a first primary hole located above the lateral extension region and a second primary hole located above the second electrode are first formed, and both are etched to the first etch stop layer. At this time, the step difference formed by the different heights of the first electrode and the second electrode can be removed, so that the etching end point of the through hole can be determined. On this basis, the first etch stop layer is etched. At this time, the first electrode and the second electrode can be exposed simultaneously by etching the same or similar thickness. Afterwards, the first etch selectivity is used for etching to expose the first etch stop layer, and then the first etch stop layer and the first dielectric layer are etched with an etch selectivity different from the first etch selectivity to expose the first electrode and the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG. 1 is a flow chart of a method for preparing a semiconductor structure in one embodiment.

[0033] 2 to 6 are schematic diagrams of structures obtained in various steps during the preparation of a semiconductor structure in one embodiment.

[0034] Figure 7 This is a SEM image of a third preset routing position filled with a metal plug in an embodiment.

[0035] Figure 8 FIG. 4 is a SEM image of the position of the second interconnection hole formed in one embodiment.

[0036] Fig. 9 FIG. 4 is a SEM image of the position of the first interconnection hole formed in one embodiment.

[0037] Description of reference numerals:

[0038] 102, first electrode; 104, first dielectric layer; 106, second electrode; 108, first etch stop layer; 109, second etch stop layer; 110, second dielectric layer; 111, first primary hole; 112, first through hole; 113, second primary hole; 114, second through hole; 115, first interconnection primary hole; 116, first interconnection hole; 117, second interconnection primary hole; 118, second interconnection hole; 120, first anti-reflection layer; 122, patterned photoresist; 124, third dielectric layer; 126, preset routing; 128, third etch stop layer; 129, third primary hole; 130, third through hole; 132, third interconnection hole. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0042] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] The relevant structures of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but include shape deviations due to, for example, manufacturing technology. The shapes shown in the drawings are schematic in nature and do not limit the scope of the present invention.

[0045] In the semiconductor manufacturing process, the back-end process usually refers to the process of completing the metal interconnection of the chip. In traditional technology, an interlayer capacitor structure is usually prepared between the metal layers of the metal interconnection layer of the chip to improve the efficiency of chip area utilization. The back-end process of various chips such as existing embedded flash memory, power devices, and radio frequency chips generally includes metal interlayer capacitors, which require the upper and lower metal plates that constitute the interlayer capacitor to be connected by etching through holes.

[0046] Due to the different heights of the upper and lower metal plates, there is a step difference, and the etching endpoint of the through hole is difficult to control. On the other hand, the chemical mechanical polishing process of the precursor will cause a large difference in the dielectric thickness between the middle and edge of the wafer due to the load effect, and the through hole etching needs to provide sufficient over-etching. At the same time, if the over-etching etched through the upper plate of the interlayer capacitor, it will cause problems such as easy breakdown of the interlayer electrical connection.

[0047] Referring to FIG. 1 , FIG. 1 shows a schematic flow chart of a method for preparing a semiconductor structure in an embodiment of the present application, which includes the following steps S10 to S40 .

[0048] S10, as shown in FIG. 2, a substrate is provided, and a first electrode 102, a first dielectric layer 104, a second electrode 106, a first etch stop layer 108 and a second dielectric layer 110 are sequentially stacked on the substrate, wherein the first electrode 102 is longer than the second electrode 106 and has a lateral extension region.

[0049] Exemplarily, the first electrode 102 and the second electrode 106 may be made of conductive materials, and the first electrode 102 and the second electrode 106 disposed opposite to each other form a capacitor.

[0050] Exemplarily, the first dielectric layer 104 may be an insulating layer, and the first electrode 102, the first dielectric layer 104 and the second electrode 106 constitute a MIM (Metal Insulator Meta) capacitor. In a feasible implementation, the first dielectric layer 104 may be a nitride, such as silicon nitride.

[0051] Exemplarily, the first dielectric layer 104 is formed on the upper surface of the first electrode 102, and the second electrode 106 covers a portion of the first dielectric layer 104, so that the length of the second electrode 106 is smaller than the first electrode 102, and a step structure is formed between the first electrode 102 and the second electrode 106. The extended area refers to the non-overlapping area of ​​the first electrode 102 and the second electrode 106 projected on the substrate.

[0052] Exemplarily, the first electrode 102 and the substrate form a step structure, the first electrode 102 and the second electrode 106 form a step structure, and the first etch stop layer 108 simultaneously covers the second electrode 106, the first dielectric layer 104, the first electrode 102 and the substrate, that is, the first etch stop layer 108 also forms a step structure.

[0053] By way of example, the second dielectric layer 110 may be an oxide layer, such as silicon oxide.

[0054] S20, such as Figure 3 As shown, the second dielectric layer 110 in the first region and the second dielectric layer 110 in the second region are etched respectively to form a first primary hole 111 and a second primary hole 113 respectively, the first region is a region of the second dielectric layer 110 directly above the lateral extension region, and the second region is a region directly above the second electrode 106, wherein the first primary hole 111 and the second primary hole 113 are not in contact with the first etch stop layer 108.

[0055] Exemplarily, the second dielectric layer 110 in the first region is etched to form a first primary hole 111, and the second dielectric layer 110 in the second region is etched to form a second primary hole 113, and the bottom of the first primary hole 111 is at a certain distance from the first electrode 102, and the bottom of the second primary hole 113 is at a certain distance from the second electrode 106.

[0056] For example, the first anti-reflection layer 120 may be formed on the second dielectric layer 110 , and the first anti-reflection layer 120 and the second dielectric layer 110 may be etched simultaneously in the first etching process to form the first primary hole 111 and the second primary hole 113 .

[0057] S30 , as shown in FIG. 4 , the second dielectric layer 110 below the first primary hole 111 and the second primary hole 113 is etched using a first etching selectivity ratio to expose the first etching stop layer 108 .

[0058] Exemplarily, the purpose of etching in this step is to etch to the first etch stop layer 108 , so the first etching selectivity in this step can be a high etching selectivity of the second dielectric layer.

[0059] Exemplarily, when the second dielectric layer 110 is an oxide layer and the first etch stop layer 108 is silicon nitride, the first etch selectivity may be a high etch selectivity of oxide / silicon nitride.

[0060] S40 , as shown in FIG. 5 and FIG. 6 , the first etch stop layer 108 and the first dielectric layer 104 located above the lateral extension region are etched using an etch selectivity different from the first etch selectivity to expose the first electrode 102 and the second electrode 106 .

[0061] Exemplarily, after the first etch stop layer 108 is exposed, the first etch stop layer 108 is further etched. At the position of the second electrode 106, the second electrode 106 is directly exposed after the first etch stop layer 108 is etched through, and at the position of the first electrode 102, after the first etch stop layer 108 is etched through, the first dielectric layer 104 needs to be etched to expose the first electrode 102.

[0062] Exemplarily, after the first electrode and the second electrode are exposed, through holes are formed on the first electrode 102 and the second electrode 106 to facilitate subsequent interconnection processes.

[0063] In the method for preparing the semiconductor structure, the first electrode 102, the first dielectric layer 104 and the second electrode 106 are first formed on the substrate, the first electrode 102 and the second electrode 106 form a step structure, the first electrode 102 has a lateral extension region relative to the second electrode 106, a first etch stop layer 108 is formed to simultaneously cover the substrate, the first electrode 102, the first dielectric layer 104 and the second electrode 106, and a second dielectric layer 110 is formed on the first etch stop layer 108. In the etching process, the first primary hole 111 located above the lateral extension region and the second primary hole 113 located above the second electrode 106 are first formed, and both are etched to the first etch stop layer 108. At this time, the step difference formed by the different heights of the first electrode 102 and the second electrode 106 can be removed, so that the etching end point of the through hole can be determined, and on this basis, the first etch stop layer 108 is etched, and at this time, the first electrode 102 and the second electrode 106 can be exposed at the same or similar thickness. Then, etching is performed using a first etching selectivity to expose the first etching stop layer 108 , and then the first etching stop layer 108 and the first dielectric layer 104 are etched using an etching selectivity different from the first etching selectivity to expose the first electrode 102 and the second electrode 106 .

[0064] It should be understood that, although the various steps in the flowchart of FIG. 1 are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in FIG. 1 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0065] In some embodiments, step S30 uses a first etching selectivity to etch the second dielectric layer 110 below the first primary hole 111 and the second primary hole 113 to expose the first etch stop layer 108, including: step S31, based on the first etch stop layer 108, using a first etching selectivity to etch the second dielectric layer 110 below the first primary hole 111 to obtain a first through hole 112, and etching the second dielectric layer 110 below the second primary hole 113 to obtain a second through hole 114.

[0066] Exemplarily, the purpose of this step is to form the first through hole 112 and the second through hole 114 to expose the first etch stop layer 108 , and the first etch selectivity can be a high etch selectivity of the second dielectric layer 110 , that is, an etch selectivity of the second dielectric layer 110 to the first etch stop layer 108 .

[0067] Exemplarily, etching based on the first etch stop layer 108 in this step means etching the second dielectric layer 110 until the first etch stop layer 108 is reached to expose the first etch stop layer 108. Optionally, the first etch stop layer 108 may be overetched to ensure that the etching reaches the position of the first etch stop layer 108.

[0068] Exemplarily, the first etching selectivity can be greater than the etching selectivity when etching the second dielectric layer, and the etching rate of the second dielectric layer 110 is greater than the etching rate of the first etch stop layer 108, which can ensure that the second dielectric layer 110 is removed and the first etch stop layer 108 is not over-etched, thereby ensuring that the first etch stop layer 108 has a margin for subsequent etching.

[0069] In some embodiments, step S40 etches the first etch stop layer 108 and the first dielectric layer 104 located above the lateral extension region using an etching selectivity different from the first etching selectivity to expose the first electrode 102 and the second electrode 106, including: step S41, etching the first etch stop layer 108 and the first dielectric layer 104 located above the lateral extension region along the first through hole 112 and the second through hole 114 using an etching selectivity different from the first etching selectivity to respectively form a first interconnection hole 116 exposing the first electrode 102, and a second interconnection hole 118 exposing the second electrode 106.

[0070] Exemplarily, the first etch stop layer 108 and the second dielectric layer 110 are made of different materials. In order to etch the first etch stop layer 108 , different etching selectivity ratios are used for etching in this step.

[0071] Exemplarily, after forming the first through hole 112 and the second through hole 114, etching is continued downward along the extension direction of the first through hole 112 until the first electrode 102 is exposed, thereby forming the first interconnection hole 116, and etching is continued downward along the extension direction of the second through hole 114 until the second electrode 106 is exposed, thereby forming the second interconnection hole 118. In this way, through through holes are formed on the first electrode 102 and the second electrode 106, which facilitates the subsequent interconnection process.

[0072] In some embodiments, a second etch stop layer 109 is further formed on the first electrode 102 and the second electrode 106, and the material of the second etch stop layer 109 is different from that of the first etch stop layer 108. Exemplarily, the second etch stop layer 109 can be used as an anti-reflection layer.

[0073] Exemplarily, the second etch stop layer 109 can act as a relay to adjust the etching selectivity to adjust the etching endpoint. The first etch stop layer 108 can be silicon nitride, and the second etch stop layer 109 can be silicon oxynitride, so that the two materials are different. Exemplarily, the second etch stop layer 109 can be a second anti-reflection layer, which can be a nitride oxide, such as silicon oxynitride. Optionally, in the preparation process of the metal interlayer capacitor, it is necessary to deposit an anti-reflection layer to reduce light reflection occurring during the photolithography process.

[0074] During the photolithography process, reflective materials such as metal need to be deposited as electrodes, which will cause a strong light reflection problem. When light hits its surface, part of the light will be reflected, and the other part will penetrate the substrate and enter the bottom layer. The reflected light will return to the photoresist layer, which may cause overexposure of the photoresist layer and cause problems such as blurring and distortion. To avoid this, an anti-reflection layer is needed to reduce the impact of reflection by absorbing or interfering with the reflected light.

[0075] When there is a second etch stop layer, in step S41, along the first through hole and the second through hole, the first etch stop layer and the first dielectric layer located above the lateral extension region are etched using an etch selectivity different from the first etch selectivity to respectively form a first interconnect hole exposing the first electrode and a second interconnect hole exposing the second electrode, including step S411 and step S412.

[0076] Step S411 , etching the first etch stop layer with a second etch selectivity based on the second etch stop layer along the first through hole and the second through hole to form a first interconnection primary hole and a second interconnection primary hole.

[0077] Exemplarily, when the second etch stop layer 109 is included, the second etch stop layer 109 is formed on the second electrode 106, the first electrode 102 has a portion of the first dielectric layer 104 in a lateral extension region beyond the second electrode 106, and the second etch stop layer 109 is formed on the portion of the first dielectric layer 104. Thereafter, the first etch stop layer 108 is formed on the second etch stop layer 109.

[0078] Exemplarily, when the first etch stop layer 108 is selectively etched based on the second etch stop layer 109, the second etch stop ratio uses the high etch selectivity of the first etch stop layer, that is, the high etch selectivity of the first etch stop layer 108 to the second etch stop layer 109. For example, when the first etch stop layer 108 is silicon nitride and the second etch stop layer 109 is silicon oxynitride, the silicon nitride / silicon oxynitride is controlled to have a high etch selectivity. Optionally, it can also be achieved by controlling the silicon oxide / oxide to have a high etch selectivity, such as using CH 2 F 2 / O 2 Gas etching.

[0079] In this way, it can be ensured that the first etch stop layer 108 is completely removed, and the second etch stop layer 109 is prevented from being over-etched.

[0080] Step S412: etching the second etch stop layer and the first dielectric layer above the lateral extension region along the first interconnection primary hole and the second interconnection primary hole using a third etching selectivity ratio to form a first interconnection hole and a second interconnection hole.

[0081] In the semiconductor structure thus obtained, the first interconnection hole 116 penetrates the second dielectric layer 110, the first etch stop layer 108, the second etch stop layer 109 and the first dielectric layer 104 to expose the first electrode 102; the second interconnection hole 118 penetrates the second dielectric layer 110, the first etch stop layer 108 and the second etch stop layer 109 to expose the second electrode 106.

[0082] Illustratively, when etching the second etch stop layer 109 and the first dielectric layer 104, the third etch selectivity uses an approximate etch selectivity of the first etch stop layer 108 to the second etch stop layer 109, such as controlling the etch selectivity to be approximately 1. In this way, the first etch stop layer 108 and the second etch stop layer 109 do not tend to be over-etched, thereby ensuring that the second etch stop layer 109 and the first dielectric layer 104 can both be removed.

[0083] By adopting the above method, when the metal layer capacitor has an anti-reflection layer, a sufficient over-etching amount can be provided by switching the etching selection ratio.

[0084] In some embodiments, the distance between the bottom surface of the first primary hole 111 and the first electrode 102 is less than 12% of the thickness of the original second dielectric layer 110 ; the distance between the bottom surface of the second primary hole 113 and the second electrode 106 is less than 12% of the thickness of the original second dielectric layer 110 .

[0085] In this embodiment, the second dielectric layer 110 is removed by etching to form the second primary hole 114 on the second electrode 106, and at this time, part of the second dielectric layer 110 is still retained on the second electrode 106. A relatively high etching rate is used, and in order to avoid directly etching the first etch stop layer 108, the etching depths of the first primary hole 111 and the second primary hole 113 are controlled, so that the thickness of the second dielectric layer 110 remaining on the second electrode 106 is less than 12% of the original thickness of the second dielectric layer, and the thickness of the second dielectric layer 110 remaining on the first electrode 102 is less than 12% of the original thickness of the second dielectric layer.

[0086] The original thickness of the second dielectric layer 110 refers to the thickness of the second dielectric layer 110 on the second electrode 106 before etching.

[0087] In one embodiment, step 20 is to respectively etch the second dielectric layer in the first region and the second dielectric layer in the second region to form a first primary hole and a second primary hole, respectively, including:

[0088] Step S21, forming a patterned photoresist on the second dielectric layer.

[0089] Exemplarily, the photoresist is a photoresist, and a patterned photoresist layer is formed by exposure. The patterned photoresist 122 exposes the formation position of the first primary hole 111 and the formation position of the second primary hole 113. In this way, the second dielectric layer 110 can be removed during etching to obtain the first primary hole 111 and the second primary hole 113.

[0090] Step S22 : pre-etching the second dielectric layer based on the patterned photoresist using a fourth etching selection ratio to form a first primary hole and a second primary hole, respectively.

[0091] Exemplarily, the purpose of etching in this step is to etch the second dielectric layer 110 at a faster etching rate. Since only the second dielectric layer 110 is etched, the fourth etching selectivity can be set to a high etching selectivity of the second dielectric layer 110, and optionally, it can be an etching selectivity of the second dielectric layer relative to the first etching stop layer 108.

[0092] Optionally, when the second dielectric layer 110 is an oxide layer and the first etch stop layer is a nitride, CF 4 / CHF 3 / O 2 The gas pair is used to etch and the etching selectivity ratio of oxide / silicon nitride (OX / SiN) is controlled to be about 2.

[0093] Exemplarily, after pre-etching the second dielectric layer 110 based on the patterned photoresist 122 using a fourth etching selection ratio to form the first primary hole 111 and the second primary hole 113 respectively in step S22 , the method further includes: S23 removing the patterned photoresist 122 .

[0094] In one embodiment, the substrate includes a third dielectric layer 124, a preset routing line 126 and a third etch stop layer 128, the preset routing line 126 is located on the third dielectric layer 124, the third etch stop layer 128 covers the preset routing line 126 and the third dielectric layer 124, the first electrode 102 is located on the third etch stop layer 128, and the material of the third etch stop layer 128 is the same as the material of the first etch stop layer 108.

[0095] Exemplarily, the third etch stop layer 128 may overlap with the first etch stop layer 108 , or the first etch stop layer 108 is formed on an upper surface of the third etch stop layer 128 .

[0096] Exemplarily, the predetermined trace 126 may be a metal conductive line.

[0097] In step S20 , the second dielectric layer 110 in the first region and the second dielectric layer 110 in the second region are etched to form the first primary hole 111 and the second primary hole 113 , respectively, and a third primary hole 129 is formed above the preset wiring 126 .

[0098] In step S30 , the second dielectric layer 110 below the first primary hole 111 and the second primary hole 113 is etched using a first etching selectivity ratio to expose the first etch stop layer 108 and form a third through hole 130 above the preset wiring 126 .

[0099] In step S40 , the first etch stop layer 108 and the first dielectric layer 104 located above the lateral extension region are etched using an etch selectivity different from the first etch selectivity to expose the first electrode 102 and the second electrode 106 while forming a third interconnect hole 132 exposing the preset wiring 126 .

[0100] Exemplarily, the material of the third etch stop layer 128 is the same as that of the first etch stop layer 108 , so when etching the first etch stop layer 108 in step S51 , the third etch stop layer 128 can be etched simultaneously to form the third interconnection hole 132 .

[0101] Thus, in the obtained semiconductor structure, the third interconnection hole 132 penetrates the second dielectric layer 110 and the third etch stop layer 128 to expose the preset wiring 126 .

[0102] See also Figure 7-Figure 9 , Figure 7 A SEM (Scanning Electron Microscope) image of a third preset wiring 126 after a metal plug is filled in the location of the third preset wiring 126 in one embodiment is shown. Figure 8 A SEM image showing the position of the second interconnection hole 118 formed in one embodiment is shown. Fig. 9 An SEM image showing the position of the first interconnection hole 116 formed in one embodiment is shown.

[0103] Depend on Figure 7 It can be seen that the formed third interconnection hole 132 is good and can be well electrically connected to the preset wiring 126 after being filled with the conductive plug. Figure 8 and Fig. 9 It can be seen that the formed first interconnection hole 116 can better expose the first electrode 102, and the second interconnection hole 118 can better expose the second electrode 106, indicating that the preparation method provided in the present application can prepare good first interconnection holes 116, second interconnection holes 118 and third interconnection holes 132.

[0104] In one embodiment, a semiconductor structure is further provided, which is prepared by the above-mentioned method for preparing the semiconductor structure.

[0105] In one embodiment, an electronic device is also provided, comprising one or more semiconductor structures as in the above embodiments. The electronic device includes, for example, data storage devices, copiers, network devices, household appliances, instruments, mobile phones, computers and other devices with data storage functions. The electronic device may include a housing and a circuit board arranged in the housing, a memory or a data read-write circuit integrated on the circuit board. The structure of the memory can refer to the relevant description in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0106] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises the following steps: Providing a substrate, and forming a first electrode, a first dielectric layer, a second electrode, a first etch stop layer and a second dielectric layer stacked in sequence on the substrate, wherein the first electrode is longer than the second electrode and has a lateral extension region; Etching the second dielectric layer in a first region and the second dielectric layer in a second region respectively to form a first primary hole and a second primary hole respectively, wherein the first region is a region of the second dielectric layer directly above the lateral extension region, and the second region is a region directly above the second electrode, wherein neither the first primary hole nor the second primary hole contacts the first etch stop layer; Etching the second dielectric layer below the first primary hole and the second primary hole using a first etching selection ratio to expose the first etching stop layer; The first etch stop layer and the first dielectric layer above the lateral extension region are etched using an etch selectivity different from the first etch selectivity to expose the first electrode and the second electrode.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of etching the second dielectric layer below the first primary hole and the second primary hole using a first etching selection ratio to expose the first etching stop layer comprises: Based on the first etch stop layer, the second dielectric layer below the first primary hole is etched to obtain a first through hole by adopting a first etch selectivity ratio, and the second dielectric layer below the second primary hole is etched to obtain a second through hole.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The etching of the first etch stop layer and the first dielectric layer above the lateral extension region using an etch selectivity different from the first etch selectivity to expose the first electrode and the second electrode comprises: Along the first through hole and the second through hole, the first etch stop layer and the first dielectric layer located above the lateral extension region are etched using an etch selectivity different from the first etch selectivity to respectively form a first interconnection hole exposing the first electrode and a second interconnection hole exposing the second electrode.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: A second etch stop layer is also formed on the first electrode and the second electrode, and a material of the second etch stop layer is different from a material of the first etch stop layer; The first etching stop layer and the first dielectric layer located above the lateral extension region are etched along the first through hole and the second through hole using an etching selectivity different from the first etching selectivity to form a first interconnection hole exposing the first electrode and a second interconnection hole exposing the second electrode, respectively, including: Along the first through hole and the second through hole, based on the second etch stop layer, the first etch stop layer is etched with a second etch selectivity to form a first interconnection primary hole and a second interconnection primary hole; The second etch stop layer and the first dielectric layer above the lateral extension region are etched along the first interconnection primary hole and the second interconnection primary hole using a third etch selectivity ratio to form the first interconnection hole and the second interconnection hole.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The distance between the bottom surface of the first primary hole and the first electrode is less than 12% of the thickness of the original second dielectric layer; The distance between the bottom surface of the second primary hole and the second electrode is less than 12% of the thickness of the original second dielectric layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The etching of the second dielectric layer in the first region and the second dielectric layer in the second region to form a first primary hole and a second primary hole respectively comprises: forming a patterned photoresist on the second dielectric layer; Based on the patterned photoresist, the second dielectric layer is pre-etched using a fourth etching selection ratio to form a first primary hole and a second primary hole, respectively.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: After pre-etching the second dielectric layer based on the patterned photoresist using a fourth etching selection ratio to form a first primary hole and a second primary hole, the method further includes: The patterned photoresist is removed.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The substrate comprises a third dielectric layer, a preset routing line and a third etch stop layer, the preset routing line is located on the third dielectric layer, the third etch stop layer covers the preset routing line and the third dielectric layer, the first electrode is located on the third etch stop layer, and the material of the third etch stop layer is the same as that of the first etch stop layer; Etching the second dielectric layer in the first region and the second dielectric layer in the second region to form a first primary hole and a second primary hole respectively, and also forming a third primary hole above the preset wiring; Etching the second dielectric layer below the first primary hole and the second primary hole using a first etching selection ratio to expose the first etch stop layer and form a third through hole above the preset wiring; The first etch stop layer and the first dielectric layer above the lateral extension region are etched using an etch selectivity different from the first etch selectivity to expose the first electrode and the second electrode while forming a third interconnect hole exposing the preset routing line.

9. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises a semiconductor structure prepared by any one of the preparation methods of claims 1 to 8, or comprises the semiconductor structure described in claim 9.

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