Semiconductor packaging structure, packaging method thereof and electronic equipment

Abstract

The invention provides a semiconductor packaging structure, a packaging method thereof and electronic equipment, relates to the technical field of electronics, and is used for solving the problem that defects are generated in semiconductor stack packaging. The semiconductor packaging structure comprises a substrate, a first chip and a second chip, wherein the first chip and the second chip are stacked on the substrate, and the first chip is located between the substrate and the second chip; the filling part surrounds the side surfaces of the first chip and the second chip and is continuous in the direction vertical to the substrate; the orthographic projection of the supporting ring on the substrate surrounds the orthographic projection of the first chip on the substrate, the supporting ring is embedded into the filling part and located on the side, close to the substrate, of the first reference plane, and the first reference plane is the plane where the surface, close to the first chip, of the second chip is located. The semiconductor packaging structure can be applied to electronic equipment.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a semiconductor packaging structure and a packaging method thereof, and an electronic device. Background Art

[0002] With the rapid development of science and technology, people have higher and higher requirements for the functions of high-tech electronic products, such as personal computers, mobile phones, smart watches, etc., and the performance of semiconductor devices is one of the key factors that determine the functions of electronic products. Semiconductor devices are usually made in the following ways: dielectric layers, conductive layers and semiconductor material layers are deposited on semiconductor substrates in sequence; each material layer is patterned by processes such as photolithography and etching to form circuit components or elements. Usually, multiple integrated circuits are formed on a semiconductor substrate. In order to protect and facilitate the use of these integrated circuits, they usually need to be packaged.

[0003] Generally speaking, packaging involves cutting the semiconductor substrate from the front-end process into small chips (Die) through a dicing process, and then gluing the cut chips to the corresponding islands of the substrate (lead frame) frame, and then using ultra-fine metal (gold, tin, copper, and aluminum) wires or conductive resins to connect the bonding pads (Bond Pad) of the chip to the corresponding pins (Lead) of the substrate to form the required circuit; and then the independent chips are packaged and protected with a plastic shell.

[0004] As the size of circuit components or elements is getting closer and closer to the physical limit, and it is difficult to further reduce the size of circuit components and elements, people have turned their attention to how to package integrated circuits with various functions together with high performance to improve the performance of semiconductor devices, while also reducing the size of semiconductor devices. Therefore, various advanced packaging technologies continue to emerge, among which stacked packaging has gained a place in advanced packaging due to its small size and low energy consumption. However, stacked packaging in the prior art also has certain problems, such as easily generating holes when filling plastic packaging materials between the stacked chips. These holes not only affect the reliability of the packaged semiconductor devices, but also cause cracks when cutting. Therefore, it is necessary to improve the stacked packaging structure and method. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor packaging structure and a packaging method thereof, and an electronic device, which are used to solve the problem that holes are easily generated in the semiconductor packaging structure and affect the stability of the semiconductor device.

[0006] To achieve the above purpose, this embodiment adopts the following technical solutions:

[0007] In a first aspect, a semiconductor packaging structure is provided, comprising: a substrate, and a first chip and a second chip stacked on the substrate, wherein the first chip is located between the substrate and the second chip; a filling portion, which surrounds the side surfaces of the first chip and the second chip and is continuous in a direction perpendicular to the substrate; and a support ring, wherein the orthographic projection of the support ring on the substrate surrounds the orthographic projection of the first chip on the substrate, the support ring is embedded in the filling portion, and is located on a side of a first reference plane close to the substrate, the first reference plane being a plane where a surface of the second chip close to the first chip is located.

[0008] The semiconductor packaging structure provided by the embodiment of the present application, on the one hand, the first chip and the second chip are stacked on the substrate, which can reduce the volume of the package and is conducive to realizing the lightness and thinness of the electronic device. On the other hand, a support ring is embedded in the filling part, and the orthographic projection of the support ring on the substrate surrounds the orthographic projection of the first chip on the substrate, and is located on the side of the first reference plane close to the substrate. The first reference plane is the plane where the surface of the second chip close to the first chip is located, so that the support ring is set in the area where bowl-shaped defects are prone to occur, and the wear resistance of the area is increased, so that the bowl-shaped defects can be improved or avoided. When filling above this area, no hole defects will be formed inside the filling part, thereby improving the stability of the semiconductor packaging structure. The improved technical problem to be solved.

[0009] In a possible implementation of the first aspect, the support ring is located between the first reference plane and the second reference plane, and the second reference plane is a plane where the surface of the first chip close to the second chip is located. In this way, by limiting the position of the support ring, the support ring and the redistribution layer can be set at the same height, and then the same layer setting can be adopted to simplify the process.

[0010] In a possible implementation of the first aspect, a redistribution layer is provided on a surface of the first chip away from the substrate, and the redistribution layer includes a dielectric layer; the filling portion includes a first filling layer, and the first filling layer surrounds at least a portion of the area between the first chip and the second chip; the material of the first filling layer is the same as that of the dielectric layer, and the support ring is embedded in the first filling layer. In this implementation, the first filling layer and the dielectric layer are made of the same material and can be implemented by the same process, thereby reducing the process flow.

[0011] In a possible implementation manner of the first aspect, the first filling layer and the dielectric layer are provided in the same layer, so that they can be implemented through the same process, thereby reducing the number of process steps.

[0012] In a possible implementation of the first aspect, the redistribution layer further includes a plurality of wiring layers, the plurality of wiring layers are stacked in a direction perpendicular to the substrate; the wiring layers are embedded in the dielectric layer, and the material of the support ring is the same as that of the wiring layers. In this embodiment, the support ring and the wiring layers can be provided by the same process, thereby simplifying the process.

[0013] In a possible implementation manner of the first aspect, the support ring is disposed in the same layer as at least one wiring layer farthest from the substrate, thereby avoiding defects caused by lack of support from the support ring when forming the final wiring layer.

[0014] In a possible implementation of the first aspect, the surface of the support ring facing away from the substrate is flush with the surface of the wiring layer farthest from the substrate facing away from the substrate. In this implementation, the height of the support ring is limited to avoid the support ring being lower than the surface of the wiring layer when the last wiring layer is formed, thereby aggravating defects.

[0015] In a possible implementation of the first aspect, the support ring penetrates the first filling layer in a direction perpendicular to the substrate, so that the support ring can be provided during the process of forming the entire redistribution layer to avoid defects.

[0016] In a possible implementation of the first aspect, the filling portion further includes a first filling portion, the first filling portion is located between the first filling layer and the substrate, and the first filling portion surrounds a side surface of the first chip; the material of the first filling layer is different from that of the first filling portion. In this way, the properties of the first filling layer can be different from those of the first filling portion, thereby avoiding stress accumulation in the filling portion.

[0017] In a possible implementation manner of the first aspect, the filling portion further includes a second filling portion provided on a side of the first filling layer away from the substrate, the second filling portion surrounds a side surface of the second chip, and a material of the first filling layer is different from that of the second filling portion.

[0018] In a possible implementation of the first aspect, there are multiple support rings, which are arranged radially from the inside to the outside in a direction parallel to the substrate. In this way, providing multiple support rings can increase the uniformity of regional wear resistance and further avoid bowl-shaped defects.

[0019] In a possible implementation of the first aspect, among the adjacent support rings, the width of the inner support ring is greater than the width of the outer support ring, and the width is the dimension in a direction parallel to the substrate. In this way, a larger support ring is arranged at a place with a large depression to reduce the depression and avoid defects.

[0020] In a second aspect, a packaging method for a semiconductor packaging structure is provided, comprising: bonding a first chip to a substrate; filling the first chip with a filling material to form a first filling portion surrounding the side of the first chip; forming a redistribution layer, a first filling layer surrounding the redistribution layer, and a support ring located in the first filling layer on the surface of the first chip away from the substrate, wherein the first filling layer is in contact with the first filling portion, and the orthographic projection of the support ring on the substrate surrounds the orthographic projection of the first chip on the substrate; bonding a second chip to the redistribution layer; filling the second chip with a filling material to form a second filling portion surrounding the second chip, and the second filling portion is in contact with the first filling layer. In a technology known to the inventor of the present application, a support ring surrounding the first chip is not provided, and when the first chip and the second chip are stacked, the gap depth-to-width ratio around the first chip is inconsistent due to misalignment when the first chip and the second chip are aligned, and a hole defect will be generated when filling around the first chip and the second chip. In another technology known to the inventor of the present application, after the first chip is stacked and set on the substrate, it is filled around the first chip, and a redistribution layer is formed on the upper surface of the first chip. The second chip is then stacked on the redistribution layer and filled around the second chip. Since there will be bowl-shaped defects on the redistribution layer, holes will also be generated after filling around the second chip. The existence of holes affects the stability of the semiconductor packaging structure, and cracks may be generated and extend into the chip when singulated and cut, destroying the chip.

[0021] In the packaging method of the semiconductor packaging structure provided in this embodiment, a support ring is provided in the same layer as the wiring layer of the redistribution layer, and the support ring surrounds the first chip, provides support for the area where the bowl-shaped defect occurs, and increases the wear resistance of the area, thereby improving or avoiding the bowl-shaped defect. Therefore, when filling around the second chip, the hole is correspondingly improved or avoided, and the stability of the semiconductor packaging structure is improved.

[0022] In a possible implementation of the second aspect, the redistribution layer includes a dielectric layer and a wiring layer, and the first filling layer and the dielectric layer are formed simultaneously. Thus, by forming the first filling layer and the dielectric layer simultaneously, the process can be reduced.

[0023] In a possible implementation of the second aspect, the support ring is formed simultaneously with at least part of the wiring layer. Thus, by forming the support ring and the wiring layer simultaneously, the process can be reduced, and the support ring can be positioned at a location where bowl-shaped defects are prone to occur, thereby avoiding defects.

[0024] In a third aspect, an electronic device is provided, comprising any semiconductor package structure in the first aspect and a printed circuit board, wherein the semiconductor package structure is combined with the printed circuit board.

[0025] The electronic device provided in this embodiment, by adopting the semiconductor packaging structure in the above technical solution, can achieve lightweight and thinness while improving the performance of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A This is a schematic diagram of a structure in which a first chip is stacked on a substrate in an embodiment of the present application;

[0027] Figure 1B A schematic diagram of a structure in which a second chip is stacked on a first chip known to the inventor of the present application;

[0028] Figure 1C This is a schematic diagram of the structure of the chip stacking package known to the inventor of the present application, which produces holes after filling;

[0029] Figure 1D This is a schematic diagram of the structure of an ideal chip stack package;

[0030] Figure 2A-2F A schematic diagram of the preparation process of another stacked package structure known to the inventor of the present application;

[0031] Figure 3 A three-dimensional schematic diagram of a semiconductor packaging structure provided in an embodiment of the present application;

[0032] Figure 4 For along Figure 3 Sectional view along the AA′ direction;

[0033] Figure 5 for Figure 4 A partial enlarged view of the portion in the middle dotted frame P2;

[0034] Figure 6A-Figure 6I A schematic diagram of a preparation process for forming a redistribution layer and other structures in a semiconductor packaging structure provided in an embodiment of the present application;

[0035] Fig. 7A For along Figure 3 A cross-sectional view in the BB′ direction;

[0036] Figure 7B For along Figure 3 Another cross-sectional view along the BB′ direction;

[0037] Figure 8A-8C A schematic diagram of a preparation process for forming a semiconductor package structure by stacking a second chip on a first chip provided in an embodiment of the application;

[0038] Fig. 9 A flowchart of a packaging method for a semiconductor packaging structure provided in an embodiment of the present application;

[0039] Fig.10A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by those skilled in the art in the ordinary sense. The terms "first", "second", "third" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0041] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to the change of the orientation of the chip or semiconductor packaging structure.

[0042] With the development of technology, people have higher and higher requirements for the functions of electronic devices. For example, to improve the portability of electronic devices, it is necessary to reduce the size of the devices and improve the integration of the devices. Another example is to improve the response speed of electronic devices and reduce delays. Increasing the number of transistors integrated in the chip is one way to achieve this. However, based on the development trend of existing memory chips, the size of transistors in the chip is approaching the physical limit, and the speed of improving the performance of a single chip by reducing the size of transistors has slowed down. Therefore, in order to reduce the size of electronic devices and improve the performance of electronic devices, technicians have moved from traditional chip packaging to multi-layer chip stacking packaging.

[0043] Multi-layer chip stacking includes substrate to substrate stacking (wafer to wafer), chip to substrate stacking (die to wafer), and chip to chip stacking (die to die). Among them, substrate to substrate stacking has the highest efficiency, but the warping of the substrate will affect the bonding accuracy of the metal pads on the two substrates. In addition, there are chips on the substrate that do not meet the requirements. Such chips are also bonded to the chip on another substrate, reducing the product yield. In the chip and substrate stacking, known good chips are selected for stacking to avoid the use of unqualified chips for packaging, taking into account both product and production yields. Therefore, chip and substrate stacking is a good compromise.

[0044] Next, combine Figures 1A to 1C To illustrate the process of chip stacking technology known to the inventor and its possible problems.

[0045] like Figure 1A , which is a schematic diagram of a structure in which a first chip 200 and a substrate 100 are stacked in a chip-substrate stacking process. The substrate 100 includes a substrate body 101 and a substrate interconnection layer 102, and the first chip 200 includes a first chip body 201 and a first interconnection layer 202. The substrate 100 is stacked by combining the substrate interconnection layer 102 with the first interconnection layer 202 of the first chip 200.

[0046] In some embodiments, the substrate body 101 and the first chip body 201 may be formed of silicon, or may be formed of other group III elements, group IV elements and / or group V elements (e.g., silicon, germanium, gallium, arsenic and combinations thereof). The substrate body 101 may also be in the form of silicon-on-insulator (SOI). The silicon-on-insulator substrate body may include a layer of semiconductor material (e.g., silicon, germanium and / or the like) formed on an insulator layer (e.g., buried oxide and / or the like), the insulator layer being formed on the silicon substrate body. The substrate body 101 is formed with circuit elements (not shown in the figure) through semiconductor process steps such as doping, photolithography, etching, deposition, etc. In some embodiments, various circuit elements may include various n-type metal-oxide semiconductor (NMOS) and / or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photodiodes, fuses and / or the like. The circuit elements on the substrate body 101 are divided into multiple regions, and the circuit elements in each region are connected by conductive wires in the substrate interconnect layer 102, so as to realize specific functions, such as logical operations, data storage, etc., and when forming the final product, the substrate body 101 will be cut, and the final product only includes one or several such regions. When there are multiple regions, the functions of the multiple regions may be the same or different. The difference between the first chip body 201 and the substrate body 101 is that the first chip body 201 does not need to be cut when forming the final product, but the circuit elements on the first chip body 201 may be one region or multiple regions. Similarly, when there are multiple regions, the functions of the multiple regions may be the same or different.

[0047] In some embodiments, the substrate interconnect layer 102 and the first interconnect layer 202 can be formed by depositing an insulating dielectric layer on the substrate body 101 and the first chip body 201, and forming a wiring layer (not shown in the figure) on the insulating dielectric layer through semiconductor process steps such as photolithography, development, etching, sputtering, chemical mechanical polishing (CMP), etc. The wiring layer may include conductive wires and bonding contacts. The insulating dielectric layer may be a low-k dielectric material, and the conductive wires and bonding contacts may be metal materials such as copper, tungsten, and tin. In some embodiments, the conductive wires and bonding contacts may also include a seed layer and a barrier layer (not shown in the figure), wherein a seed layer is formed at a preset position, and then the conductive material of the conductive wires and bonding contacts is deposited on the thin seed layer. The seed layer may contain copper, titanium, nickel, gold, manganese, the like, or a combination thereof, and may be formed by ALD, PVD, a similar process, or a combination thereof.

[0048] The circuit elements on the substrate body 101 and the first chip body 201 are interconnected through the upper substrate interconnection layer 102 and the first interconnection layer 202 to form an integrated circuit that realizes a specific function, and is connected to other circuits through bonding contacts, such as connecting to other chips and printed circuit boards. The integrated circuit here can be a logic integrated circuit, a memory integrated circuit, a sensor integrated circuit, an analog integrated circuit, etc.

[0049] In some embodiments, before stacking the first chip 200 and the substrate 100, the first chip 200 needs to be picked up from the dicing tape and placed on the substrate 100. The first chip 200 and the substrate 100 may be combined by a bonding process, and the bonding process may be eutectic bonding, metal thermal compression bonding, hybrid bonding, etc.

[0050] See also Figure 1B , Figure 1B This is a schematic diagram of a structure in which a second chip 500 is stacked on a first chip 200 in a related technology known to the inventor of the present application. Take stacking two layers of chips on a substrate 100 for packaging as an example. In some embodiments, there are multiple first chips 200, which are evenly distributed on the surface of the substrate and bonded to the substrate 100. After the first chip 200 is bonded to the substrate 100, the second chip 500 is stacked on the first chip 200, that is, the second chip 500 is bonded to the first chip 200. The structure of the second chip 500 is similar to that of the first chip 200, and will not be repeated here.

[0051] In some embodiments, before the second chip 500 is bonded to the first chip 200, a redistribution layer 400 is pre-formed on the upper surface of the first chip 200. A communication channel penetrating the first chip body 201 is provided in the redistribution layer 400, and a conductive connection is provided in the communication channel. The redistribution layer is electrically connected to the first chip 200 or the substrate 100 through the conductive connection. Due to factors such as the placement accuracy of the second chip 500 and the warping of the substrate, the alignment of the second chip 500 with the redistribution layer 400 on the first chip 200 may have errors, such as the left second chip 500 shifts to the right and the right second chip 500 shifts to the left. If some second chips 500 other than the aforementioned two second chips 500 are precisely aligned at this time, the left gap of the left second chip 500 will be inconsistent with the right gap, wherein the left gap refers to the distance between the left second chip 500 and the left adjacent second chip 500, and the right gap refers to the distance between the left second chip 500 and the right adjacent second chip 500. Therefore, the aspect ratio of the gap around the second chip 500 is inconsistent. Also, in the same gap, due to the misalignment of the second chip 500, the gap width d1 between the first chips 200 is greater than the gap width d2 between the second chips 500.

[0052] See also Figure 1C After the second chip 500 is bonded to the first chip 200, a filling material 301 is used to fill the first chip 200 and the second chip 500. In some embodiments, the filling material may include molding compounds such as epoxy resin, resin, moldable polymer, polyimide, and silicides such as silicon oxide, silicon nitride, silicon oxynitride, and silicon-glass bonding compound. The gap width d1 between the first chips 200 is different from the gap width d2 between the second chips 500, and the gap depth-to-width ratio around the second chip 500 is inconsistent. If the same filling material is used for filling, defects will occur after filling. For example, after the filling material is cured, a hole 306 will be generated inside it. The presence of the hole 306 will affect the stability of the chip. To avoid this problem, it is required that the filling material filling the gap between the first chips 200 and the filling material filling the gap between the second chips 500 have certain differences, such as differences in fluidity and volume change after curing. Firstly, the differences of these filling materials are difficult to achieve precise control; secondly, since the position of the second chip 500 after bonding is also uncertain, it is difficult to select the properties of the filling material according to the specific gap.

[0053] See also Figure 1D , Figure 1DIt is a schematic diagram of the structure of chip stacking in an ideal state, wherein the first chip 200 and the second chip 500 are not misaligned when bonded, and there are no hole defects in the filling material 301 around the first chip 200 and the second chip 500.

[0054] In order to improve the problems caused by the stacking method shown above and to achieve an ideal device, the following technical solutions are provided.

[0055] See also Figure 2A-2F , Figure 2A-2F It is a schematic diagram of the preparation process of a stacked packaging structure known to the inventor of the present application.

[0056] See also Figure 2A In some embodiments, after the first chip 200 is bonded to the substrate 100, a filling material 301 is used to fill around the first chip 200. In a specific embodiment, multiple first chips 200 are bonded simultaneously on one substrate 100, and multiple first chips 200 are arranged in a plane on the surface of the substrate 100, and the filling material 301 fills the gaps between the first chips 200. The filling material may include molding compounds such as epoxy resin, resin, moldable polymer, polyimide, etc. A dicing street (dicing street) for forming a separate package by monomerization may be provided in the gap between the first chips 200. In order to ensure the filling effect, the height of the filling material 301 after filling will be higher than the upper surface of the first chip 200. Therefore, in order to continue to stack chips on the upper surface of the first chip 200, it is necessary to planarize the upper surface of the first chip 200 and the filling material 301.

[0057] See also Figure 2B After the filling material 301 fills the first chip 200, the upper surfaces of the first chip 200 and the filling material 301 are planarized. The planarization can be performed by chemical mechanical polishing (CMP), etching or other suitable processes. After the planarization, it is expected that the upper surface of the filling material 301 is substantially coplanar with the upper surface of the first chip 200 within the process variation, and the filling material 301 surrounding the first chip 200 forms a first filling portion 311. However, due to the difference between the material of the first chip 200 and the filling material 301, a bowl-shaped depression 308 (dishing) will appear on the upper surface of the first filling portion 311 after planarization. For example, when the planarization adopts a chemical mechanical polishing process, based on reducing the loss of the process to the first chip 200, the wear resistance of the filling material 301 is inferior to that of the first chip 200. As a result, the grinding speed of the filling material 301 is higher than that of the first chip 200, so a bowl-shaped depression will be formed on the upper surface of the first filling portion 311.

[0058] After the planarization treatment, in order to realize the chip stacking arrangement, that is, to combine the second chip 500 on the upper surface of the first chip 200, it is necessary to electrically connect the second chip 500 to the substrate 100 or the first chip 200. In some embodiments, a channel (not shown in the figure) is formed on the first chip 200, which at least runs through the first chip body 201 of the first chip 200, and the electrical connection between the first chip 200 or the substrate 100 and the second chip 500 can be realized by filling the channel with conductive materials such as copper, tungsten, and polysilicon. The formation of the channel can be formed by a plasma etching process, and can also be formed by some other processes. It is easy to understand that if only by filling the conductive material in the channel to achieve electrical connection, the position of the channel will limit the position of the bonding contact of the second chip 500, which is not conducive to stacking.

[0059] Therefore, before stacking the second chip 500 on the first chip 200, a redistribution layer 400 needs to be formed on the upper surface of the first chip 200. The redistribution layer 400 is used to change the layout positions of the bonding contacts electrically connected to the second chip 500 on the upper surface of the first chip 200. In some embodiments, in order to meet some specific needs, other film layers are provided between the redistribution layer 400 and the first chip 200, such as a film layer for improving insulation.

[0060] The redistribution layer 400 includes an insulating dielectric layer 401 and a wiring layer 402. Figure 2C First, a layer of insulating dielectric material 701 is deposited on the upper surface of the first chip 200 and the first filling portion 311 to form a dielectric layer 401 in a subsequent process. The deposited insulating dielectric material 701 can be regarded as having a constant thickness, so there will also be a bowl-shaped defect 308 on the upper surface of the first filling portion 311.

[0061] Please continue to see Figure 2D , the insulating dielectric material 701 is subjected to processes such as photolithography, etching, sputtering and planarization to form an insulating dielectric layer 401 and a wiring layer 402, and the wiring layer 402 is embedded in the insulating dielectric layer 401. In the planarization process, since a wiring layer is provided in the insulating dielectric material 701 at the upper region of the first chip 200, that is, there is a conductive connection, the conductive connection increases the wear resistance at the upper region of the first chip 200. However, there is no wiring layer in the insulating dielectric material 701 above the first filling portion 311, and the wear resistance is lower than the wear resistance of the upper surface of the first chip 200. Therefore, when the planarization process is performed, the bowl-shaped defect 308 of the insulating dielectric material 701 in the upper region of the first filling portion will be aggravated. For example, the bowl-shaped defect 308 of the insulating dielectric material 701 will be larger than the opening of the bowl-shaped defect 308 of the first filling portion 311.

[0062] See also Figure 2EAfter the redistribution layer 400 is formed, the second chip 500 is combined with the redistribution layer 400 in the same manner as the first chip 200 is combined with the substrate 100. The second chip 500 is picked up from the dicing tape and placed on the redistribution layer 400. Due to factors such as substrate warping and lack of reliable reference objects, the alignment of the bonding contacts of the second chip 500 and the bonding contacts of the redistribution layer 400 may also have errors, resulting in misalignment.

[0063] See also Figure 2F The second chip 500 is filled with a filling material 301 to form a second filling portion 313. Since the first filling layer 312 has a bowl-shaped defect 308, a hole 306 may be formed in the second filling portion 313, affecting the stability of the semiconductor package structure.

[0064] exist Figure 2A-2F In the stacked packaging method shown, although the second chip 500 will also be misaligned after being combined, since the gap around the first chip 200 is filled first, and then the gap around the second chip 500 is filled, this method of filling in multiple times can improve the impact caused by the inconsistent depth-to-width ratio of the gap. Figure 2A-2F In the stacked packaging method shown, the redistribution layer 400 is formed on the upper surface of the first chip 200 only after the first chip 200 is bonded to the substrate 100, but it should be understood that the redistribution layer can also be formed on the upper surface of the first chip 200 before the first chip 200 is bonded to the substrate 100 to achieve a similar technical effect. In addition, the two stacked packaging methods with different times for forming the redistribution layer both have a planarization process step, that is, after the gap around the first chip 200 that has been bonded to the substrate 100 is filled with a filling material, there is a planarization process step. As mentioned above, the planarization process will introduce a bowl-shaped defect 308. After filling, the bowl-shaped defect 308 may cause a hole 306 to be generated in the filling material, thereby affecting the reliability of the device formed after the stacked packaging.

[0065] In order to avoid or improve the problems caused by the bowl-shaped defect 308, the present application embodiment proposes a semiconductor packaging structure. Taking two layers of chips stacked on a substrate as an example, it is easy to understand that the present application can be extended to stack multiple layers of chips on a substrate during specific implementation. Figure 3 The semiconductor package structure 1 includes: a substrate 100 and a filling portion 310, the filling portion includes a first filling portion 311, a first filling layer 312 and a second filling portion 313, and the substrate 100 includes a substrate body 101 and a substrate interconnection layer 102. The filling portion 310 is provided with a first chip 200 and a second chip 500.

[0066] The materials and structures of the substrate 100, the first filling portion 311, the first filling layer 312 and the second filling portion 313 can be the same as those of Figure 1A-Figure 2F The above are consistent with those described in the implementation method, and will not be repeated here.

[0067] like Figure 4 (along Figure 3 As shown in the cross-sectional view taken along the AA′ direction, the first chip 200 and the second chip 500 are stacked on the substrate 100, and the first chip 200 is located between the substrate 100 and the second chip 500; a redistribution layer 400 is arranged between the first chip 200 and the second chip 500.

[0068] Among them, the first chip 200 includes a first interconnection layer 202 and a first chip body 201, and the second chip 500 includes a second interconnection layer 502 and a second chip body 501. In some embodiments, the first chip 200 and the second chip 500 are packaged in the embodiment of the present application after they are manufactured in the wafer fab, that is, the first chip 200 and the second chip 500 are bare chips. In some embodiments, the first chip 200 and the second chip 500 are packaged before being packaged in the embodiment of the present application. The first chip 200 and the second chip 500 can be chips with the same function or chips with different functions, and the size relationship between the first chip 200 and the second chip 500 is not limited. For example, the size of the first chip 200 can be the same as or different from the size of the second chip 500.

[0069] In some embodiments, the first interconnect layer 202 of the first chip 200 is disposed opposite to and bonded to the substrate interconnect layer 102 of the substrate 100 , and the bonding method includes eutectic bonding, metal thermocompression bonding, hybrid bonding, etc. The second interconnect layer 502 of the second chip 500 is combined with the first chip 200 via the distribution layer 400 .

[0070] See also Figure 5 , Figure 5 for Figure 4 In the partially enlarged view of the portion within the dotted box P2, the redistribution layer 400 includes a dielectric layer 401 and a wiring layer 402. The dielectric layer 401 is made of an insulating material, such as silicon dioxide, to achieve electrical isolation. The wiring layer includes conductive wires and bonding contacts to achieve electrical connection between the second chip 500 and the first chip 200 or the substrate 100.

[0071] The filling part 310 is continuous in a direction perpendicular to the substrate 100, and the support ring 600 is embedded in the filling part 310. The filling part includes a first filling part 311, a first filling layer 312, and a second filling part 313. The first filling layer 312 is Figure 4 The portion in the dashed box P1 indicated by reference numeral 312 does not include the support ring 600 .

[0072] The first filling portion 311 surrounds the side of the first chip 200, and the second filling portion 313 surrounds the side of the second chip 500. The bottom surface of the first filling portion 311 is in close contact with the upper surface of the substrate 100 to achieve sealing of the first chip 200, etc. The second filling portion 313 is continuous with the first filling portion 311 in a direction perpendicular to the substrate surface or continuous through the first filling layer 312, and the second filling portion 313 covers the top of the second chip 500 to achieve sealing of the second chip 500, etc. In some embodiments, the second filling portion 313 may surround a partial area between the first chip 200 and the second chip 500.

[0073] The first filling layer 312 is disposed between the first filling portion 311 and the second filling portion 313 , so as to achieve continuity between the first filling portion 311 and the second filling portion 313 , that is, continuity of the filling portion 310 . At this time, the support ring 600 is embedded in the first filling layer 312 .

[0074] In some embodiments, the redistribution layer 400 may be formed on the first chip 200 before stacking packaging. For example, after the front-end manufacturing of the substrate is completed and the individualization is completed, the first chip 200 is obtained, and multiple chips are arranged and placed on a carrier with temporary bonding glue. After the gaps between the multiple chips are filled with plastic encapsulation material and the back of the chip is in the same plane with the plastic encapsulation material, the chip and the carrier are separated, and the redistribution layer 400 is formed on the back of the chip and the plane where the plastic encapsulation material is located, and finally the first chip 200 with the redistribution layer 400 is cut to obtain. Therefore, after the filling material is filled around the first chip 200 and flattened, it is not necessary to form the redistribution layer 400. At this time, the upper surface of the first filling part 311 after the flattening process is flush with the upper surface of the redistribution layer 400 to facilitate the combination of the second chip 500 and the first chip 200. That is, the second filling part 313 is arranged next to the first filling part 311, so as to achieve the continuity of the filling part 310. In these embodiments, there is no first filling layer 312, and the support ring 600 is embedded in the first filling part 311 or the second filling part 313. That is, in this embodiment, after the first chip 200 is bonded to the substrate 100 and filled to form the first filling part 311, since the redistribution layer 400 has been formed on the first chip 200, it is not necessary to set the redistribution layer 400 on the upper surface formed by the first chip 200 and the first filling part 311. Exemplarily, the support ring 600 can be formed on the upper surface of the first filling part 311 by photolithography, deposition and other steps.

[0075] It can be understood that in various situations where the support ring 600 is embedded in the filling portion 310, the orthographic projection of the support ring 600 on the substrate 100 surrounds the orthographic projection of the first chip 200 on the substrate 100. Preferably, the orthographic projection of the support ring 600 on the substrate 100 surrounds the orthographic projection of the first chip 200 on the substrate 100 and is arranged at intervals.

[0076] If the surface of the second chip 500 close to the substrate 100 is taken as the first reference plane, the support ring 600 is substantially located on the side of the first reference plane close to the substrate 100. The "substantially" here means that the influence of the process error is not considered, that is, in the actual product, the upper surface of the support ring 600 may exceed the first reference plane by a certain distance, and the distance is caused by the process error.

[0077] In some embodiments, the redistribution layer 400 may include a multi-layer dielectric layer 401 and a multi-layer wiring layer 402, that is, the dielectric layer 401 and the wiring layer 402 may have multiple layers. When forming the dielectric layer 401, the first filling layer 312 may be set in the same layer. "Setting in the same layer" means setting by the same process, which not only means using the same process, but also means setting by the same process at the same time. Specifically, it means that the dielectric layer 401 and the first filling layer 312 are formed by the same film forming process, and a film layer for forming a specific pattern is formed by the film forming process, and then the dielectric layer 401 and the first filling layer 312 are formed simultaneously by a single patterning process using the same mask. According to different formation structures, a single patterning process may include multiple exposure, development, etching and other processes, and the layer structure formed by setting in the same layer may be continuous or discontinuous. In some embodiments, more specifically, the dielectric layer 401 here is formed by depositing silicon dioxide on the upper surface of the first chip 200 by a deposition process, and silicon dioxide is also deposited on the upper surface of the first filling portion 311 by the deposition process. After the silicon dioxide film layer is formed by deposition, in order to form the wiring layer 402 on the dielectric layer 401 and embed the support ring 600 in the first filling layer 312, a photoresist is coated on the silicon dioxide film layer, and the photoresist is exposed using the same mask. After exposure, the pattern not blocked by the photoresist is obtained by development, and finally the pattern is formed on the silicon dioxide film layer by an etching process. Thus, the dielectric layer 401 located directly above the first chip 200 and the first filling layer 312 located directly above the first filling portion 311 are formed. In this embodiment, the first filling layer 312 and the dielectric layer 401 are continuously arranged. However, it is easy to understand that in some embodiments, the first filling layer 312 may not be continuously arranged with the dielectric layer 401, that is, there is a gap between the first filling layer 312 and the dielectric layer 401, and the gap is embedded by the support ring 600.

[0078] In some embodiments, the material of the dielectric layer 401 of the redistribution layer 400 is different from the material of the first filling portion 311 and the second filling portion 313. Since the dielectric layer 401 of the redistribution layer 400 and the first filling layer 312 are disposed in the same layer, the dielectric layer 401 of the redistribution layer 400 and the first filling layer 312 are made of the same material. In addition, the material of the redistribution layer 400 may be different from the filling material 301 used to fill the gap in the package, that is, the material of the first filling layer 312 is different from the material of the first filling portion 311 or the second filling portion 313. In other embodiments, the material of the first filling layer 312 may also be the same as the material of the first filling portion 311 or the second filling portion 313.

[0079] In some embodiments, the support ring 600 is disposed in the same layer as the wiring layer 402 of the redistribution layer 400. After forming the dielectric layer 401 located directly above the first chip 200 and the first filling layer 312 located directly above the first filling portion 311, a conductive material, such as copper, tungsten, etc., is disposed in the pattern produced by etching by sputtering, deposition, etc., thereby forming the wiring layer 402 and the support ring 600, and the wiring layer 402 is embedded in the dielectric layer 401. Thus, the wiring layer 402 and the support ring 600 are made of the same material. In some embodiments, the support ring 600 may not be disposed in the same layer as the wiring layer 402, thereby achieving the use of different materials for the support ring 600 and the wiring layer 402 to meet specific needs for the support ring 600. Specifically, a conductive material may be first disposed in the pattern produced by etching the dielectric layer 401, and then another material that meets the needs may be disposed in the pattern produced by etching the first filling layer 312.

[0080] In some embodiments, the support ring 600 is disposed in the first filling layer 312, and the first filling layer 312 is located on the side of the first filling portion 311 away from the substrate 100, so the support ring 600 is located on the upper surface of the first filling portion 311. When the filling material 301 is filled around the second chip 500, if the surface of the first filling layer 312 in contact with the filling material 301 is uneven, the unevenness will affect the filling and forming of the second filling portion 313 around the second chip 500, resulting in defects in the second filling portion 313, affecting the reliability of the semiconductor package structure 1. Therefore, the support ring 600 is located on the side of the plane where the lower surface of the second chip 500 is located close to the substrate 100.

[0081] The following uses the support ring 600 disposed in the first filling layer 312 to illustrate the technical effect of the support ring 600 in improving or avoiding the bowl-shaped defect 308, thereby improving or avoiding the generation of holes 306 in the second filling portion that affect the reliability of the semiconductor package structure 1.

[0082] See also Figure 6A-Figure 6I ( Figure 4A partial enlarged view of the corresponding area in the dotted box P2), Figure 6A-Figure 6I It is a schematic diagram of the formation process of the redistribution layer 400 and the first filling layer 312 .

[0083] Fig. 6A It is shown that the first chip 200 is stacked on the substrate 100. After the first chip 200 is bonded to the substrate 100, a filling material 301 may be filled around the first chip 200 to form a first filling portion 311.

[0084] Figure 6B The figure shows that the filling material 301 is filled around the first chip 200. To ensure the packaging effect, after filling, the upper surface of the filling material 301 will be higher than the upper surface of the first chip 200, which will be disadvantageous to form the redistribution layer 400 on the upper surface of the first chip 200.

[0085] Figure 6C The figure shows that the upper surface of the first chip 200 and / or the filling material 301 is planarized. After the first chip 200 is filled, the filling material 301 and the upper surface of the first chip 200 need to be planarized. Due to the difference in the material of the filling material 301 and the upper surface of the first chip 200, a bowl-shaped defect 308 will be generated on the upper surface of the filling material 301 during the planarization process.

[0086] like Fig.6D As shown, after the planarization treatment, a redistribution layer 400 is formed on the upper surface of the first chip 200 to stack the second chip 500. When forming the redistribution layer 400, an insulating dielectric material 701 is first deposited on the upper surface of the first chip 200 and the first filling portion 311 formed by planarization to form a dielectric layer 401 and a first filling layer 312, such as silicon dioxide, that is, the dielectric layer 401 and the first filling layer 312 are arranged in the same layer. It should be noted that the distinction between the dielectric layer 401 and the first filling layer 312 is based on their different positions. The dielectric layer 401 is located directly above the first chip 200, and the first filling layer 312 is located directly above the first filling portion 311. Since the planarization will generate a bowl-shaped defect 308 on the upper surface of the first filling portion 311, after the insulating dielectric material 701 is deposited on the first filling portion 311, a bowl-shaped defect 308 will also be generated at the position of the insulating dielectric material 701 corresponding to the bowl-shaped defect 308 on the first filling portion 311.

[0087] The inventor of the present application has found that the main reason for the bowl-shaped defect 308 here is that the deposition process is generally a uniform deposition. However, due to the deposition of the insulating dielectric material 701, the insulating dielectric material 701 will slow down the bowl-shaped defect 308. Specifically, due to the uniform thickness of the deposited insulating dielectric material 701, the maximum depth of the bowl-shaped defect 308 does not change, but for the portion transitioning from the edge of the flat area to the edge of the bowl-shaped area, the insulating dielectric material 701 will slow down this portion of the area, similar to the deposition on a right-angled surface that will turn the deposited surface into a circular arc surface. Therefore, within a certain error range, it can be regarded that the diameter of the bowl-shaped defect 308 becomes smaller, and the diameter can refer to the maximum size of the opening perpendicular to the depth direction of the bowl-shaped defect 308.

[0088] like Figure 6E-6F As shown, the step of forming the dielectric layer 401 also includes forming the pattern of the wiring layer 402 by processes such as exposure, development, and etching. Fig. 6E The contact hole or through hole 702 for electrically connecting the wiring layer 402 with the first chip 200 and the annular groove 601 in which the support ring 600 is embedded in the first filling layer 312 are formed. Fig. 6F The wiring groove 703 is used to form the conductive connection line in the wiring layer 402.

[0089] like Figure 6G As shown, in order to form the wiring layer 402 and the support ring 600, a conductive material 704, such as copper, is deposited on the pattern formed on the wiring layer 402 and the first filling layer 312. In some processes, in order to ensure that the conductive material is evenly applied to the preset surface, a seed layer is formed on the preset surface by sputtering before this.

[0090] like Figure 6H As shown, in order to remove the excess conductive material 704, a planarization process such as chemical and physical polishing will be performed next. Before the planarization process, since the support ring 600 is embedded in the location of the bowl-shaped defect 308, the wear resistance of the entire bowl-shaped defect 308 area is changed, making it close to the area where the wiring layer 402 is located, thereby avoiding the bowl-shaped defect on the insulating dielectric material 701 being aggravated due to the poor wear resistance of the first filling layer 312. In addition, since the bowl-shaped defect 308 is reduced when the insulating dielectric material 701 is deposited, after the support ring 600 is set in the bowl-shaped defect 308, when the planarization process is performed, the support ring 600 provides support to protect the bowl-shaped area that is mitigated by the periphery of the support ring 600. As a result, the problem of forming a hole 306 in the second filling portion caused by the defect can be mitigated or avoided.

[0091] The redistribution layer 400 may include a multi-layer dielectric layer 401 and a wiring layer 402. The multi-layer dielectric layer 401 and the wiring layer 402 may be formed by multiple layers such as Figure 6B-Figure 6F The process shown is performed with support ring 600 being provided each time.

[0092] The semiconductor packaging structure 1 provided in the embodiment of the present application is described below with reference to several specific examples.

[0093] Example 1

[0094] return Figure 3 The semiconductor package structure 1 includes a substrate 100 and a filling portion 310 . The substrate 100 includes a substrate body 101 and a substrate interconnection layer 102 . The filling portion 310 includes a first filling portion 311 , a first filling layer 312 and a second filling portion 313 .

[0095] The upper surface of the substrate 100 is in close contact with the lower surface of the filling part 310 , that is, the upper surface of the substrate 100 is in close contact with the lower surface of the first filling part 311 .

[0096] The first filling layer 312 is provided between the first filling portion 311 and the second filling portion 313, so that the filling portion 310 is continuous in a direction perpendicular to the substrate surface. The inside of the filling portion 310 forms a region for encapsulating the components to be encapsulated.

[0097] Figure 4 yes Figure 3 Cross-sectional view along the A-A' direction. A first chip 200, a redistribution layer 400 and a second chip 500 are stacked on the upper surface of the substrate 100. The first chip 200 includes a first interconnection layer 202 and a first chip body 201, and the second chip includes a second interconnection layer 502 and a second chip body 501. The first chip 200 is bonded to the substrate interconnection layer 102 through the first interconnection layer 202, and a redistribution layer 400 is formed above the first chip 200. The redistribution layer 400 is electrically connected to the first chip through conductive wires in the through holes that penetrate the first chip body 201, and the second chip 500 is bonded to the redistribution layer 400 through the second interconnection layer 502. It can be understood that the redistribution layer and the chip can be stacked in sequence above the second chip 500 to achieve a higher degree of integration.

[0098] The first filling part 311 is disposed to surround the side surface of the first chip 200 . The first filling layer 312 is disposed to surround the side surface of the redistribution layer 400 . The second filling part 313 is disposed to surround the side surface of the second chip 500 , and the second filling part 313 covers the upper surface of the second chip 500 .

[0099] See also Figure 5A support ring 600 is embedded in the first filling layer 312, and the plane where the surface of the second chip 500 close to the first chip 200 is located is taken as the first reference plane, and the support ring 600 is located on the side of the first reference plane close to the substrate 100. In this case, the upper surface of the support ring 600 will not be higher than the lower surface of the second chip 500, thereby avoiding adverse effects when setting the second filling portion 313.

[0100] In some embodiments, in a direction perpendicular to the substrate, the support ring 600 penetrates the first filling layer 312 , that is, the lower surface of the support ring 600 contacts the first filling portion 311 , and the upper surface contacts the second filling portion 313 .

[0101] Please continue to see Fig. 7A , Fig. 7A yes Figure 3 The cross-sectional view along the BB' direction in FIG. The orthographic projection of the support ring 600 on the substrate 100 is arranged around the orthographic projection of the first chip 200, and the orthographic projection of the support ring 600 is arranged at an interval from the orthographic projection of the first chip 200. In some embodiments, a sealing ring 203 is arranged in the first chip 200, and the shape of the support ring 600 is the same as the shape of the sealing ring 203, that is, the support ring 600 is a shape that is proportionally enlarged by the sealing ring 203. For example, the distance from any point on the inner side of the orthographic projection of the support ring 600 on the substrate 100 to the orthographic projection of the sealing ring 203 on the substrate 100 is equal.

[0102] Regarding the packaging method of the semiconductor packaging structure 1 in this example, in some embodiments, a first chip 200 is placed on a substrate 100, and the first chip 200 is bonded to the substrate 100. A filling material 301 is filled around the first chip 200, and the upper surface of the filling material 301 and the first chip 200 are planarized.

[0103] After the flattening process, Fig. 8A As shown, a redistribution layer 400 , a first filling layer 312 , and a support ring 600 are provided.

[0104] like Figure 8B As shown, a second chip 500 is stacked on the redistribution layer 400 .

[0105] like Figure 8C As shown, the second chip 500 is continuously filled with the filling material 301, and the filling material 301 is also located above the first filling layer 312 to form a second filling portion 313. Thus, the main steps of preparing the semiconductor package structure 1 are completed.

[0106] Since the support ring 600 is disposed in the first filling layer 312 , when a planarization process is performed after the sputtering process is completed, the wear resistance of the area where the first filling layer 312 is located is improved, which helps to improve or avoid the bowl-shaped defect.

[0107] Example 2

[0108] Example 2 is different from Example 1 in the process of forming the redistribution layer 400 , the first filling layer 312 and the support ring 600 .

[0109] Please continue to see Figure 5 The redistribution layer 400 includes a dielectric layer 401 and a wiring layer 402, and the first filling layer 312 is disposed in the same layer as the dielectric layer 401, and the wiring layer 402 is disposed in the same layer as the support ring 600. It should be emphasized that the same layer arrangement is not limited to the position in the height direction, but refers to being formed simultaneously through the same process. Therefore, the first filling layer 312 and the dielectric layer 401 are made of the same material.

[0110] Specifically, an insulating dielectric material 701 is deposited on the planarized upper surface, and a photolithography process is performed on the insulating dielectric material 701 to form a dielectric layer 401 and contact holes or through holes 702 and a wiring groove 703 for forming a wiring layer 402 in the region directly above the first chip, and a first filling layer 312 and an annular groove 601 for accommodating a support ring 600 are formed in the region directly above the first filling portion 311. Thus, the dielectric layer 401 and the first filling layer 312 are arranged on the same layer, and by arranging them on the same layer, it is possible to avoid adding additional process steps and save costs.

[0111] Then, a conductive material is disposed in the contact hole or through hole 702, the wiring groove 703 and the annular groove 601 for accommodating the support ring 600 by a sputtering process and a planarization process is performed again, so that the wiring layer 402 and the support ring 600 are formed by the same layer arrangement. For a complex redistribution layer 400, a photolithography process, a sputtering process, and a planarization process can be performed multiple times to form a multi-layer dielectric layer 401, a wiring layer 402, a first filling layer 312 and a support ring 600. It is easy to understand that after planarization, the support ring 600 is embedded in the first filling layer 312. In the above preparation process, because the conductive material is disposed in the contact hole or through hole 702, the wiring groove 703 and the annular groove 601 for accommodating the support ring 600 by the same sputtering process, the support ring 600 and the wiring layer 402 are made of the same material.

[0112] Example 3

[0113] The difference between Example 3 and Example 1 and Example 2 lies in the setting time of the redistribution layer 400. In this example, the redistribution layer 400 can be formed on the first chip 200 before the first chip 200 is combined with the substrate. For example, the redistribution layer 400 can be formed on the first chip body 201 of the first chip 200 through a front-end process, or can be formed on the first chip 200 through an RDL (Redistribution Layer) process after the front-end process is completed and the substrate is cut to form the first chip 200.

[0114] After the first chip 200 is bonded to the substrate 100, the first chip 200 is filled with the filling material 301, and then the support ring 600 is arranged on the upper part of the first filling part 311 formed by the filling material 301. The arrangement method may also be a photolithography followed by sputtering method.

[0115] In order to prevent the filling material from blocking the bonding contacts on the redistribution layer 400 so as to facilitate the stacking of the second chip 500, it is also necessary to perform a planarization process on the redistribution layer 400 and the filling material 301. Similarly, during the planarization process, by providing a support ring 600 on the upper part of the first filling portion 311, the wear resistance of the area where the first filling layer 312 is located is improved, which helps to alleviate or avoid the concave area.

[0116] It can be seen from this that, in this example, the material of the support ring 600 can be selected based on the specific differences between the filling material 301 and the support ring 600, so that the wear resistance of the surface jointly formed by the support ring 600 and the filling material 301 is consistent with the wear resistance of the redistribution layer 400 on the first chip 200, thereby avoiding the bowl-shaped defect 308 as much as possible.

[0117] After planarization, the second chip 500 is stacked on the redistribution layer 400 and then the second chip 500 can be directly filled with a filling material around it to form a second filling portion 313. Therefore, the first filling portion 311 and the second filling portion 313 are arranged immediately adjacent to each other, that is, the first filling portion 311 and the second filling portion 313 are continuous in a direction perpendicular to the substrate 100. At this time, the filling portion 310 only includes the first filling portion 311 and the second filling portion 313.

[0118] Example 4

[0119] The difference between Example 4 and Examples 1 to 3 is the number of support rings 600. In Example 3, there are multiple support rings 600. In this example, two support rings 600 are used for illustration.

[0120] In some embodiments, Figure 7B yes Figure 3 Another cross-sectional view along the B-B' direction. Figure 7BAs shown, the support ring 600 includes a support ring 600a and a second support ring 600b.

[0121] Multiple support rings 600 are arranged radially from the inside to the outside. Specifically, the size of the support ring 600a is smaller than the second support ring 600b. The support ring 600a is arranged inside the second support ring 600b, and the outer wall of the support ring 600a is arranged at a certain distance from the inner wall of the second support ring 600b.

[0122] In this example, by providing a plurality of support rings 600, the wear resistance of the area where the first filling layer 312 or the first filling portion 311 is located can be improved during the flattening process, and the wear resistance of the area does not vary significantly within the area, thereby improving the uniformity of the wear resistance within the area, and helping to further alleviate or avoid concave areas.

[0123] In some embodiments, the cross section of the second support ring 600b has a width c2 in a direction parallel to the substrate 100, and the cross section of the support ring 600a has a width c1 in a direction parallel to the substrate 100, wherein c2 is greater than c1. For the semiconductor package structure 1 after singulation, in a direction parallel to the substrate 100, the bowl-shaped defect has a greater degree of depression at a location farther from the edge of the first chip 200, and therefore, the greater the width of the support ring 600 that is farther from the edge of the first chip 200 is set, the wear resistance of the area where it is located can be increased, and the bowl-shaped depression can be more compensated.

[0124] The present application also provides a packaging method for a semiconductor packaging structure 1, such as Fig. 9 As shown, the packaging method of the semiconductor packaging structure 1 includes: S10-S50.

[0125] S10, such as Figure 1A As shown, the first chip 200 is bonded to the substrate 100 .

[0126] In some embodiments, the substrate 100 includes a substrate body 101 and a substrate interconnection layer 102, and bonding contacts are provided on the substrate interconnection layer 102; the first chip 200 includes a first chip body 201 and a first interconnection layer 202, and bonding contacts are also provided on the first interconnection layer 202. The first interconnection layer 202 is placed on the substrate interconnection layer 102 so that the bonding contacts of the two are in one-to-one correspondence and bonding is performed.

[0127] For example, Figure 2AAs shown, multiple first chips 200 can be bonded to the same substrate 100, and the gaps between the multiple chips can be used as cutting paths to facilitate the singulation operation after the subsequent packaging is completed. In some embodiments, a first chip 200 can also be bonded to a substrate 100 separately, and a filling material is filled around the first chip 200 to cover the surface of the substrate 100. Therefore, after the semiconductor package structure 1 is formed by stacking the packages, the singulation operation may not be performed. However, in order to remove surface defects such as burrs of the semiconductor package structure 1, the surface of the formed semiconductor package structure 1 may be polished.

[0128] Here, the bonding may be eutectic bonding, metal thermocompression bonding, hybrid bonding, or the like.

[0129] S20, such as Figure 2B As shown, the first chip 200 is filled with a filling material 301 surrounding it.

[0130] After the filling material 301 surrounds the first chip 200, the bottom of the filling material 301 contacts the substrate 100, fills the gaps between the plurality of first chips 200, and contacts the first chip 200 from the side, thereby surrounding the side of the first chip 200. For example, in a direction perpendicular to the substrate 100, the height of the filling material 301 may be flush with the upper surface of the first chip 200.

[0131] The height of the filling material 301 is higher than the upper surface of the first chip 200, or even covers the upper surface of the first chip 200. Therefore, a planarization process is required to expose the upper surface of the first chip 200. The planarization process can be performed by chemical mechanical polishing, etching or other suitable processes.

[0132] At this time, the filling material 301 only includes the portion surrounding the side of the first chip, thereby forming a first filling portion 311. It is desirable that, after the planarization process, the upper portion of the first chip 200 is flush with the upper surface of the first filling portion 311 and is in the same plane. However, due to the different wear resistance or corrosion resistance of the filling material 301 and the upper surface of the first chip 200, a bowl-shaped depression 308 is formed on the upper surface of the first filling portion 311 formed after the planarization process of the filling material 301, such as Figure 6C The bowl-shaped depression 308 will have an adverse effect on the packaging and should be avoided as much as possible.

[0133] S30, such as Figure 6D-6G As shown, a redistribution layer 400 , a first filling layer 312 surrounding the redistribution layer 400 , and a supporting ring 600 embedded in the first filling layer 312 are formed over a surface of the first chip 200 away from the substrate 100 .

[0134] Specifically, Fig.6DAs shown, an insulating dielectric material 701 is deposited on the surface formed by the first chip 200 and the first filling portion 311. The insulating dielectric material 701 is generally silicon nitride, silicon dioxide, etc. The insulating dielectric material 701 is generally deposited by chemical vapor deposition (CVD), and it can be considered that the insulating dielectric material 701 is uniformly deposited on the upper surface of the first chip 200 and the first filling portion 311. Due to the deposition of the insulating dielectric material 701, the insulating dielectric material 701 can alleviate the bowl-shaped defect 308.

[0135] like Figure 6E-6F As shown, a photolithography process is performed on the insulating dielectric material 701 to form a dielectric layer 401 with contact holes or through holes 702 and wiring grooves 703 above the first chip 200, and a first filling layer 312 with a support ring 600 is formed above the first filling portion 311. It can be understood that the dielectric layer 401 and the first filling layer 312 are formed simultaneously by the same process, that is, they are arranged in the same layer. The basis for distinguishing the dielectric layer 401 from the first filling layer 312 is based on their locations.

[0136] like Figure 6G-6H As shown, a conductive material 704 is deposited in the contact hole or through hole 702, the wiring groove 703 and the annular groove 601 formed by processes such as photolithography and etching to form the wiring layer 402 and the support ring 600 of the redistribution layer 400. The conductive material 704 is generally deposited by physical vapor deposition (PVD), and can also be deposited by CVD. The conductive material 704 is generally made of copper. Before depositing the conductive material 704, an isolation layer and a seed layer need to be set on the surface to prevent the conductive material from diffusing into the insulating dielectric material and affecting the insulation.

[0137] Similarly, in order to ensure the conductivity of the wiring layer 402, it is necessary to ensure that the contact hole or through hole 702, the wiring groove 703 and the annular groove 601 are filled when the conductive material 704 is deposited. Therefore, the conductive material 704 will overflow the contact hole or through hole 702, the wiring groove 703 and the annular groove 601, and a planarization process is required to remove the overflowed conductive material 704. Thus, the conductive material 704 above the first chip 200 forms the wiring layer 402, and the conductive material 704 above the first filling portion 311 forms the support ring 600.

[0138] Since the support ring 600 formed of a conductive material is added to the first filling layer 312, the wear resistance or corrosion resistance of the area where the first filling layer 312 is located is improved, and the support ring 600 provides support. Therefore, when the conductive material 704 is removed by planarization, the planarization rate of the area where the first filling layer 312 is located will be slowed down, thereby improving the bowl-shaped depression in this area.

[0139] In some embodiments, the redistribution layer 400 has multiple dielectric layers 401 and wiring layers 402. In this case, the first filling layer 312 also has multiple layers. The layers in which the support ring 600 is formed can be selected according to the degree of the bowl-shaped defect. For example, see Fig.6I , the dielectric layer 401 and the wiring layer 402 have two layers, but the support ring 600 only exists in a layer far from the first chip 200, and the method for implementing this is that when performing photolithography, etching and other processes on a layer close to the first chip 200, an annular groove 601 for setting the support ring 600 corresponding to the layer is not formed in the insulating dielectric material, so that when depositing the conductive material 704, the part of the support ring 600 corresponding to the layer will not be formed in the annular groove 601. Thus, in some embodiments, the support ring 600 is located on one side of the plane where the surface of the first chip 200 close to the second chip 500 is located, that is, the setting position of the support ring 600 is not lower than the upper surface of the first chip 200, or, in other words, at this time, the support ring 600 is located between the first chip 200 and the second chip 500.

[0140] It can be understood that in order to achieve electrical connection between the redistribution layer 400 and the second chip 500 , bonding contacts are further provided on the redistribution layer 400 .

[0141] Thus, the formed support ring 600 is located at the periphery of the redistribution layer 400 , and the first filling layer 312 is in contact with the first filling portion 311 . The orthographic projection of the support ring 600 on the substrate 100 surrounds the orthographic projection of the first chip 200 on the substrate 100 .

[0142] S40, such as Figure 8B As shown, the first surface of the second chip 500 is bonded to the redistribution layer 400 .

[0143] Bonding the first surface of the second chip 500 to the redistribution layer 400 is similar to bonding the first chip 200 to the substrate 100 , and will not be described again herein.

[0144] Since the second chip 500 is bonded to the redistribution layer 400 after the redistribution layer 400 and the first filling layer 312 are planarized, it can be seen that if the plane where the lower surface of the second chip 500 is located is the first reference plane, the support ring 600 is located on the side of the first reference plane close to the substrate 100.

[0145] S50, such as Figure 8C As shown, the filling material 301 is used to fill the side of the second chip 500 to form a second filling portion 313 surrounding the second chip 500 .

[0146] The lower surface of the filled filling material 301 contacts the redistribution layer 400 and surrounds the side of the second chip 500. It can be understood that when only two chips are stacked, the filling material 301 can cover the upper surface of the second chip 500, isolating the semiconductor package structure 1 from the external environment, thereby providing a stable environment for the first chip 200 and the second chip 500 inside the semiconductor package structure 1, and improving the service life of the semiconductor package structure 1.

[0147] In addition, since the support ring 600 is provided when the redistribution layer 400 and the first filling layer 312 are formed, the bowl-shaped defect on the first filling layer 312 is improved, thereby avoiding the formation of the hole 306 in the second filling portion 313, and improving the stability of the semiconductor package structure 1. In some embodiments, a plurality of first chips 200 and a plurality of second chips 500 are stacked and packaged on a substrate 100. Since the support ring 600 is provided on the periphery of the redistribution layer 400, the integrity of the redistribution layer 400 can be ensured when the semiconductor package structure 1 is singulated, thereby improving the yield rate.

[0148] The present application also provides an electronic device 20, which is a type of electronic device with functions such as data storage and / or program running, and includes any of the above-mentioned semiconductor packaging structures 1. Specifically, the electronic device includes but is not limited to mobile phones, tablet personal computers, laptop computers, personal digital assistants (PDAs), personal computers, notebook computers, vehicle-mounted devices, wearable devices, etc. Among them, wearable devices include but are not limited to smart bracelets, smart watches, smart head-mounted displays, smart glasses, etc.

[0149] This application takes the electronic device 20 as a laptop computer as an example for explanation. Fig.10The figure shows a schematic diagram of the structure of a laptop computer. The core components of the laptop computer include a computer motherboard 10, which is responsible for connecting various hardware devices and providing power supply and data transmission. There are many different components on the motherboard, including a processor chip 11, a memory chip 12, a power socket 13, a USB interface 14, an IDE serial port 15, etc. The computer motherboard is a printed circuit board (PCB). The main function of the motherboard is to transmit electrical signals between the components on the motherboard, and the electrical signal transmission of various chips is very frequent, especially the processor chip 11. According to the function, the chip can include a processor chip, a memory chip, a power chip, etc. The way the chip is combined with the motherboard varies according to the specific application scenario. For example, in order to improve the scalability of the laptop computer, the chip can be combined with the motherboard through a slot; and in order to ensure high-quality electrical connection, the chip can be combined with the motherboard by welding. For example, the processor chip 11 is generally installed on the motherboard 10 by welding, while the memory chip is installed on the motherboard 10 by a slot.

[0150] In some embodiments, the semiconductor packaging structure 1 may be a memory chip 12 of a laptop computer. The memory chip 12 stacks and packages multiple single memory chips. The memory chip 12 is installed on a computer motherboard and is connected to a power supply, input / output devices, etc. through the printed circuit board.

[0151] In other embodiments, the semiconductor packaging structure 1 may include a processor chip and a memory chip. The processor chip and the memory chip are stacked and packaged to form the semiconductor packaging structure 1, which is then installed on a computer motherboard and electrically connected to other components on the computer motherboard.

[0152] The above are only specific implementations of the present application, but the protection scope of the application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: A substrate, and a first chip and a second chip stacked on the substrate, wherein the first chip is located between the substrate and the second chip; a filling portion, surrounding the side surfaces of the first chip and the second chip and being continuous in a direction perpendicular to the substrate; A support ring, wherein the orthographic projection of the support ring on the substrate surrounds the orthographic projection of the first chip on the substrate, the support ring is embedded in the filling portion, and is located on a side of a first reference plane close to the substrate, and the first reference plane is a plane where a surface of the second chip close to the first chip is located.

2. The semiconductor package structure according to claim 1, wherein: The support ring is located between the first reference plane and the second reference plane, and the second reference plane is a plane where the surface of the first chip close to the second chip is located.

3. The semiconductor packaging structure according to any one of claims 1 to 2, characterized in that: A redistribution layer is arranged on a surface of the first chip away from the substrate, and the redistribution layer includes a dielectric layer; the filling part includes a first filling layer, and the first filling layer surrounds at least a part of the area between the first chip and the second chip; the material of the first filling layer is the same as that of the dielectric layer, and the support ring is embedded in the first filling layer.

4. The semiconductor package structure according to claim 3, characterized in that: The first filling layer is arranged on the same layer as the dielectric layer.

5. The semiconductor package structure according to claim 3, characterized in that: The redistribution layer further comprises a plurality of wiring layers, which are stacked and arranged in a direction perpendicular to the substrate; the wiring layers are embedded in the dielectric layer, and the material of the support ring is the same as that of the wiring layers.

6. The semiconductor package structure according to claim 5, characterized in that: The support ring is arranged in the same layer as at least one of the wiring layers which is farthest from the substrate.

7. The semiconductor package structure according to claim 5, characterized in that: A surface of the support ring facing away from the substrate is flush with a surface of the wiring layer farthest from the substrate facing away from the substrate.

8. The semiconductor package structure according to claim 3, wherein: The support ring penetrates the first filling layer in a direction perpendicular to the substrate.

9. The semiconductor packaging structure according to any one of claims 3 to 8, characterized in that: The filling part further includes a first filling part, which is located between the first filling layer and the substrate and surrounds a side surface of the first chip; and a material of the first filling layer is different from that of the first filling part.

10. The semiconductor package structure according to claim 9, wherein: The filling portion further includes a second filling portion disposed on a side of the first filling layer away from the substrate, the second filling portion surrounding a side surface of the second chip; and a material of the first filling layer is different from that of the second filling portion.

11. The semiconductor package structure according to any one of claims 1 to 10, characterized in that: The number of the support rings is multiple and they are arranged radially from inside to outside in a direction parallel to the substrate.

12. The semiconductor package structure according to claim 11, characterized in that: Among the adjacent support rings, the width of the support ring located on the inner side is greater than the width of the support ring located on the outer side, and the width is the dimension in a direction parallel to the substrate.

13. A packaging method for a semiconductor packaging structure, characterized in that: include: bonding the first chip to the substrate; Filling the first chip with a filling material to form a first filling portion surrounding a side surface of the first chip; forming a redistribution layer, a first filling layer surrounding the redistribution layer, and a support ring located in the first filling layer on a surface of the first chip away from the substrate, wherein the first filling layer is in contact with the first filling portion, and the orthographic projection of the support ring on the substrate surrounds the orthographic projection of the first chip on the substrate; bonding a second chip to the redistribution layer; The second chip is filled with a filling material around its side surface to form a second filling portion surrounding the second chip, wherein the second filling portion is in contact with the first filling layer.

14. The method according to claim 13, characterized in that The redistribution layer includes a dielectric layer and a wiring layer, and the first filling layer and the dielectric layer are formed simultaneously.

15. The method according to claim 14, characterized in that The support ring is formed simultaneously with at least a portion of the wiring layer.

16. An electronic device, characterized in that: The invention comprises a semiconductor package structure and a printed circuit board according to any one of claims 1 to 12, wherein the semiconductor package structure is combined with the printed circuit board.

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