Low-power-consumption broadband continuous time linear equalizer

Abstract

The invention discloses a continuous time linear equalizer which comprises a transconductance circuit, a transimpedance amplifier circuit and a common-mode voltage feedback circuit. The transconductance circuit comprises a pair of PMOS (P-channel Metal Oxide Semiconductor) tubes, a pair of NMOS (N-channel Metal Oxide Semiconductor) tubes, six current sources and two RC (Resistance-Capacitance) networks; two branches are arranged between the power supply and the ground. A grid electrode of the first PMOS tube is connected with a grid electrode of the first NMOS tube, a grid electrode of the second PMOS tube is connected with a grid electrode of the second NMOS tube, and the first PMOS tube and the second PMOS tube respectively receive a pair of differential input voltages. The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and a pair of differential intermediate signals is output respectively. The circuit is simple in structure and only has a primary circuit; a complementary structure of PMOS input geminate transistors and NMOS input geminate transistors is adopted, bias current is utilized to the maximum extent, power consumption is low, and compared with a traditional circuit, the current utilization rate is improved; balancing of a wide frequency band can be realized under the condition of low power consumption, and the gain is high.

Description

Technical Field

[0001] The present application relates to a continuous time linear equalization (CTLE) in a wireless communication system. Background Art

[0002] The continuous time linear equalizer is an equalizer device often used at the receiving end of a wireless communication system. CTLE is usually located at the front-end circuit of the receiver of a wireless communication system, and its performance has a great impact on the performance of the entire receiver.

[0003] See also Figure 1 This is an existing continuous time linear equalizer, including a transconductance circuit, a transimpedance amplifier circuit, and a common mode voltage feedback circuit. Among them, the transconductance circuit converts a pair of differential input voltages Vip and Vin into current (transconductance means voltage to current) to obtain a pair of differential intermediate signals Xp and Xm. The transimpedance amplifier circuit increases the transimpedance of a pair of differential intermediate signals Xp and Xm to obtain a pair of differential output voltages Vop and Vom. The common mode voltage feedback circuit obtains a feedback voltage Vcmfb from a pair of differential output voltages Vop and Vom, and feeds it back to the transconductance circuit.

[0004] See also Figure 2 ,This is Figure 1 An existing structure of a transconductance circuit in. There are two branches between the power supply and the ground, the first branch includes a current source I1 and a PMOS tube P1, and the second branch includes a current source I2 and a PMOS tube P2. One pair of PMOS tubes P1 and P2 can also be changed to a pair of NMOS tubes. The devices at the same position on the two branches have the same parameters. The RC (resistance and capacitance) network connects the output ends of the two current sources I1 and I2, that is, connects the sources of the two PMOS tubes P1 and P2. A pair of differential input voltages Vip and Vin are connected to the gates of the two PMOS tubes P1 and P2 as the input signals of the transconductance circuit. The drains of the two PMOS tubes P1 and P2 output a pair of differential intermediate signals Xp and Xm as the output signals of the transconductance circuit. The function of the transconductance circuit is to provide transconductance Gm, thereby providing gain for the CTLE. The gain Gain of the CTLE = Gm × R, and R is provided by the transimpedance amplifier circuit. The gain provided by the transconductance circuit is used to amplify the amplitude of the input signal. The source of the PMOS tube is connected to a p-type current source, the gate is connected to the input, and the drain is connected to the output. This structure is a classic structure that provides transconductance. The RC network compensates for the high-frequency gain loss of the signal during transmission, while reducing the low-frequency gain to achieve the gain balance within the frequency band. This is also the practice of the classic equalizer circuit.

[0005] Existing CTLEs usually use the architecture of transconductance circuits and transimpedance amplifier circuits. Transconductance circuits generally only have PMOS differential pairs or NMOS differential pairs. In order to obtain higher gain, CTLEs must either increase power consumption or increase the number of circuit stages. However, more circuit stages will lead to lower bandwidth and reduce the performance of CTLE. Summary of the invention

[0006] The technical problem to be solved by the present application is: how to enable a continuous-time linear equalizer to achieve a wider frequency band with low power consumption, thereby achieving a balance between the two.

[0007] In order to solve the above technical problems, the present application proposes a continuous time linear equalizer, including three parts: a transconductance circuit, a transimpedance amplifier circuit, and a common mode voltage feedback circuit; the transconductance circuit includes a pair of PMOS tubes, a pair of NMOS tubes, six current sources, and two RC networks; there are two branches between the power supply and the ground. The first branch is connected in series from the power supply to the ground with a current source 1, a PMOS tube 1, an NMOS tube 1, and a current source 5; the source of the PMOS tube 1 is connected to the output end of the current source 1, the drain of the PMOS tube 1 is connected to the drain of the NMOS tube 1, and the source of the NMOS tube 1 is connected to the input end of the current source 5; in addition, the output end of the current source 3 is connected to the output end of the current source 1, and is connected to the source of the PMOS tube 1. The second branch is connected in series from the power supply to the ground in sequence with current source 2, PMOS tube 2, NMOS tube 2, and current source 6; the source of PMOS tube 2 is connected to the output end of current source 2, the drain of PMOS tube 2 is connected to the drain of NMOS tube 2, and the source of NMOS tube 2 is connected to the input end of current source 6; the output end of current source 4 is connected to the output end of current source 2 and connected to the source of PMOS tube 2. The devices at the same position on the two branches have the same parameters. The gate of PMOS tube 1 is connected to the gate of NMOS tube 1, and the gate of PMOS tube 2 is connected to the gate of NMOS tube 2, and they receive a pair of differential input voltages respectively; the drain of PMOS tube 1 is connected to the drain of NMOS tube 1, and the drain of PMOS tube 2 is connected to the drain of NMOS tube 2, and they output a pair of differential intermediate signals respectively.

[0008] Furthermore, current source one, current source two, current source three, and current source four are p-type current sources; current source five and current source six are n-type current sources.

[0009] Furthermore, current source one and current source two are fixed current sources; current source three and current source four are current sources controlled by feedback voltage; when the feedback voltage increases, the current output by current source three and current source four decreases, and vice versa; current source five and current source six are current sources controlled by Vbn voltage; when the Vbn voltage increases, the current output by current source five and current source six increases, and vice versa.

[0010] Furthermore, the currents output by the p-type current source and the n-type current source are equal, that is, the current output by current source one + the current output by current source three = the current output by current source five, and the current output by current source two + the current output by current source four = the current output by current source six.

[0011] Furthermore, the RC network 1 connects the sources of the two PMOS tubes; the RC network 2 connects the sources of the two NMOS tubes; the RC network 1 and the RC network 2 are used to adjust the peak frequency of the continuous time linear equalizer.

[0012] Furthermore, a pair of PMOS tubes provides transconductance, a pair of NMOS tubes also provides transconductance, and the transconductances provided by the two pairs of MOS tubes are superimposed; a pair of PMOS tubes and a pair of NMOS tubes share the same current source.

[0013] Furthermore, the common-mode voltage and feedback voltage of a pair of differential input voltages are sent to the transconductance circuit replica circuit, and the transconductance circuit replica circuit outputs a Vbn voltage; the transconductance circuit replica circuit is the left half or right half of a bilaterally symmetrical transconductance circuit, while omitting the intermediate signal output of the left half or right half of the transconductance circuit, and changing the input signal position of the left half or right half of the transconductance circuit to input the common-mode voltage of the differential input voltage at that position, and changing the Vbn voltage input position of the left half or right half of the transconductance circuit to output the Vbn voltage at that position.

[0014] Furthermore, the transimpedance amplifier circuit includes a differential amplifier and two feedback resistors; the differential amplifier increases the transimpedance of a pair of differential intermediate signals to obtain a pair of differential output signals; feedback resistor three is connected to output terminal one and input terminal one of the differential amplifier, and feedback resistor four is connected to output terminal two and input terminal two of the differential amplifier.

[0015] Furthermore, the common-mode voltage feedback circuit includes a common-mode voltage extraction circuit, a transimpedance circuit replica circuit, and an operational amplifier; the common-mode voltage extraction circuit is used to extract the common-mode voltage of a pair of differential output signals; the transimpedance circuit replica circuit is a transimpedance amplifier circuit that is symmetrical up and down, but only uses the upper half of the input and output or the lower half of the input and output of the transimpedance amplifier circuit; the input terminal 1 of the operational amplifier receives the common-mode voltage output by the common-mode voltage extraction circuit, the input terminal 2 receives the absolute value of the voltage output by the transimpedance circuit replica circuit, and the output terminal of the operational amplifier outputs the feedback voltage; the function of the common-mode voltage feedback circuit is to make the output common-mode voltage of the transimpedance amplifier circuit and the output voltage of the transimpedance circuit replica circuit equal.

[0016] The technical effects achieved by the present application are: the circuit structure is simple, with only one level of circuit; the complementary structure of the PMOS input pair and the NMOS input pair is adopted to maximize the use of the bias current, with low power consumption, and improved current utilization compared to traditional circuits; and equalization of a wider frequency band can be achieved with lower power consumption under the same gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The invention is a circuit diagram of an existing continuous-time linear equalizer.

[0018] Figure 2 is a schematic diagram of an existing transconductance circuit.

[0019] Figure 3 is a schematic diagram of a transconductance circuit in a CTLE proposed in this application.

[0020] Figure 4 yes Figure 3 Schematic diagram of a block diagram of a circuit for generating a Vbn voltage.

[0021] Figure 5 yes Figure 3 Detailed schematic diagram of the Vbn voltage generation circuit.

[0022] Figure 6 is a schematic diagram of a transimpedance amplifier circuit in a CTLE proposed in the present application.

[0023] Figure 7 is a schematic diagram of a common-mode voltage feedback circuit in a CTLE proposed in this application.

[0024] Explanation of the reference numerals in the figure: Vip and Vin are a pair of differential input voltages; Xp and Xm are a pair of differential intermediate signals; Vop and Vom are a pair of differential output voltages; Vcmfb is the feedback voltage; I1 to I6 are current sources; P1 and P2 are PMOS tubes; N1 and N2 are NMOS tubes; Vbn is the gate voltage of the NMOS tube in the n-type current source; R3 and R4 are resistors; Vout_cm is the common mode voltage of the differential output voltages Vop and Vom; A1 is a differential amplifier; A2 is an operational amplifier. DETAILED DESCRIPTION

[0025] See also Figure 1, the continuous time linear equalizer proposed in this application also includes three parts: a transconductance circuit, a transimpedance amplifier circuit, and a common-mode voltage feedback circuit. The transconductance circuit converts a pair of differential input voltages Vip and Vin into currents to obtain a pair of differential intermediate signals Xp and Xm to provide transconductance gm. The transimpedance amplifier circuit increases the transimpedance of a pair of differential intermediate signals Xp and Xm to obtain a pair of differential output voltages Vop and Vom to provide resistance R while maintaining sufficient bandwidth. The gain Gain of CTLE = Gm × R. The common-mode voltage feedback circuit collects the common-mode voltage Vout_cm of a pair of differential output voltages Vop and Vom, obtains the feedback voltage Vcmfb by calculation, and feeds it back to the transconductance circuit to adjust the common-mode voltage of the transconductance circuit. The common-mode voltage feedback circuit is used to adjust the transconductance circuit to a suitable common-mode voltage to reduce the impact of the common-mode voltage deviation on the CTLE gain performance. The common-mode voltage of the transconductance circuit has an optimal value (maximum gain). Any deviation from this optimal value means that the common-mode voltage has a deviation. The common-mode voltage that allows the operating point of the transconductance circuit to play the greatest role (maximum gain) is the appropriate common-mode voltage.

[0026] See also Figure 3 This is the transconductance circuit in the CTLE proposed in the present application, including a pair of PMOS tubes P1 and P2, a pair of NMOS tubes N1 and N2, six current sources I1 to I6, and two RC networks. There are two branches between the power supply and the ground. The first branch is connected in series with a current source I1, a PMOS tube P1, an NMOS tube N1, and a current source I5 from the power supply to the ground. The source of the PMOS tube P1 is connected to the output end of the current source I1, the drain of the PMOS tube P1 is connected to the drain of the NMOS tube N1, and the source of the NMOS tube N1 is connected to the input end of the current source I5. In addition, the output end of the current source I3 is connected to the output end of the current source I1 and is connected to the source of the PMOS tube P1. The second branch is connected in series with a current source I2, a PMOS tube P2, an NMOS tube N2, and a current source I6 from the power supply to the ground. The source of the PMOS tube P2 is connected to the output end of the current source I2, the drain of the PMOS tube P2 is connected to the drain of the NMOS tube N2, and the source of the NMOS tube N2 is connected to the input end of the current source I6. In addition, the output end of the current source I4 is connected to the output end of the current source I2 and connected to the source of the PMOS tube P2. The devices at the same position on the two branches have the same parameters. The gate of the PMOS tube P1 is connected to the gate of the NMOS tube N1, and the gate of the PMOS tube P2 is connected to the gate of the NMOS tube N2, and respectively receive a pair of differential input voltages Vip and Vin as input signals of the transconductance circuit. The drain of the PMOS tube P1 is connected to the drain of the NMOS tube N1, and the drain of the PMOS tube P2 is connected to the drain of the NMOS tube N2, and respectively output a pair of differential intermediate signals Xm and Xp as output signals of the transconductance circuit.

[0027] Figure 3 In the transconductance circuit shown, current source 1 I1, current source 2 I2, current source 3 I3, and current source 4 I4 are all p-type current sources. A p-type current source refers to a current source composed of a PMOS tube, the gate of which is connected to a fixed voltage (the gates of current sources I3 and I4 are connected to a feedback voltage Vcmfb), and this fixed voltage determines the current size of the p-type current source. The source of the PMOS tube is connected to the power supply, and the drain of the PMOS tube outputs current. Current source 5 I5 and current source 6 I6 are both n-type current sources. An n-type current source refers to a current source composed of an NMOS tube, the gate of which is connected to a fixed voltage, and this fixed voltage determines the current size of the n-type current source. The source of the NMOS tube is grounded, and the drain of the NMOS tube outputs current.

[0028] Figure 3 In the transconductance circuit shown, current source 1 I1 and current source 2 I2 are fixed current sources. Current source 3 I3 and current source 4 I4 are current sources controlled by feedback voltage Vcmfb. When the feedback voltage Vcmfb increases, the current output by I3 and I4 decreases, and vice versa. Current source 5 I5 and current source 6 I6 are current sources controlled by Vbn voltage. When the Vbn voltage increases, the current output by I5 and I6 increases, and vice versa.

[0029] Figure 3 In the transconductance circuit shown, the currents output by the p-type current source and the n-type current source are equal, that is, I1+I3=I5, I2+I4=I6, ensuring that no static current flows out of the transconductance circuit, and no static current flows into the transconductance circuit from the outside. At the same time, the transconductance of the PMOS differential pair P1, P2 and the NMOS differential pair N1, N2 are equal, so that the transconductance circuit obtains the maximum transconductance under a given current condition.

[0030] Figure 3 In the transconductance circuit shown, RC network 1 connects the sources of two PMOS tubes P1 and P2. RC network 2 connects the sources of two NMOS tubes N1 and N2. RC network 1 and RC network 2 are used to adjust the peak frequency of CTLE. Perform a zero-pole analysis on the RC network. Each RC network provides a zero point and a pole. The zero point can increase the gain, and the pole can reduce the gain. By controlling the position of the zero and pole, the peak frequency can be adjusted.

[0031] Figure 3In the transconductance circuit shown, the gates of the cascaded PMOS tube P1 and NMOS tube N1 are connected, and the gates of the cascaded PMOS tube P2 and NMOS tube N2 are connected, respectively serving as a pair of differential signal input terminals. The drains of the cascaded PMOS tube P1 and NMOS tube N1 are connected, and the drains of the cascaded PMOS tube P2 and NMOS tube N2 are connected, respectively serving as a pair of differential signal output terminals. A pair of PMOS tubes P1 and P2 provide transconductance, and a pair of NMOS tubes N1 and N2 also provide transconductance, and the transconductances of these two pairs of MOS tubes are superimposed, which is Figure 2 The transconductance of the conventional transconductance circuit shown in FIG. 1 is twice that of the conventional transconductance circuit shown in FIG. The PMOS differential pair P1, P2 and the NMOS differential pair N1, N2 share the same current source, increasing the transconductance without increasing the power consumption. When the power consumption is the same, the transconductance circuit ( Figure 3 The transconductance of the circuit is the existing transconductance circuit ( Figure 2 The transconductance of the present invention is twice that of the transconductance of Figure 3 The gain of the existing transconductance circuit ( Figure 2 twice the gain of .

[0032] See also Figure 4 ,This is Figure 3 The Vbn voltage generation circuit in the FIG. A pair of differential input voltages Vip and Vin, a common mode voltage (|Vip|+|Vin|)÷2 and a feedback voltage Vcmfb are fed into the transconductance circuit replica circuit to obtain the Vbn voltage. Figure 3 The transconductance circuit shown is a bilaterally symmetrical structure. Figure 4 The transconductance circuit replica circuit in Figure 3 The transconductance circuit shown is the left half circuit or the right half circuit after omitting the two RC networks, and the Vbn voltage represents the gate voltage of the NMOS tube in the n-type current sources I5 and I6.

[0033] See also Figure 5 ,This is Figure 3 The left half of the transconductance circuit shown in the figure after omitting the two RC networks can be used as the Vbn voltage generation circuit proposed in the present application. Figure 5 In the Vbn voltage generation circuit shown, the Figure 3 The Xm signal output in Figure 3 The input Vip position in is changed to Figure 5 In this position, the differential input voltage Vip and the common mode voltage of Vin (|Vip|+|Vin|)÷2 are input, and at the same time Figure 3 Change the input position of Vbn to Figure 5 The Vbn voltage is output at this position.

[0034] See also Figure 6This is the transimpedance amplifier circuit in the CTLE proposed in the present application, including a differential amplifier A1, two feedback resistors R3 and R4. The differential amplifier A1 increases the transimpedance of a pair of differential intermediate signals Xp and Xm to obtain a pair of differential output signals Vom and Vop. Feedback resistor three R3 connects the output terminal one and input terminal one of the differential amplifier A1, and feedback resistor four R4 connects the output terminal two and input terminal two of the differential amplifier A1. The differential amplifier A1 provides sufficient transconductance to obtain sufficient impedance. The size of the feedback resistors R3 and R4 can be adjusted, and the peak amplitude (peaking) value of the CTLE can be adjusted by adjusting the load.

[0035] See also Figure 7 This is the common-mode voltage feedback circuit in the CTLE proposed in this application, including a common-mode voltage extraction circuit, a transimpedance circuit replica circuit, and an operational amplifier A2. The common-mode voltage extraction circuit is used to extract the common-mode voltage Vout_cm of a pair of differential output signals Vom and Vop, where Vout_cm = (|vop| + |vom|) ÷ 2. Figure 5 The transimpedance amplifier circuit shown is a vertically symmetrical structure. Figure 6 The replica circuit of the transimpedance circuit in Figure 5 The transimpedance amplifier circuit shown in Figure 5 The upper half of the input and output or the lower half of the input and output. The transimpedance circuit replica circuit outputs Vom or Vop, and the absolute values ​​of the two are the same. Input terminal one of the operational amplifier A2 receives the common-mode voltage Vout_cm output by the common-mode voltage extraction circuit, and input terminal two receives the absolute value of the voltage Vom or Vop output by the transimpedance circuit replica circuit, and the output terminal of the operational amplifier A2 outputs the feedback voltage Vcmfb. When input terminal one of the operational amplifier A2 is greater than input terminal two, the feedback voltage Vcmfb at the output terminal decreases. When input terminal one of the operational amplifier A2 is less than input terminal two, the feedback voltage Vcmfb at the output terminal increases. When input terminal one of the operational amplifier A2 is equal to input terminal two, the feedback voltage Vcmfb at the output terminal remains unchanged. Therefore, the function of the common-mode voltage feedback circuit is to make the output common-mode voltage (Vout_cm) of the transimpedance amplifier circuit and the output voltage (absolute value of Vom or Vop) of the transimpedance circuit replica circuit equal. Since the output voltage of the transimpedance circuit replica circuit (the absolute value of Vom or Vop) and the input common-mode voltage of the transimpedance amplifier circuit (i.e., the output common-mode voltage of the transconductance circuit, the common-mode voltage of Xp and Xm) are equal, the output of the common-mode voltage feedback circuit (Vcmfb) adjusts the p-type current source (I3, I4) in the transconductance circuit, thereby making the output common-mode voltage of the transconductance circuit (the common-mode voltage of Xp and Xm) equal to the output common-mode voltage (Vout_cm) of the transimpedance amplifier circuit.

[0036] The CTLE circuit proposed in the present application has lower power consumption and larger bandwidth under the condition of the same gain.

[0037] Under the same gain condition, the transconductance circuit proposed in this application ( Figure 3 The transconductance Gm of the traditional transconductance circuit ( Figure 2 The gain of CTLE is Gain = Gm × R. If the traditional CTLE wants to obtain the same gain as the CTLE proposed in this application, there are two solutions for the traditional CTLE. The first is to use a two-stage CTLE circuit in cascade, Gain1 × Gain2 = Gain. The disadvantage of the two-stage CTLE circuit compared to the single-stage CTLE circuit is that the power consumption is higher (twice the current drive) under the same bandwidth, and the bandwidth is lower (more components) under the same power consumption. The second is to use a one-stage CTLE circuit structure to increase the transconductance Gm. The price paid is either a larger size of the PMOS and NMOS tubes (in order to make the current larger), which will reduce the bandwidth; or a larger p-type current source (greater power consumption). The above is only a theoretical analysis. The actual circuit is likely to have a lower bandwidth and higher power consumption, depending on the circuit manufacturing process.

[0038] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should all be included in the protection scope of the present application.

Claims

1. A continuous time linear equalizer, comprising a transconductance circuit, a transimpedance amplifier circuit, and a common mode voltage feedback circuit; wherein: The transconductance circuit includes a pair of PMOS tubes, a pair of NMOS tubes, six current sources, and two RC networks; and has two branches between the power supply and the ground; The first branch is connected in series from the power supply to the ground in sequence with current source 1, PMOS tube 1, NMOS tube 1, and current source 5; the source of PMOS tube 1 is connected to the output end of current source 1, the drain of PMOS tube 1 is connected to the drain of NMOS tube 1, and the source of NMOS tube 1 is connected to the input end of current source 5; the output end of current source 3 is connected to the output end of current source 1, and is also connected to the source of PMOS tube 1; The second branch is connected in series from the power supply to the ground, with current source 2, PMOS tube 2, NMOS tube 2, and current source 6 in sequence; the source of PMOS tube 2 is connected to the output end of current source 2, the drain of PMOS tube 2 is connected to the drain of NMOS tube 2, and the source of NMOS tube 2 is connected to the input end of current source 6; the output end of current source 4 is connected to the output end of current source 2, and is also connected to the source of PMOS tube 2; The devices at the same position on the two branches have the same parameters; The gate of PMOS tube 1 is connected to the gate of NMOS tube 1, and the gate of PMOS tube 2 is connected to the gate of NMOS tube 2, respectively receiving a pair of differential input voltages; the drain of PMOS tube 1 is connected to the drain of NMOS tube 1, and the drain of PMOS tube 2 is connected to the drain of NMOS tube 2, respectively outputting a pair of differential intermediate signals.

2. The continuous time linear equalizer according to claim 1, characterized in that: Current source one, current source two, current source three, and current source four are p-type current sources; current source five and current source six are n-type current sources.

3. The continuous time linear equalizer according to claim 1, characterized in that: Current source one and current source two are fixed current sources; current source three and current source four are current sources controlled by feedback voltage; when the feedback voltage increases, the current output by current source three and current source four decreases, and vice versa; current source five and current source six are current sources controlled by Vbn voltage; when the Vbn voltage increases, the current output by current source five and current source six increases, and vice versa.

4. The continuous time linear equalizer according to claim 2, characterized in that: The currents output by the p-type current source and the n-type current source are equal, that is, the current output by current source one + the current output by current source three = the current output by current source five, and the current output by current source two + the current output by current source four = the current output by current source six.

5. The continuous time linear equalizer according to claim 1, characterized in that: RC network 1 connects the sources of two PMOS tubes; RC network 2 connects the sources of two NMOS tubes; RC network 1 and RC network 2 are used to adjust the peak frequency of the continuous time linear equalizer.

6. The continuous time linear equalizer according to claim 1, characterized in that: A pair of PMOS tubes provides transconductance, a pair of NMOS tubes also provides transconductance, and the transconductances provided by these two pairs of MOS tubes are superimposed; a pair of PMOS tubes and a pair of NMOS tubes share the same current source.

7. The continuous time linear equalizer according to claim 1, characterized in that: The common-mode voltage and feedback voltage of a pair of differential input voltages are sent to a transconductance circuit replica circuit, and the transconductance circuit replica circuit outputs a Vbn voltage; the transconductance circuit replica circuit is the left half or right half of a left-right symmetrical transconductance circuit, and the intermediate signal output of the left half or right half of the transconductance circuit is omitted, and the input signal position of the left half or right half of the transconductance circuit is changed to input the common-mode voltage of the differential input voltage at this position, and the Vbn voltage input position of the left half or right half of the transconductance circuit is changed to output the Vbn voltage at this position.

8. The continuous time linear equalizer according to claim 1, characterized in that: The transimpedance amplifier circuit includes a differential amplifier and two feedback resistors; the differential amplifier increases the transimpedance of a pair of differential intermediate signals to obtain a pair of differential output signals; feedback resistor three is connected to output terminal one and input terminal one of the differential amplifier, and feedback resistor four is connected to output terminal two and input terminal two of the differential amplifier.

9. The continuous time linear equalizer according to claim 1, characterized in that: The common-mode voltage feedback circuit includes a common-mode voltage extraction circuit, a transimpedance circuit replica circuit, and an operational amplifier; the common-mode voltage extraction circuit is used to extract the common-mode voltage of a pair of differential output signals; the transimpedance circuit replica circuit is a transimpedance amplifier circuit that is symmetrical up and down, but only uses the upper half of the input and output or the lower half of the input and output of the transimpedance amplifier circuit; the input terminal 1 of the operational amplifier receives the common-mode voltage output by the common-mode voltage extraction circuit, the input terminal 2 receives the absolute value of the voltage output by the transimpedance circuit replica circuit, and the output terminal of the operational amplifier outputs the feedback voltage; the function of the common-mode voltage feedback circuit is to make the output common-mode voltage of the transimpedance amplifier circuit and the output voltage of the transimpedance circuit replica circuit equal.

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