A spread spectrum clock generating device

Abstract

The invention discloses a spread spectrum clock generating device, comprising a frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, a frequency divider, a phase converter, a parameter generator and a DSM modulator, a first adder, and a second adder. The input end of the phase converter is connected to the frequency divider, and the output end is connected to the frequency detector and the parameter generator. The output end of the parameter generator is connected to the DSM modulator, the first adder, and the second adder. The output end of the first adder is connected to the phase converter, and the output end of the second adder is connected to the frequency divider. The spread spectrum clock generated by the invention has high precision, low jitter, and good phase noise performance, and is particularly suitable for SerDes communication systems.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and in particular relates to a spread spectrum clock generating device. Background Art

[0002] In the embedded field, traditional parallel communication methods can no longer meet the communication requirements of large data volumes and multi-device networking. Serial data transmission (SerDes) has become the mainstream method of high-speed data transmission, which places higher requirements on clock frequency and performance. For single-point frequency, as the communication rate increases, the clock center frequency also increases synchronously, and stronger electromagnetic interference (EMI) will be generated in the circuit, affecting the operation of other devices, resulting in restrictions on the development and application of this technology. For this reason, spread spectrum clock technology has been developed, which evenly distributes the power of the single-point frequency within a limited bandwidth, thereby reducing the power of the electromagnetic radiation of the single-point frequency.

[0003] Whether it is a single-point frequency or a spread spectrum clock, a phase-locked loop (PLL) technology is required. PLL is an electronic system used to generate a clock with a specific phase relationship with a reference clock. The system generally includes a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage-controlled oscillator (VCO), and a divider (DIV). Through the feedback of the entire loop, the phase of the divided clock and the reference clock is finally consistent. The output of the VCO is usually used as the target clock, and its frequency is determined by the control voltage of the LF output.

[0004] There are four existing methods for PLL to generate spread spectrum clocks: (1) Directly modulate the reference clock. Although this method has a simple structure, the digital modulation noise bandwidth is very wide and difficult to filter out through the loop. It will be directly reflected in the output clock, resulting in poor phase noise performance; (2) Modulate the control voltage of the VCO. This method has extremely high requirements on the control voltage accuracy of the VCO. Under different processes, the accuracy of spread spectrum modulation cannot be guaranteed; (3) Directly use phase interpolation to implement the divider of the feedback loop. Due to the nonlinearity of phase interpolation and the resolution problem of the interpolator itself, this method causes a large number of spurious signals to appear in the output clock, which seriously deteriorates the phase noise performance; (4) Directly use DSM to modulate the divider of the feedback loop. This method is relatively simple to implement digitally, but the quantization noise will inevitably produce fractional spurs, causing the output clock to have varying degrees of jitter. Summary of the invention

[0005] Purpose of the invention: In order to solve the problem of low precision and poor phase noise performance of the spread spectrum clock generated by the spread spectrum clock generator in the prior art, the present invention provides a spread spectrum clock generating device.

[0006] Technical solution: A spread spectrum clock generating device, including a frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a frequency divider, and also includes:

[0007] A phase converter, wherein the input end is connected to the frequency divider, the clock output end is connected to the frequency detector and the parameter generator, the overflow value output end is connected to the second adder, and the phase converter is used to synthesize the divided clock by combining at least two clocks output by the frequency divider;

[0008] A parameter generator, the output end of which is respectively connected to the DSM modulator, the first adder, and the second adder, and is used to provide the input parameter of the DSM modulator, the first phase parameter component, and the base value of the frequency divider respectively;

[0009] A DSM modulator, an output end of which is connected to a first adder for providing a second phase parameter component;

[0010] A first adder, the output end of which is connected to the phase converter, and is used to add the first phase parameter component and the second phase parameter component and then provide the result to the phase converter;

[0011] The second adder has an output end connected to the frequency divider and is used for adding the base value of the frequency divider and the overflow value of the phase converter and then providing the result to the frequency divider.

[0012] Furthermore, the phase converter includes a phase accumulator, a phase encoder, a phase inverter and a phase interpolator. The phase accumulator is used to continuously accumulate the input phase parameters; the phase encoder is used to synchronously set the flag according to the overflow state of the phase accumulator and encode the phase interpolation parameters; the phase inverter is used to exchange the two clocks of the input phase converter according to the bit flag, and reverse the phase value; the phase interpolator is used to interpolate according to the encoding and the two clocks of the input phase converter, and output the divided clock.

[0013] Furthermore, the DSM modulator at least comprises a first-stage accumulator, and a random scrambling code is added to the last bit of the first-stage accumulator in an initial state.

[0014] Furthermore, the DSM modulator is used to output a mean value of α / 2 N The discrete phase of the DSM modulator, N is the bit width of the DSM modulator, and α is the input parameter of the DSM modulator;

[0015] Where N is determined by the following formula:

[0016]

[0017] N=MW

[0018] in, is the clock resolution, is the reference clock frequency, is the upper frequency limit of the target spread spectrum clock, M is the sum of the bit width of the phase interpolator and the bit width of the DSM modulator, and W is the bit width of the phase interpolator in the phase converter.

[0019] Furthermore, the parameter generator includes an internal accumulator, and the total bit width of the internal accumulator is M+1, including a sign bit for bidirectional parameter update.

[0020] Furthermore, let the accumulator update step be , the frequency of the spread spectrum clock and The following relationship exists:

[0021]

[0022]

[0023] in, To adjust the frequency in a single step, is the clock resolution, is the spread spectrum clock frequency, is the spread spectrum clock modulation amplitude, is the reference clock frequency.

[0024] Furthermore, the parameter generator outputs preset corresponding parameters according to the divided clock, including an input parameter α of the DSM modulator, a first phase parameter component PH1, and a base value DIV_N of the frequency divider.

[0025] Furthermore, let the phase parameter output by the first adder be PH, let the second phase parameter component output by the DSM modulator be DSM, and DSM is a phase parameter component with a mean value of α / 2 N The relationship between the discrete phases of the parameters includes:

[0026] ,

[0027] PH= PH1+ DSM

[0028] Among them, n = 0, 1, 2, 3..., represents the sequence number, Represents multiple phase parameters.

[0029] Compared with the prior art, the spread spectrum clock generating device provided by the present invention has the following beneficial effects:

[0030] (1) By using a frequency divider to realize integer frequency division, combined with a phase interpolator and a DSM modulator to realize fractional frequency division, the resolution of phase interpolation can be improved to a certain index accuracy, so that the generated spread spectrum clock has high accuracy and low jitter, which is particularly suitable for application in SerDes systems, improving the applicability and reliability of the system;

[0031] (2) Using the modified DSM modulation technology, phase interpolation randomization is achieved to effectively suppress spurious frequencies;

[0032] (3) The phase converter uses phase inversion technology to ensure the continuity of phase interpolation, so as to avoid large random phase jumps caused by large changes in phase parameters, and effectively suppress the nonlinearity of the phase interpolator;

[0033] (4) The parameter generator outputs the phase parameters required by the phase converter, the input parameters required by the DSM modulator, and the frequency division base value required by the frequency divider according to the frequency division clock, so that the phase converter, DSM modulator, and frequency divider work together to achieve a better frequency division effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural schematic diagram of a spread spectrum clock generating device;

[0035] Figure 2 is a schematic diagram of the structure of a phase converter;

[0036] Figure 3 It is a phase interpolation inversion vector synthesis diagram;

[0037] Figure 4 is the phase interpolation timing;

[0038] Figure 5 It is a structural schematic diagram of a DSM modulator;

[0039] Figure 6 Output noise spectrum diagram for a common DSM modulator;

[0040] Figure 7 Output noise spectrum of the improved DSM modulator;

[0041] Figure 8 It is a fractional resolution modulation waveform;

[0042] Fig. 9 Output waveform of the phase inverter;

[0043] Fig.10 Output PRBS signal eye diagram for single frequency;

[0044] Fig.11 The frequency spectrum of the VCO output when the spread spectrum clock function is turned on and off. DETAILED DESCRIPTION

[0045] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments.

[0046] A spread spectrum clock generating device, such as Figure 1As shown, it includes a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider, and also includes:

[0047] A phase converter, the input end of which is connected to the frequency divider; the clock output end outputs the divided clock CLK_DIV, which is connected to the frequency detector and the parameter generator; the overflow value output end outputs Q, which is connected to the second adder; the phase converter is used to synthesize the divided clock CLK_DIV by combining at least two clocks P1 and P2 output by the frequency divider, and further realize fractional division on the basis of integer division realized by the frequency divider;

[0048] A parameter generator, the output end of which is respectively connected to the DSM modulator, the first adder, and the second adder, and is used to provide the input parameter α of the DSM modulator, the first phase parameter component PH1, and the base value DIV_N of the frequency divider;

[0049] A DSM modulator, an output end of which is connected to the first adder and is used to provide a second phase parameter component DSM;

[0050] A first adder, the output end of which is connected to the phase converter, and is used to add the first phase parameter component PH1 and the second phase parameter component DSM and provide the resultant to the phase converter, wherein the phase parameter after addition is recorded as PH;

[0051] The second adder has an output end connected to the frequency divider and is used for adding the base value DIV_N of the frequency divider and the overflow value Q of the phase converter and providing the result to the frequency divider.

[0052] The phase interpolator is used to interpolate according to the phase parameter PH and the two clocks P1 and P2 of the input phase converter, and output the divided clock CLK_DIV. Figure 2 As shown, the phase converter includes a phase accumulator, a phase encoder, a phase inverter and a phase interpolator. The phase accumulator is used to continuously accumulate the input phase parameter PH; the phase encoder determines whether the phase interpolation crosses the quadrant according to the overflow value Q of the phase accumulator, that is, whether clock switching is required, and synchronously sets the flag CKSWAP to encode the phase interpolation parameter; the phase inverter is used to exchange the two clocks P1 and P2 of the input phase converter according to the bit flag CKSWAP, and the phase value Reverse order (2 W - ), if CKSWAP=0, it means that the phase interpolation does not cross the quadrant, P1 and P2 are not swapped, and the phase value is not reversed; when CKSWAP=1, it means that the phase interpolation crosses the quadrant, P1 and P2 are swapped, and the phase value is reversed (2 W - ).like Figure 3As shown, when the phase interpolation parameter increases or decreases in one direction, the phase interpolation clock is always adjusted in one direction, that is, P1->P2 or P2->P1. The phase interpolator performs phase interpolation according to the input phase parameter PH and clocks P1 and P2, and outputs the target divided clock CLK_DIV, whose phase is always between P1 and P2.

[0053] In addition, the overflow value Q generated by the phase accumulator is input from the second adder, and after being added to the frequency division base value DIV_N output by the parameter generator, it is input to the frequency divider as the input parameter of the frequency divider. For example, when Q is 1, the input parameter of the frequency divider is DIV_N+1; when Q is 2, the input parameter of the frequency divider is DIV_N+2. Figure 4 As shown. It can be adjusted according to the actual spread spectrum amplitude. The larger the spread spectrum amplitude, the larger the Q. The phase converter is used to further divide the clock after integer frequency division of the divider to obtain a fractional frequency clock, and finally obtain a high-resolution target fractional frequency division clock CLK_DIV. The divided clock is sent to the frequency detector and phase detector. After the current-voltage conversion of the charge pump and the filtering and shaping of the loop filter, the voltage-controlled oscillator is controlled to output the target spread spectrum clock.

[0054] The DSM modulator at least includes a first-stage accumulator, and a random scrambling code is added to the last bit of the first-stage accumulator in the initial state, such as adding a 1-bit random scrambling code in this embodiment. Figure 5 The figure shows a three-level DSM modulator implementation method. The specific DSM modulator structure can be implemented in more than one way. The DSM modulator is used to output the DSM value, and the DSM value has an average value of α / 2. N The discrete phase of the DSM modulator, N is the bit width of the DSM modulator, and α is the input parameter of the DSM modulator. The DSM value is a random value of phase change. The subsequent first adder adds the DSM value to the first phase parameter component PH1 output by the parameter generator as the input parameter PH of the phase converter. The output noise spectrum of an ordinary DSM modulator without random scrambling is as follows: Figure 6 As shown in , because its output sequence has a certain periodicity, the spurious signals shown in the spectrum appear. Figure 7 The DSM modulator with 1-bit random scrambling code breaks up the periodicity of the sequence and effectively suppresses spurious signals.

[0055] The bit width N of the DSM modulator is determined according to the clock resolution index to be designed, and the specific relationship is as follows:

[0056] (1)

[0057] N=MW (2)

[0058] in, is the clock resolution, is the reference clock frequency, is the upper frequency limit of the target spread spectrum clock, M is the sum of the bit width of the phase interpolator and the bit width of the DSM modulator, and W is the bit width of the phase interpolator in the phase converter.

[0059] The parameter generator outputs corresponding parameters preset according to the divided clock, including the input parameter α of the DSM modulator, the first phase parameter component PH1, and the base value DIV_N of the divider. By changing these parameter values, the division ratio can be changed in real time, thereby making the VCO control voltage change in real time, producing a spread spectrum effect on its output frequency.

[0060] The parameter generator includes an internal accumulator, the total bit width of the internal accumulator is M+1, including a sign bit for bidirectional parameter update. Accumulator update step size It determines the frequency of the spread spectrum clock, and the update step size refers to the number of bits required for a single step adjustment. Assume that the accumulator update step size is , the frequency of the spread spectrum clock and The following relationship exists:

[0061] (3)

[0062] (4)

[0063] in, To adjust the frequency in a single step, is the clock resolution, is the spread spectrum clock frequency, is the spread spectrum clock modulation amplitude, is the reference clock frequency.

[0064] The PH output extreme value is related to the selection of DIV_N. Assume that the first phase parameter component is PH1, the base value of the divider is DIV_N, the phase parameter output by the first adder is PH, the second phase parameter component output by the DSM modulator is DSM, and the mean value of DSM is α / 2 N The discrete phase of DIV_N should be selected to output to the second adder. Under this optimal value, the PH value fluctuates the least and the phase interpolator is more stable. The following relationship exists between the parameters:

[0065] (5)

[0066] PH= PH1+ DSM (6)

[0067] Among them, n = 0, 1, 2, 3..., represents the sequence number, Represents multiple phase parameters.

[0068] To verify the spread spectrum effect of this embodiment, the following experiments were performed:

[0069] The external reference clock frequency is 24MHz, the upper cutoff frequency of the output spread spectrum clock is required to be 2.5GHz, the SSC modulation frequency is 33Khz, and the amplitude range is -4900ppm~0ppm. The DSM modulator is designed to have a bit width of 11bit, and the phase interpolator is designed to have a bit width of 5bit. Because bidirectional adjustment is required, the parameter unit accumulator is designed to be a signed number, so the total bit width of the parameter unit is 17bit, and the adjustable range is [-65536,65535];

[0070] The clock resolution (frequency resolution) can be calculated by formula (1): =0.1465 ppm / lsb.

[0071] The frequency adjustment range is [-9601 ppm, 9600 ppm]. For 2.5Ghz, the upper bias is 1600ppm, and the lower bias is -3400ppm. The frequency division base value, that is, the frequency division ratio DIV_N, is determined to be 104, and the parameter adjustment range is [-3400ppm, 1600ppm], corresponding to the 17-bit parameter adjustment range of [-23208 10922]; its step length is based on the above formula (3), and the single-step adjustment frequency is 13.4750ppm. According to formula (3), the corresponding 17-bit parameter step length is set to about 92.

[0072] Its modulation waveform is as follows Figure 8 As shown in Figure 1, the parameter generator sends the lower 11 bits of the 17-bit accumulator as the α value to the DSM modulator to calculate the second phase parameter component, that is, the random DSM value. The upper 6 bits are used as the fractional parameter part of the phase interpolation implementation, and are combined with the DSM value as the input parameter PH of the phase converter. The simulation results are shown in Figure 1. Figure 8 As shown, as the parameter accumulator is continuously updated, PH1 and DSM are continuously updated and merged into the actual adjustment phase parameter PH, which is mixed with random jitter in the determined phase change. After mean filtering, the fractional phase adjustment obtained is shown in the figure Mean, which represents that the divider realizes the spread spectrum effect of fractional frequency division.

[0073] The input parameter PH of the phase converter is accumulated, encoded and switched by the phase converter. Fig. 9As shown, SWAP is a flag bit. When the SWAP signal is 0, it indicates that the phase does not cross quadrants (the phase difference between P1->P2 represents one quadrant), and the P1 and P2 clocks do not need to be switched, where the P1 phase leads P2 by one VCO output clock cycle, and the PH value accumulates normally, indicating that the phase is shifted from P1 to P2. When SWAP is 1, it indicates that the current interpolation phase crosses quadrants. At this time, P1 and P2 are switched, and the P1 phase lags P2 by one VCO output clock cycle. At the same time, the PH value decreases in reverse order, indicating that the phase is shifted from P2 to P1. Therefore, from the overall point of view, the interpolation clock phase always shifts from the advanced clock to the delayed clock, and vice versa. If there is no phase switching design, when the interpolation phase crosses quadrants, the division ratio is +1 or -1, and the PH value may jump directly from 32 to 0 or other smaller values, resulting in a large jump in the PH value. Therefore, the phase converter including the phase switching structure can control the jump value of PH within a smaller range.

[0074] Fig.10 When the spread spectrum function is not enabled, the VCO outputs a single-point frequency, and the eye diagram obtained by driving the PRBS signal with this clock shows that its PP jitter is 50ps. Fig.11 As shown in the figure, the dotted box represents the signal spectrum of the VCO output when the spread spectrum function is turned off, and the solid box represents the signal spectrum of the VCO output when the spread spectrum function is turned on. After the spread spectrum, the peak power drops by 15.6dBm, and the energy of the main frequency is dispersed to -5000ppm~0ppm, achieving a better spread spectrum effect.

Claims

1. A spread spectrum clock generating device, comprising a frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a frequency divider, characterized in that: Also includes: A phase converter, wherein the input end is connected to a frequency divider, the clock output end is connected to a frequency detector and a parameter generator, and the overflow value output end is connected to a second adder. The phase converter is used to synthesize the frequency-divided clock from at least two clocks output by the frequency divider; the phase converter includes a phase accumulator, a phase encoder, a phase inverter and a phase interpolator. The phase accumulator is used to continuously accumulate the input phase parameters; the phase encoder determines whether the phase interpolation crosses quadrants according to the overflow value of the phase accumulator, that is, whether clock switching is required, and synchronously sets a flag to encode the phase interpolation parameters; The phase inverter is used to exchange the two clocks of the input phase converter according to the bit flag, and to convert the phase value When the bit flag is 0, it means that the phase interpolation does not cross the quadrant, the two clocks are not exchanged, and the phase value No reverse order; when the bit flag is 1, it means that the phase interpolation crosses the quadrant, the two clocks are exchanged, and the phase value is reversed to 2 W - , W is the bit width of the phase interpolator in the phase converter; the phase interpolator is used to interpolate according to the two clocks of the encoding and input phase converter, and output the divided clock; A parameter generator, the output end of which is respectively connected to the DSM modulator, the first adder, and the second adder, and is used to provide the input parameter of the DSM modulator, the first phase parameter component, and the base value of the frequency divider respectively; A DSM modulator, an output end of which is connected to a first adder for providing a second phase parameter component; A first adder, the output end of which is connected to the phase converter, and is used to add the first phase parameter component and the second phase parameter component and then provide the result to the phase converter; The second adder has an output end connected to the frequency divider and is used for adding the base value of the frequency divider and the overflow value of the phase converter and then providing the result to the frequency divider.

2. The spread spectrum clock generating device according to claim 1, characterized in that: The DSM modulator at least comprises a first-stage accumulator, and a random scrambling code is added to the last bit of the first-stage accumulator in an initial state.

3. The spread spectrum clock generating device according to claim 2, characterized in that: The DSM modulator is used to output a mean value of α / 2 N The discrete phase of the DSM modulator, N is the bit width of the DSM modulator, and α is the input parameter of the DSM modulator; Where N is determined by the following formula: ， N=MW, in, is the clock resolution, is the reference clock frequency, is the upper frequency limit of the target spread spectrum clock, M is the sum of the bit width of the phase interpolator and the bit width of the DSM modulator, and W is the bit width of the phase interpolator in the phase converter.

4. The spread spectrum clock generating device according to claim 1 or 2, characterized in that: The parameter generator includes an internal accumulator, and the total bit width of the internal accumulator is M+1, which includes a sign bit for bidirectional parameter update.

5. The spread spectrum clock generating device according to claim 4, characterized in that: Assume that the accumulator update step size is , the frequency of the spread spectrum clock and The following relationship exists: ， ， in, To adjust the frequency in a single step, is the clock resolution, is the spread spectrum clock frequency, is the spread spectrum clock modulation amplitude, is the reference clock frequency.

6. The spread spectrum clock generating device according to claim 1 or 2, characterized in that: The parameter generator outputs preset corresponding parameters according to the divided clock, including the input parameter α of the DSM modulator, the first phase parameter component PH1, and the base value DIV_N of the frequency divider.

7. The spread spectrum clock generating device according to claim 5, characterized in that: Assume that the phase parameter output by the first adder is PH, and the second phase parameter component output by the DSM modulator is DSM, where the mean value of DSM is α / 2. N The relationship between the discrete phases of the parameters includes: ， PH= PH1+ DSM Among them, n = 0, 1, 2, 3..., represents the sequence number, Represents multiple phase parameters.

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