CTDSM circuit for any period overshoot loop delay compensation

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a CTDSM circuit for any period overshoot loop delay compensation. According to the invention, an output signal Y of the CTDSM is delayed in a manner that the delay period is gradually increased from 1 to m, and CTDSM quantization results corresponding to the first n channels which are completely quantized are fed back to the input end of the TIADC in an analog domain manner; a CTDSM quantization result corresponding to a channel which is not completely quantized is fed back to the output end of the TIADC in a digital domain mode; afterwards, an analog domain output code word A, a digital domain compensation code word (D1-Dm-n) and a signal C2 are summed to obtain an output signal Y of the whole CTDSM circuit, finally compensation of overshoot loop delay of m unit periods is completed, and meanwhile the circuit time sequence design difficulty is greatly reduced. Wherein delay signals COA1 to COAm-n, which are obtained by delaying an input signal X through a unit period which is progressively increased from 1 to m-n, are summed and connected to the input end of ADDER0 so as to reduce the signal swing input to the input end of the TIADC.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a CTDSM circuit for arbitrary period overshoot loop delay compensation. Background Art

[0002] Continuous-Time Delta-Sigma Modulator (CTDSM) has been widely studied and applied in the field of analog integrated circuit technology due to its high precision and high bandwidth. The quantizer in CTDSM is usually implemented by cascading ADC and DAC. Due to the resolution limitation of the quantizer, it takes some time to complete the conversion, resulting in a delay in the output sequence. The DAC works after the ADC, so it can only be driven by the clock signal later, further increasing the delay. This excess loop delay (ELD) in CTDSM will cause system instability.

[0003] Assume a non-return to zero (NRZ) coded first-order CTDSM with a value of t d The overshoot loop delay of the system is as follows Figure 1 As shown, the noise transfer function (Noise Transfer Function, NTF) of the CTDSM system can be expressed as:

[0004]

[0005] It can be seen that compared with the CTDSM without overshoot loop delay, this system has two more poles, and the pole positions are related to t d Related, when t d The larger the value, the more unstable the system. d When it is greater than one cycle, the system is in an unstable state.

[0006] Regarding the compensation problem of overshoot loop delay, a design method for direct feedback path around the quantizer is proposed in the literature. Figure 2 This design method introduces a feedback path at the output of the quantizer and also passes through t d The delay to the quantizer input is introduced by introducing a feedback path to offset the overshoot loop delay.

[0007] However, the above scheme is only applicable to the case where the compensation overshoot loop delay is less than one cycle. If CTDSM uses a time-interleaved (TI) ADC with multi-channel input as its quantizer, the overshoot loop delay will be greater than 1 cycle. If the above quantizer direct feedback compensation scheme is used to compensate the overshoot loop delay of the TIADC, the incomplete quantized signal will be fed back to the input, resulting in system instability; if the TIADC with 2 channels is used to compensate for the overshoot loop delay, the input of the quantizer is:

[0008] D[n]=X[n]-Y[n-1]-Y[n-2]

[0009] Wherein, D[n] is the quantizer input signal of the nth period, X[n] is the discretized signal of the first-order CTDSM input signal of the nth period after passing through the loop filter, and Y[n] is the quantizer output signal of the nth period.

[0010] It can be seen that in the nth cycle, the quantizer output values ​​of the n-1th cycle and the n-2th cycle need to be fed back, but for the 2-channel TIADC, the n-1th cycle is still in the quantization stage and cannot feed back the correct output signal, resulting in errors in the overall circuit. This limits the development of CTDSM in the field of high speed and high precision, so how to compensate for the overshoot loop delay greater than one cycle is an urgent problem to be solved in the research of high-performance CTDSM. Summary of the invention

[0011] In view of the above problems or shortcomings, the present invention provides a CTDSM circuit for compensating overshoot loop delay in any period, which is applicable to the case where a TIADC with any number of channels is used as a CTDSM quantizer. By introducing multiple feedback paths that meet the design conditions from the output of the quantizer to the input of the quantizer, the overshoot loop delay is compensated.

[0012] A CTDSM circuit for arbitrary period overshoot loop delay compensation is composed of the following six modules: Figure 3 As shown, it includes module 001, module 002, module 003, module 004, module 005 and module 006.

[0013] If the number of channels of TIADC used as CTDSM quantizer is m, then for CTDSM, an overshoot loop delay of m cycles will be generated. According to the working principle of TIADC, when sampling is performed in the m+1th cycle, the m channels have different degrees of quantization results. It is assumed that the first n channels of the m channels have been completely quantized, and although the remaining channels have not completed quantization, they have generated quantization codewords to different degrees.

[0014] The module 001 includes three parts: an adder ADDERx, a loop filter and a sampling switch connected in sequence. The adder ADDERx serves as the input of the module 001, connecting the input signal X of the entire CTDSM circuit and the output signal D of the module 004. m The output of the sampling switch is used as the output of module 001 and connected to the input of module 002. Module 001 uses adder ADDERx to add input signals X and D m The differential operation is performed, and after loop filtering, discretization is achieved through sampling switches.

[0015] The module 002 is composed of n+1 adders, which are cascaded sequentially from ADDER0 to ADDERn. The input of adder ADDER0 is connected to the output (sampling switch) of module 001 and the output signal C of module 003. 1 The input of adder ADDER1 is connected to the output of ADDER0 and the output signal D of module 004. m The input of adder ADDER2 is connected to the output of ADDER1 and the output signal D of module 004. m-1 , ... The input of adder ADDERn is connected to the output of ADDERn-1 and the output signal D of module 004 m-n+1 ; The output of adder ADDERn is connected to the input of module 005 as the output of module 002.

[0016] The module 003 is composed of mn unit cycle delay modules (Z -1 ), mn coarse ADCs (coarse precision analog-to-digital converters) and a summer SUMMER0. The coarseADC architecture can be implemented using high-speed, low-precision ADCs such as flashADCs (flash analog-to-digital converters); where m is the total number of channels in TIADC, and n is the number of channels that have been fully quantized in TIADC during the m+1th working cycle.

[0017] The input signal of module 003 is the input signal X of the entire CTDSM circuit. The input of the first unit cycle delay module is connected to the input signal X of the entire CTDSM circuit, and a signal XD is obtained which is a result of signal X being delayed by one unit cycle. 1 ; The input of the second unit cycle delay module is connected to XD 1 , we get the signal XD which is a signal X delayed by 2 unit cycles. 2 ; ...the input of the mnth unit cycle delay module is connected to XD m-n-1 , we get the signal XD after the signal X is delayed by mn unit cycles m-n .

[0018] And connect a coarse ADC after each unit cycle delay module to get the signal XD 1 to XD m-n The quantized signal COA corresponding to each other 1 To COA m-n .

[0019] The input of summer SUMMER0 is connected to the quantized signal COA 1 To COA m-n , the quantized signal COA 1 To COA m-n After summing, the output signal C is divided into two paths 1 and C 2 , where the first output signal C 1 Connect to the input of module 002 (adder ADDER0), the second output signal C 2 Connected to the input end of the summer 1 in module 006.

[0020] The module 004 is composed of m unit cycle delay modules (Z -1 ) are sequentially cascaded to form a delay loop with a delay cycle number of m. The input of module 004 is connected to the output signal Y of the entire CTDSM circuit, and the signal Y is delayed by a unit cycle with a delay cycle number increasing from m-n+1 to m. After the m-n+1th unit cycle delay module, the signal Y obtains an output signal D with a delay cycle number of m-n+1. m-n+1 ; ... After the m-1th unit cycle delay module, the signal Y obtains the output signal D with a delay cycle number of m-1 m-1 After the mth unit cycle delay module, the signal Y obtains the output signal D with a delay cycle number of m. m At the same time, the output signal D of module 004 m It is also connected to the input terminal (adder ADDERx) of module 001. The function of module 004 is to delay the input signal Y by a unit cycle with the delay cycle number increasing from m-n+1 to m, and obtain the output signal D m-n+1 To D m .

[0021] The module 005 is composed of m channels of TIADC, the input of the module 005 is connected to the output of the module 002 , and the output signal A of the module 005 is connected to the input of the module 006 .

[0022] The module 006 is composed of mn unit-cycle delay modules and a summer 1. The mn unit-cycle delay modules are cascaded in sequence to obtain a delay path with a delay cycle number of mn.

[0023] The delay path delays the signal Y by unit cycles with the delay number increasing from 1 to mn. The input of the first unit cycle delay module is connected to the signal Y, and the signal D is obtained by delaying the signal Y by one unit cycle. 1 ; The input of the second unit cycle delay module is connected to signal D 1 , we get signal D which is the signal Y delayed by 2 unit cycles 2 ; ...the input of the mnth unit cycle delay module is connected to the signal D m-n-1 , we get the signal D after signal Y is delayed by mn unit cycles m-n .

[0024] The input of summer 1 (the input of module 006) is connected to the output signal A of module 005 and the second output signal C of module 003. 2 and the delay path output signal D 1 To D m-n , and for signal A, signal C 2 and signal D 1 To D m-n The output of the summer 1 is used as the output signal Y of the entire CTDSM circuit.

[0025] Furthermore, the module 002 compares the output signal of the module 001 with the C 1 The signal is differentially calculated to obtain the output of ADDER0, and then the output signal of ADDER0 is compared with D m The signal is differentially calculated to obtain the output of ADDER1, and then the output signal of ADDER1 is compared with D m-1 The signal is differentially operated to obtain the output of ADDER2. The above steps are repeated to obtain the output of ADDERn. The output signal of ADDERn is the output signal of module 002, which is connected to the input of module 005.

[0026] Furthermore, the loop filter adopts a cascade integrator CIFB with feedback or a cascade integrator CIFF with feedforward.

[0027] From the working principle of TIADC, it can be known that assuming a TIADC with a total number of channels of m. When sampling is performed in the m+1th cycle, in the CTDSM circuit, if the quantization result of the CTDSM corresponding to channel p (p is a positive integer, and p≤m) is to be fed back to the input or output of the TIADC, it can be equivalent to feeding back the output signal of the entire CTDSM circuit of the pth cycle to the input or output of the TIADC, that is, delaying the output signal Y of the entire CTDSM circuit by m-p+1 unit cycles and then feeding it back to the input or output of the TIADC, so that the feedback operation of the quantization results between the channels of the TIADC can be converted into a delayed feedback operation of the output signal Y of the entire CTDSM circuit.

[0028] The present invention delays the output signal Y of CTDSM by increasing the number of delay cycles from 1 to m. According to the number of channels that have been completely quantized when sampling in the m+1 cycle, n is used. The CTDSM quantization result corresponding to the channel that has been completely quantized in the current working cycle is fed back to the input end of TIADC in the analog domain, that is, the delayed signal D obtained by delaying the signal Y by increasing the number of unit cycles from m-n+1 to m is m-n+1 To D m Feedback to the input of TIADC; at the same time, the CTDSM quantization results corresponding to the channels that have not been fully quantized in the current working cycle are fed back to the output of TIADC in the digital domain, that is, the delayed signal D obtained by delaying the signal Y by a unit period increasing from 1 to mn 1 To D m-n Feedback to the output of TIADC. However, since only the quantization results of CTDSM corresponding to channels m-n+1 to channel m, a total of n channels, are fed back to the input of TIADC, the signal swing input to the input of TI ADC will exceed the input swing of TI ADC. In order to limit the signal swing input to the input of TI ADC, the input signals of CTDSM corresponding to channels 1 to mn, a total of mn channels, are summed and connected to the input of ADDER0 during sampling, that is, the input signal X of the entire CTDSM circuit is delayed by a unit period from 1 to mn to obtain the delayed quantization signal COA. 1 To COA m-n The sum is connected to the input terminal of ADDER0. The present invention completes the compensation of the overshoot loop delay of m unit cycles through the above steps, and at the same time greatly reduces the difficulty of circuit timing design.

[0029] In summary, the present invention delays the output signal Y of CTDSM by increasing the number of cycles from 1 to m, and feeds back the CTDSM quantization results corresponding to the first n channels that have been completely quantized to the input end of TIADC; the CTDSM quantization results corresponding to the channels that are not completely quantized are fed back to the output end of TIADC to compensate for the overshoot loop delay. The present invention is applicable to the case where TIADC with any number of channels is used as a CTDSM quantizer, improves the stability of the CTDSM circuit, and greatly reduces the difficulty of circuit timing design, providing support for the development of CTDSM in the field of high speed and high precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 For d Schematic diagram of a first-order CTDSM circuit with overshoot loop delay;

[0031] Figure 2 A schematic diagram of a first-order CTDSM circuit with overshoot loop delay using a quantizer direct feedback compensation scheme;

[0032] Figure 3 A schematic diagram of the compensation scheme architecture of the m-channel TIADC used as a CTDSM quantizer in the present invention;

[0033] Figure 4 is a circuit block diagram of a 2-cycle overshoot loop delay compensation in a CTDSM in an embodiment;

[0034] Figure 5 FIG. 4 is a schematic diagram of a loop filter structure used in an embodiment. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0036] A CTDSM circuit for arbitrary cycle overshoot loop delay compensation, as shown in the attached Figure 4 As shown in FIG. 1 , the CTDSM in this embodiment is based on a 2-channel time-interleaved noise-shaping SAR ADC (TINSSAR ADC) with a 2-cycle overshoot loop delay. The loop filter architecture used by the CTDSM is a cascade integrator CIFF with a feedforward structure. The system block diagram is shown in the attached figure. Figure 5 shown.

[0037] First, assume that the input of the CTDSM circuit is signal X, the output of the CTDSM circuit is Y, the input of the TINSSARADC is signal D, the output signal of the TINSSARADC is F, and the quantization noise of the TINSSARADC is E.

[0038] It is known that in the first-order CTDSM, the input signal has an overshoot loop delay t d The corresponding expression for sampling is:

[0039]

[0040] Where τ is the number of delayed cycles, which is a positive integer.

[0041] According to the attached Figure 4 , we can get formula 1 as:

[0042]

[0043] The formula 2 is:

[0044]

[0045] D+E·(1-Z -1 )=F (2)

[0046] The formula 3 is:

[0047] F+XY·Z -1 =Y (3)

[0048] Substituting equation 1 and equation 2 into equation 3, we get:

[0049]

[0050] Y=Z -1 X+(1-Z -1 ) 2 E

[0051] Finally, the signal transfer function of the CTDSM circuit is Z -1 , the noise transfer function is (1-Z -1 ) 2 .

[0052] It can be seen from the above embodiments that the present invention delays the output signal Y of CTDSM by delaying the number of cycles from 1 to m, and feeds back the CTDSM quantization results corresponding to the first n channels that have been fully quantized to the input end of TIADC through the analog domain; the CTDSM quantization results corresponding to the channels that are not fully quantized are fed back to the output end of TIADC through the digital domain; then, the analog domain output codeword A and the digital domain compensation codeword (D1-Dm-n) and the signal C2 are summed to obtain the output signal Y of the entire CTDSM circuit, and finally the compensation of the overshoot loop delay of m unit cycles is completed, and the difficulty of circuit timing design is greatly reduced. The delay signals COA1 to COAm-n obtained by delaying the input signal X of the entire CTDSM circuit by unit cycles from 1 to mn are summed and connected to the input end of ADDER0 to reduce the signal swing input to the input end of TIADC. The present invention effectively compensates for the overshoot loop delay of any cycle in the CTDSM with TIADC as the quantizer, improves the stability of the CTDSM circuit, and provides support for the development of CTDSM in the field of high speed and high precision.

Claims

1. A CTDSM circuit for arbitrary period overshoot loop delay compensation, characterized in that: It includes module 001, module 002, module 003, module 004, module 005 and module 006; The module 001 includes three parts: an adder ADDERx, a loop filter and a sampling switch connected in sequence; the adder ADDERx serves as the input of the module 001, connecting the input signal X of the entire CTDSM circuit and the output signal D of the module 004. m The output of the sampling switch is connected to the input of module 002 as the output of module 001; module 001 adds input signals X and D through adder ADDERx m Perform differential operation, and after loop filtering, realize discretization through sampling switches; The module 002 is composed of n+1 adders, which are cascaded sequentially from ADDER0 to ADDERn; wherein the input of adder ADDER0 is connected to the output of module 001 and the output signal C1 of module 003, and the input of adder ADDER1 is connected to the output of ADDER0 and the output signal D m The input of adder ADDER2 is connected to the output of ADDER1 and the output signal D of module 004. m-1 , ... The input of adder ADDERn is connected to the output of ADDERn-1 and the output signal D of module 004 m-n+1 The output of adder ADDERn is connected to the input of module 005 as the output of module 002; The module 003 is composed of mn unit cycle delay modules, mn coarseADCs and a summer 0; wherein m is the total number of channels of TIADC, and n is the number of channels that have been fully quantized in TIADC during the m+1th working cycle; The input signal of module 003 is the input signal X of the entire CTDSM circuit; the input of the first unit cycle delay module is connected to the input signal X of the entire CTDSM circuit, and a signal XD1 of signal X delayed by one unit cycle is obtained; the input of the second unit cycle delay module is connected to XD1, and a signal XD2 of signal X delayed by two unit cycles is obtained; ... the input of the mnth unit cycle delay module is connected to XD m-n-1 , we get the signal XD after the signal X is delayed by mn unit cycles m-n ; A coarse ADC is connected after each unit cycle delay module to obtain signals XD1 to XD m-n The quantized signals COA1 to COA1 correspond to each other one by one. m-n ; The input of summer SUMMER0 is connected to the quantized signal COA1 to COA m-n , the quantized signal COA1 to COA m-n After summing, two output signals C1 and C2 are generated, wherein the first output signal C1 is connected to the input end of module 002, and the second output signal C2 is connected to the input end of the summer 1 in module 006; The module 004 is composed of m unit cycle delay modules cascaded in sequence to obtain a delay loop with a delay cycle number of m; the input of the module 004 is connected to the output signal Y of the entire CTDSM circuit, and the signal Y is delayed by a unit cycle with the delay cycle number increasing from m-n+1 to m; after the m-n+1th unit cycle delay module, the signal Y obtains an output signal D with a delay cycle number of m-n+1. m-n+1 ; ... After the m-1th unit cycle delay module, the signal Y obtains the output signal D with a delay cycle number of m-1 m-1 After the mth unit cycle delay module, the signal Y obtains the output signal D with a delay cycle number of m. m Module 004 delays the input signal Y by increasing the number of delay cycles from m-n+1 to m, and obtains the output signal D m-n+1 To D m ; The module 005 is composed of m channels of TIADC, the input of the module 005 is connected to the output of the module 002, and the output signal A of the module 005 is connected to the input of the module 006; The module 006 is composed of mn unit period delay modules and a summer 1, and the mn unit period delay modules are cascaded in sequence to obtain a delay path with a delay period number of mn; The delay path delays the signal Y by unit cycles increasing from 1 to mn; the input of the first unit cycle delay module is connected to the signal Y, and the signal D1 of the signal Y delayed by 1 unit cycle is obtained; the input of the second unit cycle delay module is connected to the signal D1, and the signal D2 of the signal Y delayed by 2 unit cycles is obtained; ... the input of the mnth unit cycle delay module is connected to the signal D m-n-1 , we get the signal D after signal Y is delayed by mn unit cycles m-n ; The input of summer 1 is connected to the output signal A of module 005, the second output signal C2 of module 003 and the signals D1 to D1 output by the delay path. m-n , and for signal A, signal C2 and signals D1 to D m-n Perform a summing operation; the output of the summer SUMMER1 serves as the output signal Y of the entire CTDSM circuit.

2. The CTDSM circuit for arbitrary period overshoot loop delay compensation as claimed in claim 1, characterized in that: The module 002 performs a differential operation on the output signal of the module 001 and the C1 signal to obtain the output of ADDER0, and then compares the output signal of ADDER0 with the D m The signal is differentially calculated to obtain the output of ADDER1, and then the output signal of ADDER1 is compared with D m-1 The signal is differentially operated to obtain the output of ADDER2. The above steps are repeated to obtain the output of ADDERn. The output signal of ADDERn is the output signal of module 002, which is connected to the input of module 005.

3. The CTDSM circuit for arbitrary period overshoot loop delay compensation as claimed in claim 1, characterized in that: The loop filter adopts a cascade integrator CIFB with feedback or a cascade integrator CIFF with feedforward.

4. The CTDSM circuit for arbitrary period overshoot loop delay compensation as claimed in claim 1, characterized in that: The coarseADC is implemented using a flashADC flash analog-to-digital converter.

5. The CTDSM circuit for arbitrary period overshoot loop delay compensation as claimed in claim 1, characterized in that: The specific engineering process is: When sampling in the m+1 cycle, the number of channels that have been fully quantized is n; The input signals of the CTDSM corresponding to the channels 1 to mn during sampling are summed and connected to the input of ADDER0, that is, the input signal X of the entire CTDSM circuit is delayed by a unit cycle from 1 to mn to obtain the delayed quantization signals COA1 to COA m-n The summation is connected to the input of ADDER0 to limit the signal swing input to the TI ADC input; The CTDSM quantization result corresponding to the channel that has been fully quantized in the current working cycle is fed back to the input of TIADC in the analog domain, that is, the delayed signal D obtained by delaying the signal Y from the unit cycle increasing from m-n+1 to m m-n+1 To D m Feedback to the input of TIADC; At the same time, the CTDSM quantization results corresponding to the channels that have not been fully quantized in the current working cycle are fed back to the output end of TIADC in the digital domain, that is, the delayed signal D1 to D1 obtained by delaying the signal Y from 1 to mn unit cycles is transmitted. m-n Feedback to the output of TIADC; the summator SUMMER1 of module 006 is used for signal A, signal C2 and signal D1 to D m-n Perform a summing operation; the output of the summer SUMMER1 serves as the output signal Y of the entire CTDSM circuit.

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