Super-multiple coexisting attractor generation circuit and construction method thereof

Abstract

The invention relates to a super-multiple coexistence attractor generation circuit and a construction method thereof, the super-multiple coexistence attractor generation circuit comprises a very simple chaotic oscillation system and an equivalent realization circuit of a magnetic control memristor, and the very simple chaotic oscillation system and the equivalent realization circuit of the magnetic control memristor are connected to generate a super-multiple attractor coexistence phenomenon; an active magnetic control memristor is adopted to replace an extremely simple chaotic oscillation system, and a gain resistor is arranged in front of an inverted input end of an operational amplifier U4, so that a super-multi-coexistence attractor generation circuit is realized. The circuit is simple in structure, can generate 21 attractors with different topological structures, and has a wide application prospect in information security fields such as secret communication and image encryption.

Description

Technical Field

[0001] The present invention relates to the technical field of digital circuits, and in particular to a circuit for generating a large number of coexisting attractors and a construction method thereof. Background Art

[0002] Memristor chaotic system is a research hotspot and frontier topic in the field of modern nonlinear systems. The bifurcation in the inductive hyperchaotic circuit based on active memristor is mainly caused by the resistance linearly coupled with the RC bridge oscillator in the circuit and the negative resistance in the memristor that realizes the current inverter. When the parameters in the circuit change, the inductive hyperchaotic circuit has dynamic behaviors such as coexistence bifurcation modes and coexistence attractors.

[0003] In the field of nonlinear chaotic circuits, the improved memristor chaotic circuit after the introduction of memristors exhibits complex dynamic behaviors under different initial conditions. In recent years, with the in-depth study of memristor chaotic circuits, super multistability has begun to become a popular research direction. With the change of initial conditions, the system with fixed control parameters shows the phenomenon of coexistence of infinite attractors, but the topological structures of most coexisting attractors are relatively similar, and their applications in the field of information security are limited, especially the research on memristor circuit systems with simple structures and complex multistability is relatively small. Therefore, the applicant proposes a circuit for generating super-multi coexisting attractors and a method for constructing it. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned shortcomings and provide a circuit for generating a large number of coexisting attractors and a construction method thereof, which can generate attractors of various topological structures and have broad application prospects in the field of information security.

[0005] The object of the present invention is achieved in that: A circuit for generating super-multiple coexisting attractors, comprising a minimalist chaotic oscillation system and an equivalent realization circuit of a magnetically controlled memristor, wherein the minimalist chaotic oscillation system is connected with the equivalent realization circuit of a magnetically controlled memristor to generate a super-multiple attractor coexistence phenomenon; The minimalist chaotic oscillation system includes a first integral channel, a second integral channel and a third integral channel. The first integral channel includes a first integrator, which corresponds to an input terminal, and the input terminal is connected to the state variable -0.1 v y v z The second integration channel includes a second integrator, a multiplier M 1 and the reverse amplifier, which correspond to two input terminals, one of which is connected to the state variable - v b , and the other input terminal is connected to the state variable 0.1 v z2 ; The third integration channel includes a third integrator and a multiplier M 2, which corresponds to two input terminals, one of which is connected to the state variable v y v z , and the other input terminal is connected to the state variable v x ; The equivalent realization circuit of the magnetically controlled memristor includes a fourth integrator circuit, a multiplier M 3. Multiplier M 4. Absolute value operation circuit and addition operation circuit, the state variable corresponding to the input end of the equivalent implementation circuit v x After the fourth integrator performs the integral operation, the output state variable is - v w , and the state variable - v w After passing through the absolute value operation circuit, the output | v w |, and then output through the multiplier| v w | v x ; Finally, the output is through the addition circuit W ( v w ) v x .

[0006] Furthermore, the input terminal of the first integral channel is connected in series with a resistor R a After the operational amplifier U 1, the inverting input of the operational amplifier U 1. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output state variable 1 v x .

[0007] Furthermore, the second integral channel accesses the state variable - v b The input series resistor R Then connected to the operational amplifier U 2 inverting input terminal; the second integral channel is connected to the state variable 0.1 v z 2 The input terminal is then connected in series with another resistor of 0.1 R After the operational amplifier U2, the inverting input terminal of the operational amplifier U 2. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output state variable of output terminal 2 v y .

[0008] Furthermore, the operational amplifier U 2 output and multiplier M 1 input connection, the multiplier M The other input of 1 is connected to the state variable - v z , the multiplier M The output terminal of 1 outputs the state variable -0.1 v y v z .

[0009] Furthermore, the multiplier M 1 output and operational amplifier U 3. A series resistor of 0.1 is placed between the input terminals R , the operational amplifier U 3. Connect a resistor in parallel between the inverting input and output R , the operational amplifier U Output terminal 3 outputs state variable v y v z .

[0010] Furthermore, the access state variable of the third integration channel v y v z The input series resistor R After the operational amplifier U 4; the other access state variable of the third integral channel v x The input end is connected to the equivalent circuit of the magnetically controlled memristor and then connected to the operational amplifier. U 4, the inverting input of the operational amplifier U 4. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output terminal 4 outputs state variable - v z The operational amplifier U The output of 4 and the multiplier M 2 input terminals are connected to the multiplier M2, the two input terminals of the operational amplifier are shorted. U The output terminal 4 outputs the state variable 0.1 v z 2 Furthermore, the fourth integrator circuit includes a resistor R w ,capacitance C and operational amplifiers U 5. The resistor R w One end is connected to the input end of the equivalent circuit, and the other end is connected to the operational amplifier U 5, the inverting input terminal of the operational amplifier U 5. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U The output terminal of 5 outputs the state variable - v w .

[0011] Furthermore, the absolute value operation circuit includes an operational amplifier U 6. Resistance R 1 and resistor R 2. The operational amplifier U The inverting input terminals of 6 are connected to the operational amplifier U 5 output and multiplier M 3. The operational amplifier U 6. Connect the resistor to the output terminal R 1. Resistance R 2 is connected to GND, resistor R 1 and resistor R The other end of 2 is connected to serve as a multiplier M 3 input terminal.

[0012] Furthermore, the adding circuit includes a resistor R α and resistor R β , the resistor R α One end of the resistor is connected to the input end of the equivalent circuit. R β One end of the multiplier M 4 output terminals are connected, the resistor R α and R β The other end of is connected to serve as the output end of the equivalent implementation circuit.

[0013] A method for constructing the above-mentioned super-multiple coexisting attractor generation circuit includes the following contents: S1. Establish a type of minimalist chaotic system, which can generate up-down symmetrical coexisting single-wing chaotic attractors under different initial states. Its mathematical model is as follows: ;

[0014] In the above formula, x , y , z is the state variable, a To control the parameters; S2. Change the variables of the above mathematical model x Modified to the magnetically controlled memristor term, the dimensionless equation of the memristor-like chaotic system with many coexisting attractors is: ; In the above formula, x , y , z and w are 4 state variables, a is the control parameter of the original three-dimensional system; w is the dimensionless state variable of the magnetically controlled memristor, and W ( w )= α - β | w |; S3. Set control parameters a = 3.6, α =1, β = 0.05, the initial state is (1, 0, 7, 0), numerical simulation is performed, and the phase trajectory diagram of the simulation results is obtained; S4. Using the circuit of a minimalist chaotic oscillation system, the equation for generating a circuit for generating a large number of coexisting attractors of a memristor chaotic system is as follows: ; S5. The equivalent circuit equation of the equivalent implementation circuit of the magnetically controlled memristor is as follows: .

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a circuit for generating a super-multiple coexisting attractors and a construction method thereof, adopting an active magnetically controlled memristor to replace a minimalist chaotic oscillation system, and setting a gain resistor before the inverting input terminal of the operational amplifier U4 to realize a circuit for generating a super-multiple coexisting attractors. The present invention introduces an ideal magnetically controlled memristor to replace the gain resistor in the circuit, and realizes a circuit for generating a super-multiple coexisting attractors of a memristor-type chaotic system. The circuit has a simple structure and can generate attractors of 21 different topological structures, and has broad application prospects in information security fields such as confidential communications and image encryption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the circuit principle of the extremely simple chaotic oscillation system of the present invention.

[0017] Figure 2 The figure is a schematic diagram of the circuit principle of the equivalent realization circuit of the magnetic controlled memristor of the present invention.

[0018] FIG. 3 is a diagram of a super-multiple coexisting attractor circuit simulation of the present invention. x – z Phase trajectory diagram on a plane.

[0019] Figure 4 The typical attractor obtained by numerical simulation of the memristor chaotic system of the present invention is x – z Phase trajectory diagram on a plane.

[0020] Figure 5 The typical attractor obtained by numerical simulation of the memristor chaotic system of the present invention is w – y Phase trajectory diagram on a plane.

[0021] FIG. 6 is a diagram of a super-multiple coexisting attractor circuit simulation of the present invention. v x – v Phase trajectory diagram on the z-plane.

[0022] Figure 7 The typical attractors captured by the experimental measurement of the circuit for generating a large number of coexisting attractors of the present invention are v x – v z Phase trajectory diagram on a plane.

[0023] Figure 8 The typical attractors captured by the experimental measurement of the circuit for generating a large number of coexisting attractors of the present invention are v w – v y Phase trajectory diagram on a plane. DETAILED DESCRIPTION

[0024] In order to better understand the technical solution of the present invention, the following will be described in detail in conjunction with the relevant illustrations. It should be understood that the following specific embodiments are not intended to limit the specific implementation of the technical solution of the present invention, and are only implementations that can be adopted by the technical solution of the present invention. It should be noted that the description of the positional relationship of each component in this article, such as component A being located above component B, is based on the description of the relative positions of the components in the illustration, and is not intended to limit the actual positional relationship of the components.

[0025] Embodiment 1: See also Figure 1-Figure 8 , Figure 1 A circuit principle schematic diagram of the minimalist chaotic oscillation system of the present invention is drawn. As shown in the figure, the present invention relates to a super-multiple coexisting attractor generation circuit, which includes a minimalist chaotic oscillation system and an equivalent realization circuit of a magnetically controlled memristor, and the minimalist chaotic oscillation system and the equivalent realization circuit of a magnetically controlled memristor are connected to generate a super-multiple attractor coexistence phenomenon.

[0026] The minimalist chaotic oscillation system includes a first integral channel, a second integral channel and a third integral channel. The first integral channel includes a first integrator, which corresponds to an input terminal, and the input terminal is connected to the state variable -0.1 v y v z , then the input terminal series resistor R a After the operational amplifier U 1, the inverting input of the operational amplifier U 1. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output state variable 1 v x ; The second integration channel includes a second integrator, a multiplier M 1 and the inverting amplifier, which correspond to two input terminals, one of which is connected to the state variable – v b , then the input terminal series resistor R Then connected to the operational amplifier U 2's inverting input; the other input is connected to the state variable 0.1 v z 2 Then the input terminal is connected in series with another resistor 0.1 R After the operational amplifier U 2, the inverting input terminal of the operational amplifier U 2. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output state variable of output terminal 2 v y ; The operational amplifier U 2 output and multiplier M 1 input connection, the multiplier M The other input of 1 is connected to the state variable – v z , the multiplierM Output state variable of 1 –0.1 v y v z ; The multiplier M 1 output and operational amplifier U 3. A series resistor of 0.1 is placed between the input terminals R , the operational amplifier U 3. Connect a resistor in parallel between the inverting input and output R , the operational amplifier U Output state variable of output terminal 3 v y v z ; The third integration channel includes a third integrator and a multiplier M 2, which corresponds to two input terminals, one of which is connected to the state variable v y v z , then the series resistor R After the operational amplifier U 4's inverting input; the other input is connected to the state variable v x , then connect the equivalent circuit of the magnetically controlled memristor to the operational amplifier U 4, the inverting input of the operational amplifier U 4. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output 4 outputs state variable – v z ; The operational amplifier U The output of 4 and the multiplier M 2 input terminals are connected to the multiplier M 2, the two input terminals of the operational amplifier are shorted. U The output terminal 4 outputs the state variable 0.1 v z 2 .

[0027] The equivalent realization circuit of the magnetically controlled memristor includes a fourth integrator circuit, a multiplier M 3. Multiplier M 4. Absolute value operation circuit and addition operation circuit. The state variables corresponding to the input end of this equivalent implementation circuit are v x After the fourth integrator performs the integral operation, the output state variable is – vw , and the state variable – v w After passing through the absolute value operation circuit, the output | v w |, and then output through the multiplier| v w | v x ; Finally, the output is through the addition circuit W ( v w ) v x ; The fourth integrator circuit includes a resistor R w ,capacitance C and operational amplifiers U 5. The resistor R w One end is connected to the input end of the equivalent circuit, and the other end is connected to the operational amplifier U 5, the inverting input terminal of the operational amplifier U 5. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output 5 outputs state variable – v w ; The absolute value operation circuit includes an operational amplifier U 6. Resistance R 1 and resistor R 2. The operational amplifier U The inverting input terminals of 6 are connected to the operational amplifier U 5 output and multiplier M 3. The operational amplifier U 6. Connect the resistor to the output terminal R 1. Resistance R 2 is connected to GND, resistor R 1 and resistor R The other end of 2 is connected to serve as a multiplier M 3 input terminal; The adding circuit includes a resistor R α and resistor R β , the resistor R α One end of the resistor is connected to the input end of the equivalent circuit. R β One end of the multiplier M 4 output terminals are connected, the resistor R αand R β The other end of is connected to serve as the output end of the equivalent implementation circuit.

[0028] The operational amplifier U 1. U 2. U 3. U 4. U 5 and U The non-inverting input terminals of 6 are all grounded.

[0029] The above operational amplifier U 1. U 2. U 3. U 4. U 5 and U 6 The AD711KN operational amplifier can be used. M 1. M 2. M 3 and M 4 The AD633JN multiplier can be used.

[0030] See Figure 3- Figure 8 FIG3 plots the super-multiple coexisting attractors obtained by simulating the super-multiple coexisting attractor circuit of the present invention. x – z Phase trajectory diagram on the plane, i.e., numerical simulation diagram. In the figure, the labeled color is consistent with the attractor color. C represents the chaotic attractor, P1 represents the period 1 ring, P2 represents the period 2 ring, and P4 represents the period 4 ring. Different initial states (10 -6 , 0, m , 0) generates 21 coexistence attractors with different topological structures, including chaos, periodic one ring, periodic two rings and periodic four rings. As shown in the figure, the invention relates to a construction method of a circuit for generating super-multiple coexistence attractors, based on the above-mentioned circuit for generating super-multiple coexistence attractors, including the following contents: S1. Establish a type of minimalist chaotic system, which can generate up-down symmetrical coexisting single-wing chaotic attractors under different initial states. Its mathematical model is as follows: ;

[0031] In the above formula, x , y , z is the state variable, a To control the parameters; S2. Change the variables of the above mathematical model x Modified to the magnetically controlled memristor term, the dimensionless equation of the memristor-like chaotic system with many coexisting attractors can be established as: ; In the above formula, x , y , z and w are 4 state variables, a is the control parameter of the original three-dimensional system. w is the dimensionless state variable of the magnetically controlled memristor, and W ( w )= α - β | w |.

[0032] S3. Set control parameters a = 3.6, α =1, β = 0.05, the initial state is (1, 0, 7, 0), and numerical simulation is performed to obtain Figure 4 and Figure 5 The simulation results shown are different from the upper and lower single-wing attractors of the original system. Figure 4 and Figure 5 The two-wing chaotic attractor is shown in xz and wy Phase trajectory diagram on a plane.

[0033] S4. Using the circuit of a minimalist chaotic oscillation system, the equation for generating a circuit for generating a large number of coexisting attractors of a memristor chaotic system is as follows: ; The component parameter values ​​of the circuit are obtained through normalized calculation, as shown in Table 1 below:

[0034] S5. The equivalent circuit equation of the equivalent implementation circuit of the magnetically controlled memristor is as follows: .

[0035] See FIG. 6 , which is a diagram showing the experimental simulation results of the circuit for generating a multi-coexisting attractor according to the present invention, and the initial voltage parameter is (10 -6 , 0, m , 0), unit V; it can be concluded from the experiment that the circuit simulation results are almost consistent with the numerical simulation results in Figure 3.

[0036] See also Figure 7 and Figure 8 , Figure 7 and Figure 8This is a typical attractor diagram captured by the super-multiple coexisting attractor circuit experiment of the present invention. The initial voltage parameters are (1, 0, 7, 0), unit V. During the experiment, the experimental waveform is captured by the UTD4204C digital storage oscilloscope. It can be concluded from the experiment that the circuit experimental results are consistent with Figure 4 and Figure 5 The numerical simulation results are almost consistent with those in .

[0037] The above are only specific application examples of the present invention and do not constitute any limitation on the protection scope of the present invention. Any technical solution formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the present invention.

Claims

1. A circuit for generating a large number of coexisting attractors, characterized in that: Including the equivalent realization circuit of the minimalist chaotic oscillation system and the magnetically controlled memristor, the minimalist chaotic oscillation system and the equivalent realization circuit of the magnetically controlled memristor are connected to produce the coexistence phenomenon of super-multiple attractors; The minimalist chaotic oscillation system includes a first integral channel, a second integral channel and a third integral channel. The first integral channel includes a first integrator, which corresponds to an input terminal, and the input terminal is connected to the state variable -0.1 v y v z The second integration channel includes a second integrator, a multiplier M 1 and the reverse amplifier, which correspond to two input terminals, one of which is connected to the state variable - v b , and the other input terminal is connected to the state variable 0.1 v z 2 ; The third integration channel includes a third integrator and a multiplier M 2, which corresponds to two input terminals, one of which is connected to the state variable v y v z , and the other input terminal is connected to the state variable v x ; The equivalent realization circuit of the magnetically controlled memristor includes a fourth integrator circuit, a multiplier M 3. Multiplier M 4. Absolute value operation circuit and addition operation circuit, the state variable corresponding to the input end of the equivalent implementation circuit v x After the fourth integrator performs the integral operation, the output state variable is - v w , and the state variable - v w After passing through the absolute value operation circuit, the output | v w |, and then output through the multiplier| v w | v x ; Finally, the output is through the addition circuit W ( v w ) v x .

2. The circuit for generating a super-multiple coexisting attractors according to claim 1, characterized in that: The input terminal of the first integration channel is connected in series with a resistor R a After the operational amplifier U 1, the inverting input of the operational amplifier U 1. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output state variable 1 v x .

3. The circuit for generating a super-multiple coexisting attractors according to claim 1, characterized in that: The second integral channel access state variable - v b The input series resistor R Then connected to the operational amplifier U 2 inverting input terminal; the second integral channel is connected to the state variable 0.1 v z 2 The input terminal is then connected in series with another resistor of 0.1 R After the operational amplifier U 2, the inverting input of the operational amplifier U 2. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output state variable of output terminal 2 v y .

4. The circuit for generating a super-multiple coexisting attractors according to claim 3, characterized in that: The operational amplifier U 2 output and multiplier M 1 input connection, the multiplier M The other input of 1 is connected to the state variable - v z , the multiplier M The output terminal of 1 outputs the state variable -0.1 v y v z .

5. The circuit for generating a super-multiple coexisting attractors according to claim 4, characterized in that: The multiplier M 1 output and operational amplifier U 3. A series resistor of 0.1 is placed between the input terminals R , the operational amplifier U 3. Connect a resistor in parallel between the inverting input and output R , the operational amplifier U Output terminal 3 outputs state variable v y v z .

6. The circuit for generating a super-multiple coexisting attractors according to claim 1, characterized in that: The access state variable of the third integration channel v y v z The input series resistor R After the operational amplifier U 4; the other access state variable of the third integral channel v x The input end is connected to the equivalent circuit of the magnetically controlled memristor and then connected to the operational amplifier. U 4, the inverting input terminal of the operational amplifier U 4. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U Output terminal 4 outputs state variable - v z The operational amplifier U The output of 4 and the multiplier M 2 input terminals are connected to the multiplier M 2, the two input terminals of the operational amplifier are shorted. U The output terminal 4 outputs the state variable 0.1 v z 2 .

7. The circuit for generating a super-multiple coexisting attractors according to claim 1, characterized in that: The fourth integrator circuit includes a resistor R w ,capacitance C and operational amplifiers U 5. The resistor R w One end is connected to the input end of the equivalent circuit, and the other end is connected to the operational amplifier U 5, the inverting input terminal of the operational amplifier U 5. Connect a capacitor in parallel between the inverting input and output C , the operational amplifier U The output terminal of 5 outputs the state variable - v w .

8. The circuit for generating a super-multiple coexisting attractors according to claim 1, characterized in that: The absolute value operation circuit includes an operational amplifier U 6. Resistance R 1 and resistor R 2. The operational amplifier U The inverting input terminals of 6 are connected to the operational amplifier U 5 output and multiplier M 3. The operational amplifier U 6. Connect the resistor to the output terminal R 1. Resistance R 2 is connected to GND, resistor R 1 and resistor R The other end of 2 is connected to serve as a multiplier M 3 input terminal.

9. The circuit for generating a super-multiple coexisting attractors according to claim 1, characterized in that: The adding circuit includes a resistor R α and resistor R β , the resistor R α One end of the resistor is connected to the input end of the equivalent circuit. R β One end of the multiplier M 4 output terminals are connected, the resistor R α and R β The other end of is connected to serve as the output end of the equivalent implementation circuit.

10. A method for constructing a circuit for generating a super-multiple coexisting attractors according to claim 1, characterized in that: Includes the following: S1. Establish a type of minimalist chaotic system, which can generate up-down symmetrical coexisting single-wing chaotic attractors under different initial states. Its mathematical model is as follows: ； In the above formula, x , y , z is the state variable, a To control the parameters; S2. Change the variables of the above mathematical model x Modified to the magnetically controlled memristor term, the dimensionless equation of the memristor-like chaotic system with many coexisting attractors is: ； In the above formula, x , y , z and w are 4 state variables, a is the control parameter of the original three-dimensional system; in w is the dimensionless state variable of the magnetically controlled memristor, and W ( w )= α - β | w |; S3. Set control parameters a = 3.6, α =1, β =0.05, the initial state is (1, 0, 7, 0), numerical simulation is performed, and the phase trajectory diagram of the simulation results is obtained; S4. Using the circuit of a minimalist chaotic oscillation system, the equation for generating a circuit for generating a large number of coexisting attractors of a memristor chaotic system is as follows: ； S5. The equivalent circuit equation of the equivalent implementation circuit of the magnetically controlled memristor is as follows: 。

Images