Printed circuit board and package-on-package structure

Abstract

The invention provides a printed circuit board and a package-on-package structure. The printed circuit board includes: a first insulating layer; a cavity unit including a first cavity penetrating a portion of the first insulating layer from an upper surface of the first insulating layer in a thickness direction and a second cavity penetrating another portion of the first insulating layer from the first cavity; a first wiring layer disposed on an upper side of the first insulating layer; a second wiring layer disposed on a lower side of the first insulating layer; and a third wiring layer at least partially embedded in the first insulating layer and disposed at a height between the first wiring layer and the second wiring layer in the thickness direction. The third wiring layer includes a plurality of pads, at least a portion of an upper surface of each of the plurality of pads is exposed from the first insulating layer through the cavity unit, and a width of the first cavity is wider than a width of the second cavity in a cross section.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0116123 filed on September 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board and a stacked packaging structure. Background Art

[0003] As the performance of smartphones improves, the thickness of electronic components mounted on packaging substrates is increasing, but the thickness of the device needs to be reduced or maintained. Therefore, it is necessary to form a cavity on the packaging substrate for mounting the electronic components. Summary of the invention

[0004] One of the various objects of the present disclosure is to provide a printed circuit board that can be thinned while including a cavity that allows electronic components to be mounted.

[0005] Another object of the present disclosure is to provide a printed circuit board which can improve thermal characteristics by increasing the thickness of electronic components mounted in a cavity.

[0006] Another object of the present disclosure is to provide a printed circuit board which can be applied to a substrate-on-substrate structure or a package-on-package structure to reduce a space between boards.

[0007] One of the various aspects of the present disclosure is to form a cavity unit including a first cavity and a second cavity of different sizes in a printed circuit board (used as a lower substrate in a substrate-on-substrate structure or a stacked package structure), wherein the cavity unit is capable of exposing a plurality of pads arranged at a height between a plurality of wiring layers based on a thickness direction.

[0008] For example, according to one aspect of the present disclosure, a printed circuit board may include: a first insulating layer; a cavity unit including a first cavity and a second cavity, the first cavity penetrating a portion of the first insulating layer from an upper surface of the first insulating layer in a thickness direction, and the second cavity penetrating another portion of the first insulating layer from the first cavity in the thickness direction; a first wiring layer disposed on an upper side of the first insulating layer; a second wiring layer disposed on a lower side of the first insulating layer; and a third wiring layer at least partially buried in the first insulating layer and disposed at a height between the first wiring layer and the second wiring layer in the thickness direction. The third wiring layer may include a plurality of pads, at least a portion of an upper surface of each of the plurality of pads being exposed from the first insulating layer through the cavity unit, and in a cross section, a width of the first cavity may be wider than a width of the second cavity.

[0009] For example, according to one aspect of the present disclosure, a printed circuit board may include: a first insulating layer; a cavity unit including a first cavity and a second cavity, the first cavity penetrating a portion of the first insulating layer from an upper surface of the first insulating layer in a thickness direction, and the second cavity penetrating another portion of the first insulating layer from the first cavity in the thickness direction; a first wiring layer disposed on an upper side of the first insulating layer; a second wiring layer disposed on a lower side of the first insulating layer; and a third wiring layer at least partially buried in the first insulating layer and disposed at a height between the first wiring layer and the second wiring layer in the thickness direction. The third wiring layer may include a plurality of pads, at least a portion of an upper surface of each of the plurality of pads being exposed from the first insulating layer through the cavity unit, and in a plane, an area of ​​the first cavity may be larger than an area of ​​the second cavity.

[0010] For example, according to another aspect of the present disclosure, a stacked packaging structure includes: the printed circuit board; an electronic component, which is arranged in the cavity unit and connected to the plurality of pads through a plurality of second electrical connection metals; and a wiring board, which has another cavity unit and is connected to the printed circuit board through a plurality of first electrical connection metals, and the other cavity unit is at least partially overlapped with the cavity unit in the thickness direction, wherein the electronic component is arranged between the printed circuit board and the wiring board, and at least a portion of the electronic component is arranged in the cavity unit, and at least another portion of the electronic component is arranged in the other cavity unit.

[0011] As one of various effects of the present disclosure, a printed circuit board can be provided which can be thinned while including a cavity for mounting an electronic component.

[0012] As another effect of the present disclosure, a printed circuit board can be provided which can improve thermal characteristics by increasing the thickness of an electronic component mounted in a cavity.

[0013] As another effect of the present disclosure, a printed circuit board can be provided, which can be applied to a substrate-on-substrate structure or a package-on-package structure to reduce a space between boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example of an electronic device system; Figure 2 is a perspective view schematically showing an example of an electronic device; Figure 3 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board; Figure 4 It is shown Figure 3 A schematic plan view of a printed circuit board in a top view; FIG. 5A to FIG. 5J is a schematic diagram showing the manufacturing Figure 3 A cross-sectional view of an example of a process for producing a printed circuit board; Figure 6 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board; Figure 7 It is schematically shown Figure 6 A plan view of a printed circuit board from a top view; Figure 8 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board; Fig. 9 It is schematically shown Figure 8 A plan view of a printed circuit board from a top view; Fig.10 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board; Fig.11 It is schematically shown Fig.10 a top plan view of a printed circuit board; and Fig.12 is a cross-sectional view schematically illustrating an example embodiment of a substrate-on-substrate structure or a package-on-package structure. DETAILED DESCRIPTION

[0015] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of elements may be exaggerated or reduced for clear description.

[0016] Electronic device.

[0017] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0018] Reference Figure 1 , the electronic device 1000 accommodates a main board 1010 therein. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also connected to other electronic components to be described below through various signal lines 1090.

[0019] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be connected to each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0020] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access Plus (HSPA+), High Speed ​​Downlink Packet Access Plus (HSDPA+), High Speed ​​Uplink Packet Access Plus (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless standards or protocols and wired standards or protocols specified hereafter. However, the network-related component 1030 is not limited thereto and may also include components compatible with or communicating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be connected to the chip-related component 1020.

[0021] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto and may also include passive components in the form of chip components for various other purposes. In addition, other components 1040 may be connected to each other together with chip-related components 1020 and / or network-related components 1030.

[0022] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, but may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD) drive, and a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0023] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, or an automotive component. However, the electronic device 1000 is not limited thereto and may be any other electronic device that processes data.

[0024] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0025] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. The mainboard 1110 may be housed in the smart phone 1100, and the electronic component 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the electronic components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may have the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is mounted on its upper surface. Alternatively, the component package 1121 may have the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0026] Printed circuit board.

[0027] Figure 3 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board.

[0028] Figure 4 It is shown Figure 3 Schematic plan view of a printed circuit board from a top view.

[0029] Referring to the drawings, a printed circuit board 100A according to an example embodiment may include: a first insulating layer 111; a cavity unit C including a first cavity c1 and a second cavity c2, the first cavity c1 penetrating a portion of the first insulating layer 111 from an upper surface of the first insulating layer 111 in a thickness direction, and the second cavity c2 penetrating another portion of the first insulating layer 111 from the first cavity c1 in a thickness direction; a first wiring layer 121 disposed on an upper side of the first insulating layer 111; a second wiring layer 122 disposed on a lower side of the first insulating layer 111; and a third wiring layer 123 at least partially buried in the first insulating layer 111 and disposed at a height between the first wiring layer 121 and the second wiring layer 122 in a thickness direction. The third wiring layer 123 may include a plurality of pads P, at least a portion of an upper surface of each of the plurality of pads P being exposed from the first insulating layer 111 through the cavity unit C. As an example, an upper surface of the third wiring layer 123 exposed through the cavity unit C and a surface of the first insulating layer 111 exposed through the cavity unit C may be disposed at the same height. The size of the first cavity c1 may be greater than the size of the second cavity c2. The size may refer to the width in the cross section, the area in the plane, and the depth in the thickness direction. For example, in the cross section, the width of the first cavity c1 may be wider than the width of the second cavity c2, in the plane, the area of ​​the first cavity c1 may be larger than the area of ​​the second cavity c2, and in the thickness direction, the depth of the first cavity c1 may be deeper than the depth of the second cavity c2.

[0030] In this way, the printed circuit board 100A according to the example embodiment may have a cavity unit C, the cavity unit C includes a first cavity c1 and a second cavity c2 of different sizes formed in the first insulating layer 111, and the cavity unit C may expose a plurality of pads P embedded in the first insulating layer 111 and disposed at a height between the first wiring layer 121 and the second wiring layer 122 based on the thickness direction. Therefore, even when the electronic component is mounted in the cavity unit C, the total thickness of the printed circuit board 100A may be reduced by the cavity unit C. In addition, since the cavity unit C can have a considerable depth, the thickness of the mounted electronic component may be increased, and as a result, the thermal characteristics may be improved. In addition, the printed circuit board 100A of such a structure may be used as a substrate-on-substrate structure or a lower substrate of a stacked package structure, in which case the interval between the upper substrate and the lower substrate may be reduced, thereby reducing the size of the solder ball disposed between the substrates in order to expect a finer ball pitch or increase the number of input / output terminals.

[0031] In addition, the printed circuit board 100A according to the example embodiment may further include a first resist layer 141 disposed on the upper surface of the first insulating layer 111 and having a first opening h1 exposing at least a portion of the first wiring layer 121. The cavity unit C may further include a third cavity c3 connected to the first cavity c1 by passing through the upper and lower surfaces of the first resist layer 141 in the thickness direction. In a cross section, the width of the third cavity c3 may be wider than the width of the first cavity c1, and in a plane, the area of ​​the third cavity c3 is larger than the area of ​​the first cavity c1. In this way, the printed circuit board 100A may also have a third cavity c3 of a different size from the first cavity c1 and the second cavity c2 formed in the first resist layer 141. Therefore, the cavity unit C may also be enlarged, and as a result, the above-mentioned effect may be more easily achieved.

[0032] In addition, the printed circuit board 100A according to the example embodiment may further include: a first via layer 131 penetrating the first insulating layer 111 and connecting at least a portion of each of the first wiring layer 121 and the second wiring layer 122 to each other; and a second via layer 132 penetrating the first insulating layer 111 and connecting at least a portion of each of the second wiring layer 122 and the third wiring layer 123 to each other. In a cross section, the thickness of the first via layer 131 may be thicker than the thickness of the second via layer 132. In this way, the second via layer 132 thinner than the first via layer 131 may be formed in the first insulating layer 111, and a plurality of pads P may be connected to the second wiring layer 122 via a shorter path through the second via layer 132. Therefore, the electrical connection path of the electronic components mounted in the cavity unit C may be further shortened, and as a result, signal characteristics, etc. may be further improved.

[0033] In addition, the printed circuit board 100A according to the example embodiment may further include: a second insulating layer 112 disposed on the lower surface of the first insulating layer 111; a fourth wiring layer 124 disposed on the lower surface of the second insulating layer 112; a third via layer 133 penetrating the second insulating layer 112 and connecting at least a portion of each of the second wiring layer 122 and the fourth wiring layer 124 to each other; and a second resist layer 142 disposed on the lower surface of the second insulating layer 112 and having a second opening h2 exposing at least a portion of the fourth wiring layer 124. Each of the first via layer 131, the second via layer 132, and the third via layer 133 may have a tapered shape in which the width of its lower end is wider than the width of its upper end in a cross section. As described above, the printed circuit board 100A may have a multi-layer coreless board structure, and if necessary, may have a multi-layer structure with more layers than those shown in the drawings.

[0034] In addition, the first wiring layer 121 may include: a first-first wiring layer 121-1 buried in the upper side of the first insulating layer 111; and a first-second wiring layer 121-2 disposed on the upper surface of the first insulating layer 111. The first-first wiring layer 121-1 and the first-second wiring layer 121-2 may be connected to each other. The size of the cross section of the first-second wiring layer 121-2 may be different from the cross-sectional size of the first-first wiring layer 121-1. For example, the size of the cross section of the first-second wiring layer 121-2 may be wider than the cross-sectional size of the first-first wiring layer 121-1, and the upper surface of the first-first wiring layer 121-1 and the lower surface of the first-second wiring layer 121-2 may be in direct contact with each other. In addition, the first opening h1 of the first resist layer 141 may expose at least a portion of the first-second wiring layer 121-2. As described above, the first wiring layer 121 may have a multilayer form in which buried patterns and protruding patterns of different sizes are connected. Therefore, by increasing the thickness of the first resist layer 141, a deeper depth of the third cavity c3 can be achieved, and further, when the printed circuit board 100A according to the example embodiment is used as a substrate-on-substrate structure or a lower substrate in a stacked package structure, the reliability of connection with the solder ball can be further improved.

[0035] In addition, at least two of the plurality of pads P may have different shapes on a plane. For example, when at least one of the plurality of pads P has a circular shape on a plane, the other pads may have a square shape on a plane. However, the present disclosure is not limited thereto, and of course, in addition to a circle and a square, more diverse shapes (such as an ellipse or other polygons) may be applied. In this way, as a process feature described below, the printed circuit board 100A may form a plurality of pads P of various shapes in the cavity unit C, by which the degree of freedom of design may be increased.

[0036] In addition, the thickness of the first-first wiring layer 121-1 may be substantially the same as the depth of the first cavity c1. For example, the first cavity c1 may be formed by removing a metal block (e.g., a metal block 321 described below) formed in the same process as the first-first wiring layer 121-1 from the first insulating layer 111 after forming the first insulating layer 111. In this way, the first cavity c1 may be formed by using the process of forming the first-first wiring layer 121-1, and thus, the cavity unit C may be formed more easily and quickly.

[0037] Hereinafter, components of a printed circuit board 100A according to example embodiments will be described in more detail with reference to the accompanying drawings.

[0038] Each of the first insulating layer 111 and the second insulating layer 112 may include an insulating material.

[0039] The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material prepared by impregnating an inorganic filler, an organic filler, and / or a glass fiber (such as a glass fabric exemplified by glass cloth) into these resins. For example, the insulating material may be a non-photosensitive insulating material such as an Ajinomoto built-up film (ABF) or a prepreg (PPG), but the present disclosure is not limited thereto, and other polymer materials may be used as the insulating material. The first insulating layer 111 and the second insulating layer 112 may include the same insulating material or may include different insulating materials. The first insulating layer 111 and the second insulating layer 112 may have a boundary with each other, or may be integrated to the extent that the boundary between them is unclear.

[0040] Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include copper (Cu), but the present disclosure is not limited thereto. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may perform various functions according to its design. For example, the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may have various forms such as lines, planes, and pads. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer), respectively. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include only an electroplating layer (e.g., an electroplated copper layer) without including an electroless plating layer (e.g., a chemical copper plating layer). If necessary, the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may also include a metal foil (e.g., a copper foil) or a sputtering layer. In addition, each of the first-second wiring layer 121-2, the second wiring layer 122, and the fourth wiring layer 124 may include a seed layer (such as a chemical copper plating layer and / or a copper foil), while the first-first wiring layer 121-1 and the third wiring layer 123 may not include a seed layer.

[0041] Each of the first via layer 131, the second via layer 132, and the third via layer 133 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the first via layer 131, the second via layer 132, and the third via layer 133 may include copper (Cu), but the present disclosure is not limited thereto. Each of the first via layer 131, the second via layer 132, and the third via layer 133 may include a micro via. The micro via may be a filled via that fills the via hole, or may be a conformal via arranged along the wall surface of the via hole. The micro via may be arranged in a stacked type and / or staggered type. The micro vias of the first via layer 131, the second via layer 132, and the third via layer 133 may perform various functions according to the design of the corresponding layer. For example, the first via layer 131, the second via layer 132, and the third via layer 133 may include a ground via, a power via, and a signal via. Each of the first via layer 131, the second via layer 132, and the third via layer 133 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer), but the present disclosure is not limited thereto. The first via layer 131, the second via layer 132, and the third via layer 133 may have a sputtering layer formed instead of an electroless plating layer, and may include both a sputtering layer and an electroless plating layer. Each micro via in the first via layer 131, the second via layer 132, and the third via layer 133 may have a shape that tapers in the same direction.

[0042] The first resist layer 141 and the second resist layer 142 may include a liquid solder resist or a film type solder resist, but are not limited thereto, and may include other types of insulating materials such as ABF. The first resist layer 141 may have a first opening h1, the second resist layer 142 may have a second opening h2, and may have a surface treatment layer formed on a pattern exposed through the first opening h1 and the second opening h2 as required.

[0043] FIG. 5A to FIG. 5J is a schematic diagram showing the manufacturing Figure 3 A cross-sectional view of an example of a process for a printed circuit board.

[0044] Reference Figure 5A , the first-first wiring layer 121-1 and the first metal block 321 are formed on both surfaces of the separation carrier 310. The first metal layer m1 and the second metal layer m2 may be disposed on both surfaces of the separation carrier 310, and the first-first wiring layer 121-1 and the first metal block 321 may be formed by, for example, an electroplating process using the second metal layer m2 as a seed layer.

[0045] Reference Figure 5B, a second metal block 322 is formed on the first metal block 321. The second metal block 322 may be formed, for example, by an electroplating process using the first metal block 321 as a seed layer. The second metal block 322 may include a different type of metal from the first metal block 321. For example, the first metal block 321 may include copper (Cu), and the second metal block 322 may include nickel (Ni), but the present disclosure is not limited thereto.

[0046] Reference Figure 5C , the third wiring layer 123 includes a plurality of pads P formed on the second metal block 322. The third wiring layer 123 may be formed by, for example, an electroplating process using the second metal block 322 as a seed layer. The plurality of pads P may be formed in various shapes.

[0047] Reference Figure 5D , a first insulating layer 111 is formed on both surfaces of the separation carrier 310 to bury the first metal block 321 and the second metal block 322 and the first-first wiring layer 121-1 and the third wiring layer 123 therein. The first insulating layer 111 may be formed by a lamination process. In addition, a second wiring layer 122 and a first via layer 131 and a second via layer 132 are formed on and in the first insulating layer 111. The via holes for the first via layer 131 and the second via layer 132 may be formed by laser processing or the like. The second wiring layer 122 and the first via layer 131 and the second via layer 132 may be formed using, for example, an additive process (AP), a semi-additive process (SAP), a modified SAP (MSAP), a hole sealing (TT) process, or the like.

[0048] Reference Figure 5E , a second insulating layer 112 is formed on the first insulating layer 111 to bury the second wiring layer 122 therein. The second insulating layer 112 may be formed by a lamination process. For example, the second insulating layer 112 may be formed by stacking resin coated copper foil (RCC, Resin Clad Copper) and the like. For example, the third metal layer m3 may be stacked on the outermost side of the second insulating layer 112.

[0049] Reference Fig. 5F , the manufactured stacked body is separated from the separation carrier 310. For example, the first metal layer m1 and the second metal layer m2 may be separated from each other, and the second metal layer m2 may remain in the separated stacked body.

[0050] Reference Figure 5G, a fourth wiring layer 124 and a third via layer 133 are formed on and in the second insulating layer 112. In addition, a first-second wiring layer 121-2 and a third metal block 323 are formed on the first insulating layer 111. The third metal block 323 may include the same metal as the first metal block 321, for example, copper (Cu). A via hole for the third via layer 133 may be formed by laser processing or the like. The first-second wiring layer 121-2, the fourth wiring layer 124, the third metal block 323, and the third via layer 133 may be formed using, for example, an additive process (AP), a semi-additive process (SAP), a modified SAP (MSAP), a hole sealing (TT) process, or the like. The first-second wiring layer 121-2 and the third metal block 323 may include a second metal layer m2, and the fourth wiring layer 124 may include a third metal layer m3.

[0051] Reference Figure 5H , a first resist layer 141 is formed on the first insulating layer 111, and a second resist layer 142 is formed on the second insulating layer 112. The first resist layer 141 and the second resist layer 142 may be formed by a coating process or a lamination process. Next, a first opening h1 and a second opening h2 and a third cavity c3 are formed in the first resist layer 141 and the second resist layer 142. Each of the first opening h1 and the second opening h2 and the third cavity c3 may be formed by laser processing, but the present disclosure is not limited thereto, and other methods such as etching may be used. The surfaces exposed by the first opening h1 and the second opening h2 may be surface-treated (such as gold plating).

[0052] Reference Fig.5I , a first cavity c1 may be formed in the first insulating layer 111. The first cavity c1 may be formed by etching the first metal block 321 and the third metal block 323. The second metal block 322 may include a different type of metal from the first metal block 321 and the third metal block 323, thereby protecting the plurality of pads P.

[0053] Reference Figure 5J , a second cavity c2 is formed in the first insulating layer 111. The second cavity c2 may be formed by etching the second metal block 322. The second metal block 322 may include a different type of metal from the plurality of pads P, and therefore, the plurality of pads P are hardly affected by the etching operation. Through a series of processes, the printed circuit board 100A according to the above-described example embodiment may be manufactured.

[0054] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described exemplary embodiment, and thus, a repeated description thereof will be omitted.

[0055] Figure 6 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board.

[0056] Figure 7 It is schematically shown Figure 6 A plan view of a printed circuit board from a top perspective.

[0057] Referring to the drawings, compared with the printed circuit board 100A according to the above-described example embodiment, in a printed circuit board 100B according to another example embodiment, based on the surface of the first insulating layer 111 as the bottom surface of the cavity unit C, the upper surface of each of the plurality of pads P may be recessed downward to form a step portion with the bottom surface of the cavity unit C. For example, a recess r may be formed on the upper surface of each of the plurality of pads P. Electrically connected metals (such as solder balls) are connected to each other through the recess r, thereby more effectively preventing the occurrence of a short circuit. The plurality of pads P and the above-described second metal block 322 may be formed using the same material (such as the same metal (such as copper (Cu) or nickel (Ni))), so during the etching process of forming the recess r, a portion of each of the plurality of pads P may be removed together with the second metal block 322, but the present disclosure is not limited thereto.

[0058] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described exemplary embodiment, and thus, a repeated description thereof will be omitted.

[0059] Figure 8 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board.

[0060] Fig. 9 It is schematically shown Figure 8 A plan view of a printed circuit board from a top perspective.

[0061] Referring to the drawings, compared with the printed circuit board 100A according to the above-described example embodiment, a printed circuit board 100C according to another example embodiment may further include a pillar portion 125 that fills at least a portion of the first opening h1 to be connected to the exposed portion of the first-second wiring layer 121-2 and is extended on the upper surface of the first resist layer 141. The effect of the cavity unit C may be further enhanced by the pillar portion 125. The pillar portion 125 may be formed by a plating process such as electroless plating (e.g., chemical copper plating) and electroplating (e.g., electroplated copper). The pillar portion 125 may include various pillars such as a signal pillar, a power pillar, and a ground pillar. The pillar portion 125 may include the above-described metal material such as copper (Cu).

[0062] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described exemplary embodiment, and thus, a repeated description thereof will be omitted.

[0063] Fig.10 is a cross-sectional view schematically showing another example embodiment of a printed circuit board, and Fig.11 It is schematically shown Fig.10 A plan view of a printed circuit board from a top perspective.

[0064] Referring to the drawings, compared with the printed circuit board 100A according to the above-described example embodiment, in a printed circuit board 100D according to another example embodiment, the upper surface of each of the plurality of pads P may be recessed downward based on the bottom surface of the cavity unit C to form a stepped portion with the bottom surface of the cavity unit C. For example, a recess r may be formed on the upper surface of each of the plurality of pads P. Electrical connection metals (such as solder balls) may be connected to each other through the recess r, thereby more effectively preventing the occurrence of a short circuit. The plurality of pads P and the above-described second metal block 322 may be formed using the same material (such as the same metal (such as copper (Cu) or nickel (Ni))), so during the etching process of forming the recess r, a portion of each of the plurality of pads P may be removed together with the second metal block 322, but the present disclosure is not limited thereto. In addition, the printed circuit board 100D may further include a pillar portion 125 disposed on the upper surface of the first resist layer 141, filling at least a portion of the first opening h1 and connected to the exposed portion of the first-second wiring layer 121-2. The effect of the cavity unit C may be further enhanced by the pillar portion 125. The pillar portion 125 may be formed by a plating process such as electroless plating (e.g., chemical copper plating) and electroplating (e.g., electroplated copper). The pillar portion 125 may include various pillars such as a signal pillar, a power pillar, and a ground pillar. The pillar portion 125 may include the above-mentioned metal material such as copper (Cu).

[0065] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described exemplary embodiment, and thus, a repeated description thereof will be omitted.

[0066] Fig.12 is a cross-sectional view schematically illustrating an example embodiment of a substrate-on-substrate structure or a package-on-package structure.

[0067] Reference Fig.12In the substrate-on-substrate structure or the package-on-package structure 500 according to the example embodiment, the second substrate 100-2 may be disposed on the first substrate 100-1, the electronic component 210 may be disposed between the first substrate 100-1 and the second substrate 100-2, the first substrate 100-1 and the second substrate 100-2 may be connected by a first electrical connection metal 221, the electronic component 210 may be mounted on the first substrate 100-1 by a second electrical connection metal 222, and the first cavity unit C1 of the first substrate 100-1 and the second cavity unit C2 of the second substrate 100-2 may be connected. At least partially overlapped in the thickness direction, at least a portion of the electronic component 210 may be disposed in the first cavity unit C1 of the first substrate 100-1, at least another portion of the electronic component 210 may be disposed in the second cavity unit C2 of the second substrate 100-2, the third electrical connection metal 223 may be attached to the lower surface of the first substrate 100-1, the passive component 230 may be mounted on the lower surface of the first substrate 100-1 through the fourth electrical connection metal 224, and the space between the first substrate 100-1 and the second substrate 100-2 may be filled with a known molding material 250. The first substrate 100-1 and the second substrate 100-2 may be at least one of the above-mentioned printed circuit boards 100A, 100B, 100C, and 100D. For example, the second substrate 100-2 may be connected to the above-mentioned first wiring layer 121 and / or the above-mentioned pillar 125 through a plurality of first electrical connection metals 221. In addition, as an example, the electronic component 210 may be disposed between the first substrate 100-1 and the second substrate 100-2. In addition, the electronic component 210 can be connected to the above-mentioned multiple pads P through multiple second electrical connection metals 222. The second substrate 100-2 can be a core-type wiring board or a coreless wiring board. The wiring board can be an organic interposer, but is not limited thereto, and can be a silicon interposer if necessary. The electronic component 210 can be an active component and / or a passive component, preferably, a semiconductor chip, but the present disclosure is not limited thereto. The passive component 230 can be a chip capacitor and / or a chip inductor, but the present disclosure is not limited thereto. Each of the first electrical connection metal 221, the second electrical connection metal 222, the third electrical connection metal 223, and the fourth electrical connection metal 224 can be a solder ball or the like. This substrate-on-substrate structure or stacked package structure 500 can reduce the spacing between the first substrate 100-1 and the second substrate 100-2, and thus can reduce the size of the first electrical connection metal 221 disposed between the substrates, thereby expecting a finer ball pitch or increasing the number of input / output terminals. In addition, the total thickness can be minimized, and the electronic component 210 can still have a sufficient thickness. Therefore, thermal characteristics can be improved.

[0068] The other contents are substantially the same as those described with respect to the above-mentioned printed circuit boards 100A, 100B, 100C, and 100D, and therefore, redundant descriptions thereof will be omitted.

[0069] In the present disclosure, the expression "covering" may include the case of covering at least a part as well as the case of covering the whole, and may also include the case of direct covering as well as the case of indirect covering. In addition, the expression "filling" may include not only the case of complete filling but also the case of approximately filling, for example, may include the case of having some holes or gaps.

[0070] In the present disclosure, the meaning of "cross section" may refer to the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when the object is observed from the side. In addition, the meaning of "plane" may refer to the plane shape when an object is cut horizontally, or the plane shape when the object is observed from a top-down perspective or an upward perspective.

[0071] In the present disclosure, thickness, width, length, depth, etc. can be measured with a scanning microscope or an optical microscope based on a cross section of a polished or cut printed circuit board. The cut section can be a vertical section or a horizontal section, and each value of thickness, width, length, depth, etc. can be measured based on the required cut section. When the value is not constant, the value can be determined as the average value of the values ​​measured at any five points. The width of the upper and / or lower part of the via or cavity can be measured on a cross section cut along the central axis of the via or cavity in the thickness direction of the substrate. The depth of the via or cavity can be measured as the distance from the upper part to the lower part of each object on a cross section cut along the central axis of each object in the thickness direction of the substrate.

[0072] In the present disclosure, "lower" in the lower side, lower part, and lower surface is used to refer to the downward direction relative to the cross section of the drawing, and "upper" in the upper side, upper part, and upper surface is used to refer to the opposite direction thereof. In addition, "side" in the side part, side surface, etc. is used to indicate a direction perpendicular to the upper surface and the lower surface. However, this is a direction defined for the convenience of explanation, and the scope of the claims is not particularly limited by the description of such a direction, and the concepts of "upper" and "lower" may be changed at any time.

[0073] In the present disclosure, "connection" includes not only direct connection but also indirect connection through an adhesive layer or the like. In addition, "electrical connection" is a concept including both physical connection and non-physical connection. In addition, expressions such as "first" and "second" are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component without departing from the scope of the claims.

[0074] The expression "exemplary embodiment" used in this disclosure does not mean the same embodiment, and is provided to illustrate different unique features. However, the exemplary embodiments presented above do not exclude being implemented in combination with features of other exemplary embodiments. For example, even if matters described in a particular exemplary embodiment are not described in other exemplary embodiments, they can be understood as descriptions related to other exemplary embodiments unless there are contrary or contradictory descriptions of matters in other exemplary embodiments.

[0075] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless otherwise clearly stated in the context, a singular expression includes a plural expression.

[0076] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a first insulating layer; a cavity unit, comprising a first cavity and a second cavity, wherein the first cavity penetrates a portion of the first insulating layer from an upper surface of the first insulating layer in a thickness direction, and the second cavity penetrates another portion of the first insulating layer from the first cavity in the thickness direction; A first wiring layer, arranged on an upper side of the first insulating layer; A second wiring layer is arranged on the lower side of the first insulating layer; as well as a third wiring layer at least partially buried in the first insulating layer and provided at a height between the first wiring layer and the second wiring layer in the thickness direction, wherein the third wiring layer includes a plurality of pads, at least a portion of an upper surface of each of the plurality of pads is exposed from the first insulating layer through the cavity unit, and In cross section, the width of the first cavity is wider than the width of the second cavity.

2. The printed circuit board according to claim 1, wherein: In the thickness direction, the depth of the first cavity is deeper than the depth of the second cavity.

3. The printed circuit board according to claim 1, wherein: Based on a surface of the first insulating layer as a bottom surface of the cavity unit, the upper surface of each of the plurality of pads is recessed downward to form a stepped portion with the bottom surface of the cavity unit.

4. The printed circuit board according to claim 1, wherein: At least two of the plurality of pads have different shapes in plane.

5. The printed circuit board according to claim 1, wherein The first wiring layer includes: a first-first wiring layer buried in the upper side of the first insulating layer; and a first-second wiring layer provided on the upper surface of the first insulating layer. The first-first wiring layer and the first-second wiring layer are connected to each other, and A size of a cross section of the first-second wiring layer is different from a size of a cross section of the first-first wiring layer.

6. The printed circuit board according to claim 5, wherein: A size of the cross section of the first-second wiring layer is wider than a size of the cross section of the first-first wiring layer.

7. The printed circuit board according to claim 5, wherein: The depth of the first cavity is the same as the thickness of the first-first wiring layer.

8. The printed circuit board according to claim 5, wherein: The first-first wiring layer and the first-second wiring layer are in contact with each other.

9. The printed circuit board according to claim 1, further comprising: a first resist layer disposed on the upper surface of the first insulating layer and having a first opening exposing at least a portion of the first wiring layer, wherein the cavity unit further comprises a third cavity connected to the first cavity by passing through the upper surface and the lower surface of the first resist layer in the thickness direction, and In cross section, the width of the third cavity is wider than the width of the first cavity.

10. The printed circuit board according to claim 9, further comprising: A pillar portion fills at least a portion of the first opening to be connected to the exposed portion of the first wiring layer and is provided on an upper surface of the first resist layer.

11. The printed circuit board according to claim 1, further comprising: a second insulating layer, disposed on a lower surface of the first insulating layer; A fourth wiring layer is arranged on the lower surface of the second insulating layer; a first via layer that penetrates the first insulating layer and connects at least a portion of each of the first wiring layer and the second wiring layer to each other; a second via layer that penetrates the first insulating layer and connects at least a portion of each of the second wiring layer and the third wiring layer to each other; as well as a third via layer penetrating the second insulating layer and connecting at least a portion of each of the second wiring layer and the fourth wiring layer to each other, Wherein, in the cross section, the thickness of the first via layer is thicker than the thickness of the second via layer.

12. The printed circuit board according to claim 11, wherein Each of the first via layer, the second via layer, and the third via layer has a tapered shape in which a width of a lower end thereof is wider than a width of an upper end thereof in a cross section.

13. The printed circuit board according to claim 11, further comprising: A second resist layer is provided on the lower surface of the second insulating layer and has a second opening exposing at least a portion of the fourth wiring layer.

14. The printed circuit board according to claim 1, wherein: An upper surface of the third wiring layer exposed through the cavity unit and a surface of the first insulating layer exposed through the cavity unit are disposed at the same height.

15. A printed circuit board, comprising: a first insulating layer; a cavity unit, comprising a first cavity and a second cavity, wherein the first cavity penetrates a portion of the first insulating layer from an upper surface of the first insulating layer in a thickness direction, and the second cavity penetrates another portion of the first insulating layer from the first cavity in the thickness direction; A first wiring layer, arranged on an upper side of the first insulating layer; A second wiring layer is arranged on the lower side of the first insulating layer; as well as a third wiring layer at least partially buried in the first insulating layer and provided at a height between the first wiring layer and the second wiring layer in the thickness direction, wherein the third wiring layer includes a plurality of pads, at least a portion of an upper surface of each of the plurality of pads is exposed from the first insulating layer through the cavity unit, and In a plane, an area of ​​the first cavity is larger than an area of ​​the second cavity.

16. The printed circuit board according to claim 15, further comprising: a first resist layer disposed on the upper surface of the first insulating layer and having a first opening exposing at least a portion of the first wiring layer, wherein the cavity unit further comprises a third cavity connected to the first cavity by passing through the upper surface and the lower surface of the first resist layer in the thickness direction, and In a plane, an area of ​​the third cavity is larger than an area of ​​the first cavity.

17. The printed circuit board according to claim 16, further comprising: a second insulating layer, disposed on the lower side of the first insulating layer; a fourth wiring layer, disposed below the second insulating layer; a first via layer that penetrates the first insulating layer and connects at least a portion of each of the first wiring layer and the second wiring layer to each other; a second via layer that penetrates the first insulating layer and connects at least a portion of each of the second wiring layer and the third wiring layer to each other; a third via layer penetrating the second insulating layer and connecting at least a portion of each of the second wiring layer and the fourth wiring layer to each other; as well as A second resist layer is provided under the second insulating layer and has a second opening exposing at least a portion of the fourth wiring layer.

18. The printed circuit board according to claim 15, further comprising: An electronic component is disposed in the cavity unit and connected to the plurality of pads through a plurality of second electrical connection metals.

19. A stacked package structure, comprising: A printed circuit board according to any one of claims 1 to 17, an electronic component disposed in the cavity unit and connected to the plurality of pads through a plurality of second electrical connection metals; as well as a wiring board having another cavity unit and connected to the printed circuit board through a plurality of first electrical connection metals, and the another cavity unit at least partially overlaps the cavity unit in the thickness direction, The electronic component is disposed between the printed circuit board and the wiring board, and at least a portion of the electronic component is disposed in the cavity unit, and at least another portion of the electronic component is disposed in the other cavity unit.

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