Wiring substrate, laminated wiring substrate, and method for manufacturing wiring substrate

Abstract

The invention provides a wiring substrate, a laminated wiring substrate, and a method for manufacturing the wiring substrate. The wiring substrate has a first wiring structure and a second wiring structure. The first wiring structure has a mounting surface on which the semiconductor element is mounted and a back surface on the opposite side from the mounting surface. The second wiring structure is formed on the back surface of the first wiring structure. The second wiring structure has a reinforcing insulating layer, a cavity, an electronic component, and a filling resin layer. The reinforcing insulating layer is formed on the back surface of the first wiring structure. The cavity is formed by cutting the reinforcing insulating layer in a direction toward the back surface of the first wiring structure. The electronic component is located in the cavity. The filling resin layer is filled into the cavity for covering the electronic component. The purpose of the present invention is to suppress the diffusion of noise from a semiconductor element.

Description

Technical Field

[0001] The present invention relates to a wiring substrate, a laminated wiring substrate and a method for manufacturing the wiring substrate. Background Art

[0002] Conventionally, there is known a laminated wiring substrate in which, for example, a relay substrate having fine wiring is laminated on a main substrate. In such a laminated wiring substrate, a semiconductor element is sometimes mounted on the relay substrate, and electronic elements such as capacitors are mounted on the main substrate around the relay substrate. The electronic elements mounted on the main substrate have the function of reducing noise generated by the semiconductor elements mounted on the relay substrate.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2001-144207 Summary of the invention

[0004] However, the above-mentioned laminated wiring substrate has a problem that noise from semiconductor elements may spread. Specifically, the semiconductor element mounted on the relay substrate and the electronic element mounted on the main substrate are connected via the wiring of the relay substrate and the wiring of the main substrate, so the length of the wiring between the semiconductor element and the electronic element becomes longer, and the inductance of the wiring increases. As a result, the noise from the semiconductor element will not be sufficiently reduced in the electronic element, and may spread to the periphery of the semiconductor element.

[0005] The technology disclosed in the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wiring substrate, a multilayer wiring substrate, and a method for manufacturing a wiring substrate that can suppress the diffusion of noise from a semiconductor element.

[0006] The wiring substrate disclosed in the present application has a first wiring structure and a second wiring structure in one form. The first wiring structure has a mounting surface for semiconductor elements and a back surface opposite to the mounting surface. The second wiring structure is formed on the back surface of the first wiring structure. The second wiring structure has a reinforced insulating layer, a cavity, an electronic component and a filling resin layer. The reinforced insulating layer is formed on the back surface of the first wiring structure. The cavity is formed by cutting the reinforced insulating layer in a direction toward the back surface of the first wiring structure. The electronic component is located in the cavity. The filling resin layer is filled into the cavity to cover the electronic component.

[0007] According to one aspect of the wiring board disclosed in the present application, it is possible to suppress the spread of noise from semiconductor elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a diagram showing the structure of a substrate according to an embodiment.

[0009] Figure 2It is a diagram showing the structure of a first wiring substrate according to the embodiment.

[0010] Figure 3 This is a flowchart showing a method for manufacturing a first wiring substrate according to an embodiment.

[0011] Figure 4 It is a figure which shows the specific example of a glass support body.

[0012] Figure 5 It is a diagram showing a specific example of the seed layer forming step.

[0013] Figure 6 It is a figure which shows a specific example of the process of forming a resist layer.

[0014] Figure 7 It is a diagram showing a specific example of the electrode pad forming process.

[0015] Figure 8 It is a figure which shows a specific example of the resist layer removal process.

[0016] Fig. 9 It is a diagram showing a specific example of the seed layer removal step.

[0017] Fig.10 It is a diagram showing a specific example of the insulating layer forming step.

[0018] Fig.11 It is a diagram showing a specific example of the seed layer forming step.

[0019] Fig.12 It is a figure which shows a specific example of the process of forming a resist layer.

[0020] Fig.13 It is a figure which shows a specific example of the electrolytic copper plating process.

[0021] Fig.14 It is a figure which shows a specific example of the resist layer removal process.

[0022] Fig.15 It is a diagram showing a specific example of the seed layer removal step.

[0023] Fig.16 It is a diagram showing a specific example of the solder adding step.

[0024] Fig.17 It is a figure which shows a specific example of the adhesive layer forming process.

[0025] Fig.18 1 is a flowchart showing a method for manufacturing a substrate according to an embodiment.

[0026] Fig.19 It is a diagram showing a specific example of the first wiring board mounting process.

[0027] Fig. 20 It is a figure which shows the specific example of the glass support body peeling process.

[0028] Fig.21 A diagram showing a structural example of a semiconductor device.

[0029] Fig. 22 1 is a flowchart showing a method for forming a second wiring structure according to the embodiment.

[0030] Fig.23 It is a diagram showing a specific example of the step of forming a reinforced insulating layer.

[0031] Fig.24 It is a diagram showing a specific example of the through-hole forming step.

[0032] Fig.25 It is a diagram showing a specific example of the seed layer forming step.

[0033] Fig.26 It is a figure which shows a specific example of the process of forming a resist layer.

[0034] Fig. 27 It is a figure which shows a specific example of the electrolytic copper plating process.

[0035] Fig.28 It is a figure which shows a specific example of the resist layer removal process.

[0036] Fig.29 It is a diagram showing a specific example of the seed layer removal step.

[0037] Fig.30 It is a diagram showing a specific example of the cavity forming step.

[0038] Fig.31 It is a diagram showing a specific example of the electronic component arrangement process.

[0039] Fig.32 It is a diagram showing a specific example of the electronic component embedding process.

[0040] Fig.33 It is a diagram showing a specific example of the through-hole forming step.

[0041] Fig.34 It is a diagram showing the structure of a first wiring substrate according to Modification 1 of the embodiment.

[0042] Fig.35 It is a diagram showing a specific example of the cavity forming step.

[0043] Fig.36 It is a diagram showing a specific example of the electronic component arrangement process.

[0044] Fig.37It is a diagram showing the structure of a first wiring substrate according to Modification 2 of the embodiment.

[0045] Fig.38 It is a diagram showing the structure of a first wiring substrate according to Modification 3 of the embodiment.

[0046] Fig.39 It is a diagram showing a specific example of the cavity forming step.

[0047] Fig.40 It is a diagram showing a specific example of the electronic component arrangement process.

[0048] Fig.41 It is a diagram showing the structure of a first wiring substrate according to Modification 4 of the embodiment.

[0049] Fig.42 It is a figure which shows a specific example of the recessed portion forming process.

[0050] Fig.43 It is a diagram showing a specific example of the electronic component arrangement process.

[0051] Explanation of symbols

[0052] 100: first wiring substrate

[0053] 110: First wiring structure

[0054] 110a: upper surface

[0055] 110b: Lower surface

[0056] 112: first film layer

[0057] 113: Second film layer

[0058] 114: The third film layer

[0059] 115: Fourth film layer

[0060] 116: Wiring layer

[0061] 120: Second wiring structure

[0062] 123: Strengthen the insulation layer

[0063] 124:Filling resin layer

[0064] 130: Electronic components

[0065] 170: Cavity

[0066] 200: Second wiring substrate

[0067] 300: Glass support DETAILED DESCRIPTION

[0068] Hereinafter, embodiments of the wiring substrate, the laminated wiring substrate, and the method for manufacturing the wiring substrate disclosed in the present application will be described in detail based on the drawings. In addition, the technology disclosed in the present application is not limited to the embodiments.

[0069] Implementation

[0070] Figure 1 1 is a diagram showing the structure of a substrate according to an embodiment. Figure 1 , a cross section of a substrate according to an embodiment is schematically shown. Figure 1 The substrate shown is a laminated wiring substrate in which a first wiring substrate 100 is laminated on a second wiring substrate 200. Figure 1 The direction from the second wiring substrate 200 to the first wiring substrate 100 is upward, and the direction from the first wiring substrate 100 to the second wiring substrate 200 is downward. However, the first wiring substrate 100 and the second wiring substrate 200 may be manufactured and used, for example, upside down, and may be manufactured and used in any posture.

[0071] The first wiring substrate 100 is a relay substrate having a first wiring structure 110 on which a plurality of thin film layers are stacked, and a second wiring structure 120 as a base layer. An electrode pad 111 is formed on the upper surface 110a of the first wiring structure 110. The electrode pad 111 is formed of a conductor such as copper, for example, and is a connection terminal when a semiconductor element is bonded to the first wiring substrate 100. That is, when a semiconductor element is bonded to the first wiring substrate 100, the semiconductor element is mounted on the upper surface 110a of the first wiring structure 110, and the electrode pad 111 is bonded to an electrode of the semiconductor element by solder. In addition, an electrode pad 121 is formed on the lower surface of the second wiring structure 120. The electrode pad 121 is formed of a conductor such as copper, for example, and is a connection terminal when the first wiring substrate 100 is bonded to the second wiring substrate 200. In addition, the electrode pad 121 is connected to the wiring of the first wiring structure 110 via the wiring layer and via hole inside the second wiring structure 120.

[0072] The second wiring substrate 200 is a main substrate having a core layer 210, a build-up layer 220 stacked on the upper surface of the core layer 210, and a build-up layer 230 stacked on the lower surface of the core layer 210. An electrode pad 221 is formed on the upper surface of the build-up layer 220, and an electrode pad 231 is formed on the lower surface of the build-up layer 230. The electrode pad 221 is formed of, for example, a conductor such as copper, and is a connection terminal when the second wiring substrate 200 is joined to the first wiring substrate 100. The electrode pad 231 is formed of, for example, a conductor such as copper, and is a connection terminal when the second wiring substrate 200 is joined to an external element such as a motherboard. In addition, wiring that electrically connects the electrode pad 221 to the electrode pad 231 is formed inside the core layer 210, inside the build-up layer 220, and inside the build-up layer 230.

[0073] The first wiring substrate 100 is mounted on the second wiring substrate 200. That is, the electrode pad 121 as the connection terminal of the first wiring substrate 100 and the electrode pad 221 as the connection terminal of the second wiring substrate 200 are joined by solder 201. In addition, an adhesive layer 101 is formed between the lower surface of the first wiring substrate 100 (that is, the lower surface of the second wiring structure 120) and the upper surface of the second wiring substrate 200. The adhesive layer 101 adheres the first wiring substrate 100 and the second wiring substrate 200 in a state of covering a part of the side surface of the first wiring substrate 100.

[0074] The first wiring substrate 100 and the second wiring substrate 200 joined by the adhesive layer 101 and the solder 201 are manufactured separately. The first wiring substrate 100 is manufactured on a support made of glass, for example. That is, the first wiring structure 110 is formed on the glass support in a state where the upper surface 110a of the first wiring structure 110 faces the glass support side, and the second wiring structure 120 is laminated on the lower surface 110b of the first wiring structure 110 to manufacture the first wiring substrate 100. Then, after the first wiring substrate 100 and the second wiring substrate 200 manufactured on the glass support are joined by the adhesive layer 101 and the solder 201, the glass support is peeled off from the first wiring substrate 100. As the adhesive layer 101, an insulating resin such as an epoxy resin or a polyimide resin is used.

[0075] Here, refer to Figure 2 , the structure of an intermediate structure formed in the process of manufacturing the first wiring substrate 100 is described. Figure 2 FIG. 1 is a diagram showing a structure of a first wiring substrate 100 according to the embodiment. Figure 2The intermediate structure of the first wiring substrate 100 shown in the figure includes: a glass support 300; a first wiring structure 110 formed on the glass support 300; and a second wiring structure 120 laminated on the lower surface 110b of the first wiring structure 110. The first wiring structure 110 and the second wiring structure 120 are manufactured in a state of being turned upside down on the glass support 300. In addition, an electronic component 130 is embedded in the second wiring structure 120.

[0076] The glass support 300 is a support having a flat upper surface, and a peeling layer 301 is formed on the upper surface. For example, a silicone or acrylic adhesive material is used for the peeling layer 301. The first wiring substrate 100 is obtained by peeling the glass support 300 from the peeling layer 301. For example, the glass support 300 is peeled from the peeling layer 301 after the first wiring substrate 100 and the second wiring substrate 200 manufactured on the glass support 300 are bonded together via the adhesive layer 101 and the solder 201. In addition, a support other than the glass support 300 may be used, and the material of the support may be metal, silicon, ceramic, etc.

[0077] The first wiring structure 110 is a structure having a first thin film layer 112, a second thin film layer 113, a third thin film layer 114, and a fourth thin film layer 115, and having a thickness of, for example, about 30 to 50 μm. At this time, four thin film layers are laminated on the upper surface of the glass support 300 to form the first wiring structure 110, but the number of thin film layers laminated on the upper surface of the glass support 300 may not be four. The first thin film layer 112 to the fourth thin film layer 115 are thin film layers each formed by forming a wiring layer 116 including fine wiring on the insulating layer 110c. The wiring layers 116 of the first thin film layer 112 to the fourth thin film layer 115 are connected through vias 117 penetrating the insulating layer 110c. The via 117 is formed in a truncated cone shape, and its diameter on the electrode pad 111 side is smaller than its diameter on the electrode pad 121 side.

[0078] The insulating layers 110c of the first to fourth thin film layers 112 to 115 are formed using, for example, a photosensitive insulating resin. When forming the fine wiring layer 116 on each insulating layer 110c, a resist is formed on the upper surface of the insulating layer 110c and patterned and electrolytic copper plating is performed.

[0079] The electrode pad 111 is embedded in the bottommost first film layer 112. The electrode pad 111 is formed of a conductor such as copper, and is used as a connection terminal when the semiconductor element is bonded to the first wiring substrate 100. The surface (lower surface) of the first film layer 112 located on the upper surface side of the glass support 300 forms the upper surface 110a of the first wiring structure 110 as the mounting surface of the semiconductor element, and the electrode pad 111 is exposed from the first film layer 112 on the upper surface 110a of the first wiring structure 110. The electrode pad 111 is connected to the wiring layer 116 of the second film layer 113 through a via 117 penetrating the insulating layer 110c of the first film layer 112. As the insulating layer 110c, a photosensitive insulating resin such as epoxy resin or polyimide resin can be used.

[0080] The second wiring structure 120 is a structure having a reinforced insulating layer 123 and a filling resin layer 124 and having a thickness of, for example, about 50 to 100 μm. The reinforced insulating layer 123 is formed by impregnating a reinforcing member such as glass fiber with an insulating resin. By including a reinforcing member in the reinforced insulating layer 123, the rigidity of the second wiring structure 120 becomes greater than the rigidity of the first wiring structure 110, and the strength of the first wiring substrate 100 is improved. The insulating resin impregnated with the reinforcing member of the reinforced insulating layer 123 is, for example, a resin cured by thermal curing such as epoxy resin or polyimide resin. A wiring layer 125 is formed on the surface of the reinforced insulating layer 123. The wiring layer 125 is connected to the wiring of the first wiring structure 110 through a via 126 penetrating the reinforced insulating layer 123. The via 126 is formed in a truncated cone shape, and its diameter on the electrode pad 111 side is smaller than that on the electrode pad 121 side. An electronic component 130 is buried in the reinforced insulating layer 123. A cavity for accommodating the electronic element 130 is formed in the reinforced insulating layer 123 .

[0081] The filling resin layer 124 is a layer formed continuously with the filling resin 135 filled into the cavity in the electronic component embedding process described below. Electrode pads 121 and wiring 127 are formed on the surface of the filling resin layer 124. The electrode pad 121 is formed of a conductor such as copper, and is a connection terminal when the first wiring substrate 100 is joined to the second wiring substrate 200. The wiring 127 is formed of a conductor such as copper, and is a transmission wiring for transmitting input and output signals of the electronic component 130. After the electronic component embedding process, vias 122 and 128 are formed in the filling resin layer 124, and the electrode pad 121 or wiring 127 on the surface of the filling resin layer 124 is connected to the wiring layer 125 on the surface of the reinforcing insulating layer 123 or the electrode 131 of the electronic component 130. The vias 122 and 128 are formed in a truncated cone shape, and the diameter thereof on the electrode pad 111 side is smaller than the diameter on the electrode pad 121 side. The filling resin layer 124 may be formed using the same reinforcing member and insulating resin as the reinforcing insulating layer 123. As the electronic element 130, an electronic element other than a capacitor, such as an inductor or a semiconductor element, may be used.

[0082] The electronic component 130 is, for example, an electronic component such as a capacitor, and has a function of reducing noise generated by a semiconductor element mounted on the upper surface 110a of the first wiring structure 110. The electronic component 130 is embedded in the reinforced insulating layer 123. That is, the electronic component 130 is embedded in the second wiring structure 120 by filling the filling resin 135 around the electronic component 130.

[0083] Thus, in the embodiment, the electronic element 130 is embedded in the second wiring structure 120, so the semiconductor element mounted on the upper surface 110a of the first wiring structure 110 and the electronic element 130 are connected only via the wiring of the first wiring substrate 100 as a relay substrate. That is, the semiconductor element and the electronic element 130 are connected via the electrode pad 111, the wiring layer 116, the via 117, the wiring layer 125, the via 126, the wiring 127 and the via 128 of the first wiring substrate 100. Thus, compared with the structure in which the semiconductor element and the electronic element mounted on the main substrate are connected via the wiring of the relay substrate and the wiring of the main substrate, the length of the wiring between the semiconductor element and the electronic element 130 can be shortened, and the inductance of the wiring can be reduced. As a result, the noise from the semiconductor element can be efficiently reduced in the electronic element 130, so the diffusion of the noise from the semiconductor element can be suppressed. As a reinforcing member for reinforcing the insulating layer 123, a reinforcing member other than glass fiber such as carbon fiber can be used.

[0084] Furthermore, in the embodiment, electronic component 130 is embedded in second wiring structure 120 including a reinforcing member. Therefore, the resistance to stress applied to electronic component 130 can be improved, and the possibility of damage to electronic component 130 can be reduced.

[0085] Furthermore, in the embodiment, the thickness of the second wiring structure 120 is greater than that of the first wiring structure 110. Therefore, the restriction on the element size of the electronic element 130 embedded in the second wiring structure 120 can be reduced.

[0086] In the embodiment, the first wiring structure 110 is formed on the glass support 300 with the upper surface 110a as the mounting surface of the semiconductor element facing the glass support 300. Therefore, the strength of the first wiring substrate 100 is increased, and the handling efficiency of the first wiring substrate 100 is improved.

[0087] in addition, Figure 2 The glass support 300 shown in the figure is peeled off from the first wiring substrate 100 after the first wiring substrate 100 and the second wiring substrate 200 are bonded, but the time point for peeling off the glass support 300 is not limited thereto. Figure 2 The glass support 300 is peeled off at the stage where the first wiring substrate 100 is formed on the glass support 300 shown.

[0088] Then, refer to Figure 3 The flowchart shown in the figure is for manufacturing Figure 2 A method for manufacturing the first wiring substrate 100 shown will be specifically described. Figure 3 1 is a flowchart showing a method for manufacturing the first wiring substrate 100 according to the embodiment.

[0089] First, a glass support 300 is prepared as a support for manufacturing the first wiring substrate 100 (step S101). Figure 4 As shown, a release layer 301 is formed on the flat upper surface of a glass support 300 . Figure 4 3 is a diagram showing a specific example of the glass support 300. In addition, a support other than the glass support 300 may be used, and the material of the support may be metal, silicon, ceramics, or the like.

[0090] Then, for example Figure 5 As shown, the seed layer 302 is formed on the upper surface of the separation layer 301 of the glass support 300 by, for example, sputtering of copper (step S102 ). Figure 5 It is a diagram showing a specific example of the seed layer forming step.

[0091] Then, for example Figure 6As shown, a resist layer 151 having an opening 151a is formed on the seed layer 302 (step S103). The resist layer 151 is formed using, for example, a dry film resist, and the opening 151a can be formed by, for example, photolithography or laser processing. Figure 6 It is a figure which shows a specific example of the process of forming a resist layer.

[0092] After the resist layer 151 is formed, the electrode pad 111 is formed by electrolytic copper plating with power supplied from the seed layer 302 (step S104). Figure 7 As shown, the electrode pad 111 is formed on the seed layer 302 exposed in the opening 151 a of the resist layer 151 . Figure 7 It is a diagram showing a specific example of the electrode pad forming process.

[0093] Next, for example Figure 8 As shown, the resist layer 151 is removed (step S105). Figure 8 1 is a diagram showing a specific example of the resist layer removal step. To remove the resist layer 151, for example, caustic soda or an amine-based alkaline stripping solution is used.

[0094] After the resist layer 151 is removed, the useless portion of the seed layer 302 is removed by flash etching (step S106). Specifically, an etching solution that dissolves the seed layer 302 is used to dissolve the exposed portion of the seed layer 302 that is not in contact with the electrode pad 111, for example. Fig. 9 As shown, the release layer 301 is exposed at a portion other than the portion in contact with the electrode pad 111 . Fig. 9 3 is a diagram showing a specific example of the seed layer removal process. In addition, the seed layer 302 in contact with the electrode pad 111 still remains after the flash etching, but Fig. 9 Illustration omitted.

[0095] After the seed layer 302 is removed, the first wiring structure 110 is formed on the peeling layer 301. First, the insulating layer 110c of the first thin film layer 112 is formed on the peeling layer 301 so as to cover the electrode pad 111 (step S107). The insulating layer 110c is formed using a photosensitive insulating resin, and a through hole is formed by photolithography. Specifically, for example, Fig.10 As shown, at a position corresponding to the electrode pad 111 , a through hole 112 a for exposing the upper surface of the electrode pad 111 is formed in the insulating layer 110 c of the first film layer 112 . Fig.10 The surface (lower surface) of the first thin film layer 112 located on the upper surface side of the glass support 300 forms the upper surface 110a of the first wiring structure 110 as the mounting surface of the semiconductor element, and the electrode pad 111 is exposed from the first thin film layer 112 on the upper surface 110a of the first wiring structure 110.

[0096] Next, a seed layer is formed on the surface of the insulating layer 110c of the first thin film layer 112 by, for example, sputtering of copper (step S108). Fig.11 As shown, a seed layer 112b is formed, and the seed layer 112b covers the surface of the electrode pad 111 exposed in the through hole 112a and the surface of the insulating layer 110c of the first thin film layer 112 including the inner wall of the through hole 112a. Fig.11 It is a diagram showing a specific example of the seed layer forming step.

[0097] After the seed layer 112b is formed, a resist layer for forming the wiring layer 116 of the first thin film layer 112 is formed on the seed layer 112b (step S109). Fig.12 As shown, a resist layer 152 is formed on the seed layer 112b by patterning using exposure and development, and the resist layer 152 has openings in wiring pattern formation portions of fine wiring. Fig.12 It is a figure which shows a specific example of the process of forming a resist layer.

[0098] After the resist layer 152 is formed, for example, by electrolytic copper plating with power supplied from the seed layer 112b, the wiring layer 116 and the via hole 117 of the first thin film layer 112 are formed on the seed layer 112b exposed from the opening of the resist layer 152 (step S110). Fig.13 As shown, electrolytic copper is filled into the through hole 112a to form a via hole 117, and a wiring layer 116 having fine wiring is formed. Fig.13 It is a figure which shows a specific example of the electrolytic copper plating process.

[0099] After forming the wiring layer 116 and the via hole 117 of the first thin film layer 112 by electrolytic copper plating, for example, Fig.14 As shown, the resist layer 152 is removed (step S111). Fig.14 1 is a diagram showing a specific example of the resist layer removal step. To remove the resist layer 152, for example, caustic soda or an amine-based alkaline stripping solution is used.

[0100] After the resist layer 152 is removed, the unnecessary portion of the seed layer 112b is removed by flash etching (step S112), thereby completing the first thin film layer 112 of the first wiring structure 110. Fig.15 As shown, the seed layer 112 b other than the portion in contact with the wiring layer 116 and the via hole 117 is removed, and the first thin film layer 112 having the insulating layer 110 c , the wiring layer 116 and the via hole 117 is stacked on the release layer 301 . Fig.15 1 is a diagram showing a specific example of the seed layer removal process. In addition, the seed layer 112b in contact with the wiring layer 116 and the via hole 117 still remains after the flash etching, but Fig.15Illustration omitted.

[0101] The thin film layers forming the first wiring structure 110 may also be stacked in multiple layers, so whether the process is finished is determined based on whether the stacking of the thin film layers is completed (step S113). If the stacking of the thin film layers is not completed (step S113 is no), the same process as the formation of the first thin film layer 112 is repeated to form the thin film layers after the second thin film layer 113.

[0102] On the other hand, if the lamination of the thin film layer is completed (step S113 is yes), the first wiring structure 110 is completed, and the second wiring structure 120 is formed on the lower surface 110b of the first wiring structure 110 (step S114). That is, the reinforcing insulating layer 123 and the filling resin layer 124 are sequentially laminated on the lower surface 110b of the first wiring structure 110 to form the second wiring structure 120 having the wiring layer 125, the electrode pad 121 and the wiring 127 and embedded with the electronic element 130. The formation process of the second wiring structure 120 will be described in detail below.

[0103] After forming the second wiring structure 120, the Figure 2 That is, an intermediate structure is formed in which the first wiring structure 110 and the second wiring structure 120 are formed on the glass support 300. The first wiring structure 110 and the second wiring structure 120 constitute the first wiring substrate 100.

[0104] Next, in order to bond the first wiring substrate 100 to the second wiring substrate 200, for example, Fig.16 As shown, solder 201 is attached to electrode pad 121 of first wiring substrate 100 (step S115). Fig.16 It is a diagram showing a specific example of the solder adding step.

[0105] After the solder 201 is attached to the electrode pad 121 of the first wiring substrate 100, for example Fig.16 As shown, an adhesive layer 101 covering the electrode pad 121 and the solder 201 is formed on the lower surface of the second wiring structure 120 where the electrode pad 121 is located (step S116). Fig.17 It is a figure which shows a specific example of the adhesive layer forming process.

[0106] Then, refer to Fig.18 The flowchart shown in the figure is for manufacturing Figure 1 The method for manufacturing the substrate shown will be specifically described. Fig.18 1 is a flowchart showing a method for manufacturing a substrate according to an embodiment.

[0107] First, the first wiring substrate 100 manufactured on the glass support 300 is mounted on the second wiring substrate 200 via the adhesive layer 101 (step S121). Fig.19 As shown, the first wiring substrate 100 and the second wiring substrate 200 are bonded together by the adhesive layer 101 in such a manner that the electrode pad 121 of the first wiring substrate 100 and the electrode pad 221 of the second wiring substrate 200 are connected via the solder 201 . Fig.19 It is a diagram showing a specific example of the first wiring board mounting process.

[0108] After the first wiring substrate 100 and the second wiring substrate 200 are bonded together by the adhesive layer 101 and the solder 201, for example, Fig. 20 As shown, the glass support 300 is peeled off from the peeling layer 301 of the first wiring substrate 100 (step S122). Fig. 20 It is a figure which shows the specific example of the glass support body peeling process.

[0109] Next, by removing the peeling layer 301 (step S123), the Figure 1 The illustrated embodiment is a laminated wiring substrate in which a first wiring substrate 100 and a second wiring substrate 200 are laminated.

[0110] Figure 1 The laminated wiring substrate shown can be used, for example, in a semiconductor device that carries a semiconductor element such as a semiconductor chip. Fig.21 As shown, the semiconductor chip 400 is mounted on the upper surface 110 a of the first wiring substrate 100 . Fig.21 4 is a diagram showing a structural example of a semiconductor device. The electrode 410 of the semiconductor chip 400 is bonded to the electrode pad 111 of the first wiring substrate 100 by solder 401. In addition, the bonded portion between the electrode 410 and the electrode pad 111 is encapsulated by an underfill resin 402. Thus, a semiconductor device is obtained in which the semiconductor chip 400 is mounted on the first wiring substrate 100 as a relay substrate via the underfill resin 402.

[0111] In this semiconductor device, the electronic element 130 is embedded in the second wiring structure 120. Therefore, the semiconductor chip 400 mounted on the upper surface 110a of the first wiring structure 110 is connected to the electronic element 130 only via the wiring of the first wiring substrate 100 as a relay substrate. That is, the semiconductor chip 400 and the electronic element 130 are connected via the electrode pad 111, the wiring layer 116, the via 117, the wiring layer 125, the via 126, the wiring 127 and the via 128 of the first wiring substrate 100. As a result, compared with the structure in which the semiconductor chip 400 and the electronic element mounted on the main substrate are connected via the wiring of the relay substrate and the wiring of the main substrate, the length of the wiring between the semiconductor chip 400 and the electronic element 130 can be shortened, and the inductance of the wiring can be reduced. As a result, the noise from the semiconductor chip 400 can be efficiently reduced in the electronic element 130, so that the noise diffusion from the semiconductor chip 400 can be suppressed.

[0112] Then, refer to Fig. 22 The flowchart shown in FIG. 1 specifically describes the process of forming the second wiring structure 120 of the first wiring substrate 100 . Fig. 22 1 is a flowchart showing a method for forming second wiring structure 120 according to the embodiment. Fig. 22 The formation process of the second wiring structure 120 shown in FIG. Figure 3 Step S114.

[0113] First, a reinforced insulating layer 123 is formed on the lower surface 110b of the first wiring structure 110, and the reinforced insulating layer 123 covers the outermost wiring layer 116 of the first wiring structure 110 (step S131). Fig.23 As shown, the uncured reinforcing insulating layer 123 is laminated on the lower surface 110b of the first wiring structure 110, and the wiring layer 116 is covered with the reinforcing insulating layer 123. The reinforcing insulating layer 123 formed on the lower surface 110b of the first wiring structure 110 is thermally cured. Fig.23 It is a diagram showing a specific example of the step of forming a reinforced insulating layer.

[0114] Next, a through hole is formed in the reinforcing insulating layer 123 (step S132). Fig.24 As shown, a through hole 123a is formed which penetrates the reinforcing insulating layer 123 and exposes the surface of the outermost wiring layer 116 of the first wiring structure 110. Fig.24 1 is a diagram showing a specific example of the through hole forming process. The through hole 123a can be formed by laser processing, for example. The residual material (smear) of the insulating resin generated by the laser processing is removed by desmear treatment.

[0115] After forming the through hole 123a, a seed layer is formed on the surface of the reinforcing insulating layer 123 by, for example, sputtering of copper (step S133). Fig.25 As shown, a seed layer 123b is formed to cover the surface of the wiring layer 116 exposed in the through hole 123a and the surface of the reinforcing insulating layer 123 including the inner wall of the through hole 123a. Fig.25 It is a diagram showing a specific example of the seed layer forming step.

[0116] After the seed layer 123b is formed, a resist layer for forming the wiring layer 125 is formed on the seed layer 123b (step S134). Fig.26 As shown, a resist layer 161 is formed on the seed layer 123b by patterning using exposure and development, and the resist layer 161 has an opening in the wiring pattern forming portion. Fig.26 It is a figure which shows a specific example of the process of forming a resist layer.

[0117] After the resist layer 161 is formed, for example, by electrolytic copper plating with power supplied from the seed layer 123b, the wiring layer 125 and the via hole 126 are formed on the seed layer 123b exposed from the opening of the resist layer 161 (step S135). Fig. 27 As shown, electrolytic copper plating is filled into through-hole 123a to form via 126, and wiring layer 125 having a predetermined wiring pattern is formed. Fig. 27 1 is a diagram showing a specific example of the electrolytic copper plating process. In the region of the reinforced insulating layer 123 that is intended to accommodate the electronic element 130, the wiring layer 125 and the via hole 126 are not arranged. Fig. 27 In the example of FIG. 1 , the electronic element 130 is planned to be housed in a region near the center of the reinforced insulating layer 123 , and therefore the wiring layer 125 and the via 126 are not arranged in this region.

[0118] After forming the wiring layer 125 and the via hole 126 by electrolytic copper plating, for example, Fig.28 As shown, the resist layer 161 is removed (step S136). Fig.28 1 is a diagram showing a specific example of the resist layer removal step. To remove the resist layer 161, for example, caustic soda or an amine-based alkaline stripping solution is used.

[0119] After the resist layer 161 is removed, the useless portion of the seed layer 123b is removed by flash etching (step S137). Specifically, the seed layer 123b that is not in contact with the wiring layer 125 and the via hole 126 is removed, for example. Fig.29 As shown, the reinforced insulating layer 123 is exposed except for the portion in contact with the wiring layer 125 and the via 126 . Fig.291 is a diagram showing a specific example of the seed layer removal process. In addition, the seed layer 123b in contact with the wiring layer 125 and the via 126 still remains after the flash etching, but Fig.29 Illustration omitted.

[0120] After the seed layer 123b is removed, a cavity is formed in a predetermined area of ​​the reinforced insulating layer 123 for receiving the electronic element 130 (step S138). Fig.30 As shown, the reinforced insulating layer 123 is cut in a direction toward the lower surface 110 b of the first wiring structure 110 to form the cavity 170 . Fig.30 170 is a diagram showing a specific example of the cavity forming process. The cavity forming process can be realized by laser processing using a CO 2 laser, for example. The reinforcing insulating layer 123 is cut to the lower surface 110 b of the first wiring structure 110 , so that the lower surface 110 b of the first wiring structure 110 is exposed at the bottom surface of the cavity 170 .

[0121] Next, the electronic component 130 is placed in the cavity 170 (step S139). Fig.31 As shown, electronic component 130 is temporarily bonded to lower surface 110b of first wiring structure 110 in cavity 170 using a semi-cured adhesive material (not shown). Fig.31 It is a diagram showing a specific example of the electronic component arrangement process.

[0122] After the electronic component 130 is disposed in the cavity 170, the filling resin 135 is filled into the cavity 170 to embed the electronic component 130 (step S140). Fig.32 As shown, the filling resin 135 is filled into the cavity 170 to form a filling resin layer 124 extending above the electronic element 130 . Thus, the electronic element 130 is buried in the reinforced insulating layer 123 . Fig.32 1 is a diagram showing a specific example of the electronic component embedding process. After the filling resin 135 is filled into the cavity 170 and the filling resin layer 124 is formed, the resin is thermally cured. At the same time, the adhesive for temporarily bonding the electronic component 130 is also thermally cured, so that the electronic component 130 is fixed on the lower surface 110b of the first wiring structure 110 in the cavity 170. By fixing the electronic component 130 on the lower surface 110b of the first wiring structure 110, the heat generated by the electronic component 130 is conducted in the wiring layer 116 of the first wiring structure 110, thereby efficiently dissipating the heat to the outside of the first wiring structure 110. As the adhesive for temporarily bonding the electronic component 130, an adhesive composed of an insulating resin such as an epoxy resin or a polyimide resin can be used.

[0123] Next, a through hole is formed in the filling resin layer 124 (step S141). Fig.33 As shown, through holes 124 a penetrating the filling resin layer 124 and exposing the wiring layer 125 on the surface of the reinforcing insulating layer 123 and through holes 124 b penetrating the filling resin layer 124 and exposing the electrodes 131 of the electronic element 130 are formed. Fig.33 2 is a diagram showing a specific example of a through-hole forming step. The through-holes 124a and 124b can be formed by laser processing, for example.

[0124] The electrode pad 121 and the wiring 127 on the surface of the filling resin layer 124 are formed at the position where the through holes 124a and 124b are formed (step S142). The electrode pad 121 and the wiring 127 are formed, for example, by SAP (Semi Additive Process). While forming the electrode pad 121 and the wiring 127, the via holes 122 and 128 are formed, so that the electrode pad 121 or the wiring 127 on the surface of the filling resin layer 124 is connected to the wiring layer 125 on the surface of the reinforcing insulating layer 123 or the electrode 131 of the electronic element 130. Thus, the second wiring structure 120 in which the electronic element 130 is embedded is completed.

[0125] Then, refer to Figure 34 to Figure 43 Various modifications of the embodiment will be described. In the various modifications described below, the same reference numerals may be used to denote the same parts as those of the embodiment, thereby omitting duplicate descriptions.

[0126] Fig.34 1 is a diagram showing a structure of a first wiring substrate 100 according to a first modification of the embodiment. In the first wiring substrate 100 according to the first modification, the fixing method of the electronic component 130 embedded in the reinforced insulating layer 123 is different from that of the above-described embodiment.

[0127] Specifically, in Modification 1, the cavity of the reinforcing insulating layer 123 does not penetrate to the lower surface 110b of the first wiring structure 110, and the bottom of the cavity is formed by the reinforcing insulating layer 123. Next, the electronic component 130 is fixed on the reinforcing insulating layer 123 forming the bottom of the cavity.

[0128] In Modification 1, by fixing the electronic element 130 on the reinforced insulating layer 123 forming the bottom surface of the cavity, the reinforced insulating layer 123 can be located between the electronic element 130 and the lower surface 110b of the first wiring structure 110. Therefore, the resistance to the stress applied to the electronic element 130 can be further improved, and the possibility of damage to the electronic element 130 can be further reduced.

[0129] Next, refer to Fig.35 and Fig.36, a method for manufacturing the first wiring substrate 100 of the modification example 1 of the manufacturing embodiment will be specifically described. In the method for manufacturing the first wiring substrate 100 of the modification example 1, the cavity forming step ( Fig. 22 Step S138) and the electronic component configuration step ( Fig. 22 Step S139) is different from the implementation method. Fig.35 It is a diagram showing a specific example of the cavity forming step. Fig.36 It is a diagram showing a specific example of the electronic component arrangement process.

[0130] After the seed layer 123b is removed, a cavity is formed in a predetermined area of ​​the reinforced insulating layer 123 for receiving the electronic element 130. Fig.35 As shown, the reinforcing insulating layer 123 is cut to a position that does not reach the lower surface 110 b of the first wiring structure 110 to form the cavity 170 . The bottom surface of the cavity 170 is formed by the reinforcing insulating layer 123 .

[0131] Next, the electronic component 130 is disposed in the cavity 170. Specifically, for example, Fig.36 As shown, the electronic component 130 is temporarily bonded to the reinforced insulating layer 123 located at the bottom surface of the cavity 170 using a semi-cured adhesive material (not shown). Then, in the subsequent electronic component embedding process, while the filling resin layer 124 is thermally cured, the adhesive temporarily bonding the electronic component 130 is also thermally cured, so that the electronic component 130 is fixed to the reinforced insulating layer 123 located at the bottom surface of the cavity 170. By fixing the electronic component 130 to the reinforced insulating layer 123 located at the bottom surface of the cavity 170, the reinforced insulating layer 123 is located between the electronic component 130 and the lower surface 110b of the first wiring structure 110, and the resistance to the stress applied to the electronic component 130 is further improved. Thereafter, implementation Fig. 22 The steps after step 140 are performed to complete the first wiring substrate 100 of variation example 1.

[0132] Fig.37 1 is a diagram showing a structure of a first wiring substrate 100 according to a second modification of the embodiment. In the first wiring substrate 100 according to the second modification of the embodiment, the point that a plurality of electronic components 130 are embedded in a second wiring structure 120 is different from the first modification described above.

[0133] Specifically, in Modification 2, a plurality of cavities 170 are formed in the reinforced insulating layer 123 of the second wiring structure 120, and the plurality of electronic components 130 are respectively located in the plurality of cavities 170. Next, the filling resin layer 124 of the second wiring structure 120 is filled into the plurality of cavities 170 to cover the plurality of electronic components 130. Thus, the plurality of electronic components 130 are embedded in the second wiring structure 120.

[0134] As described above, in Modification 2, since the plurality of electronic components 130 are embedded in the second wiring structure 120 , the noise from the semiconductor element can be effectively reduced in the plurality of electronic components 130 , and the spread of the noise from the semiconductor element can be further suppressed.

[0135] Fig.38 1 is a diagram showing a structure of a first wiring substrate 100 according to a third modification of the embodiment. In the first wiring substrate 100 according to the third modification, the fixing method of the electronic component 130 embedded in the reinforced insulating layer 123 is different from that of the above-described embodiment.

[0136] Specifically, in Modification 3, pad 118 is formed on wiring layer 116, which is the outermost layer of first wiring structure 110, and the cavity of reinforcing insulating layer 123 reaches pad 118. In addition, pad 118 can be formed by using a resist having an opening corresponding to the shape of pad 118 when forming wiring layer 116. Next, electronic element 130 is fixed on pad 118 exposed from the bottom surface of the cavity of reinforcing insulating layer 123.

[0137] In Modification 3, electronic component 130 is fixed on pad 118 of wiring layer 116 , so that heat generated by electronic component 130 is conducted in wiring layer 116 of first wiring structure 110 , thereby efficiently dissipating heat to the outside of first wiring structure 110 .

[0138] Next, refer to Fig.39 and Fig.40 , a method for manufacturing the first wiring substrate 100 of the third modification of the manufacturing embodiment will be specifically described. In the method for manufacturing the first wiring substrate 100 of the third modification, the cavity forming step ( Fig. 22 Step S138) and the electronic component configuration step ( Fig. 22 Step S139) is different from the implementation method. Fig.39 It is a diagram showing a specific example of the cavity forming step.

[0139] Fig.40 is a diagram showing a specific example of the electronic component configuration process. Fig.39In the embodiment, before the cavity forming step is performed, the pad 118 is already formed on the outermost wiring layer 116 of the first wiring structure 110 .

[0140] After the seed layer 123b is removed, a cavity is formed in a predetermined area of ​​the reinforced insulating layer 123 for receiving the electronic element 130. Fig.39 As shown, the reinforcing insulating layer 123 is cut to the pad 118 to form the cavity 170. The cavity forming step can be achieved by, for example, performing laser processing using a CO2 laser. In the laser processing, the pad 118 acts as a stop layer for the laser, so that the cavity 170 with a flat bottom surface can be obtained. The pad 118 is exposed on the bottom surface of the cavity 170. The pad 118 has a planar shape (e.g., a rectangle) that is larger than the planar shape of the bottom surface of the cavity 170. Therefore, the side surface of the pad 118 is located at a position further outward than the side surface of the cavity 170.

[0141] Next, the electronic component 130 is disposed in the cavity 170. Specifically, for example, Fig.40 As shown, the electronic component 130 is temporarily bonded to the pad 118 located on the bottom surface of the cavity 170 using a semi-cured adhesive material (not shown). Then, in the subsequent electronic component embedding process, while the filling resin layer 124 is thermally cured, the adhesive temporarily bonding the electronic component 130 is also thermally cured, thereby fixing the electronic component 130 on the pad 118 located on the bottom surface of the cavity 170. By fixing the electronic component 130 on the pad 118 of the wiring layer 116, the heat generated by the electronic component 130 is conducted in the wiring layer 116 of the first wiring structure 110, thereby efficiently dissipating the heat to the outside of the first wiring structure 110. Thereafter, the implementation Fig. 22 The steps after step 140 are performed to complete the first wiring substrate 100 of variation example 3.

[0142] Fig.41 1 is a diagram showing a structure of first wiring substrate 100 according to Modification 4 of the embodiment. In first wiring substrate 100 according to Modification 4, the structure of the cavity of reinforcing insulating layer 123 and the structure of filling resin layer 124 are different from those in the above-described embodiment.

[0143] Specifically, in Modification 4, the side surface of the cavity of the reinforcing insulating layer 123 has a recess 171 at a position adjacent to the bottom surface of the cavity. Next, a part of the filling resin layer 124 is stored in the recess 171 of the cavity.

[0144] In the fourth modification, by storing a part of the filling resin layer 124 in the concave portion 171 of the cavity, it is possible to improve the adhesion between the filling resin layer 124 and the cavity of the reinforcing insulating layer 123 by the anchor effect.

[0145] Next, refer to Fig.42 and Fig.43 , a manufacturing method of the first wiring substrate 100 of the modification example 4 of the manufacturing embodiment is specifically described. In the manufacturing method of the first wiring substrate 100 of the modification example 4, it is different from the modification example 3 in that a concave portion forming step is included between the cavity forming step and the electronic component placement step. Furthermore, in the manufacturing method of the first wiring substrate 100 of the modification example 4, the electronic component placement step is different from the modification example 3. Fig.42 It is a figure which shows a specific example of the recessed portion forming process. Fig.43 It is a diagram showing a specific example of the electronic component arrangement process.

[0146] After forming the cavity 170 reaching the pad 118 in the reinforced insulating layer 123 (see Fig.39 ), a concave portion 171 is formed on the side of the cavity 170. Specifically, the pad 118 is removed by etching, thereby, for example, Fig.42 As shown, a recess 171 is formed on the side surface of the cavity 170. At the bottom surface of the cavity 170, the lower surface 110b of the first wiring structure 110 is exposed.

[0147] Next, the electronic component 130 is disposed in the cavity 170. Specifically, for example, Fig.43 As shown, the electronic component 130 is temporarily bonded to the lower surface 110b of the first wiring structure 110 in the cavity 170 using a semi-cured adhesive material (not shown). Then, in the subsequent electronic component embedding process, while the filling resin layer 124 is thermally cured, the adhesive that temporarily bonds the electronic component 130 is also thermally cured, thereby fixing the electronic component 130 on the lower surface 110b of the first wiring structure 110 in the cavity 170. In addition, in the electronic component embedding process, by storing a portion of the filling resin layer 124 in the recessed portion 171 of the cavity, the adhesion between the filling resin layer 124 and the cavity 170 of the reinforced insulating layer 123 can be improved through the anchoring effect. Thereafter, the implementation Fig. 22 The steps after step 140 are performed to complete the first wiring substrate 100 of variation example 4.

[0148] As described above, the wiring substrate of the embodiment (as an example, the first wiring substrate 100) has a first wiring structure (as an example, the first wiring structure 110) and a second wiring structure (as an example, the second wiring structure 120). The first wiring structure has a mounting surface of the semiconductor element (as an example, the upper surface 110a) and a back surface opposite to the mounting surface (as an example, the lower surface 110b). The second wiring structure is formed on the back of the first wiring structure. The second wiring structure has a reinforced insulating layer (as an example, the reinforced insulating layer 123), an electronic component (as an example, the electronic component 130) and a filling resin layer (as an example, the filling resin layer 124). The reinforced insulating layer is formed on the back of the first wiring structure. The electronic component is located in a cavity (as an example, the cavity 170) formed by cutting the reinforced insulating layer in the direction toward the back of the first wiring structure. The filling resin layer is filled into the cavity to cover the electronic component. As a result, the diffusion of noise from the semiconductor element can be suppressed.

Claims

1. A wiring substrate, characterized in that: have: A first wiring structure having a mounting surface for a semiconductor element and a back surface opposite to the mounting surface; as well as a second wiring structure formed on the back side of the first wiring structure, The second wiring structure has: a reinforced insulating layer formed on the back surface of the first wiring structure; a cavity formed by cutting the reinforced insulating layer in a direction toward the back surface of the first wiring structure; an electronic component located in the cavity; and A filling resin layer is filled into the cavity to cover the electronic component.

2. The wiring substrate according to claim 1, wherein: The electronic component is located in the cavity formed by cutting the reinforced insulating layer to the back surface of the first wiring structure, and is fixed to the back surface of the first wiring structure.

3. The wiring substrate according to claim 1, wherein: The electronic component is located in the cavity formed by cutting the reinforced insulating layer to a position that does not reach the back surface of the first wiring structure, and is fixed to the reinforced insulating layer forming the bottom surface of the cavity.

4. The wiring substrate according to claim 1, wherein: The second wiring structure has a plurality of the electronic components. The plurality of electronic components are respectively located in the plurality of cavities formed by cutting the reinforced insulating layer in a direction toward the back surface of the first wiring structure. The filling resin layer is filled into the plurality of cavities to cover the plurality of electronic components.

5. The wiring substrate according to claim 1, wherein: The thickness of the second wiring structure is greater than or equal to the thickness of the first wiring structure.

6. The wiring substrate according to claim 1, wherein: It also has a support body, The first wiring structure is formed on the support body in a state where the mounting surface faces the support body side.

7. A laminated wiring substrate, which is formed by laminating a wiring substrate on another wiring substrate, characterized in that: The wiring substrate comprises: A first wiring structure having a mounting surface for a semiconductor element and a back surface opposite to the mounting surface; as well as a second wiring structure formed on the back side of the first wiring structure, The second wiring structure has: a reinforced insulating layer formed on the back surface of the first wiring structure; a cavity formed by cutting the reinforced insulating layer in a direction toward the back surface of the first wiring structure; an electronic component located within the cavity; and A filling resin layer is filled into the cavity to cover the electronic component.

8. The laminated wiring substrate according to claim 7, wherein: An electrode pad is provided on the opposite surface of the filling resin layer which is located opposite to the first wiring structure. Other electrode pads are provided on the surface of the other wiring substrate. The electrode pad is electrically connected to the other electrode pads, and the wiring substrate is stacked on the other wiring substrates.

9. A method for manufacturing a wiring substrate, characterized in that: The process is as follows: forming a first wiring structure having a mounting surface for a semiconductor element and a back surface opposite to the mounting surface; as well as forming a second wiring structure on the back side of the first wiring structure, The step of forming the second wiring structure includes: forming a reinforced insulating layer on the back surface of the first wiring structure; cutting the reinforced insulating layer in a direction toward the back surface of the first wiring structure to form a cavity; disposing an electronic component in the formed cavity; and The cavity is filled with a filling resin for covering the electronic component.

10. The method for manufacturing a wiring substrate according to claim 9, wherein: The step of forming the first wiring structure includes: preparing a support; and The first wiring structure is formed on the support body so that the mounting surface is in contact with the support body.

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