Enhanced semiconductor structure and manufacturing method thereof
By etching the trench in the silicon carbide junction field effect transistor and doping in situ selective epitaxial to form a third semiconductor layer with multi-layer doping concentration and width, the lattice damage and channel width inaccurate when ion implantation forms a PN junction is solved, and higher device reliability and lower open-state resistance are achieved.
Patent Information
- Application Number
- CN202311091211.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-28
- Publication Date
- 2025-03-04
AI Technical Summary
In the prior art, when silicon carbide junction field effect transistors form PN junctions through ion implantation, it is easy to cause lattice damage and inaccurate channel width, which in turn affects the reliability of the device.
By sequentially growing the first semiconductor layer of the first conductive type and the second semiconductor layer on the substrate, and etching the trench on the side of the second semiconductor layer away from the substrate, the selective epitaxial second conductive type third semiconductor layer is in situ doped in the trench, the third semiconductor layer having at least two different doping concentrations in the first direction and at least two different widths in the second direction.
The PN junction between the third semiconductor layer and the first semiconductor layer formed by in-situ doping selective epitaxial method is realized, which improves the width accuracy of the channel and the reliability of the device, and adjusts the shape of the depletion layer and the channel, reduces the open-state resistance and increases the breakdown voltage.
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Figure CN119562541A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an enhanced semiconductor structure and a manufacturing method thereof. Background Art
[0002] Silicon carbide junction field effect transistor (SiC JFET) is a depletion-mode device that controls the drain-source current by applying voltage to the PN junction to change the conduction channel. Silicon carbide JFET devices have the advantages of simple driving, no gate oxide layer, and high reliability, and are very suitable for use in high-temperature, high-voltage, and high-reliability power systems.
[0003] The selective doping in silicon carbide devices to obtain the above-mentioned PN junction is achieved through ion implantation. First, a very high ion implantation energy is required during the implantation process, which places high demands on the implantation equipment; second, high ion implantation energy can easily cause great damage to the lattice of the implanted material; in addition, the diffusion of the implanted ions makes the channel width inaccurate, and the unreliable PN junction is easily broken down, resulting in leakage. Summary of the invention
[0004] In view of this, the embodiments of the present disclosure provide an enhanced semiconductor structure and a method for manufacturing the same to solve the problems caused by forming a PN junction of a silicon carbide junction field effect transistor through ion implantation in the prior art.
[0005] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing an enhanced semiconductor structure, characterized in that it includes the following steps:
[0006] S1, providing a substrate of a first conductivity type;
[0007] S2, sequentially growing a first semiconductor layer of a first conductivity type and a second semiconductor layer of a first conductivity type on the substrate, wherein the substrate and the second semiconductor layer have a higher doping concentration than the first semiconductor layer;
[0008] S3, etching a groove on a side of the second semiconductor layer away from the substrate, wherein the groove penetrates the second semiconductor layer and partially penetrates the first semiconductor layer;
[0009] S4. In-situ doping and selective epitaxially growing a third semiconductor layer of a second conductivity type in the groove, wherein the third semiconductor layer has at least two different doping concentrations along a first direction and at least two different widths along a second direction, wherein the first direction is perpendicular to the plane of the substrate, and the second direction is parallel to an extension direction of the groove.
[0010] As an optional embodiment, along the first direction, the doping concentration of the third semiconductor layer varies in a periodic manner, gradually increases, gradually decreases, increases first and then decreases, or decreases first and then increases.
[0011] As an optional embodiment, along the first direction, the width of the third semiconductor layer changes in a manner of being constant, gradually increasing, or gradually decreasing.
[0012] As an optional embodiment, along the second direction, the width of the third semiconductor layer varies in a manner of gradually increasing, gradually decreasing, increasing in a step-like manner, decreasing in a step-like manner, first increasing and then decreasing, or first decreasing and then increasing.
[0013] As an optional embodiment, a projection shape of a side wall of the third semiconductor layer extending along the second direction on a plane where the substrate is located is a sine wave, a rectangular wave or a triangular wave.
[0014] As an optional embodiment, the sidewall of the third semiconductor layer extending along the second direction has a plurality of protrusions, and along the second direction, the widths of the plurality of protrusions first increase and then decrease.
[0015] As an optional embodiment, a plurality of the protrusions are arranged at intervals or adjacent to each other.
[0016] As an optional embodiment, along the second direction, the widths of two adjacent third semiconductor layers are complementary.
[0017] As an optional embodiment, the groove is etched twice to form a bottom rounded structure.
[0018] As an optional embodiment, the step S3 further includes:
[0019] S31 , performing ion implantation on the surface of the first semiconductor layer exposed by the groove to form a fourth semiconductor layer of the second conductivity type.
[0020] As an optional embodiment, the fourth semiconductor layer has a doping concentration greater than that of the third semiconductor layer.
[0021] As an optional embodiment, the step S4 further includes:
[0022] S41, in-situ doping and selective epitaxially growing a third semiconductor layer of the second conductivity type in the trench, wherein the thickness of the third semiconductor layer is greater than the depth of the trench.
[0023] S42, using chemical mechanical polishing to remove excess third semiconductor layer from the surface of the second semiconductor layer, and planarizing the surface of the second semiconductor layer.
[0024] As an optional embodiment, the step S4 further includes:
[0025] S5. Form a source, a drain and a gate, wherein the source is located on a surface of the second semiconductor layer away from the substrate, the drain is located on a surface of the substrate away from the second semiconductor layer, and the gate is located on a surface of the third semiconductor layer away from the substrate.
[0026] According to another aspect of the present disclosure, an embodiment of the present disclosure provides an enhanced semiconductor structure, characterized in that it includes:
[0027] A substrate of a first conductivity type, a first semiconductor layer, and a second semiconductor layer are stacked in sequence, wherein the substrate and the second semiconductor layer have a higher doping concentration than the first semiconductor layer;
[0028] a groove, the groove penetrating the second semiconductor layer and partially penetrating the first semiconductor layer, wherein a third semiconductor layer of the second conductivity type is provided in the groove;
[0029] The third semiconductor layer has at least two different doping concentrations along a first direction and at least two different widths along a second direction, the first direction is perpendicular to the plane where the substrate is located, and the second direction is parallel to the extension direction of the groove.
[0030] As an optional embodiment, the depth of the groove is 0.1-2 μm.
[0031] As an optional embodiment, the distance between two adjacent grooves is 0.1-1 μm.
[0032] As an optional embodiment, the enhanced semiconductor structure further comprises:
[0033] A fourth semiconductor layer of the second conductivity type is located in the first semiconductor layer below the trench.
[0034] As an optional embodiment, the width of the fourth semiconductor layer is greater than or equal to the width of the third semiconductor layer.
[0035] As an optional embodiment, the thickness of the fourth semiconductor layer is 50-500 nm.
[0036] The present disclosure provides an enhanced semiconductor structure and a method for manufacturing the same. The present disclosure comprises a stacked arrangement of a substrate of a first conductive type, a first semiconductor layer, and a second semiconductor layer, an etching groove penetrating the second semiconductor layer and partially penetrating the first semiconductor layer, and in-situ doping and selective epitaxially growing a third semiconductor layer of a second conductive type in the groove, wherein the third semiconductor layer has at least two different doping concentrations along a first direction and at least two different widths along a second direction.
[0037] Beneficial effect 1: The present invention etches the grooves and then selectively epitaxies the third semiconductor layer in situ, so that the third semiconductor layer with different conductivity types forms a PN junction with the first semiconductor layer, and the channel is in a depletion state when the gate voltage is 0, thereby realizing an enhanced semiconductor structure. The method of etching the grooves can control the shape of the third semiconductor layer by controlling the shape of the grooves, thereby regulating the shape of the depletion layer and the shape of the channel, while the method of in-situ doping and selective epitaxy can control the doping concentration of the third semiconductor layer, thereby changing the equivalent width of the depletion layer. The combination of the two methods can regulate the depletion layer and the channel of the semiconductor structure in multiple dimensions. In addition, the third semiconductor layer is formed by the method of in-situ doping and selective epitaxy, which avoids the lattice damage to the first semiconductor layer caused by the ion implantation method, and avoids the inaccurate width of the third semiconductor layer caused by the diffusion effect of the ion implantation method, thereby improving the width accuracy of the channel between the third semiconductor layers, so as to improve the reliability of the enhanced semiconductor structure.
[0038] Beneficial effect 2: The present invention simultaneously adjusts the width of the third semiconductor layer along the first direction and the second direction, thereby adjusting the shape of the depletion layer of the PN junction formed by the third semiconductor layer and the first semiconductor layer. On the one hand, when the gate voltage is 0, the channel is completely pinched off by the depletion layer to realize an enhanced semiconductor structure. On the other hand, when in the on state, the shape of the conduction channel changes with the shape of the third semiconductor layer, thereby having a larger electron movement path and reducing the on-state resistance of the semiconductor structure.
[0039] Beneficial effect 3: The present disclosure partially modulates the carrier concentration in the first semiconductor layer, that is, modulates the carrier concentration in the channel, by controlling the doping concentration of the third semiconductor layer. The effect of the locally modulated carrier concentration is: in the off state, the change in the doping concentration of the third semiconductor layer can increase the depletion layer width, reduce the peak electric field, and thus increase the breakdown voltage; in the on state, the structure has the characteristic of reducing the on-resistance, so that the semiconductor structure has a lower voltage drop at the same time under the condition of high current density when it is turned on. Thereby improving the energy conversion efficiency of the system using the structure.
[0040] Beneficial effect 4: before the second epitaxial growth of the third semiconductor layer in the trench, the present invention forms a fourth semiconductor layer of the same conductivity type as the third semiconductor layer by ion implantation in the trench, which is beneficial to improving the lattice quality of the third semiconductor layer, thereby improving the reliability of the overall device structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1 Shown is a flow chart of a method for manufacturing an enhanced semiconductor structure provided by an embodiment of the present disclosure.
[0042] Figures 2 to 7c Shown Figure 1Schematic diagram of the intermediate structure corresponding to the process shown.
[0043] Figures 8a to 8i Shown is a schematic top view of an intermediate structure of an enhanced semiconductor structure provided by an embodiment of the present disclosure.
[0044] Figure 9a to Figure 9g Shown is a schematic top view of an intermediate structure of an enhanced semiconductor structure provided by an embodiment of the present disclosure.
[0045] Figures 10a to 10e The figure shows a schematic diagram of the variation of doping concentration of multiple sub-layers of the third semiconductor layer along a direction away from the substrate in an embodiment of the present disclosure.
[0046] Fig.11 Shown is a schematic diagram of an intermediate structure of an enhanced semiconductor structure provided by an embodiment of the present disclosure.
[0047] Fig.12 Shown is a schematic structural diagram of an enhanced semiconductor structure provided by an embodiment of the present disclosure.
[0048] Figures 13a to 13c Shown is a schematic structural diagram of an enhanced semiconductor structure provided by an embodiment of the present disclosure.
[0049] Fig.14 Shown is a schematic structural diagram of an enhanced semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0050] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0051] In order to solve the problems caused by the formation of PN junction by ion implantation of silicon carbide junction field effect transistor in the prior art, the present disclosure provides an enhanced semiconductor structure and a manufacturing method thereof, wherein a substrate of a first conductive type, a first semiconductor layer and a second semiconductor layer are stacked, a groove is etched to penetrate the second semiconductor layer and partially penetrate the first semiconductor layer, and a third semiconductor layer of a second conductive type is selectively epitaxially doped in situ in the groove, wherein the third semiconductor layer has at least two different doping concentrations along a first direction and at least two different widths along a second direction. The width accuracy of the third semiconductor layer can be improved by using the in-situ doping selective epitaxial method, thereby improving the width accuracy of the channel between the third semiconductor layers, so as to improve the reliability of the enhanced semiconductor structure.
[0052] Combine the following Figures 1 to 14An enhanced semiconductor structure and a method for manufacturing the same mentioned in the present disclosure are further illustrated by way of example.
[0053] Figure 1 Shown is a flow chart of a method for manufacturing an enhanced semiconductor structure provided by an embodiment of the present disclosure; Figures 2 to 7c Shown Figure 1 Schematic diagram of the intermediate structure corresponding to the process shown.
[0054] Step S1: Figure 2 As shown, a first conductive type substrate 10 is provided. The material of the substrate 10 includes silicon carbide.
[0055] Step S2: Figure 3 As shown, a first semiconductor layer 20 of a first conductivity type and a second semiconductor layer 30 of a first conductivity type are sequentially grown on a substrate 10, and the substrate 10 and the second semiconductor layer 30 have a higher doping concentration than the first semiconductor layer 20. The material of the first semiconductor layer 20 and the second semiconductor layer 30 is the same as that of the substrate 10, including silicon carbide.
[0056] Step S3: Figure 4a As shown, a trench 31 is etched on a side of the second semiconductor layer 30 away from the substrate 10 , and the trench 31 penetrates the second semiconductor layer 30 and partially penetrates the first semiconductor layer 20 .
[0057] In this embodiment, the depth of the groove 31 is 0.1-2 μm, and the spacing between two adjacent grooves 31 is 0.1-1 μm. The channel width of the semiconductor structure can be controlled by controlling the spacing between two adjacent grooves 31. The width of the groove 31 can be constant in the direction away from the substrate 10 (e.g. Figure 4a As shown), gradually increase (as shown Figure 4b as shown) or gradually decreases (as shown Figure 4c As shown in FIG. 3 , by controlling the width of the trench 31, the width of the third semiconductor layer 40 subsequently grown in the trench 31 can be controlled. Figure 5 As shown, the groove 31 can be etched twice to form a bottom rounded structure. The bottom rounded structure of the groove 31 reduces the electric field strength at the bottom of the groove 31, thereby increasing the breakdown voltage.
[0058] In one embodiment, step S3 further includes:
[0059] Step S31: Figure 6As shown, ion implantation is performed on the surface of the first semiconductor layer 20 exposed by the groove 31 to form a fourth semiconductor layer 41 of the second conductivity type. The fourth semiconductor layer 41 has a doping concentration greater than that of the third semiconductor layer 40 subsequently grown in the groove 31 to prevent the injection of minority carriers during forward operation. Due to the diffusion of the implanted ions, the width of the fourth semiconductor layer 41 is greater than or equal to the width of the groove 31, that is, the width of the fourth semiconductor layer 41 is greater than or equal to the width of the third semiconductor layer 40 subsequently grown in the groove 31. The thickness of the fourth semiconductor layer 41 is 50-500nm. Before the third semiconductor layer 40 is epitaxially grown for the second time in the groove 31, ion implantation is performed in the groove 31 to form a fourth semiconductor layer 41 of the same conductivity type as the third semiconductor layer 40, which is beneficial to improve the lattice quality of the third semiconductor layer 40 subsequently grown on the surface of the fourth semiconductor layer 41, thereby improving the reliability of the overall device structure.
[0060] Step S4: Figure 7a As shown, a third semiconductor layer 40 of a second conductivity type is selectively epitaxially doped in situ in the groove 31, and the third semiconductor layer 40 has at least two different doping concentrations along a first direction and at least two different widths along a second direction, the first direction is perpendicular to the plane where the substrate 10 is located, and the second direction is parallel to the extension direction of the groove 31. After etching the groove 31, the third semiconductor layer 40 is selectively epitaxially doped in situ, so that the third semiconductor layer 40 of different conductivity types and the first semiconductor layer 20 form a PN junction, and the channel is in a depletion state when the gate voltage is 0, thereby realizing an enhanced semiconductor structure. The method of etching the groove 31 can control the shape of the third semiconductor layer 40 by controlling the shape of the groove 31, thereby regulating the shape of the depletion layer and the channel, while the method of in-situ doping and selective epitaxy can control the doping concentration of the third semiconductor layer 40, thereby changing the equivalent width of the depletion layer. The combination of the two methods can regulate the depletion layer and the channel of the semiconductor structure in multiple dimensions. Furthermore, the third semiconductor layer 40 is formed by an in-situ doping and selective epitaxial method, thereby avoiding lattice damage to the first semiconductor layer 20 caused by the ion implantation method, and avoiding inaccurate width of the third semiconductor layer 40 caused by the diffusion effect of the ion implantation method, thereby improving the width accuracy of the channel between the third semiconductor layers 40, so as to improve the reliability of the enhanced semiconductor structure.
[0061] In this embodiment, since the width of the groove 31 along the first direction can be constant (eg Figure 4a As shown), gradually increase (as shown Figure 4b as shown) or gradually decreases (as shown Figure 4c As shown in FIG. 1 , the width of the third semiconductor layer 40 subsequently grown in the trench 31 can be controlled by controlling the width of the trench 31, so the width of the third semiconductor layer 40 along the first direction can also remain unchanged (as shown in FIG. 1 ). Figure 7a As shown), gradually increase (as shown Figure 7b as shown) or gradually decreases (as shown Figure 7c As shown). By designing the width of the groove 31 to adjust the width of the third semiconductor layer 40, the contact interface between the third semiconductor layer 40 and the side of the first semiconductor layer 20 is an inclined surface. The third semiconductor layer 40 and the first semiconductor layer 20 have different conductivity types, that is, the contact interface of the formed PN junction can be an inclined surface. By controlling the shape of the PN junction contact interface, the breakdown voltage is effectively improved and the reverse breakdown voltage is increased. On the other hand, in the on state, since the contact interface is an inclined surface, the conduction channel is also an inclined channel. The electrons flowing from the source to the drain can be dispersed to both sides while flowing downward, which increases the movement path of the electrons, thereby further reducing the on-state resistance of the semiconductor structure.
[0062] In this embodiment, Figures 8a to 8i FIG. 1 is a schematic top view of an intermediate structure of an enhanced semiconductor structure provided by an embodiment of the present disclosure. The width variation of the third semiconductor layer 40 grown in the trench 31 can also be controlled by controlling the width variation of the trench 31 along the second direction. Along the second direction, the width variation of the third semiconductor layer 40 is gradually increased (e.g., Figure 8a As shown), gradually decrease (as shown Figure 8b As shown), step-like increase, step-like decrease, increase first and then decrease (as shown Figure 8c as shown) or decreases first and then increases (as shown Figure 8d Optionally, the projection shape of the sidewall of the third semiconductor layer 40 extending along the second direction on the plane where the substrate 10 is located may be a sine wave (eg Figure 8e As shown), rectangular wave (as Figure 8f as shown) or a triangle wave (as Figure 8g Optionally, the sidewall of the third semiconductor layer 40 extending along the second direction has a plurality of protrusions 41, and along the second direction, the width of the plurality of protrusions 41 increases first and then decreases, and the plurality of protrusions 41 are arranged at intervals (such as Figure 8h as shown) or adjacent to each other (as shown Figure 8i By changing the width of the third semiconductor layer 40 along the second direction, on the one hand, the channel shape can be changed, the electron movement path can be increased, thereby reducing the on-state resistance, and on the other hand, the depletion layer width can be changed to reduce the peak electric field, thereby increasing the breakdown voltage. On the other hand, the shape of the gate 51 can be the same as the shape of the third semiconductor layer 40, which can provide different gate control capabilities at different positions, thereby improving the linearity of the semiconductor device.
[0063] In this embodiment, Figure 9a to Figure 9g FIG. 1 is a schematic top view of an intermediate structure of an enhanced semiconductor structure provided by an embodiment of the present disclosure. The width variation of the third semiconductor layer 40 grown in the trench 31 is controlled by controlling the width variation of the trench 31 along the second direction. Figure 9a to Figure 9gAs shown, along the second direction, the widths of two adjacent third semiconductor layers 40 are complementary, that is, the sum of the widths of the two adjacent third semiconductor layers 40 remains unchanged, and the channel width between the two adjacent third semiconductor layers 40 remains unchanged. On the one hand, the shape of the conduction channel changes with the shape of the third semiconductor layer 40, thereby having a larger electron movement path and reducing the on-state resistance of the semiconductor structure. On the other hand, the channel width between the two adjacent third semiconductor layers 40 remains unchanged, which can improve the uniformity of the channel conduction current, thereby improving the stability of the semiconductor structure.
[0064] In this embodiment, Figures 10a to 10e FIG. 4 is a schematic diagram showing the variation of the doping concentration of the third semiconductor layer along a direction away from the substrate according to an embodiment of the present disclosure. Along the first direction, the doping concentration of the third semiconductor layer 40 varies in a periodic manner (eg Fig.10a As shown), gradually increase (as shown Fig.10b As shown), gradually decrease (as shown Fig.10c As shown), first increase and then decrease (as shown Fig.10d as shown) or decreases first and then increases (as shown Fig.10e As shown). The doping concentration of the third semiconductor layer 40 is controlled by an in-situ doping selective epitaxial process to locally modulate the carrier concentration in the first semiconductor layer 20, that is, to modulate the carrier concentration in the channel. The effect of the locally modulated carrier concentration is: in the off state, the change in the doping concentration of multiple sublayers of the third semiconductor layer 40 can increase the depletion layer width, reduce the peak electric field, and thus increase the breakdown voltage; in the on state, the structure has the characteristic of reducing the on-resistance, so that the semiconductor structure has a lower voltage drop at the same time under the condition of high current density when it is turned on. Thereby improving the energy conversion efficiency of the system using the structure.
[0065] In one embodiment, Fig.11 The figure shows an intermediate structure schematic diagram of an enhanced semiconductor structure provided by an embodiment of the present disclosure, and step S4 further includes:
[0066] Step S41: In-situ doping and selective epitaxy of a third semiconductor layer 40 of the second conductivity type is performed in the trench 31, and the thickness of the third semiconductor layer 40 is greater than the depth of the trench 31. The third semiconductor layer 40 has a healing plane (such as Fig.11 shown).
[0067] Step S42: chemical mechanical polishing is used to remove the excess third semiconductor layer 40 on the surface of the second semiconductor layer 30, and the surface of the second semiconductor layer 30 is flattened. Chemical mechanical polishing (CMP) can remove the excess third semiconductor layer 40 on the surface of the second semiconductor layer 30 and obtain a flat surface without scratches and impurities. The thickness of the third semiconductor layer 40 is strictly controlled without growth, and the surface quality of the semiconductor structure after chemical mechanical polishing is good.
[0068] In one embodiment, Fig.12 The structure diagram of the enhanced semiconductor structure provided by an embodiment of the present disclosure is shown. After step S4, the following steps are further included:
[0069] Step S5: forming a source electrode 51, a drain electrode 52 and a gate electrode 53, wherein the source electrode 51 is located on the surface of the second semiconductor layer 30 away from the substrate 10, the drain electrode 52 is located on the surface of the substrate 10 away from the second semiconductor layer 30, and the gate electrode 53 is located on the surface of the third semiconductor layer 40 away from the substrate 10, forming Fig.12 semiconductor structure.
[0070] According to another aspect of the present disclosure, the present disclosure also provides an enhanced semiconductor structure. Figures 13a to 13c FIG. 1 is a schematic diagram of a structure of an enhanced semiconductor structure provided by an embodiment of the present disclosure. Fig.13a As shown, the enhanced semiconductor structure includes: a substrate 10 of the first conductivity type, a first semiconductor layer 20 and a second semiconductor layer 30 which are stacked in sequence, the substrate 10 and the second semiconductor layer 30 having a higher doping concentration than the first semiconductor layer 20; a groove 31, the groove 31 penetrates the second semiconductor layer 30 and partially penetrates the first semiconductor layer 20, and a third semiconductor layer 40 of the second conductivity type is provided in the groove 31; wherein the third semiconductor layer 40 has at least two different doping concentrations along the first direction and at least two different widths along the second direction, the first direction is perpendicular to the plane where the substrate 10 is located, and the second direction is parallel to the extension direction of the groove 31. The depth of the groove 31 is 0.1-2μm, and the spacing between two adjacent grooves 31 is 0.1-1μm. The channel width of the semiconductor structure can be controlled by controlling the spacing between two adjacent grooves 31. Fig.13a As shown, the enhanced semiconductor structure further includes a source 51 located on the second semiconductor layer 30 away from the surface of the substrate 10 , a drain 52 located on the substrate 10 away from the surface of the second semiconductor layer 30 , and a gate 53 located on the third semiconductor layer 40 away from the surface of the substrate 10 .
[0071] In this embodiment, the width of the third semiconductor layer 40 is constant along the first direction (eg Fig.13a ), gradually increase (such as Fig.13bas shown) or gradually decreases (as shown Fig.13c As shown). By designing the width of the groove 31 to adjust the width of the third semiconductor layer 40, the contact interface between the third semiconductor layer 40 and the side of the first semiconductor layer 20 is an inclined surface. The third semiconductor layer and the first semiconductor layer have different conductivity types, that is, the contact interface of the formed PN junction can be an inclined surface. By controlling the shape of the PN junction contact interface, the breakdown voltage is effectively improved and the reverse breakdown voltage is increased. On the other hand, in the on state, since the contact interface is an inclined surface, the conduction channel is also an inclined channel. The electrons flowing from the source to the drain can be dispersed to both sides while flowing downward, which increases the moving path of the electrons, thereby further reducing the on-state resistance of the semiconductor structure.
[0072] In this embodiment, the width of the third semiconductor layer 40 gradually increases along the second direction (eg Figure 8a As shown), gradually decrease (as shown Figure 8b As shown), step-like increase, step-like decrease, increase first and then decrease (as shown Figure 8c as shown) or decreases first and then increases (as shown Figure 8d Optionally, the projection shape of the sidewall of the third semiconductor layer 40 extending along the second direction on the plane where the substrate 10 is located may be a sine wave (eg Figure 8e As shown), rectangular wave (as Figure 8f as shown) or a triangle wave (as Figure 8g Optionally, the sidewall of the third semiconductor layer 40 extending along the second direction has a plurality of protrusions 41, and along the second direction, the width of the plurality of protrusions 41 increases first and then decreases, and the plurality of protrusions 41 are arranged at intervals (such as Figure 8h as shown) or adjacent to each other (as shown Figure 8i By changing the width of the third semiconductor layer 40 along the second direction, on the one hand, the channel shape can be changed, the electron movement path can be increased, thereby reducing the on-state resistance, and on the other hand, the depletion layer width can be changed to reduce the peak electric field, thereby increasing the breakdown voltage. On the other hand, the shape of the gate 51 can be the same as the shape of the third semiconductor layer 40, which can provide different gate control capabilities at different positions, thereby improving the linearity of the semiconductor structure.
[0073] In this embodiment, Figure 9a to Figure 9g FIG. 1 is a schematic top view of an intermediate structure of an enhanced semiconductor structure provided by an embodiment of the present disclosure. The width variation of the third semiconductor layer 40 grown in the trench 31 is controlled by controlling the width variation of the trench 31 along the second direction. Figure 9a to Figure 9gAs shown, along the second direction, the widths of two adjacent third semiconductor layers 40 are complementary, that is, the sum of the widths of the two adjacent third semiconductor layers 40 remains unchanged, and the channel width between the two adjacent third semiconductor layers 40 remains unchanged. On the one hand, the shape of the conduction channel changes with the shape of the third semiconductor layer 40, thereby having a larger electron movement path and reducing the on-state resistance of the semiconductor structure. On the other hand, the channel width between the two adjacent third semiconductor layers 40 remains unchanged, which can improve the uniformity of the channel conduction current, thereby improving the stability of the semiconductor structure.
[0074] In this embodiment, along the first direction, the doping concentration of the third semiconductor layer 40 changes in a periodic manner (eg Fig.10a As shown), gradually increase (as shown Fig.10b As shown), gradually decrease (as shown Fig.10c As shown), first increase and then decrease (as shown Fig.10d as shown) or decreases first and then increases (as shown Fig.10e As shown). The doping concentration of the third semiconductor layer 40 is controlled by an in-situ doping selective epitaxial process to locally modulate the carrier concentration in the first semiconductor layer 20, that is, to modulate the carrier concentration in the channel. The effect of the locally modulated carrier concentration is: in the off state, the change in the doping concentration of multiple sublayers of the third semiconductor layer 40 can increase the depletion layer width, reduce the peak electric field, and thus increase the breakdown voltage; in the on state, the structure has the characteristic of reducing the on-resistance, so that the semiconductor structure has a lower voltage drop at the same time under the condition of high current density when it is turned on. Thereby improving the energy conversion efficiency of the system using the structure.
[0075] In one embodiment, Fig.14 FIG. 1 is a schematic diagram of the structure of an enhanced semiconductor structure provided by an embodiment of the present disclosure. Fig.14 As shown, the enhanced semiconductor structure further includes: a fourth semiconductor layer 41 of the second conductivity type, and the fourth semiconductor layer 41 is located in the first semiconductor layer 20 below the groove 31. The fourth semiconductor layer 41 has a doping concentration greater than that of the third semiconductor layer 40 to prevent the injection of minority carriers during forward operation. Due to the diffusion of the injected ions, the width of the fourth semiconductor layer 41 is greater than or equal to the width of the groove 31, that is, the width of the fourth semiconductor layer 41 is greater than or equal to the width of the third semiconductor layer 40 subsequently grown in the groove 31. The thickness of the fourth semiconductor layer 41 is 50-500nm. Before preparing the third semiconductor layer 40, a fourth semiconductor layer 41 of the same conductivity type as the third semiconductor layer 40 is first formed, which is beneficial to improve the lattice quality of the third semiconductor layer 40 subsequently grown on the surface of the fourth semiconductor layer 41, thereby improving the reliability of the overall device structure.
[0076] The present disclosure provides an enhanced semiconductor structure and a method for manufacturing the same, comprising stacking a substrate of a first conductive type, a first semiconductor layer, and a second semiconductor layer, etching a groove that penetrates the second semiconductor layer and partially penetrates the first semiconductor layer, and in-situ doping and selective epitaxy are performed in the groove to form a third semiconductor layer of the second conductive type. The third semiconductor layer has at least two different doping concentrations along a first direction and at least two different widths along a second direction. The in-situ doping and selective epitaxy method can improve the width accuracy of the third semiconductor layer, thereby improving the width accuracy of the channel between the third semiconductor layers, thereby improving the reliability of the enhanced semiconductor structure.
[0077] It should be understood that the term "including" and its variations used in the present disclosure are open inclusions, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.
[0078] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A method for manufacturing an enhanced semiconductor structure, characterized in that: The following steps are involved: S1, providing a substrate (10) of a first conductivity type; S2, sequentially growing a first semiconductor layer (20) of a first conductivity type and a second semiconductor layer (30) of a first conductivity type on the substrate (10), wherein the substrate (10) and the second semiconductor layer (30) have a higher doping concentration than the first semiconductor layer (20); S3, etching a groove (31) on a side of the second semiconductor layer (30) away from the substrate (10), wherein the groove (31) penetrates the second semiconductor layer (30) and partially penetrates the first semiconductor layer (20); S4. In-situ doping and selective epitaxy of a third semiconductor layer (40) of a second conductivity type is performed in the groove (31), wherein the third semiconductor layer (40) has at least two different doping concentrations along a first direction and at least two different widths along a second direction, wherein the first direction is perpendicular to the plane where the substrate (10) is located, and the second direction is parallel to the extension direction of the groove (31).
2. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: Along the first direction, the doping concentration of the third semiconductor layer (40) varies in a periodic manner, gradually increases, gradually decreases, increases first and then decreases, or decreases first and then increases.
3. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: Along the first direction, the width of the third semiconductor layer (40) varies in the following ways: unchanged, gradually increasing, or gradually decreasing.
4. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: Along the second direction, the width of the third semiconductor layer (40) changes in a manner of gradually increasing, gradually decreasing, increasing in a step-like manner, decreasing in a step-like manner, increasing first and then decreasing, or decreasing first and then increasing.
5. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: The projection shape of the side wall of the third semiconductor layer (40) extending along the second direction on the plane where the substrate (10) is located is a sine wave, a rectangular wave or a triangular wave.
6. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: The side wall of the third semiconductor layer (40) extending along the second direction has a plurality of protrusions (41), and along the second direction, the widths of the plurality of protrusions (41) first increase and then decrease.
7. The method for manufacturing an enhanced semiconductor structure according to claim 6, characterized in that: The plurality of protrusions (41) are arranged at intervals or adjacent to each other.
8. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: Along the second direction, the widths of two adjacent third semiconductor layers (40) are complementary.
9. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: The groove (31) is etched twice to form a bottom rounded structure.
10. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: The step S3 further comprises: S31, performing ion implantation on the surface of the first semiconductor layer (20) exposed by the groove (31) to form a fourth semiconductor layer (41) of the second conductivity type.
11. The method for manufacturing an enhanced semiconductor structure according to claim 10, characterized in that: The fourth semiconductor layer (41) has a doping concentration greater than that of the third semiconductor layer (40).
12. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: The step S4 further comprises: S41, in-situ doping and selective epitaxially forming a third semiconductor layer (40) of the second conductivity type in the trench (31), wherein the thickness of the third semiconductor layer (40) is greater than the depth of the trench (31). S42: using chemical mechanical polishing to remove the redundant third semiconductor layer (40) on the surface of the second semiconductor layer (30), and performing a planarization process on the surface of the second semiconductor layer (30).
13. The method for manufacturing an enhanced semiconductor structure according to claim 1, characterized in that: The step S4 further comprises: S5. Forming a source electrode (51), a drain electrode (52) and a gate electrode (53), wherein the source electrode (51) is located on a surface of the second semiconductor layer (30) away from the substrate (10), the drain electrode (52) is located on a surface of the substrate (10) away from the second semiconductor layer (30), and the gate electrode (53) is located on a surface of the third semiconductor layer (40) away from the substrate (10).
14. An enhanced semiconductor structure, characterized in that: include: A substrate (10) of a first conductivity type, a first semiconductor layer (20) and a second semiconductor layer (30) are stacked in sequence, wherein the substrate (10) and the second semiconductor layer (30) have a higher doping concentration than the first semiconductor layer (20); A groove (31), the groove (31) penetrates the second semiconductor layer (30) and partially penetrates the first semiconductor layer (20), and a third semiconductor layer (40) of the second conductivity type is provided in the groove (31); The third semiconductor layer (40) has at least two different doping concentrations along a first direction and at least two different widths along a second direction, the first direction is perpendicular to the plane where the substrate (10) is located, and the second direction is parallel to the extension direction of the groove (31).
15. The enhanced semiconductor structure according to claim 14, characterized in that: The depth of the groove (31) is 0.1-2 μm.
16. The enhanced semiconductor structure according to claim 14, characterized in that: The distance between two adjacent grooves (31) is 0.1-1 μm.
17. The enhanced semiconductor structure according to claim 14, characterized in that: The enhanced semiconductor structure further comprises: A fourth semiconductor layer (41) of the second conductivity type, wherein the fourth semiconductor layer (41) is located in the first semiconductor layer (20) below the trench (31).
18. The enhanced semiconductor structure according to claim 17, characterized in that: The width of the fourth semiconductor layer (41) is greater than or equal to the width of the third semiconductor layer (40).
19. The enhanced semiconductor structure according to claim 17, characterized in that: The thickness of the fourth semiconductor layer (41) is 50-500 nm.