Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, an epitaxial layer, a gate electrode, a source electrode, a drain electrode, a passivation layer, a floating conductive layer and an organic material layer. The epitaxial layer is disposed on the substrate. The gate electrode is disposed on the epitaxial layer. The source electrode and the drain electrode are arranged on the epitaxial layer and located on the two sides of the gate electrode. The passivation layer is disposed on the gate electrode, the source electrode and the drain electrode. The floating conductive layer is disposed on the passivation layer. The organic material layer is disposed on the floating conductive layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure and a method for forming the same, and more particularly to a semiconductor structure including a floating conductive layer and a method for forming the same. Background Art

[0002] Gallium nitride (GaN) materials are widely used because of their wide band-gap and strong polarization effect. For example, GaN-based semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) including heterojunction structures.

[0003] However, in a high electron mobility transistor, there may be charge trapping and / or uneven electric field distribution between or within its layers, which may lead to degradation of the electrical performance of the high electron mobility transistor. Therefore, although existing semiconductor structures and their formation methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor structures and their formation methods. Summary of the invention

[0004] The semiconductor structure disclosed in the present invention may include a floating conductive layer disposed between a passivation layer and an organic material layer, thereby reducing or avoiding degradation of the components below due to the charge trapping effect of the organic material layer. Furthermore, the floating conductive layer can avoid the electric field interaction between the contact pad on the upper layer of the floating conductive layer and the field plate on the lower layer, which causes electrical degradation of the components. In addition, by disposing a floating conductive layer in the semiconductor structure, the semiconductor structure can also be prevented from being affected by external electromagnetic interference (EMI), thereby avoiding unexpected failures. Therefore, the semiconductor structure disclosed in the present invention can be free from the effects of charge trapping effects, electric field interactions between upper and lower metal layers, and / or external electromagnetic interference, thereby improving the reliability of the semiconductor structure.

[0005] In some embodiments, the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, an epitaxial layer, a gate electrode, a source electrode and a drain electrode, a passivation layer, a floating conductive layer and an organic material layer. The epitaxial layer is disposed on the substrate. The gate electrode is disposed on the epitaxial layer. The source electrode and the drain electrode are disposed on the epitaxial layer and are located on both sides of the gate electrode. The passivation layer is disposed on the gate electrode, the source electrode and the drain electrode. The floating conductive layer is disposed on the passivation layer. The organic material layer is disposed on the floating conductive layer.

[0006] In some embodiments, the present disclosure provides a method for forming a semiconductor structure. Provide a substrate. Form an epitaxial layer on the substrate. Form a gate electrode on the epitaxial layer. Form a source electrode and a drain electrode on the epitaxial layer, and the source electrode and the drain electrode are located on both sides of the gate electrode. Form a passivation layer on the gate electrode, the source electrode, and the drain electrode. Form a floating conductive layer on the passivation layer. Form an organic material layer on the floating conductive layer.

[0007] The semiconductor structure and the method for forming the same disclosed in the present invention can be applied to various types of electronic devices and the methods for forming the same. To make the components and advantages of the present invention more clearly understood, various embodiments are given below and described in detail with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read together with the drawings, the present disclosure can be more fully understood from the following detailed description. It is worth noting that, in accordance with standard practice in the industry, the components are not drawn to scale. In fact, the size of each component can be arbitrarily enlarged or reduced for clarity.

[0009] Figures 1 to 9 Each of them is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.

[0010] Fig.10 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure.

[0011] Fig.11 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.

[0012] Fig.12 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure.

[0013] Fig.13 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.

[0014] Fig.14 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure.

[0015] [Explanation of symbols]

[0016] 1,2,3:Semiconductor structure

[0017] 100:Substrate

[0018] 120: epitaxial layer

[0019] 140: bottom dielectric layer

[0020] 160: bottom metal layer

[0021] 200: Gate electrode

[0022] 220: first interlayer dielectric layer

[0023] 240: Gate field plate

[0024] 260: Second interlayer dielectric layer

[0025] 320: Source electrode

[0026] 330: Source field plate

[0027] 340: Drain electrode

[0028] 400: passivation layer

[0029] 500: floating conductive layer

[0030] 510: floating conductive frame

[0031] 520: floating conductive strip

[0032] 600: organic material layer

[0033] 720: Gate contact pad

[0034] 740: Source contact pad

[0035] 760: Drain contact pad

[0036] AA: Active Area

[0037] D1: First direction

[0038] D2: Second direction

[0039] D3: Third direction

[0040] t: thickness. DETAILED DESCRIPTION

[0041] The semiconductor structure of each embodiment of the present disclosure is described in detail below. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used for example and not for limitation of the present disclosure. In addition, similar and / or corresponding element symbols may be used in different embodiments to indicate similar and / or corresponding elements to clearly describe the present disclosure. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0042] It should be understood that relative terms may be used in various embodiments, such as "lower" or "bottom" or "upper" or "top" to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side. The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered part of the disclosure.

[0043] Furthermore, when a first material layer is said to be located on or over a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0044] In addition, it should be understood that the ordinal numbers used in the specification and the patent application, such as "first", "second", etc., are used to modify the elements, and are not intended to imply any previous ordinal numbers of the elements, nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of the ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The patent application and the specification may not use the same words, for example, the first element in the specification may be the second element in the patent application.

[0045] In some embodiments of the present disclosure, terms related to bonding and connection, such as "connect", "interconnect", "bond", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with other structures disposed between the two structures. Such terms related to connection and bonding may also include situations where both structures are movable, or where both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

[0046] In the text, the terms "approximate", "about", "substantially" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantity given here is an approximate quantity, that is, in the absence of a specific description of "about", "approximately", "substantially", the meaning of "about", "approximately", "substantially" can still be implied. The term "range is between a first value and a second value" means that the range includes the first value, the second value and other values ​​between them. Furthermore, there may be a certain error between any two values ​​or directions used for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees. If the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0047] Certain words are used throughout the specification and patent application in this disclosure to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document is not intended to distinguish between components that have the same function but different names. In the following specification and patent application, words such as "comprise", "contain", "have" are open-ended words, so they should be interpreted as "including but not limited to...". Therefore, when the terms "comprise", "contain" and / or "have" are used in the description of this disclosure, they specify the existence of corresponding parts, areas, steps, operations and / or elements, but do not exclude the existence of one or more corresponding parts, areas, steps, operations and / or elements.

[0048] It should be understood that the following embodiments may replace, reorganize, or combine components in different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Components between embodiments may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0050] In the present disclosure, each direction is not limited to three axes such as the X-axis, Y-axis and Z-axis of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the cross-sectional schematic diagram described herein is a schematic diagram for observing the XZ plane (the plane formed by the first direction D1 and the third direction D3), and the top view schematic diagram described herein is a schematic diagram for observing the XY plane (the plane formed by the first direction D1 and the second direction D2). In some embodiments, the normal direction of the substrate described herein is the third direction D3.

[0051] Reference Figure 1 , which is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. Generally speaking, a semiconductor-on-insulator substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polysilicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like. In some embodiments, the substrate 100 may be an undoped substrate or a doped substrate, such as a substrate doped with a p-type or n-type dopant. In some embodiments, the substrate 100 may be a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may be a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate.

[0052] In some embodiments, an epitaxial layer 120 may be formed on the substrate 100. In some embodiments, the epitaxial layer 120 may include a channel layer (not shown) and a barrier layer (not shown). In some embodiments, the channel layer may be disposed on the substrate 100, and the barrier layer may be disposed on the channel layer. Due to the presence of a heterogeneous interface between the channel layer and the barrier layer, and the difference in lattice constants between the channel layer and the barrier layer, a two-dimensional electron gas (2DEG) is formed near the top surface of the channel layer. In some embodiments, the two-dimensional electron gas is formed in the channel layer and adjacent to the barrier layer. In some embodiments, the two-dimensional electron gas can serve as a current path for the semiconductor structure.

[0053] In some embodiments, the channel layer may include a III-V compound semiconductor material, such as a III-nitride, but the disclosure is not limited thereto. For example, the channel layer may include gallium nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), the like, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the barrier layer may include a III-V compound semiconductor material, such as a III-nitride, but the disclosure is not limited thereto. For example, the barrier layer may include aluminum nitride, aluminum gallium nitride, aluminum indium nitride, indium aluminum gallium nitride, the like, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the channel layer may include gallium nitride, and may include aluminum gallium nitride. In some embodiments, the channel layer and / or the barrier layer may be formed by a deposition process. The deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), the like, or a combination thereof, but the present disclosure is not limited thereto.

[0054] In some embodiments, a buffer layer (not shown) may be further formed between the substrate 100 and the channel layer to reduce the lattice dislocation between the substrate 100 and the channel layer, thereby reducing defects. In some embodiments, the buffer layer may include a III-V compound semiconductor material, such as a III-nitride. For example, the buffer layer may include gallium nitride, aluminum nitride, aluminum gallium nitride, aluminum indium nitride, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the buffer layer may be formed by a deposition process.

[0055] In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer to reduce the lattice difference between the substrate 100 and other layers disposed on the substrate 100, thereby improving the epitaxial quality and reliability. In some embodiments, the nucleation layer may include aluminum nitride, aluminum gallium nitride, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the nucleation layer may be formed by a deposition process.

[0056] In some embodiments, a bottom dielectric layer 140 may be formed on the epitaxial layer 120. In some embodiments, the bottom dielectric layer 140 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the bottom dielectric layer 140 may be silicon nitride. In some embodiments, the bottom dielectric layer 140 may be formed by a deposition process.

[0057] Reference Figure 2 , which is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, a bottom metal layer 160 may be formed in the bottom dielectric layer 140. For example, in some embodiments, the bottom dielectric layer 140 may be patterned to form a groove (not shown) exposing the top surface of the epitaxial layer 120, and then the bottom metal layer 160 is formed in the groove. In some embodiments, the bottom metal layer 160 may include a metal, and the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the bottom metal layer 160 may be an ohmic contact.

[0058] Reference Figure 3, which is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, a gate electrode 200 may be formed on the epitaxial layer 120. In some embodiments, the gate electrode 200 may be formed on the bottom dielectric layer 140 between the bottom metal layers 160. In some embodiments, the gate electrode 200 may include a conductive material, for example, the conductive material may include a metal, a metal nitride, a semiconductor material, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the metal may include gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the metal nitride may include titanium nitride, molybdenum nitride, tungsten nitride, tantalum nitride, the like, or a combination thereof, but the present disclosure is not limited thereto. The semiconductor material may include polycrystalline silicon or polycrystalline germanium. In some embodiments, the conductive material may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, the like, or a combination thereof, but the present disclosure is not limited thereto.

[0059] Reference Figure 4 , which is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, a first interlayer dielectric layer 220 may be blanket-formed on the gate electrode 200, the bottom dielectric layer 140, and the bottom metal layer 160. In some embodiments, the first interlayer dielectric layer 220 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first interlayer dielectric layer 220 may be formed by a deposition process.

[0060] Reference Figure 5 , which is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, a gate field plate 240 may be formed on the gate electrode 200. In some embodiments, the first interlayer dielectric layer 220 may be patterned to expose the top surface of the gate electrode 200. Next, a gate field plate 240 is formed on the exposed top surface of the gate electrode 200 so that the gate field plate 240 is electrically connected to the gate electrode 200. In some embodiments, the gate field plate 240 may cover at least a portion of the top surface of the gate electrode 200. In some embodiments, the gate field plate 240 may extend along a first direction D1. In some embodiments, the gate field plate 240 may extend from the gate electrode 200 toward a subsequently formed drain electrode ( Figure 6In some embodiments, the projection of the gate electrode 200 on the substrate 100 and the projection of the gate field plate 240 on the substrate 100 may partially overlap and partially not overlap. In other embodiments, the projection of the gate electrode 200 on the substrate 100 may be within the projection of the gate field plate 240 on the substrate 100. Accordingly, the charge distribution in the semiconductor structure can be adjusted by setting the gate field plate 240. For example, the charge concentrated at the edge of the gate electrode 200 is dispersed. In other embodiments, the gate field plate 240 may be omitted from the semiconductor structure.

[0061] like Figure 5 As shown, in some embodiments, a second interlayer dielectric layer 260 may be blanket formed on the gate field plate 240 and the first interlayer dielectric layer 220. In some embodiments, the material and formation method of the second interlayer dielectric layer 260 may be the same as or different from the material and formation method of the first interlayer dielectric layer 220.

[0062] Reference Figure 6 , which is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, a source electrode 320 and a drain electrode 340 may be formed on the epitaxial layer 120. In some embodiments, the material and formation method of the source electrode 320 and / or the drain electrode 340 may be the same as or different from the material and formation method of the gate electrode 200. In some embodiments, the source electrode 320 and the drain electrode 340 are respectively disposed on both sides of the gate electrode 200. In some embodiments, the first interlayer dielectric layer 220 and the second interlayer dielectric layer 260 may be patterned to expose the top surfaces of the bottom metal layer 160 located on both sides of the gate electrode 200, respectively. Then, the source electrode 320 and the drain electrode 340 are respectively formed on the top surfaces of the bottom metal layer 160 located on both sides of the gate electrode 200, so that the source electrode 320 and the drain electrode 340 are electrically connected to the bottom metal layer 160. In some embodiments, the edge of the gate field plate 240 (for example, as Figure 6 The right edge of the gate field plate 240 as shown may be interposed between the gate electrode 200 and the drain electrode 340 .

[0063] In some embodiments, a source field plate 330 may be formed on the source electrode 320 so that the source field plate 330 is electrically connected to the source electrode 320. In some embodiments, the material and formation method of the source field plate 330 may be the same as or different from the material and formation method of the gate field plate 240. In some embodiments, the source field plate 330 may be located on the gate field plate 240. In some embodiments, the source field plate 330 may be disposed on the second interlayer dielectric layer 260. In some embodiments, the source field plate 330 may cover the side surface of the source electrode 320 and may expose the top surface of the source electrode 320.

[0064] In some embodiments, the source field plate 330 may extend along the first direction D1. In some embodiments, the projection of the gate field plate 240 on the substrate 100 is within the projection of the source field plate 330 on the substrate 100. In some embodiments, the source field plate 330 may extend from the source electrode 320 toward the drain electrode 340 so that the edge of the source field plate 330 (e.g., Figure 6 The right edge of the source field plate 330 shown in FIG. 1 may be between the gate electrode 200 and the drain electrode 340. In some embodiments, the source field plate 330, the gate field plate 240, and the gate electrode 200 overlap each other in the normal direction of the substrate 100. In some embodiments, the source field plate 330 may completely cover the top surface of the gate field plate 240 in the normal direction of the substrate 100. In some embodiments, the source field plate 330 may be closer to the drain electrode 340 than the gate field plate 240. Accordingly, the charge distribution in the semiconductor structure may be adjusted by setting the source field plate 330. In other embodiments, the source field plate 330 may be omitted from the semiconductor structure.

[0065] Reference Figure 7 , which is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, a passivation layer 400 may be formed on the gate electrode 200, the source electrode 320, and the drain electrode 340. In some embodiments, a passivation layer 400 may be formed on the second interlayer dielectric layer 260, the source electrode 320, the source field plate 330, and the drain electrode 340. In some embodiments, the material and formation method of the passivation layer 400 may be the same as or different from the material and formation method of the first interlayer dielectric layer 220.

[0066] It should be noted that, generally speaking, after forming the passivation layer 400, a back-end of line (BEOL) process is subsequently performed. For example, an organic material layer may be directly formed on the passivation layer 400. However, the method for forming a semiconductor structure of the present disclosure may further include forming a floating conductive layer on the passivation layer 400 and between the passivation layer 400 and the organic material layer. In other words, the floating conductive layer of the present disclosure may be inserted between the passivation layer 400 and the organic material layer to enhance the electrical properties of the semiconductor structure.

[0067] Reference Figure 8 , which is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, a floating conductive layer 500 may be formed on the passivation layer 400. In some embodiments, the floating conductive layer 500 may be disposed above a current path formed by the two-dimensional electron gas, that is, the current path formed by the two-dimensional electron gas may be between the substrate 100 and the floating conductive layer 500.

[0068] In some embodiments, the floating conductive layer 500 may be in direct contact with the passivation layer 400. In some embodiments, the floating conductive layer 500 may be electrically insulated from other elements, and is therefore referred to as "floating". In other words, the floating conductive layer 500 is not in contact with the gate electrode 200, the source electrode 320, and the drain electrode 340, so that the floating conductive layer 500 may be electrically insulated from the gate electrode 200, the source electrode 320, and the drain electrode 340. In some embodiments, the floating conductive layer 500 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a semiconductor material, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the metal may include gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the metal nitride may include titanium nitride, molybdenum nitride, tungsten nitride, tantalum nitride, the like, or a combination thereof, but the present disclosure is not limited thereto. The semiconductor material may include polysilicon or polycrystalline germanium. Since the floating conductive layer 500 may include a conductive material and be a conductor, the floating conductive layer 500 may have an effect of adjusting an electrostatic field.

[0069] In some embodiments, the floating conductive layer 500 may have a thickness t in the normal direction of the substrate 100. In some embodiments, the thickness t may be greater than or equal to 1um and less than or equal to 10um. For example, the thickness t may be 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, or any value between the aforementioned values ​​or a numerical range consisting of any values, but the present disclosure is not limited thereto. When the thickness t of the floating conductive layer 500 is less than 1um, the floating conductive layer 500 may be broken, thereby reducing the effect of the floating conductive layer 500 in improving the charge distribution. When the thickness t of the floating conductive layer 500 is greater than 10um, the probability that the organic material layer subsequently disposed on the floating conductive layer 500 is difficult to form may be increased because the material of the organic material layer is a flowable material.

[0070] In some embodiments, the floating conductive layer 500 may cover the active area AA between the source electrode 320 and the drain electrode 340. In some embodiments, the floating conductive layer 500 may cover a portion or all of the top surface of the source electrode 320. In some embodiments, the floating conductive layer 500 may cover a portion or all of the top surface of the drain electrode 340. In some embodiments, the projection of the source field plate 330 on the substrate 100 is within the projection of the floating conductive layer 500 on the substrate 100. In some embodiments, in the normal direction of the substrate 100, the floating conductive layer 500, the source field plate 330, the gate field plate 240, and the gate electrode 200 overlap with each other. In some embodiments, in the normal direction of the substrate 100, the floating conductive layer 500 may completely cover the top surface of the source field plate 330. Accordingly, the charge distribution of the semiconductor structure can be adjusted by adjusting the thickness and relative position of the floating conductive layer 500.

[0071] Reference Fig. 9 , which is a cross-sectional schematic diagram of a semiconductor structure 1 according to an embodiment of the present disclosure. In some embodiments, an organic material layer 600 may be formed on the floating conductive layer 500. In some embodiments, the organic material layer 600 may be in direct contact with the floating conductive layer 500. In some embodiments, the floating conductive layer 500 may be inserted between the passivation layer 400 and the organic material layer 600, and the floating conductive layer 500 may be in direct contact with the passivation layer 400 and the organic material layer 600, respectively. In some embodiments, the organic material layer 600 may include a polymer material, but the present disclosure is not limited thereto. In some embodiments, the organic material layer 600 may include polyimide (PI), poly(p-phenylene benzobisoxazole), PBO), benzocyclobutadiene (BCB), epoxy resin, silicone, molding material, the like, or a combination thereof, but the present disclosure is not limited thereto. For example, the organic material layer 600 may include polyimide.

[0072] In some embodiments, a gate contact pad 720, a source contact pad 740, and a drain contact pad 760 may be formed on the organic material layer 600, and the gate contact pad 720, the source contact pad 740, and the drain contact pad 760 are electrically connected to the gate electrode 200, the source electrode 320, and the drain electrode 340, respectively, so as to obtain the semiconductor structure 1 of the present disclosure. For example, a circuit under pad (CUP) structure may be formed. It should be noted that since any suitable method may be used to perform the wiring of the above-mentioned electrical connection, Fig. 9The connection method of the gate contact pad 720, the source contact pad 740 and the drain contact pad 760 to the gate electrode 200, the source electrode 320 and the drain electrode 340 is not specifically shown. In some embodiments, the material and formation method of the gate contact pad 720, the source contact pad 740 and / or the drain contact pad 760 may be the same as or different from the material and formation method of the gate electrode 200. In some embodiments, as Fig. 9 As shown, in the normal direction of the substrate 100 , the gate contact pad 720 may be disposed on the gate electrode 200 , the source contact pad 740 may be disposed on the source electrode 320 , and the drain contact pad 760 may be disposed on the drain electrode 340 .

[0073] It should be noted that the semiconductor structure usually needs to be provided with an organic material layer 600 for back-end processing, thereby strengthening the physical strength of the semiconductor structure. However, since the organic molecules in the organic material layer 600 may have a dipole moment, the organic material layer 600 may induce charge in the semiconductor structure, and cause the charge to accumulate in the components below the organic material layer 600, thereby causing the semiconductor structure to deteriorate or even fail. For example, before the organic material layer 600 and the gasket (gate contact pad 720, source contact pad 740 and drain contact pad 760) are formed, the semiconductor structure can pass the electrical test of high voltage (e.g., 700 volts (V)) and high temperature (e.g., 150 degrees Celsius). However, after the organic material layer 600 and the gasket are formed, the semiconductor structure cannot pass the electrical test. Therefore, it can be observed that the formation of the organic material layer 600 and the gasket will cause the electrical degradation of the semiconductor structure. Accordingly, since the floating conductive layer 500 of the present disclosure is floating and not electrically connected to other elements, and is a conductor and has the effect of adjusting the electrostatic field, the floating conductive layer 500 can redistribute the charges in the semiconductor structure 1, thereby avoiding the charge trapping effect generated by the organic material layer 600. Accordingly, the floating conductive layer 500 can improve the reliability of the semiconductor structure 1.

[0074] Reference Fig.10 , which is a schematic top view of a semiconductor structure 1 according to an embodiment of the present disclosure. Fig.10 show Fig. 9 The schematic top view of the semiconductor structure 1 is shown. For the convenience of explanation, Fig.10Some elements are omitted, and the floating conductive layer 500, the organic material layer 600, the gate contact pad 720, the source contact pad 740 and the drain contact pad 760 are shown. In some embodiments, when viewed from a top view, the gate contact pad 720, the source contact pad 740 and the drain contact pad 760 are located on the organic material layer 600 and on the floating conductive layer 500. Accordingly, since the floating conductive layer 500 can be used as a barrier, the floating conductive layer 500 can prevent the electric field interaction between the gate contact pad 720, the source contact pad 740 and the drain contact pad 760 disposed above the organic material layer 600 and the source field plate 330 and the gate field plate 240 disposed below the organic material layer 600, thereby degrading the electrical properties of the semiconductor structure 1. In addition, the floating conductive layer 500 can also be used as a shielding member for electromagnetic waves, so that the floating conductive layer 500 can prevent the elements disposed below the floating conductive layer 500 from being affected by external electromagnetic interference.

[0075] Hereinafter, the same or similar element numbers and descriptions are omitted.

[0076] Reference Fig.11 , which is a cross-sectional schematic diagram of a semiconductor structure 2 according to an embodiment of the present disclosure. In some embodiments, Fig.11 As shown, the semiconductor structure 2 may include a gate contact pad 720, a source contact pad 740 and a drain contact pad 760, but in Fig.11 Not shown in the cross section shown.

[0077] Reference Fig.12 , which is a schematic top view of a semiconductor structure 2 according to an embodiment of the present disclosure. Fig.12 show Fig.11 FIG. 2 is a schematic top view of a semiconductor structure 2 shown in FIG. Fig.12 Some elements are omitted to show the floating conductive layer 500, the organic material layer 600, the gate contact pad 720, the source contact pad 740, and the drain contact pad 760. In some embodiments, when viewed from a top view, the floating conductive layer 500 may be between the gate contact pad 720 and the drain contact pad 760. In some embodiments, when viewed from a top view, the floating conductive layer 500 may be between the source contact pad 740 and the drain contact pad 760. In some embodiments, the floating conductive layer 500 is spaced a distance from the gate contact pad 720, the source contact pad 740, and the drain contact pad 760, respectively. In some embodiments, Fig.12 Two gate contact pads 720 are shown, and the two gate contact pads 720 are respectively disposed on both sides of the source contact pad 740, and the two gate contact pads 720 are electrically connected to each other to reduce the wiring resistance between the gate contact pads 720, but the present disclosure is not limited thereto. In other embodiments, the semiconductor structure 2 may include one or more than two gate contact pads 720.

[0078] Reference Fig.13 , which is a cross-sectional schematic diagram of a semiconductor structure 3 according to an embodiment of the present disclosure. In some embodiments, Fig.13 As shown, the semiconductor structure 3 may include a gate contact pad 720, a source contact pad 740 and a drain contact pad 760, but in Fig.13 Not shown in the cross section shown. In some embodiments, the floating conductive layer 500 may expose a portion of the top surface of the source electrode 320 in the normal direction of the substrate 100. In some embodiments, the floating conductive layer 500 may expose a portion of the top surface of the drain electrode 340 in the normal direction of the substrate 100. In some embodiments, the passivation layer 400 may be in direct contact with the organic material layer 600 at a position on a portion of the top surface of the source electrode 320. In some embodiments, the passivation layer 400 may be in direct contact with the organic material layer 600 at a position on a portion of the top surface of the drain electrode 340. In some embodiments, the floating conductive layer 500 may be surrounded by the passivation layer 400 and the organic material layer 600. In some embodiments, the floating conductive layer 500 may be buried in the organic material layer 600. In some embodiments, the passivation layer 400 may directly contact the bottom surface of the floating conductive layer 500, and the organic material layer 600 may directly contact the side surface and the top surface of the floating conductive layer 500.

[0079] Reference Fig.14 , which is a schematic top view of a semiconductor structure 3 according to an embodiment of the present disclosure. Fig.14 show Fig.13 FIG. 3 is a schematic top view of a semiconductor structure 3. For ease of explanation, Fig.14 Some elements are omitted to show the floating conductive layer 500, the organic material layer 600, the gate contact pad 720, the source contact pad 740 and the drain contact pad 760. In some embodiments, when viewed from a top view, the floating conductive layer 500 may be between the gate contact pad 720 and the drain contact pad 760, and the floating conductive layer 500 may be between the source contact pad 740 and the drain contact pad 760.

[0080] In some embodiments, the floating conductive layer 500 may include a floating conductive frame 510 and a plurality of floating conductive strips 520. In some embodiments, the floating conductive frame 510 may be located between the gate contact pad 720 and the drain contact pad 760, and the floating conductive frame 510 may be located between the source contact pad 740 and the drain contact pad 760. In some embodiments, the floating conductive frame 510 may have a closed hollow shape. For example, the floating conductive frame 510 may be frame-shaped, ring-shaped, the like, or a combination thereof, but the present disclosure is not limited thereto.

[0081] In some embodiments, the plurality of floating conductive strips 520 may be located in the floating conductive frame 510, that is, the floating conductive frame 510 may surround each of the plurality of floating conductive strips 520. In some embodiments, each of the plurality of floating conductive strips 520 is arranged spaced apart from each other. In some embodiments, each of the plurality of floating conductive strips 520 extends along the first direction D1 and is spaced apart from each other in the second direction D2.

[0082] In some embodiments, any of the semiconductor structures 1 to 3 of the present disclosure may be a high electron mobility transistor, or further processes may be performed on any of the semiconductor structures 1 to 3 of the present disclosure to form a high electron mobility transistor.

[0083] Accordingly, the present disclosure can improve the reliability of the semiconductor structure by disposing a floating conductive layer between the passivation layer and the organic material layer, so that the semiconductor structure is protected from the charge capture effect, the electric field interaction between the upper and lower metal layers, and / or the influence of external electromagnetic interference. For example, the floating conductive layer can prevent the charge induced by the organic material layer from accumulating in the elements below the organic material layer, thereby preventing the semiconductor structure from deteriorating. For example, the floating conductive layer can prevent the electric field interaction between the contact pad disposed above the organic material layer and the field plate disposed below the organic material layer, thereby preventing the semiconductor structure from deteriorating. For example, the floating conductive layer can prevent the semiconductor structure from being affected by external electromagnetic interference.

[0084] The scope of protection of the present disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand from the disclosure of the present disclosure the processes, machines, manufactures, material compositions, devices, methods and steps currently or developed in the future, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the aforementioned processes, machines, manufactures, material compositions, devices, methods and steps. Any embodiment or claim of the present disclosure is not required to achieve all the purposes, advantages and / or features described in the present disclosure.

[0085] Several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: a substrate; an epitaxial layer disposed on the substrate; a gate electrode disposed on the epitaxial layer; A source electrode and a drain electrode are disposed on the epitaxial layer and located on both sides of the gate electrode; a passivation layer, disposed on the gate electrode, the source electrode and the drain electrode; a floating conductive layer, disposed on the passivation layer; and An organic material layer is disposed on the floating conductive layer.

2. The semiconductor structure according to claim 1, characterized in that: The floating conductive layer covers an active region between the source electrode and the drain electrode.

3. The semiconductor structure according to claim 2, characterized in that: The floating conductive layer covers a top surface of the source electrode and a top surface of the drain electrode.

4. The semiconductor structure according to claim 1, characterized in that Also includes: A gate field plate is connected to the gate electrode, disposed on the gate electrode, and extends from the gate electrode toward the drain electrode.

5. The semiconductor structure according to claim 4, characterized in that: Also includes: A source field plate is connected to the source electrode and is disposed on the gate field plate and extends from the source electrode toward the drain electrode, wherein a projection of the gate field plate on the substrate is within a projection of the source field plate on the substrate.

6. The semiconductor structure according to claim 5, characterized in that: A projection of the source field plate on the substrate is within a projection of the floating conductive layer on the substrate.

7. The semiconductor structure according to claim 1, characterized in that: Also includes: a gate contact pad, disposed on the organic material layer and electrically connected to the gate electrode; a source contact pad, disposed on the organic material layer and electrically connected to the source electrode; and a drain contact pad, disposed on the organic material layer and electrically connected to the source electrode; The gate contact pad, the source contact pad and the drain contact pad are located on the floating conductive layer.

8. The semiconductor structure according to claim 1, characterized in that: Also includes: a gate contact pad, disposed on the organic material layer and electrically connected to the gate electrode; a source contact pad, disposed on the organic material layer and electrically connected to the source electrode; and a drain contact pad, disposed on the organic material layer and electrically connected to the drain electrode; The floating conductive layer is located between the gate contact pad and the drain contact pad and between the source contact pad and the drain contact pad.

9. The semiconductor structure according to claim 8, characterized in that: The floating conductive layer further comprises: a floating conductive frame located between the gate contact pad and the drain contact pad and between the source contact pad and the drain contact pad; and A plurality of floating conductive strips are located in the floating conductive frame, and each of the plurality of floating conductive strips is arranged at intervals.

10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming an epitaxial layer on the substrate; forming a gate electrode on the epitaxial layer; forming a source electrode and a drain electrode on the epitaxial layer, wherein the source electrode and the drain electrode are located on both sides of the gate electrode; forming a passivation layer on the gate electrode, the source electrode and the drain electrode; forming a floating conductive layer on the passivation layer; and An organic material layer is formed on the floating conductive layer.

Images