Integrated circuit device and method of manufacturing same

Abstract

An integrated circuit device may include: a plurality of device isolation layers extending longitudinally in a first horizontal direction; a plurality of gap filling insulating layers disposed apart from each other in the first horizontal direction; a plurality of gate structures longitudinally extending in a second horizontal direction perpendicular to the first horizontal direction and on the plurality of gap filling insulating layers; the first source / drain region and the second source / drain region are respectively arranged on two sides of a first gate structure in the plurality of gate structures relative to the first horizontal direction; an insulating block under the first source / drain region; and an insulating barrier between the first source / drain region and the insulating block. The insulating barrier may cover a lower surface of the first source / drain region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0115603 filed in the Korean Intellectual Property Office on August 31, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to an integrated circuit device, and more particularly, to an integrated circuit device including a power rail. Background Art

[0004] As electronic technology advances, the size reduction of integrated circuit devices has been rapidly progressing. Because semiconductor devices require operation accuracy and fast operation speed, various studies are being conducted to optimize the structure of transistors included in semiconductor devices. Summary of the invention

[0005] The inventive concept provides an integrated circuit device with enhanced integration and reliability.

[0006] The inventive concept provides a method of manufacturing an integrated circuit device with enhanced integration and reliability.

[0007] According to an embodiment conceived in the present invention, an integrated circuit device may include: a plurality of device isolation layers extending longitudinally in a first horizontal direction, the plurality of device isolation layers being arranged separately from each other in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; a plurality of gap-filling insulating layers being arranged separately from each other along the first horizontal direction between adjacent device isolation layers among the plurality of device isolation layers; a plurality of gate structures being arranged separately from each other in the first horizontal direction, the plurality of gate structures being on the plurality of gap-filling insulating layers and extending longitudinally in the second horizontal direction; a first source / drain region and a second source / drain region being respectively arranged on both sides of a first gate structure among the plurality of gate structures relative to the first horizontal direction; an insulating block below the first source / drain region; an insulating barrier between the first source / drain region and the insulating block, the insulating barrier covering a lower surface of the first source / drain region; and a lower contact portion being separated from the insulating block in the first horizontal direction, a first gap-filling insulating layer among the plurality of gap-filling insulating layers being between the lower contact portion and the insulating block, the lower contact portion contacting a lower surface of the second source / drain region, and the lower contact portion being below the second source / drain region.

[0008] According to an embodiment of the present invention, an integrated circuit device may include: a plurality of device isolation layers, separated from each other in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction, the plurality of device isolation layers defining sidewalls of a back side groove, the back side groove extending longitudinally along the first horizontal direction between adjacent device isolation layers among the plurality of device isolation layers; a plurality of gap filling insulating layers, in the back side grooves, and arranged separated from each other in the first horizontal direction; a plurality of insulating barriers, in the back side grooves, and respectively arranged between adjacent gap filling insulating layers among the plurality of gap filling insulating layers; a first source / drain region, in the plurality of insulating barriers a first insulating barrier among the plurality of insulating barriers; a second source / drain region, on a second insulating barrier among the plurality of insulating barriers; a gate structure, between the first source / drain region and the second source / drain region, the gate structure being on a first gap-filling insulating layer among the plurality of gap-filling insulating layers; a first insulating block, facing a lower surface of the first source / drain region in a vertical direction, the first insulating barrier being between the first insulating block and a lower surface of the first source / drain region; and a lower contact portion, separated from the first insulating block in a first horizontal direction, the first gap-filling insulating layer being between the lower contact portion and the first insulating block, the lower contact portion passing through the second insulating barrier and contacting the second source / drain region.

[0009] According to an embodiment of the present invention, an integrated circuit device may include: a plurality of device isolation layers extending longitudinally in a first horizontal direction, the plurality of device isolation layers being arranged apart from each other in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; a plurality of gap-filling insulating layers being arranged apart from each other along the first horizontal direction between adjacent device isolation layers among the plurality of device isolation layers; a nanosheet structure being located apart from an upper surface of a first gap-filling insulating layer among the plurality of gap-filling insulating layers in a vertical direction and facing the upper surface of the first gap-filling insulating layer, the nanosheet structure including a nanosheet or nanosheets in a vertical direction; A plurality of nanosheets spaced apart from each other; a gate structure on a first gap-filling insulating layer, the gate structure extending longitudinally in a second horizontal direction and surrounding the nanosheet structure; a first source / drain region and a second source / drain region, respectively arranged on both sides of the gate structure in the first horizontal direction; an insulating block below the first source / drain region; an insulating barrier between the first source / drain region and the insulating block in a vertical direction, the vertical height of the upper surface of the insulating barrier being higher than the lower surface of the gate structure; and a lower contact portion separated from the insulating block in the first horizontal direction, the first gap-filling insulating layer being between the lower contact portion and the insulating block, the lower contact portion being below the second source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1is a plan layout diagram of some elements of an integrated circuit device according to an embodiment;

[0012] Figure 2A is along Figure 1 A cross-sectional view taken along the line X1-X1′, Figure 2B is shown along Figure 1 The cross-sectional surface taken along the line Y1-Y1′ and along Figure 1 A cross-sectional view of the cross-sectional surface taken along the line Y2-Y2′, Figure 2C yes Figure 2A An enlarged view of area EX1, and Figure 2D yes Figure 2B An enlarged view of region EX2;

[0013] Figure 3A and Figure 3B is a cross-sectional view for describing an integrated circuit device according to some other embodiments, Figure 3A is along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional surface taken along the line X1-X1′, and Figure 3B yes Figure 3A An enlarged view of area EX3;

[0014] Figure 4A and Figure 4B is a cross-sectional view for describing an integrated circuit device according to some other embodiments; Figure 4A is along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional surface taken along the line X1-X1′, and Figure 4B yes Figure 4A A magnified view of region EX4;

[0015] Figure 5A and Figure 5B is a cross-sectional view for describing an integrated circuit device according to some other embodiments; Figure 5A is along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional surface taken along the line X1-X1′, and Figure 5B yes Figure 5A an enlarged view of region EX5; and

[0016] FIG. 6A to FIG. 19B is a cross-sectional view showing a method of manufacturing an integrated circuit device according to an embodiment in process order, Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig.12 , Fig.13 , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A The process sequence is shown along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional surface taken along the line X1-X1′, and Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B and Fig.19B The process sequence is shown along Figure 1 The cross-sectional surface taken along the line Y1-Y1′ and along Figure 1 A cross-sectional view of the cross-sectional surface taken along the line Y2-Y2′. DETAILED DESCRIPTION

[0017] Although the term "equal to" is used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being "equal to" another element, it should be understood that the element or value may be "equal to" the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0018] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, like reference numerals refer to like elements, and their repeated description will be omitted.

[0019] In this article, the vertical direction may be defined as the Z direction, and the horizontal direction may be defined as a direction perpendicular to the Z direction. The first horizontal direction and the second horizontal direction may be defined as directions intersecting each other. The first horizontal direction may be referred to as the X direction, and the second horizontal direction may be referred to as the Y direction. The vertical height may be referred to as the height relative to the vertical direction (Z direction).

[0020] Figure 1 is a plan layout diagram of some elements of the integrated circuit device 100 according to an embodiment. Figure 2A is along Figure 1 A cross-sectional view taken along the line X1-X1′, Figure 2B is shown along Figure 1 The cross-sectional surface taken along the line Y1-Y1′ and along Figure 1 A cross-sectional view of the cross-sectional surface taken along the line Y2-Y2′, Figure 2C yes Figure 2A An enlarged view of area EX1, and Figure 2D yes Figure 2B An enlarged view of region EX2.

[0021] According to the following reference Figure 1 as well as FIG. 2A to FIG. 2D In the described embodiment, the integrated circuit device 100 may configure a logic cell including an active region having a nanowire or nanosheet shape and a gate-all-around (GAA) type field effect transistor (FET) device including a gate surrounding the active region. For example, the integrated circuit device 100 may include a multi-bridge channel (MBC) FET (MBCFET) device. However, the inventive concept is not limited thereto, and the integrated circuit device 100 may include a planar FET device and a finFET device.

[0022] refer to Figure 1 as well as FIG. 2A to FIG. 2D , the integrated circuit device 100 may include a backside structure BSS, and a frontside structure FSS on the backside structure BSS. According to an embodiment, the backside structure BSS may include a plurality of device isolation layers 114, a plurality of gap-filling insulating layers 222, a plurality of insulating blocks 212, a plurality of lower contacts 232, and a backside power rail. According to an embodiment, the frontside structure FSS may include a plurality of nanosheet stacks NSS, a plurality of gate electrodes 160, a plurality of source / drain regions 130, a plurality of insulating barriers 124, and a plurality of upper contacts 172.

[0023] According to an embodiment, a plurality of device isolation layers 114 may extend longer in a first horizontal direction (X direction) and may be separated from each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction), and each of a plurality of back trenches BT is between the plurality of device isolation layers 114. For example, a plurality of device isolation layers 114 may extend in parallel in the first horizontal direction (X direction). For example, a plurality of back trenches BT may extend longer in the first horizontal direction (X direction) and may be defined by a plurality of device isolation layers 114.

[0024] In some embodiments, the device isolation layer 114 may include at least one material selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0025] According to an embodiment, a plurality of gap-filling insulating layers 222 may be arranged separately from each other along a first horizontal direction (X direction) in each of a plurality of back trenches BT. A plurality of gap-filling insulating layers 222 may extend along a vertical direction (Z direction) in a plurality of back trenches BT. According to an embodiment, both sidewalls of the plurality of gap-filling insulating layers 222 in a second horizontal direction (Y direction) may contact the device isolation layer 114.

[0026] In some embodiments, the plurality of gap-filling insulating layers 222 may include silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof, but the embodiment is not limited thereto. The terms "SiN", "SiO", "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein may each represent a material composed of the elements included in the corresponding term, and may not be a chemical formula representing a stoichiometric relationship.

[0027] According to an embodiment, an active structure may be disposed on each of the plurality of gap-filling insulating layers 222. For example, the active structure may have a fin shape, a nanowire shape, or a nanosheet shape. FIG. 2A to FIG. 2C In the figure, the active structure is shown as a nanosheet stack NSS, but is not limited thereto.

[0028] According to an embodiment, a plurality of nanosheet stacks NSS may be respectively disposed on a plurality of gap-filling insulating layers. The nanosheet stack NSS may also be referred to as a nanosheet structure. According to an embodiment, each of the plurality of nanosheet stacks NSS may include at least one nanosheet. According to an embodiment, each of the plurality of nanosheet stacks NSS may be disposed in a vertical direction (Z direction) at a position separated from the upper surface of the corresponding gap-filling insulating layer 222 among the plurality of gap-filling insulating layers 222.

[0029] Each of the plurality of nanosheet stacks NSS may include a plurality of nanosheets separated from each other in the vertical direction (Z direction) and vertically overlapped with each other, and may include, for example, a first nanosheet N1, a second nanosheet N2, a third nanosheet N3, and a fourth nanosheet N4. The term "nanosheet" used herein may refer to a conductive structure including a cross-sectional surface substantially perpendicular to the direction of current flow. A nanosheet must be understood to include a nanowire. In addition, in this article, a plurality of nanosheets N1 to N4 or a nanosheet stack NSS may be referred to as a channel region.

[0030] The first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 may have different distances from the upper surface of the gap filling insulating layer 222 relative to the vertical direction (Z direction). Each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4, each included in the nanosheet stack NSS, may include a channel region. For example, each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 may have a thickness selected in the range of about 4 nm to about 6 nm relative to the vertical direction (Z direction), but is not limited thereto. In some embodiments, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have substantially the same thickness in the vertical direction (Z direction). In some other embodiments, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different thicknesses in the vertical direction (Z direction).

[0031] In some embodiments, at least some of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4, each included in one nanosheet stack NSS, may have different thicknesses in the vertical direction (Z direction). In some other embodiments, at least some of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 may have the same width in the first horizontal direction (X direction).

[0032] According to an embodiment, a plurality of gate structures 162 that cross the plurality of device isolation layers 114 and extend longer in the second horizontal direction (Y direction) may be disposed on the plurality of device isolation layers 114. According to an embodiment, a plurality of gap-filling insulating layers 222 may be disposed respectively in regions where the plurality of gate structures 162 intersect the plurality of back trenches BT, and the plurality of gate structures 162 may respectively cover the plurality of nanosheet stacks NSS on the plurality of gap-filling insulating layers 222 and surround the plurality of nanosheets N1 to N4. For example, a first group of nanosheet stacks NSS arranged in the second horizontal direction (Y direction) among the plurality of nanosheet stacks NSS may be surrounded by a first gate structure 162 among the plurality of gate structures 162. According to an embodiment, each of the plurality of gate structures 162 may include a portion that contacts and overlaps with a corresponding nanosheet stack among the plurality of nanosheet stacks NSS.

[0033] According to an embodiment, a plurality of transistors may be respectively formed at portions where a plurality of nanosheet stacks NSS respectively overlap with a plurality of gate structures 162. According to an embodiment, the plurality of transistors may include a PMOS transistor and an NMOS transistor. For example, each of the plurality of transistors may include at least one nanosheet stack NSS, a gate structure 162 surrounding the at least one nanosheet stack NSS, and a source / drain region 130 facing the at least one nanosheet stack NSS in a first horizontal direction (X direction).

[0034] In some embodiments, each of the plurality of nanosheets N1 to N4 may include an undoped silicon (Si) layer. In some other embodiments, each of the plurality of nanosheets N1 to N4 may include a doped Si layer. For example, when the plurality of nanosheets N1 to N4 configure a PMOS transistor, the plurality of nanosheets N1 to N4 may include a Si layer doped with a p-type dopant, and when the plurality of nanosheets N1 to N4 configure an NMOS transistor, the plurality of nanosheets N1 to N4 may include a Si layer doped with an n-type dopant. However, the inventive concept is not limited thereto. The p-type dopant may be selected from boron (B) and gallium (Ga). The n-type dopant may be selected from phosphorus (P), arsenic (As) and antimony (Sb).

[0035] According to an embodiment, a plurality of gate structures 162 may surround a plurality of nanosheet stacks NSS and may extend in parallel along a second horizontal direction (Y direction) on a plurality of gap-filling insulating layers 222. For example, a plurality of gate structures 162 may be separated from each other in a first horizontal direction (X direction). According to an embodiment, a plurality of gate structures 162 may each include a gate electrode 160, and a gate dielectric layer 152 disposed between the nanosheet stacks NSS and the gate electrode 160.

[0036] According to an embodiment, each of the plurality of gate electrodes 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M may cover the upper surface of the nanosheet stack NSS and may extend in the second horizontal direction (Y direction). The plurality of sub-gate portions 160S may be connected as a whole with the main gate portion 160M, and each of the plurality of sub-gate portions 160S may be disposed between two adjacent nanosheets of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4, and between the first nanosheet N1 and the gap-filling insulating layer 222. With respect to the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions 160S may be less than the thickness of the main gate portion 160M.

[0037] In some embodiments, each of the plurality of gate electrodes 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC. However, the material configuring the plurality of gate electrodes 160 is not limited thereto.

[0038] In some embodiments, the gate dielectric layer 152 may include a stacked structure of an interface dielectric layer and a high-k dielectric layer. The interface dielectric layer may include a low-k dielectric layer having a dielectric constant of about 9 or less, and may include, for example, silicon oxide, silicon oxynitride, or a combination thereof. In some other embodiments, the interface dielectric layer may be omitted. The high-k dielectric layer may include a material having a dielectric constant greater than that of silicon oxide. For example, the high-k dielectric layer may have a dielectric constant of about 10 to about 25. The high-k dielectric layer may include Hf oxide, but is not limited thereto.

[0039] According to embodiments, upper surfaces of the plurality of gate structures 162 may be covered by a capping insulating pattern 168. For example, each of the gate electrode 160 and the gate dielectric layer 152 may be covered by the capping insulating pattern 168. In some embodiments, the capping insulating pattern 168 may include silicon nitride.

[0040] According to an embodiment, both sidewalls of each of the gate structure 162 and the capping insulating pattern 168 may be covered by the outer insulating spacer 116. The outer insulating spacer 116 may cover both sidewalls of the main gate 160M on the upper surface of the plurality of nanosheet stacks NSS. The outer insulating spacer 116 may be separated from the gate electrode 160 with the gate dielectric layer 152 between them.

[0041] According to an embodiment, a plurality of source / drain regions 130 may be alternately arranged in a first horizontal direction (X direction) and a second horizontal direction (Y direction) between a plurality of gate structures 162. According to an embodiment, a plurality of source / drain regions 130 may be separated from each other in a first horizontal direction (X direction), and a plurality of nanosheet stacks NSS are between the plurality of source / drain regions 130. For example, a plurality of source / drain regions 130 and a plurality of nanosheet stacks NSS may be alternately arranged in a first horizontal direction (X direction). According to an embodiment, two source / drain regions 130 adjacent to each other in a second horizontal direction (Y direction) may be separated from each other in a second horizontal direction (Y direction), and an inter-gate insulating layer 144 described below may be between the two source / drain regions 130. In some embodiments, each of the plurality of source / drain regions 130 may fill a portion of a corresponding back trench BT in a plurality of back trenches BT.

[0042] According to an embodiment, both sidewalls of each of the plurality of nanosheet stacks NSS in the first horizontal direction (X direction) may face the corresponding source / drain region 130. According to an embodiment, the plurality of source / drain regions 130 may face the sub-gate portion 160S of the gate electrode 160 and the plurality of nanosheets N1 to N4 disposed adjacent to the sub-gate portion 160S of the gate electrode 160 in the first horizontal direction (X direction). For example, both sidewalls of each of the plurality of source / drain regions 130 in the first horizontal direction (X direction) may contact one gate structure 162 and a portion of the nanosheet stack NSS.

[0043] According to an embodiment, each of the plurality of source / drain regions 130 may include a pair of source / drain barrier members 132, and a source / drain body 134 between the pair of source / drain barrier members 132. According to an embodiment, the pair of source / drain barrier members 132 may cover the sub-gate portion 160S of the gate electrode 160 and the plurality of nanosheets N1 to N4 disposed adjacent to the sub-gate portion 160S of the gate electrode 160 on both sides of the pair of source / drain barrier members 132 in the first horizontal direction (X direction). For example, the pair of source / drain barrier members 132 may contact one side surface of each of the plurality of nanosheets N1 to N4 and may face the sub-gate portion 160S of the gate electrode 160, with the gate dielectric layer 152 between the pair of source / drain barrier members 132 and the sub-gate portion 160S of the gate electrode 160. According to an embodiment, the source / drain body 134 can be separated from the multiple nanosheets N1 to N4 and the sub-gate portion 160S on both sides of the source / drain body 134 in the first horizontal direction (X direction), and the corresponding source / drain barrier 132 is between the source / drain body 134 and the multiple nanosheets N1 to N4 and the sub-gate portion 160S.

[0044] In some embodiments, a pair of source / drain barriers 132 may be separated from each other in a first horizontal direction (X direction), with the source / drain body 134 between the pair of source / drain barriers 132. In some embodiments, each source / drain barrier 132 may be disposed between the source / drain body 134 and the plurality of nanosheets N1 to N4, and may extend in a vertical direction (Z direction). In some embodiments, a pair of source / drain barriers 132 may include a material different from or the same as that of the source / drain body 134, but may have a different composition ratio.

[0045] In some embodiments, the first group of source / drain regions 130 including some of the plurality of source / drain regions 130 may configure a PMOS transistor. In some embodiments, the source / drain barrier 132 and the source / drain body 134 of the first group of source / drain regions 130 may each include Si doped with a p-type dopant. 1-x Ge xa layer (where 0.0 < x ≤ 0.6), and the germanium (Ge) content ratio of the source / drain body 134 can be higher than the Ge content ratio in the source / drain blocker 132. In some embodiments, the Ge content ratio of the source / drain blocker 132 can be about 0.0 at.% or greater and about 20 at.% or less, and for example, can be about 15 at.% or greater and about 30 at.% or less. The Ge content ratio of the source / drain body 134 can be about 30 at.% or greater and about 60 at.% or less, and for example, can be about 40 at.% or greater and about 60 at.% or less. However, the inventive concept is not limited to the above description. In some embodiments, the p-type dopant can be at least one material selected from boron (B) and gallium (Ga), but is not limited thereto. In some embodiments, the first group of source / drain regions 130 may further include a first semiconductor capping layer (not shown) covering the upper surface of the source / drain body 134. The first semiconductor capping layer (not shown) can include a SiGe layer having a Ge content ratio lower than that of the undoped Si layer, the Si layer doped with a p-type dopant, or the source / drain body 134.

[0046] In some other embodiments, a second group of source / drain regions 130 including some of the plurality of source / drain regions 130 can be configured as NMOS transistors. The source / drain blockers 132 of the second group of source / drain regions 130 can each include a Si layer, and the source / drain bodies 134 can include a Si layer doped with an n-type dopant. In some other embodiments, the source / drain blockers 132 and the source / drain bodies 134 can each include a Si layer doped with an n-type dopant, and the content ratio of the n-type dopant in the source / drain body 134 can be higher than the content ratio of the n-type dopant in the source / drain blocker 132. The n-type dopant can be selected from P, As, and Sb, but is not limited thereto. In some embodiments, the second group of source / drain regions 130 may further include a second semiconductor capping layer (not shown) covering the upper surface of the source / drain body 134. The second semiconductor capping layer (not shown) can include an undoped Si layer or a Si layer doped with an n-type dopant. When the second semiconductor capping layer (not shown) includes a Si layer doped with an n-type dopant, the content ratio of the n-type dopant in the second semiconductor capping layer (not shown) can be lower than the content ratio of the n-type dopant in the source / drain blocker 132.

[0047] As Figure 2B shown, trench side insulation spacers 119 can be disposed on the plurality of device isolation layers 114, and the trench side insulation spacers 119 cover the lower portions of the sidewalls of each of the plurality of source / drain regions 130 in the second horizontal direction (Y direction). For example, the trench side insulation spacers 119 can contact the lower sidewalls of each of the plurality of source / drain regions 130.

[0048] In some embodiments, the uppermost portion of the trench side insulating spacer 119 may have a vertical height higher than the lowermost surface of each of the plurality of source / drain regions 130. In some embodiments, the trench side insulating spacer 119 may define a plurality of backside trenches BT together with the plurality of device isolation layers 114.

[0049] In some embodiments, the trench side insulating spacer 119 may include SiN, SiO, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The terms "SiN", "SiO", "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein may each represent a material composed of the elements included in the corresponding term, and may not be a chemical formula representing a stoichiometric relationship.

[0050] According to an embodiment, a plurality of device isolation layers 114, a plurality of source / drain regions 130, trench side insulating spacers 119, and outer insulating spacers 116 may be covered by an insulating liner 142. According to an embodiment, an inter-gate insulating layer 144 may be disposed on the insulating liner 142. According to an embodiment, the insulating liner 142 and the inter-gate insulating layer 144 may be disposed between two source / drain regions 130 adjacent to each other along the second horizontal direction (Y direction).

[0051] In some other embodiments, the insulating liner 142 may be omitted. In this case, the inter-gate insulating layer 144 may contact the plurality of source / drain regions 130 .

[0052] In some other embodiments, the insulating liner 142 may include SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO 2 In some embodiments, the inter-gate insulating layer 144 may include silicon nitride, silicon oxide, SiON, SiOCN, or a combination thereof.

[0053] According to an embodiment, the plurality of source / drain regions 130 may include a plurality of first source / drain regions 130a and a plurality of second source / drain regions 130b. According to an embodiment, the plurality of first source / drain regions 130a and the plurality of second source / drain regions 130b may be separated from each other in a first horizontal direction (X direction), with one nanosheet stack NSS between the plurality of first source / drain regions 130a and the plurality of second source / drain regions 130b. For example, the first source / drain regions 130a may each be used as a drain region, and the plurality of second source / drain regions 130b may each be used as a source region. Figure 1, it is shown that a plurality of first source / drain regions 130a are arranged in a row in the second horizontal direction (Y direction), and a plurality of second source / drain regions 130b are separated from the plurality of first source / drain regions 130a and arranged in a row in the second horizontal direction (Y direction), and a gate structure 162 is between the plurality of second source / drain regions 130b and the plurality of first source / drain regions 130a, but the inventive concept is not limited thereto. For example, at least one first source / drain region 130a and at least one second source / drain region 130b may be arranged between two adjacent gate structures 162 in the second horizontal direction (Y direction). In some embodiments, the plurality of first source / drain regions 130a and the plurality of second source / drain regions 130b may have the same shape, such as Figure 2A and Figure 2B In some other embodiments, the plurality of first source / drain regions 130a and the plurality of second source / drain regions 130b may have different shapes, and, for example, may have different horizontal widths or different vertical thicknesses.

[0054] According to an embodiment, the integrated circuit device 100 may further include a plurality of upper contacts 172 on the plurality of first source / drain regions 130a. Each of the plurality of upper contacts 172 may extend longer in the vertical direction (Z direction) between a pair of gate structures 162 adjacent to each other among the plurality of gate structures 162. A metal silicide layer (not shown) may be disposed between the first source / drain regions 130a and the upper contacts 172.

[0055] Each of the plurality of upper contacts 172 may fill the interior of an upper contact hole 172H that passes through the inter-gate insulating layer 144 and the insulating liner 142 in the vertical direction (Z direction) and extends to each of the plurality of first source / drain regions 130a. In some embodiments, the plurality of upper contacts 172 may electrically connect the plurality of first source / drain regions 130a to wirings (not shown) on the plurality of upper contacts 172. Each of the plurality of first source / drain regions 130a may be separated from the upper contact 172, with a metal silicide layer (not shown) between each of the plurality of first source / drain regions 130a and the upper contact 172. Each of the plurality of first source / drain regions 130a may surround the lower portion of a corresponding one of the plurality of upper contacts 172 at the outside of each upper contact hole 172H.

[0056] In some embodiments, the metal silicide layer (not shown) may include titanium silicide, but is not limited thereto. In some other embodiments, the metal silicide layer (not shown) may be omitted. In some embodiments, each of the plurality of upper contacts 172 may include a metal, a conductive metal nitride, or a combination thereof. For example, each of the plurality of upper contacts 172 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), TiN, TaN, an alloy thereof, or a combination thereof.

[0057] According to an embodiment, each of the plurality of insulating blocks 212 may be disposed on the lower surface of the corresponding first source / drain region 130a in the plurality of first source / drain regions 130a. For example, the plurality of insulating blocks 212 may overlap the plurality of first source / drain regions 130a in the vertical direction (Z direction). According to an embodiment, the plurality of insulating blocks 212 may extend in the vertical direction (Z direction) in the plurality of back trenches BT, and the two sidewalls of each of the plurality of insulating blocks 212 in the first horizontal direction (X direction) may face and contact the gap-filling insulating layer 222, and the two sidewalls of each of the plurality of insulating blocks 212 in the second horizontal direction (Y direction) may face and contact the device isolation layer 114.

[0058] According to an embodiment, the plurality of insulating barriers 124 may be respectively disposed between the plurality of first source / drain regions 130a and the plurality of insulating blocks 212. The plurality of insulating barriers 124 may cover the lower surfaces of the plurality of first source / drain regions 130a in the plurality of backside trenches BT. For example, the lower surface of each of the plurality of first source / drain regions 130a may face the upper surface of the corresponding insulating block 212 of the plurality of insulating blocks 212, and the insulating barrier 124 is between the lower surface of each of the plurality of first source / drain regions 130a and the upper surface of the corresponding insulating block 212 of the plurality of insulating blocks 212.

[0059] According to an embodiment, an upper surface 124U of each of the plurality of insulating barriers 124 may contact a lower surface of a pair of source / drain barriers 132 and a lower surface of one source / drain body 134. According to an embodiment, a pair of source / drain barriers 132 and a source / drain body 134 of each of the plurality of first source / drain regions 130a may be separated from an insulating block 212 and a plurality of gap-filling insulating layers 222, with the insulating barriers 124 being between the pair of source / drain barriers 132 and the source / drain body 134 of each of the plurality of first source / drain regions 130a and the insulating block 212 and the plurality of gap-filling insulating layers 222. For example, the plurality of gap-filling insulating layers 222 may include sidewalls facing the plurality of insulating barriers 124 and / or the plurality of insulating blocks 212, and may completely cover a lower surface 162L of the gate structure 162.

[0060] refer to Figure 2C and Figure 2D, the lower surface 162L of each of the plurality of gate structures 162 may be disposed at a first vertical height LV1. For example, the gate dielectric layer 152 covering the lower surface of the lowest portion of each of the plurality of gate electrodes 160 may be disposed at the first vertical height LV1. According to an embodiment, the upper surface 124U of each of the plurality of insulating barriers 124 may be disposed at a second vertical height LV2 that is higher than the first vertical height LV1. In some embodiments, the upper surface 124U of each of the plurality of insulating barriers 124 may be disposed at a vertical height higher than the lower surface of the lowest end portion of the sub-gate portion 160S of each of the plurality of gate electrodes 160. For example, the upper surface of each of the plurality of gap-filling insulating layers 222 may contact the lower surface 162L of each of the plurality of gate structures 162, and may be disposed at a vertical height lower than the upper surface 124U of each of the plurality of insulating barriers 124.

[0061] According to an embodiment, both sidewalls of each of the plurality of insulating barriers 124 in the first horizontal direction (X direction) may each include a portion facing the gate structure 162. In some embodiments, both sidewalls of each of the plurality of insulating barriers 124 in the first horizontal direction (X direction) may be separated from the lowermost sub-gate portion 160S of the gate electrode 160, with the gate dielectric layer 152 between both sidewalls of each of the plurality of insulating barriers 124 in the first horizontal direction (X direction) and the lowermost sub-gate portion 160S of the gate electrode 160.

[0062] In some embodiments, the lower surface of each of the plurality of insulating blocks 124 may be disposed at a vertical height lower than the first vertical height LV1. In this case, both sidewalls of each of the plurality of insulating blocks 124 in the first horizontal direction (X direction) may include portions that contact and face the plurality of gap-filling insulating layers 222. In some other embodiments, the lower surface of each of the plurality of insulating blocks 124 may be disposed at a vertical height higher than or equal to the first vertical height LV1. In this case, the sidewalls of each of the plurality of insulating blocks 212 may include portions that face the plurality of gate structures 162.

[0063] In some embodiments, both sidewalls of each of the plurality of insulating barrier members 124 in the second horizontal direction (Y direction) may include a portion contacting the trench side insulating spacer 119 and a portion contacting the device isolation layer 114 .

[0064] In some embodiments, the plurality of insulating barriers 124 and the plurality of insulating blocks 212 may each include SiN, SiO, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein may each represent a material composed of the elements included in the corresponding term, and may not be a chemical formula representing a stoichiometric relationship.

[0065] In some embodiments, the plurality of insulating barriers 124 may include a material different from that of the plurality of gap-filling insulating layers 222. In some embodiments, the plurality of insulating blocks 212 may include a material different from that of the plurality of gap-filling insulating layers 222.

[0066] According to an embodiment, the plurality of insulating barriers 124 of the integrated circuit device 100 may cover the lower surface of each of the plurality of first source / drain regions 130a so as not to be exposed. The plurality of insulating barriers 124 may protect the plurality of first source / drain regions 130a so as not to be etched during the manufacturing process of the integrated circuit device 100, or may limit and / or prevent leakage current from occurring when the peripheral semiconductor material that is not removed and remains contacts the plurality of first source / drain regions 130a. For example, the plurality of insulating barriers 124 may be disposed between the plurality of first source / drain regions 130a and the plurality of gap-filling insulating layers 222, and the plurality of gap-filling insulating layers 222 may completely contact the lower surface 162L of the gate structure 162 and may be separated from the first source / drain regions 130a. Therefore, power loss caused by the integrated circuit device 100 may be limited and / or prevented, and therefore, electrical reliability may be enhanced.

[0067] According to an embodiment, each of the plurality of lower contacts 232 may be disposed on a lower surface of a corresponding second source / drain region 130b among the plurality of second source / drain regions 130b, each of the plurality of lower contacts 232 filling a portion of a corresponding back side trench BT among the plurality of back side trenches BT and extending in a vertical direction (Z direction). For example, each of the plurality of lower contacts 232 may vertically overlap with a corresponding second source / drain region 130b among the plurality of second source / drain regions 130b, and may contact a corresponding second source / drain region 130b among the plurality of second source / drain regions 130b. According to an embodiment, an upper surface 232U of each of the plurality of lower contacts 232 may contact a lower surface of a pair of source / drain barrier members 132 and a lower surface of a source / drain body 134.

[0068] According to an embodiment, both sidewalls of each of the plurality of lower contacts 232 in the first horizontal direction (X direction) may include portions facing and contacting gap-filling insulating layer 222, and both sidewalls of each of the plurality of lower contacts 232 in the second horizontal direction (Y direction) may include portions facing and contacting device isolation layer 114. According to an embodiment, the plurality of gap-filling insulating layers 222 may be disposed between the plurality of insulating blocks 212 and the plurality of lower contacts 232 in the first horizontal direction (X direction).

[0069] and Figure 1 Different from the illustration of FIG. 1 , when two first source / drain regions 130 a are arranged adjacent to each other along the first horizontal direction (X direction) and the gate structure 162 is between the two first source / drain regions 130 a, two insulating blocks 212 respectively disposed under the two first source / drain regions 130 a may be separated from each other in the first horizontal direction (X direction), and the gap-filling insulating layer 222 is between the two insulating blocks 212. Similarly, Figure 1 Different from the illustration of FIG. 1 , in the case where two second source / drain regions 130 b are arranged adjacent to each other in the first horizontal direction (X direction) and the gate structure 162 is between the two second source / drain regions 130 b, two lower contacts 232 respectively disposed under the two second source / drain regions 130 b may be separated from each other in the first horizontal direction (X direction), with the gap-filling insulating layer 222 being between the two lower contacts 232. For example, in each back-side trench BT, each of the plurality of insulating blocks 212 and a corresponding lower contact 232 among the plurality of lower contacts 232 may be separated from each other and may be arranged in the first horizontal direction (X direction), with the gap-filling insulating layer 222 being between each of the plurality of insulating blocks 212 and a corresponding lower contact 232 among the plurality of lower contacts 232.

[0070] According to an embodiment, an upper surface 232U of each of the plurality of lower contacts 232 may be disposed at a second vertical height LV2, which is the same vertical height as an upper surface 124U of each of the plurality of insulating barriers 124. According to an embodiment, an upper surface 232U of each of the plurality of lower contacts 232 may be disposed at a vertical height higher than a lower surface 162L of each of the plurality of gate structures 162. In this case, two sidewalls of each of the plurality of lower contacts 232 in the first horizontal direction (X direction) may include portions facing the plurality of gate structures 162. For example, two sidewalls of each of the plurality of lower contacts 232 in the first horizontal direction (X direction) may include portions facing the lowermost sub-gate portion 160S of the gate electrode 160, with the gate dielectric layer 152 between the portions and the lowermost sub-gate portion 160S of the gate electrode 160. In some embodiments, two sidewalls of each of the plurality of lower contacts 232 in the second horizontal direction (Y direction) may include portions contacting and facing the trench side insulating spacers 119.

[0071] In some embodiments, the plurality of second source / drain regions 130b may include a flat bottom profile, and the plurality of lower contacts 232 may completely cover the lower surface of the plurality of second source / drain regions 130b. For example, the plurality of lower contacts 232 may contact the plurality of second source / drain regions 130b, or may not pass through the plurality of second source / drain regions 130b and extend to the interior of the plurality of second source / drain regions 130b.

[0072] In some embodiments, the plurality of lower contacts 232 may include a conductive material. The conductive material may include, for example, doped polysilicon or metal, but the embodiment is not limited thereto. In some embodiments, the plurality of lower contacts 232 may include a metal body extending in a vertical direction (Z direction) and a conductive barrier layer surrounding the metal body. The metal body may include Ru, Co, W, or a combination thereof. The conductive barrier layer may include Ti, TiN, Ta, TaN, or a combination thereof.

[0073] exist FIG. 2A to FIG. 2D , it is shown that the upper surfaces 124U of the plurality of insulating blocks 124, the upper surfaces 232U of the plurality of lower contacts 232, and the upper surfaces of the plurality of insulating blocks 212 each have a flat shape, but the embodiment is not limited thereto. For example, each of the upper surfaces 124U of the plurality of insulating blocks 124, the upper surfaces 232U of the plurality of lower contacts 232, and the upper surfaces of the plurality of insulating blocks 212 may independently have an upward convex shape or a downward convex shape.

[0074] According to an embodiment, a lower surface of each of the plurality of gap-filling insulating layers 222, a lower surface of a corresponding insulating block 212 among the plurality of insulating blocks 212, a lower surface of a corresponding lower contact portion 232 among the plurality of lower contacts 232, and a lower surface of a corresponding device isolation layer 114 among the plurality of device isolation layers 114 may be configured with a first coplanar surface BSSB.

[0075] According to an embodiment, with respect to the first horizontal direction (X direction), the plurality of insulating barriers 124 may have a first horizontal width wx1, the plurality of insulating blocks 212 may have a second horizontal width wx2, and the plurality of lower contacts 232 may have a third horizontal width wx3. In some embodiments, the first horizontal width wx1 may be the same as the second horizontal width wx2. For example, the sidewall of each of the plurality of insulating barriers 124 and the sidewall of the corresponding insulating block 212 in the plurality of insulating blocks 212 may be configured with a coplanar surface. In some embodiments, the third horizontal width wx3 may be the same as the first horizontal width wx1 and the second horizontal width wx2. In some other embodiments, each of the first horizontal width wx1, the second horizontal width wx2, and the third horizontal width wx3 may gradually narrow toward the first coplanar surface BSSB in the vertical direction (Z direction). In this case, the first horizontal width wx1 may be greater than the second horizontal width wx2. In some embodiments, with respect to the same vertical height, the first horizontal width wx1 of the plurality of insulating barriers 124 may be the same as the third horizontal width wx3 of the plurality of lower contacts 232. In some embodiments, with respect to the same vertical height, the second horizontal width wx2 of the plurality of insulating blocks 212 may be the same as the third horizontal width wx3 of the plurality of lower contacts 232 .

[0076] According to an embodiment, with respect to the second horizontal direction (Y direction), the plurality of insulating blocks 212 may have a fourth horizontal width wy1, the plurality of insulating blocks 212 may have a fifth horizontal width wy2, and the plurality of lower contacts 232 may have a sixth horizontal width wy3. In some embodiments, the width of each of the plurality of back trenches BT in the second horizontal direction (Y direction) may gradually increase in the vertical direction (Z direction) toward the first coplanar surface BSSB in a direction away from the lower surface of the corresponding source / drain region 130 in the plurality of source / drain regions 130. In some embodiments, each of the fourth horizontal width wy1, the fifth horizontal width wy2, and the sixth horizontal width wy3 may gradually increase toward the first coplanar surface BSSB. For example, the plurality of insulating blocks 212 may be disposed at a lower vertical height than the plurality of insulating blocks 124 in the back trenches BT, and the fifth horizontal width wy2 may be greater than the fourth horizontal width wy1. In some embodiments, with respect to the same vertical height, the fourth horizontal width wy1 of the plurality of insulating blocks 124 may be the same as the sixth horizontal width wy3 of the plurality of lower contacts 232. In some embodiments, with respect to the same vertical height, the fifth horizontal width wy2 of the plurality of insulating blocks 212 may be the same as the sixth horizontal width wy3 of the plurality of lower contacts 232 .

[0077] According to an embodiment, the integrated circuit device 100 may include a metal power rail 254 extending along the first horizontal direction (X direction) in a partial region of the first coplanar surface BSSB. According to an embodiment, the metal power rail 254 may be configured to contact the lower surface of each of the plurality of lower contacts 232 and apply a voltage to the plurality of second source / drain regions 130 b. The metal power rail 254 may be surrounded by a lower insulating layer 252 covering another region of the first coplanar surface BSSB.

[0078] In some embodiments, the plurality of metal power rails 254 may include a metal wiring layer, and a conductive barrier layer surrounding the metal wiring layer. The detailed configuration of the metal wiring layer and the conductive barrier layer, each configuring the metal power rail 254, may be substantially the same as the metal body and the conductive barrier layer, each configuring the lower contact 232. In some embodiments, the lower insulating layer 252 may include silicon oxide, silicon nitride, silicon carbide, a low-k dielectric material, or a combination thereof.

[0079] Figure 3A and Figure 3B is a cross-sectional view for describing an integrated circuit device 100a according to some other embodiments, Figure 3A is along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional surface taken along the line X1-X1′, and Figure 3B yes Figure 3A A magnified view of area EX3. Figure 3A and Figure 3B In, with Figure 1 as well as FIG. 2A to FIG. 2D The same reference numerals refer to similar elements, and repeated descriptions thereof are omitted.

[0080] According to an embodiment, the insulating barrier 124 and the insulating block 212 may be sequentially arranged one by one on the lower surface of each of the plurality of source / drain regions 130. According to an embodiment, one insulating barrier 124 and one insulating block 212 may configure one insulating structure, and the insulating structure may extend in a vertical direction (Z direction) on the lower surface of each of the plurality of source / drain regions 130. According to an embodiment, in each back side trench BT, a plurality of gap filling insulating layers 222 may be arranged separately from each other in a first horizontal direction (X direction), with one insulating structure between the plurality of gap filling insulating layers 222.

[0081] For example, a first group of insulating barriers 124 including some of the plurality of insulating barriers 124 may cover lower surfaces of the plurality of first source / drain regions 130a, and a first group of insulating blocks 212 including some of the plurality of insulating blocks 212 may extend in a vertical direction (Z direction) below the lower surfaces of the plurality of first source / drain regions 130a. For example, a second group of insulating barriers 124 including some of the plurality of insulating barriers 124 may cover lower surfaces of the plurality of second source / drain regions 130b, and a second group of insulating blocks 212 including some of the plurality of insulating blocks 212 may extend in a vertical direction (Z direction) below the lower surfaces of the plurality of second source / drain regions 130b.

[0082] In some embodiments, the plurality of lower contacts 232 may pass through the second group of insulating blocks 212 and the second group of insulating barriers 124 in the vertical direction (Z direction), and may contact the lower surfaces of the plurality of second source / drain regions 130b. For example, a portion of each of the plurality of lower contacts 232 may extend to the interior of the corresponding second source / drain region 130b in the plurality of second source / drain regions 130b. In some embodiments, the upper surfaces of the plurality of lower contacts 232 may be disposed at a vertical height higher than the lower surfaces of the plurality of source / drain regions 130. For example, the upper surfaces of the plurality of lower contacts 232 may be disposed at a vertical height higher than the second vertical height LV2.

[0083] In some embodiments, a metal silicide layer (not shown) may be disposed between the plurality of second source / drain regions 130 b and the plurality of lower contacts 232. Each of the plurality of second source / drain regions 130 b may be separated from the lower contact 232 with a metal silicide layer (not shown) therebetween.

[0084] In some embodiments, the width of each of the plurality of lower contacts 232 in the first horizontal direction (X direction) may gradually narrow in the vertical direction (Z direction) in the direction away from the first coplanar surface BSSB. For example, the width of the upper portion of each of the plurality of lower contacts 232 in the first horizontal direction (X direction) may be narrower than the width of the lower portion of each of the plurality of lower contacts 232 in the first horizontal direction (X direction). For example, the third horizontal width wx3 of the plurality of lower contacts 232 may gradually increase toward the first coplanar surface BSSB.

[0085] In some embodiments, the third horizontal width wx3 of the plurality of lower contacts 232 may be narrower than the first horizontal width wx1 of the plurality of insulating barriers 124, and may be narrower than the second horizontal width wx2 of the plurality of insulating blocks 212. In some embodiments, the plurality of lower contacts 232 may be separated from the plurality of gap-filling insulating layers 222, with the plurality of insulating barriers 124 and the plurality of insulating blocks 212 being between the plurality of lower contacts 232 and the plurality of gap-filling insulating layers 222. In some embodiments, the plurality of lower contacts 232 may be separated from the plurality of gate structures 162, with the second group of insulating barriers 124 being between the plurality of lower contacts 232 and the plurality of gate structures 162.

[0086] Figure 4A and Figure 4B is a cross-sectional view for describing an integrated circuit device 100 b according to some other embodiments. Figure 4A is along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional surface taken along the line X1-X1′, and Figure 4B yes Figure 4A A magnified view of area EX4. Figure 4A and Figure 4B In, with Figure 1 as well as FIG. 2A to FIG. 2D The same reference numerals refer to similar elements, and repeated descriptions thereof are omitted.

[0087] According to an embodiment, the plurality of insulating barriers 124 may cover lower surfaces of the plurality of source / drain regions 130. According to an embodiment, a first group of insulating barriers 124 including some of the plurality of insulating barriers 124 may cover lower surfaces of the plurality of first source / drain regions 130a, and a second group of insulating barriers 124 including some of the plurality of insulating barriers 124 may cover lower surfaces of the plurality of second source / drain regions 130b.

[0088] According to an embodiment, each of the plurality of lower contacts 232 may include a first portion 232a and a second portion 232b, wherein the first portion 232a extends along a vertical direction (Z direction) between two gap-filling insulating layers 222 adjacent to each other along a first horizontal direction (X direction), and the second portion 232b extends from the first portion 232a, passes through the second group of insulating barriers 124 in the vertical direction (Z direction), and contacts a corresponding second source / drain region 130b among the plurality of second source / drain regions 130b.

[0089] In some embodiments, the upper surface of the first portion 232a of each of the plurality of lower contacts 232 may contact the lower surface of the second group of insulating barriers 124. In some embodiments, the second portion 232b of each of the plurality of lower contacts 232 may include a portion extending to the inside of the corresponding second source / drain region 130b of the plurality of second source / drain regions 130b. In some embodiments, the upper surface of the second portion 232b may be disposed at a vertical height higher than the second vertical height LV2.

[0090] In some embodiments, the second portion 232 b of each of the plurality of lower contacts 232 may be separated from the plurality of gate structures 162 in the first horizontal direction (X direction), with the second group of insulating barriers 124 being between the second portion 232 b of each of the plurality of lower contacts 232 and the plurality of gate structures 162. For example, the plurality of lower contacts 232 may be separated from the plurality of gate electrodes 160, with the second group of insulating barriers 124 being between the plurality of lower contacts 232 and the plurality of gate electrodes 160, and thus, the electrical reliability of the integrated circuit device 100 b may be ensured.

[0091] In some embodiments, the seventh horizontal width wx31 is the width of the first portion 232a in the first horizontal direction (X direction), the eighth horizontal width wx32 is the width of the second portion 232b in the first horizontal direction (X direction), and the seventh horizontal width wx31 may be greater than the eighth horizontal width wx32. In some embodiments, the seventh horizontal width wx31 of the first portion 232a may be the same as the first horizontal width wx1 of the plurality of insulating barriers 124, and may be the same as the second horizontal width wx2 of the plurality of insulating blocks 212. In some embodiments, the seventh horizontal width wx31 of the first portion 232a may be constant regardless of the vertical height. In some embodiments, the eighth horizontal width wx32 of the second portion 232b may gradually decrease in the vertical direction (Z direction) in the direction away from the first coplanar surface BSSB.

[0092] Figure 5A and Figure 5B is a cross-sectional view for describing an integrated circuit device 100 c according to some other embodiments. Figure 5A is along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional surface taken along the line X1-X1′, and Figure 5B yes Figure 5A Detailedly, refer to the above Figure 5A and Figure 5B The difference between the described integrated circuit device 100c and the integrated circuit device 100b may be whether the lower insulating liner 230 is disposed between the first portion 232a of each of the plurality of lower contacts 232 and the adjacent gap-filling insulating layer 222. Figure 5A and Figure 5B In, with Figure 1 , FIG. 2A to FIG. 2D , Figure 4A as well as Figure 4B The same reference numerals refer to similar elements, and repeated descriptions thereof are omitted.

[0093] According to an embodiment, a lower insulating liner 230 may be disposed on a lower surface of each of the plurality of second group insulating barriers 124, the lower insulating liner 230 covering a sidewall of a first portion 232a of each of the plurality of lower contacts 232. According to an embodiment, the lower insulating liner 230 may be disposed between the first portion 232a of each of the plurality of lower contacts 232 and an adjacent gap-filling insulating layer 222. For example, the first portion 232a of each of the plurality of lower contacts 232 may be separated from the gap-filling insulating layer 222 in a first horizontal direction (X direction), with the lower insulating liner 230 between the first portion 232a of each of the plurality of lower contacts 232 and the gap-filling insulating layer 222.

[0094] According to an embodiment, the first portion 232a and the second portion 232b of each of the plurality of lower contacts 232 may overlap each other in the vertical direction (Z direction). In some embodiments, the sidewalls of the first portion 232a and the sidewalls of the second portion 232b may be configured with coplanar surfaces and extend. In some embodiments, the lower insulating liner 230 may vertically overlap with the second group of insulating barriers 124. For example, the first portion 232a may not vertically overlap with the second group of insulating barriers 124.

[0095] In some embodiments, the seventh horizontal width wx31 of the first portion 232a of each of the plurality of lower contacts 232 may be smaller than the first horizontal width wx1 of the plurality of insulating barriers 124, and may be smaller than the second horizontal width wx2 of the plurality of insulating blocks 212. In some embodiments, the seventh horizontal width wx31 of the first portion 232a may be constant regardless of the vertical height. In some embodiments, the eighth horizontal width wx32 of the second portion 232b may gradually decrease in the vertical direction (Z direction) in a direction away from the first coplanar surface BSSB.

[0096] FIG. 6A to FIG. 19B is a cross-sectional view showing a method of manufacturing an integrated circuit device according to an embodiment in process order, Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig.12 , Fig.13 , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A The process sequence is shown along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional surface taken along the line X1-X1′, and Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B and Fig.19B The process sequence is shown along Figure 1 The cross-sectional surface taken along the line Y1-Y1′ and along Figure 1 A cross-sectional view of the cross-sectional surface taken along the line Y2-Y2′. FIG. 6A to FIG. 19B In, with Figure 1 as well as FIG. 2A to FIG. 2D The same reference numerals refer to similar elements, and repeated descriptions thereof are omitted.

[0097] refer to Fig. 6A and Figure 6B , a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS may be alternately stacked one by one on the substrate 102, and then, a plurality of fin structures FA may be defined on the substrate 102 by etching a portion of the substrate 102, the plurality of sacrificial semiconductor layers 104, and the plurality of nanosheet semiconductor layers NS. The plurality of fin structures FA may protrude from the main surface 102M of the substrate 102 in a vertical direction (Z direction). Subsequently, a device isolation layer 114 may be formed covering the sidewalls of each of the plurality of fin structures FA. The stacked structure of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS may remain on the fin top FT of each of the plurality of fin structures FA.

[0098] In some embodiments, the substrate 102 may include a semiconductor (e.g., Si or Ge) or a compound semiconductor (e.g., SiGe, SiC, GaAs, InAs, InGaAs, or InP). The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" used herein may each represent a material composed of the elements included in the corresponding term, and may not be a chemical formula representing a stoichiometric relationship. For example, the substrate 102 may be a bulk Si substrate.

[0099] The plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS may include semiconductor materials having different etching selectivities, respectively. In some embodiments, the plurality of nanosheet semiconductor layers NS may include a Si layer, and the plurality of sacrificial semiconductor layers 104 may include a SiGe layer. In some embodiments, the Ge content ratio of the plurality of sacrificial semiconductor layers 104 may be constant. The SiGe layer configuring the plurality of sacrificial semiconductor layers 104 may have a constant Ge content ratio selected from a range of about 5 at.% to about 60 at.% (e.g., a range of about 10 at.% to about 40 at.%). The Ge content ratio of the SiGe layer configuring the plurality of sacrificial semiconductor layers 104 may be selected differently according to the circumstances.

[0100] refer to Fig. 7A and Figure 7B , a plurality of dummy gate structures DGS may be formed on the stacked structure of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS. Each of the plurality of dummy gate structures DGS may extend longer in the second horizontal direction (Y direction). Each of the plurality of dummy gate structures DGS may have a structure in which an oxide layer D122, a dummy gate layer D124, and a capping layer D126 are sequentially stacked. In some embodiments, the dummy gate layer D124 may include polysilicon, and the capping layer D126 may include silicon nitride.

[0101] Subsequently, an inner gate insulating spacer 118 covering both sidewalls of the dummy gate structure DGS may be formed, and then, a spacer 119 covering the fin structure FA, the dummy gate structure DGS, and the inner gate insulating spacer 118 may be formed. For example, the inner gate insulating spacer 118 may include SiN. For example, the spacer 119 may include SiOCN, SiCN, or a combination thereof. In some embodiments, the spacer 119 may include a single layer including SiOCN. In some other embodiments, the spacer 119 may include a SiOCN layer covering the inner gate insulating spacer 118, and an oxide layer covering the SiOCN layer.

[0102] refer to Fig. 8A and Figure 8B, by etching a portion of the spacer 119, an outer insulating spacer 116 covering both sidewalls of the dummy gate structure DGS can be formed from the inner gate insulating spacer 118 and the spacer 119. While the outer insulating spacer 116 is formed, since the spacer 119 is etched, the fin structure FA can be exposed. The fin structure FA and the spacer 119 exposed as described above can be etched, and thus, a first recess R1 can be formed on the fin structure FA. An etching process using a dry etching process, a wet etching process, or a combination thereof can be performed to form the first recess R1. In some embodiments, the lower surface of the first recess R1 can be set at a vertical height lower than the upper surface of each of the plurality of device isolation layers 114, and can be set at a vertical height higher than the main surface 102M of the substrate 102.

[0103] While the etching process for forming the first recess R1 is performed, a first recess-side insulating spacer 119 covering both sidewalls of the fin structure FA may be formed in a region adjacent to the first recess R1 .

[0104] After the first recess R1 is formed in the fin structure FA, the plurality of nanosheet semiconductor layers NS (see Fig. 7A and Figure 7B ) may be divided into a plurality of nanosheet stacks NSS. Each of the plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, a third nanosheet N3, and a fourth nanosheet N4.

[0105] refer to Fig.9A and Fig. 9B ,exist Fig. 8A and Figure 8B A plurality of sacrificial semiconductor blocks 122 filling a portion of the first recess R1 may be formed from the resulting material. The plurality of sacrificial semiconductor blocks 122 may be formed by selectively epitaxially growing a semiconductor material from the fin structure FA exposed through the first recess R1. In some embodiments, the plurality of sacrificial semiconductor blocks 122 may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or an epitaxially grown SiGe layer.

[0106] In some embodiments, the upper surface of each of the plurality of sacrificial semiconductor blocks 122 may be disposed at a vertical height lower than the lower surface of the lowermost sacrificial semiconductor layer 104 of the plurality of sacrificial semiconductor layers 104 stacked in the vertical direction (Z direction). In some embodiments, the top profile of each of the plurality of sacrificial semiconductor blocks 122 may be formed to be flat by adjusting the epitaxial growth temperature.

[0107] refer to Fig. 10A and Fig. 10B ,exist Fig.9A and Fig. 9BIn the resulting material, a plurality of insulating barriers 124 filling a portion of the first recess R1 may be formed on the plurality of sacrificial semiconductor blocks 122, respectively. In some embodiments, the vertical height of the upper surface of each of the plurality of insulating barriers 124 may be set at a vertical height higher than the lower surface of the lowermost sacrificial semiconductor layer 104 among the plurality of sacrificial semiconductor layers 104 stacked in the vertical direction (Z direction).

[0108] refer to Fig.11A and Fig. 11B ,exist Fig. 10A and Fig. 10B In the resulting material, a plurality of source / drain regions 130 may be formed by selectively epitaxially growing a semiconductor material in the first recess R1. For example, a source / drain barrier 132 and a source / drain body 134 may be sequentially formed in the first recess R1.

[0109] In some embodiments, a semiconductor material may be epitaxially grown from the sidewalls of each of the plurality of sacrificial semiconductor layers 104 and the sidewalls of each of the plurality of nanosheets N1 to N4 exposed by the first recess R1 to form a source / drain barrier 132. In some embodiments, the source / drain barrier 132 may cover the sidewalls of each of the plurality of sacrificial semiconductor layers 104 and the sidewalls of each of the plurality of nanosheets N1 to N4. For example, a portion adjacent to the sidewalls of each of the plurality of sacrificial semiconductor layers 104 and the sidewalls of each of the plurality of nanosheets N1 to N4 may be a portion of the upper surface of each of the plurality of insulating barriers 124 and may be covered by the source / drain barrier 132, and the other portion of the upper surface may be exposed.

[0110] In some embodiments, a low pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process may be performed by using a source material including an elemental semiconductor precursor to form the source / drain barrier 132. The elemental semiconductor precursor may include an element such as Si or Ge.

[0111] For example, a Si source and a Ge source may be used to form the source / drain barrier 132. The Si source may be silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), dichlorosilane (SiH 2 Cl 2 ), but not limited thereto. The Ge source can use germanium (GeH 4 ), digermane (Ge 2 H 6 ), trigermane (Ge3 H 8 ), Tetragermane (Ge 4 H 10 ), dichlorogermane (Ge 2 H 2 Cl 2 ), but is not limited thereto. When the source / drain blocking member 132 includes a SiGe layer doped with boron (B), a B source as well as a Si source and a Ge source may also be used to form a B-doped SiGe layer. The B source may use diborane (B 2 H 6 ), phenylborane, tetraborane and pentaborane, but not limited thereto. In some embodiments, when the epitaxial growth process for forming the source / drain barrier 132 is performed, a B dopant ion implantation process using a B source may be performed in-situ.

[0112] In some embodiments, a portion of the upper surface of each of the plurality of insulating barriers 124 that is not covered by the source / drain barrier 132 and a source / drain body 134 covering the source / drain barrier 132 may be formed on the plurality of insulating barriers 124. A process similar to the description of the process of forming the source / drain barrier 132 may be performed for forming the source / drain body 134. In some embodiments, the process of forming the source / drain body 134 may be performed by the process of in-situ and forming the source / drain barrier 132.

[0113] Subsequently, an insulating liner 142 covering the plurality of source / drain regions 130 may be formed, and an intergate insulating layer 144 may be formed on the insulating liner 142 , and then, an upper surface of the capping layer D126 may be exposed by planarizing the insulating liner 142 and the intergate insulating layer 144 .

[0114] refer to Fig.12 , can be obtained by Fig.11A and Fig. 11B The resulting material removes the capping layer D126 to expose the upper surface of the dummy gate layer D124, and a portion of each of the insulating liner 142 and the inter-gate insulating layer 144 can be removed so that the upper surface of the inter-gate insulating layer 144 and the upper surface of the dummy gate layer D124 are set at approximately the same height.

[0115] refer to Fig.13 , can be obtained by Fig.12The dummy gate layer D124 and the oxide layer D122 under the dummy gate layer D124 are removed from the resulting material to set a gate space GS, and the plurality of nanosheet stacks NSS may be exposed through the gate space GS. Subsequently, as the plurality of sacrificial semiconductor layers 104 remaining on the fin structure FA are removed through the gate space GS, the gate space GS may be expanded to a space between the first nanosheet N1 and the fin top FT of the fin structure FA, and between the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4.

[0116] In some embodiments, the difference in etching selectivity between the plurality of sacrificial semiconductor layers 104 and the first to fourth nanosheets N1 to N4 can be used to selectively remove the plurality of sacrificial semiconductor layers 104. Liquid or gas etchants can be used to selectively remove the plurality of sacrificial semiconductor layers 104. In some embodiments, based on CH 3 COOH etchants (e.g., CH 3 COOH、HNO 3 and HF compounds, or CH 3 COOH, H 2 O 2 An etchant composed of a compound of MgO and HF may be used to selectively remove the plurality of sacrificial semiconductor layers 104 , but the inventive concept is not limited thereto.

[0117] Subsequently, a gate dielectric layer 152 covering the exposed surfaces of the first nanosheet N1 , the second nanosheet N2 , the third nanosheet N3 , the fourth nanosheet N4 , and the fin structure FA may be formed. An atomic layer deposition (ALD) process may be used to form the gate dielectric layer 152 .

[0118] refer to Fig.14A and Fig. 14B A gate-forming conductive layer (not shown) may be formed on the gate dielectric layer 152 to cover the upper surface of the gate inter-insulating layer 144 to fill the gate space GS (see Fig.13 ). The gate-forming conductive layer (not shown) may include a metal, a metal nitride, a metal carbide, or a combination thereof. An ALD process or a CVD process may be used to form the gate-forming conductive layer (not shown). Subsequently, a gate structure 162 may be formed by removing a portion of the upper surface of each of the gate-forming conductive layer (not shown), the gate dielectric layer 152, and the external insulating spacer 116, so that the upper surface of the inter-gate insulating layer 144 is exposed, and a portion of the upper portion of the gate space GS is cleared again. Subsequently, a capping insulating pattern 168 filling the gate space GS may be formed on the gate structure 162.

[0119] refer to Fig.15A and Fig. 15B ,exist Fig.14A and Fig. 14B In the resulting material, a plurality of upper contact holes 172H exposing a plurality of first source / drain regions 130a can be formed by removing a portion of the insulating liner 142 and a portion of the inter-gate insulating layer 144, and then, the plurality of upper contact holes 172H can be extended longer toward the substrate 102 by removing a portion of each of the plurality of first source / drain regions 130a through the plurality of upper contact holes 172H using an anisotropic etching process. Subsequently, a metal silicide layer (not shown) can be formed on the plurality of first source / drain regions 130a exposed at the bottom of the plurality of upper contact holes 172H. In an embodiment, the following process can be performed to form a metal silicide layer (not shown): a metal liner (not shown) conformally covering the exposed surfaces of the plurality of first source / drain regions 130a is formed, and a reaction with the metal liner and the metal included in the plurality of first source / drain regions 130a is induced by heat treatment. Subsequently, a plurality of upper contacts 172 can be formed on the metal silicide layer. Subsequently, a plurality of front wiring layers (not shown) covering the upper surface of the inter-gate insulating layer 144, and the upper surfaces of the plurality of upper contacts 172 and the plurality of capping insulating patterns 168 may be formed, and thus, a plurality of front wiring layers (not shown) may be formed. Figure 1 Front structure of FSS.

[0120] refer to Fig.16A and Fig. 16B , a carrier substrate (not shown) may be attached to the front structure FSS, and then, the back surface of the substrate 102 may be polished so that the plurality of sacrificial semiconductor blocks 122 are exposed. In this process, a portion of each of the plurality of device isolation layers 114, a portion of the substrate 102, and a portion of each of the plurality of sacrificial semiconductor blocks 122 may be removed. For example, the plurality of sacrificial semiconductor blocks 122 may each serve as an etch stop layer, and the plurality of source / drain regions 130 may be self-aligned by the exposed plurality of sacrificial semiconductor blocks 122.

[0121] In some embodiments, the polishing process can remove the Fig.16A and Fig. 16B The substrate 102 is formed at a lower vertical height than the first recess R1 shown, and thus, a plurality of back trenches BT defining the boundaries of the fin structure FA may be formed. For example, the plurality of back trenches BT may extend in parallel in a first horizontal direction (X direction), and a plurality of sacrificial semiconductor blocks 122 and a plurality of residual blocks 103 may be disposed in the plurality of back trenches BT, the plurality of residual blocks 103 being portions of the substrate 102 that are retained and not removed.

[0122] refer to Fig.17A and Fig. 17B ,exist Fig.16A and Fig. 16BIn the resulting material, the first hole pattern HP1 can be formed by removing the plurality of sacrificial semiconductor blocks 122 exposed through the back surface. For example, the plurality of sacrificial semiconductor blocks 122 can be removed by dry etching or wet etching, but the embodiment is not limited thereto. For example, the first hole pattern HP1 can be defined by the plurality of residual blocks 103, the plurality of device isolation layers 114, and the plurality of insulating barriers 124.

[0123] Subsequently, a plurality of insulating blocks 212 filling the first hole pattern HP1 may be formed. For example, the plurality of insulating blocks 212 may be formed by polishing the back surface until the plurality of residual blocks 103 are exposed after forming a spin-coated layer filling the first hole pattern HP1.

[0124] refer to Fig.18A and Fig.18B ,exist Fig.17A and Fig. 17B In the resulting material, the second hole pattern HP2 can be formed by removing the plurality of residual blocks 103 exposed through the back surface. In some embodiments, the plurality of residual blocks 103 can be removed by wet etching, and thus, the residual blocks 103 up to the corners of the second hole pattern HP2 can be easily removed while limiting and / or preventing damage to the plurality of gate structures 162.

[0125] In some embodiments, the second hole pattern HP2 may be defined by a plurality of insulating blocks 212, a plurality of device isolation layers 114, a plurality of insulating barriers 124, and a plurality of gate structures 162. In some embodiments, the second hole pattern HP2 may completely expose the lower surfaces of the plurality of gate structures 162. For example, the width of the second hole pattern HP2 in the first horizontal direction (X direction) may be equal to the sum of the width of the lowermost sub-gate portion 160S and the width of the gate dielectric layer 152 covering the two sidewalls of the lowermost sub-gate portion 160S in the first horizontal direction (X direction). Even in this case, the lower portions of the plurality of source / drain regions 130 may be protected by the insulating barriers 124, and thus, the lower portions of the plurality of source / drain regions 130 may be restricted and / or prevented from being damaged by etching. Therefore, a portion of each of the plurality of residual blocks 103 adjacent to the lower portions of the plurality of source / drain regions 130 may not be retained so as to prevent the lower portions of the plurality of source / drain regions 130 from being exposed and removed together with the residual blocks 103. Furthermore, it is possible to prevent power loss from occurring in the integrated circuit device due to a portion of the remaining residual block 103 .

[0126] Subsequently, a plurality of gap-filling insulating layers 222 filling the second hole pattern HP2 may be formed. For example, the plurality of gap-filling insulating layers 222 may be formed by polishing the back surface until the plurality of residual blocks 103 are exposed after forming a spin-coated layer filling the second hole pattern HP2.

[0127] refer to Fig.19A and Fig.19B ,exist Fig.18A and Fig.18B In the resulting material, an etching mask (not shown) may be formed on the back surface, the etching mask (not shown) exposing the insulating block 212 vertically overlapping the plurality of second source / drain regions 130b, and then, a lower contact hole 232H exposing the lower surface of the second source / drain region 130b may be formed by removing the insulating barrier 124 and the insulating block 212 below the plurality of second source / drain regions 130b. In some embodiments, the plurality of gap-filling insulating layers 222 may have an etching selectivity relative to the plurality of insulating barriers 124 and the plurality of insulating blocks 212. In some embodiments, the source / drain barrier 132 and the source / drain body 134 of the plurality of second source / drain regions 130b may be exposed through the lower contact hole 232H. Subsequently, a conductive material may be filled into the lower contact hole 232H, and then, a plurality of lower contacts 232 may be formed by polishing the back surface. Thus, lower surfaces of the plurality of lower contacts 232 , lower surfaces of the plurality of gap-filling insulating layers 222 , lower surfaces of the plurality of insulating blocks 212 , and lower surfaces of the plurality of device isolation layers 114 may configure a first coplanar surface BSSB.

[0128] refer to FIG. 2A to FIG. 2D ,exist Fig.19A and Fig.19B Of the resulting material, an insulating material layer (not shown) may be formed on the first coplanar surface BSSB, and then, a metal power rail 254 and a lower insulating layer 252 may be formed by filling a conductive material into a hole pattern (not shown) formed by removing a portion of the insulating material layer.

[0129] In the above, reference has been made to FIG. 6A to FIG. 19B Describes the manufacturing Figure 1 as well as FIG. 2A to FIG. 2D The method of the integrated circuit device 100 shown in the figure is described in detail, but it can be seen by a person skilled in the art that various modifications and changes can be made within the scope of the present invention. FIG. 3A to FIG. 5B The integrated circuit device shown, and the integrated circuit devices with various structures implemented by modifying and changing the integrated circuit device.

[0130] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: A plurality of device isolation layers extending longitudinally in a first horizontal direction, wherein the plurality of device isolation layers are arranged separately from each other in a second horizontal direction, wherein the second horizontal direction is perpendicular to the first horizontal direction; a plurality of gap-filling insulating layers, arranged separately from each other along the first horizontal direction between adjacent device isolation layers among the plurality of device isolation layers; a plurality of gate structures, arranged apart from each other in the first horizontal direction, the plurality of gate structures being on the plurality of gap-filling insulating layers and extending longitudinally in the second horizontal direction; A first source / drain region and a second source / drain region are respectively arranged at two sides of a first gate structure among the plurality of gate structures with respect to the first horizontal direction; an insulating block, below the first source / drain region; an insulating barrier, between the first source / drain region and the insulating block, the insulating barrier covering a lower surface of the first source / drain region; as well as A lower contact portion is separated from the insulating block in the first horizontal direction, a first gap-filling insulating layer among the plurality of gap-filling insulating layers is between the lower contact portion and the insulating block, the lower contact portion contacts the lower surface of the second source / drain region, and the lower contact portion is below the second source / drain region.

2. The integrated circuit device according to claim 1, wherein: The first source / drain region is separated from the first gap-filling insulating layer, and the insulating barrier is between the first source / drain region and the first gap-filling insulating layer.

3. The integrated circuit device according to claim 1, wherein: One sidewall of the insulating barrier in the first horizontal direction includes a portion contacting the first gate structure.

4. The integrated circuit device according to claim 1, wherein: At the same vertical height, the width of the insulating block in the first horizontal direction is equal to the width of the lower contact portion in the first horizontal direction.

5. The integrated circuit device according to claim 1, wherein: The first gap-filling insulating layer completely covers a lower surface of the first gate structure.

6. The integrated circuit device according to claim 1, further comprising: a nanosheet structure separated from an upper surface of the first gap-filling insulating layer in a vertical direction and facing the upper surface of the first gap-filling insulating layer, wherein: The first gate structure surrounds the nanosheet structure on the first gap-filling insulating layer, and The nanosheet structure includes one nanosheet, or a plurality of nanosheets spaced apart from each other in the vertical direction.

7. The integrated circuit device according to claim 6, wherein: The first source / drain region includes a source / drain blocking member and a source / drain body, The source / drain blocking member covers a side surface of the nanosheet structure and a portion of a side surface of the first gate structure. The source / drain body faces the first gate structure in the first horizontal direction, the source / drain blocking member is between the source / drain body and the first gate structure, and A lower surface of the source / drain body contacts the insulating barrier.

8. The integrated circuit device according to claim 1, wherein: A lower surface of the device isolation layer, lower surfaces of the plurality of gap-filling insulating layers, a lower surface of the insulating block, and a lower surface of the lower contact provide a first coplanar surface.

9. The integrated circuit device according to claim 8, further comprising: a back power rail on the first coplanar surface, wherein The back power rail contacts the lower contact.

10. The integrated circuit device according to claim 1, wherein: A vertical height of an upper surface of the insulating barrier is equal to a vertical height of an upper surface of the lower contact portion.

11. An integrated circuit device comprising: a plurality of device isolation layers, separated from each other in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction, the plurality of device isolation layers defining sidewalls of a backside trench, the backside trench extending longitudinally along the first horizontal direction between adjacent device isolation layers among the plurality of device isolation layers; a plurality of gap-filling insulating layers, arranged in the backside trench and spaced apart from each other in the first horizontal direction; a plurality of insulating barriers, in the backside trench and respectively disposed between adjacent gap-filling insulating layers among the plurality of gap-filling insulating layers; a first source / drain region on a first insulating barrier among the plurality of insulating barriers; a second source / drain region on a second insulating barrier among the plurality of insulating barriers; a gate structure between the first source / drain region and the second source / drain region, the gate structure being on a first gap-filling insulating layer among the plurality of gap-filling insulating layers; A first insulating block facing a lower surface of the first source / drain region in a vertical direction, wherein the first insulating barrier is between the first insulating block and the lower surface of the first source / drain region; as well as A lower contact is separated from the first insulating block in the first horizontal direction, the first gap-filling insulating layer is between the lower contact and the first insulating block, the lower contact passes through the second insulating barrier and contacts the second source / drain region.

12. The integrated circuit device according to claim 11, further comprising: a second insulating block facing the lower surface of the second source / drain region in the vertical direction, the second insulating barrier being between the second insulating block and the lower surface of the second source / drain region, The lower contact portion passes through the second insulating block and the second insulating barrier and contacts the second source / drain region.

13. The integrated circuit device according to claim 11, wherein: A first portion of the lower contact is in the backside trench and faces the first gap-filling insulating layer in the first horizontal direction, The first portion of the lower contact portion contacts a lower surface of the second insulating barrier, a second portion of the lower contact protrudes from an upper surface of the first portion in the vertical direction and passes through the second insulating barrier, and The second portion of the lower contact contacts the second source / drain region.

14. The integrated circuit device according to claim 11, further comprising: an insulating liner between the lower contact portion and the first gap-filling insulating layer, wherein: The first portion of the lower contact faces the first gap-filling insulating layer in the first horizontal direction, and the insulating liner is between the first portion of the lower contact and the first gap-filling insulating layer. The first portion of the lower contact is in the backside trench, The second portion of the lower contact portion extends from the first portion in the vertical direction, and The second portion of the lower contact passes through the second insulating barrier and contacts the second source / drain region.

15. The integrated circuit device according to claim 11, wherein: The lower surface of the gate structure is at a first vertical height, An upper surface of at least one of the plurality of insulating barriers is at a second vertical height, and The second vertical height is higher than the first vertical height.

16. The integrated circuit device according to claim 11, wherein: A material of the first insulating block is different from a material of the plurality of gap-filling insulating layers.

17. An integrated circuit device comprising: A plurality of device isolation layers extending longitudinally in a first horizontal direction, wherein the plurality of device isolation layers are arranged separately from each other in a second horizontal direction, wherein the second horizontal direction is perpendicular to the first horizontal direction; a plurality of gap-filling insulating layers, arranged separately from each other along the first horizontal direction between adjacent device isolation layers among the plurality of device isolation layers; a nanosheet structure located vertically apart from an upper surface of a first gap-filling insulating layer among the plurality of gap-filling insulating layers and facing the upper surface of the first gap-filling insulating layer, the nanosheet structure comprising one nanosheet or a plurality of nanosheets spaced apart from each other in the vertical direction; a gate structure, on the first gap-filling insulating layer, the gate structure extending longitudinally in the second horizontal direction and surrounding the nanosheet structure; A first source / drain region and a second source / drain region are respectively arranged at two sides of the gate structure in the first horizontal direction; an insulating block, below the first source / drain region; an insulating barrier, between the first source / drain region and the insulating block along the vertical direction, wherein the vertical height of the upper surface of the insulating barrier is higher than the lower surface of the gate structure; as well as A lower contact portion is separated from the insulating block in the first horizontal direction, the first gap-filling insulating layer is between the lower contact portion and the insulating block, and the lower contact portion is below the second source / drain region.

18. The integrated circuit device according to claim 17, wherein: An upper surface of the insulation barrier is at the same vertical height as an upper surface of the lower contact.

19. The integrated circuit device according to claim 17, wherein: The first source / drain region includes a source / drain blocking member and a source / drain body, The source / drain blocking member covers a side surface of the nanosheet structure and a portion of a side surface of the gate structure. The source / drain body faces the gate structure in the first horizontal direction, the source / drain blocking member is between the source / drain body and the gate structure, and The source / drain body contacts an upper surface of the insulating barrier.

20. The integrated circuit device according to claim 17, wherein: A material of the insulating block is different from a material of the plurality of gap-filling insulating layers.

Images