Preparation method of solar cell and solar cell

Abstract

The invention provides a preparation method of a solar cell and the solar cell. The preparation method of the solar cell comprises the following steps: sequentially forming a first tunneling layer, a first doped silicon layer, a second tunneling layer and a second doped silicon layer on a silicon substrate; forming a patterned mask, wherein the patterned mask exposes at least part of the second doped silicon layer; the exposed second doped silicon layer is etched by using an etching solution to form a pyramid structure, the second tunneling layer plays a role of etching the barrier layer, and the height of at least part of the pyramid structure is equal to the thickness of the second doped silicon layer; and printing paste on the pyramid structure, and sintering the paste to form an electrode. The second tunneling layer is used as the barrier layer, and the height of the pyramid structure is controlled by controlling the thickness of the second doped silicon layer, so that the contact resistance is reduced. In addition, in the process of forming the second doped silicon layer, the intrinsic silicon layer plays a role of a buffer layer, so that doping elements can be prevented from expanding and penetrating through the second tunneling layer or can be prevented from expanding and penetrating through the second tunneling layer.

Description

Technical Field

[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] Improving the contact performance between the slurry and the doped silicon layer can reduce the contact resistance and improve the photoelectric conversion efficiency of the battery. In addition, in the process of preparing the doped polysilicon layer, avoiding the diffusion of doping elements can improve the passivation effect and further reduce the contact resistance. Therefore, how to improve the contact performance of the slurry and avoid the diffusion of doping elements is one of the important research directions in this field. Summary of the invention

[0003] The technical problem to be solved by the present application is to provide a method for preparing a solar cell and a solar cell, wherein the method for preparing a solar cell and the solar cell can improve the contact performance of the slurry and avoid diffusion of doping elements, thereby improving the photoelectric conversion efficiency.

[0004] To solve the above technical problems, the present application provides a method for preparing a solar cell, comprising: sequentially forming a first tunneling layer, a first doped silicon layer, a second tunneling layer and a second doped silicon layer on a silicon substrate; forming a patterned mask, wherein the patterned mask exposes at least a portion of the second doped silicon layer; etching the exposed second doped silicon layer using an etching solution to form a pyramid structure, wherein the second tunneling layer acts as an etching barrier layer, and the height of at least a portion of the pyramid structure is equal to the thickness of the second doped silicon layer; and printing a slurry on the pyramid structure, and sintering the slurry to form an electrode.

[0005] In an embodiment of the present application, the first doped silicon layer is doped polysilicon, and / or the second doped silicon layer is doped polysilicon, wherein the thickness of the second doped silicon layer is 60 nm to 100 nm.

[0006] In one embodiment of the present application, the height of the pyramid structure is 60nm-100nm.

[0007] In an embodiment of the present application, a method for forming the second doped silicon layer includes: forming an intrinsic silicon layer on the second tunneling layer; and forming the second doped silicon layer on the intrinsic silicon layer.

[0008] In one embodiment of the present application, the method for forming the patterned mask includes: forming phosphorus-doped silicon oxide on the second doped silicon layer; using a laser to remove a portion of the phosphorus-doped silicon oxide to expose at least a portion of the second doped silicon layer to form the patterned mask.

[0009] In one embodiment of the present application, the phosphorus-doped silicon oxide is used as a mask, and an alkaline solution is used to etch the second doped silicon layer exposed by the phosphorus-doped silicon oxide to form the pyramid structure.

[0010] On the other hand, the present application also proposes a solar cell, comprising: a silicon substrate; a first tunneling layer, a first doped silicon layer, a second tunneling layer, and a second doped silicon layer, which are stacked on the silicon substrate; at least a portion of the second doped silicon layer has a pyramid structure, and the height of at least a portion of the pyramid structure is equal to the thickness of the second doped silicon layer; and an electrode, which is in contact with the pyramid structure.

[0011] In an embodiment of the present application, the first doped silicon layer is doped polysilicon, and / or the second doped silicon layer is doped polysilicon, wherein the thickness of the second doped silicon layer is 60 nm to 100 nm.

[0012] In one embodiment of the present application, the height of the pyramid structure is 60nm-100nm.

[0013] In an embodiment of the present application, the doping concentration of the second doped silicon layer is greater than the doping concentration of the first doped silicon layer.

[0014] In an embodiment of the present application, the second tunneling layer covers a local area of ​​the first doped silicon layer, and the second doped silicon layer is located on the second tunneling layer.

[0015] Compared with the prior art, this application has the following advantages:

[0016] (1) By combining the use of the second tunneling layer as a barrier layer and controlling the thickness of the second doped silicon layer, the height of at least part of the pyramid structure is controlled to be equal to the thickness of the second doped silicon layer. In this way, the pyramid structure can provide more contacts for slurry sintering, thereby forming more silver-silicon alloys, which is beneficial to reducing contact resistance.

[0017] (2) In the process of forming the second doped silicon layer, the intrinsic silicon layer acts as a buffer layer, which can prevent or reduce the diffusion of doped elements through the second tunneling layer, thereby ensuring or improving the integrity of the second tunneling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings:

[0019] Figure 1 is a schematic flow chart of a method for preparing a solar cell in one embodiment of the present application;

[0020] Figures 2 to 5It is a cross-sectional schematic diagram of an intermediate product in the process of preparing a solar cell in one embodiment of the present application.

[0021] Reference numerals

[0022] Silicon substrate 210 Pyramid structure 270

[0023] First tunneling layer 220 First electrode 280

[0024] The first doped silicon layer 230 and the third doped silicon layer 290

[0025] The second tunneling layer 240 and the first passivation layer 310

[0026] Second doped silicon layer 250 Second electrode 320

[0027] Patterned mask 260 Second passivation layer 330 DETAILED DESCRIPTION

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0029] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0030] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0031] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0032] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0033] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0034] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0035] Next, the preparation method of the solar cell and the solar cell of the present application are described through examples.

[0036] refer to Figure 1 The schematic diagram of the process of a method for preparing a solar cell in an embodiment is shown. The method of this embodiment includes the following steps S110 to S140.

[0037] Step S110: sequentially forming a first tunneling layer, a first doped silicon layer, a second tunneling layer, and a second doped silicon layer on a silicon substrate;

[0038] Step S120: forming a patterned mask, wherein the patterned mask exposes at least a portion of the second doped silicon layer;

[0039] Step S130: etching the exposed second doped silicon layer using an etching solution to form a pyramid structure, wherein the second tunneling layer acts as an etching barrier layer, and the height of at least part of the pyramid structure is equal to the thickness of the second doped silicon layer;

[0040] Step S140: printing slurry on the pyramid structure, and sintering the slurry to form an electrode.

[0041] Next, steps S110 to S140 are described in detail.

[0042] refer to Figure 2As shown, in step S110, a first tunneling layer 220, a first doped silicon layer 230, a second tunneling layer 240, and a second doped silicon layer 250 are sequentially formed on the back side of the silicon substrate 210, the second tunneling layer 240 covers a local area of ​​the first doped silicon layer 230, and the second doped silicon layer 250 is formed on the second tunneling layer 240. The first tunneling layer 220 and the second tunneling layer 240 may be silicon oxide, and the thickness may be 1nm to 2nm, for example, the thickness is 1nm, 1.5nm or 2nm. The first doped silicon layer 230 and / or the second doped silicon layer 250 may be an N-type or P-type doped polysilicon layer, and the doping type of the first doped silicon layer 230 may be the same as the doping type of the second doped silicon layer 250.

[0043] In one embodiment, the method for forming the second doped silicon layer 250 includes the following steps 1 and 2:

[0044] Step 1: First, an intrinsic silicon layer is formed on the second tunneling layer. The thickness of the intrinsic silicon layer may be 10 nm to 20 nm, for example, 10 nm, 15 nm or 20 nm. The intrinsic silicon layer may cover a partial area of ​​the second tunneling layer.

[0045] Step 2: Form a second doped silicon layer on the intrinsic silicon layer. In the process of forming the second doped silicon layer, the intrinsic silicon layer acts as a buffer layer, which can avoid or reduce the diffusion of doped elements through the second tunneling layer, thereby ensuring or improving the integrity of the second tunneling layer. In short, the intrinsic silicon layer can block doped elements (such as phosphorus atoms) from diffusing through the second tunneling oxygen. In addition, the doping concentration of the second doped silicon layer can be increased because increasing the doping concentration will not cause the doped elements to diffuse through the second tunneling layer. The phosphorus doping concentration of the second doped silicon layer can reach 1E+21cm -3 The field passivation improvement brought by high doping concentration can increase the opening voltage of solar cells by 0.5mV to 1mV.

[0046] refer to Figure 2 and Figure 3 As shown, in step S120, a patterned mask 260 is formed, and the patterned mask 260 exposes the second doped silicon layer 250. Figure 3 In the embodiment, the patterned mask 260 exposes the entire second doped silicon layer 250 and covers the surface of the first doped silicon layer 230 away from the silicon substrate 210. In some other embodiments, the patterned mask 260 may expose a portion of the second doped silicon layer 250 and cover a portion of the surface of the second doped silicon layer 250 away from the silicon substrate 210.

[0047] In one embodiment, the method for forming the patterned mask 260 includes the following steps 3 and 4:

[0048] Step 3: forming phosphorus-doped silicon oxide on the second doped silicon layer 250;

[0049] Step 4: Use laser to remove part of the phosphorus-doped silicon oxide to expose at least part of the second doped silicon layer to form a patterned mask 260 .

[0050] refer to Figure 3 and Figure 4 As shown, in step S130, the exposed second doped silicon layer 250 is etched with an etching solution to form a pyramid structure 270, and the second tunneling layer 240 acts as an etching barrier layer, and the height of at least part of the pyramid structure 270 is equal to the thickness of the second doped silicon layer 250. Specifically, the exposed second doped silicon layer 250 is etched with an etching solution using the patterned mask 260 as a protective layer, and the second tunneling layer 240 located below the second doped silicon layer 250 does not react with the etching solution, so it can serve as an etching barrier layer to prevent the etching solution from continuing to etch. In the process of etching the second doped silicon layer 250, at least part of the second doped silicon layer 250 is etched to a depth equal to the thickness of the second doped silicon layer 250, and the second tunneling layer 240 blocks the etching solution from continuing to etch, so at least part of the pyramid structure 270 has a height equal to the thickness of the second doped silicon layer 250. In short, the above embodiment uses the second tunneling layer 240 as a barrier layer and controls the thickness of the second doped silicon layer 250 to control the height of at least part of the pyramid structure 270 to be equal to the thickness of the second doped silicon layer 250 .

[0051] In one embodiment, the process of etching the second doped silicon layer includes using the phosphorus-doped silicon oxide in the above embodiment as a mask and etching the second doped silicon layer exposed by the phosphorus-doped silicon oxide using an alkaline solution to form a pyramid structure.

[0052] In one embodiment, the thickness of the second doped silicon layer is 60nm to 100nm, for example, the thickness is 60nm, 70m, 80nm, 90nm or 100nm, and the height of the pyramid structure is 60nm to 100nm, for example, the height is 60nm, 70m, 80nm, 90nm or 100nm. The thickness of the second doped silicon layer limits the maximum height of the pyramid structure, so that a pyramid structure with a height much smaller than that of the prior art can be prepared.

[0053] refer to Figure 4 and Figure 5 As shown, in step S140, a paste is printed on the pyramid structure 270, and the paste is sintered to form a first electrode 280, which penetrates the second passivation layer 330 and contacts the pyramid structure. Since the height of the pyramid structure of the present application is relatively small, the pyramid structure can provide more contact points for the paste to be sintered, thereby forming more silver-silicon alloys, which is conducive to reducing the contact resistance. The contact resistance of the present application can reach 0.1Ω / cm 2, the fill factor (FF) can be increased by 0.3 to 0.5.

[0054] A detailed, specific and non-limiting example is given below to help better understand the above embodiment.

[0055] This example includes the following steps:

[0056] The first step: texturing the N-type silicon substrate;

[0057] Step 2: Use a tubular diffusion furnace to diffuse boron to form a PN junction;

[0058] Step 3: Remove the borosilicate glass (BSG) on the back and sides of the N-type silicon substrate, and then polish the back of the N-type silicon substrate;

[0059] Step 4: using plasma enhanced chemical deposition (PECVD) to sequentially deposit a first tunneling layer with a thickness of 1nm to 2nm, a lightly doped in-situ amorphous silicon with a thickness of 10nm to 20nm, a second tunneling layer with a thickness of 1nm to 2nm, a heavily doped in-situ amorphous silicon with a thickness of 60nm to 100nm, and a mask layer of phosphorus-doped silicon oxide with a thickness of 10nm to 20nm on the back side of the N-type silicon substrate;

[0060] Step 5: Using laser patterning to open the film, a portion of the mask layer formed in the fourth step is opened to form a patterned mask, and the opened film area is the metallization paste printing area;

[0061] Step 6: In a solution containing 1% to 1.5% KOH and 0.05% to 0.10% conventional texturing additive (ADD), at a temperature of 50±10°C and a time of 80s to 120s, a pyramid structure with a height of 60nm to 100nm is formed in the film-opening area, and the non-film-opening area is not changed due to the protection of the mask;

[0062] Step 7: Annealing in an annealing furnace to effectively dope phosphorus atoms, while introducing oxygen to oxidize the film-opening area to form phosphorus silicon glass (PSG);

[0063] Step 8: Remove the front PSG;

[0064] Step 9: Remove the doped polysilicon layer on the front side in the alkaline tank of the tank cleaning machine, then remove the BSG, BPSG and PSG on the front, side and back sides in the acid tank, and then perform standard RCA cleaning;

[0065] Step 10: Deposit Al2O3 with a thickness of 6±2nm on the front and back sides using an atomic layer deposition process (ALD);

[0066] Step 11: forming silicon nitride on the front and back surfaces;

[0067] Step 12: Prepare electrodes through screen printing and sintering processes. Specifically, screen printing prints the slurry on the silicon nitride located on the pyramid structure. After sintering, the slurry burns through the silicon nitride and aluminum oxide to form an electrode in contact with the pyramid structure.

[0068] On the other hand, the present application also proposes a solar cell, Figure 5 As shown, the solar cell in this embodiment includes a silicon substrate 210, a first tunneling layer 220, a first doped silicon layer 230, a second tunneling layer 240 and a second doped silicon layer 250 stacked on the silicon substrate 210, at least a portion of the second doped silicon layer 250 has a pyramid structure 270, the height of at least a portion of the pyramid structure 270 is equal to the thickness of the second doped silicon layer 250, and the solar cell also includes a first electrode 280 in contact with the pyramid structure 270.

[0069] In one embodiment, the first doped silicon layer 230 is doped polysilicon, and / or the second doped silicon layer 250 is doped polysilicon, and the thickness of the second doped silicon layer 250 is 60nm-100nm, for example, the thickness is 60nm, 70m, 80nm, 90nm or 100nm. The height of the pyramid structure can be 60nm-100nm, for example, the height is 60nm, 70m, 80nm, 90nm or 100nm.

[0070] In one embodiment, the doping concentration of the second doped silicon layer 250 is greater than the doping concentration of the first doped silicon layer 230 .

[0071] exist Figure 5 In some embodiments, the second tunneling layer 240 covers a local area of ​​the first doped silicon layer 230, and the second doped silicon layer 250 is located on the second tunneling layer 240. In other embodiments, the second tunneling layer 240 may cover the entire surface of the first doped silicon layer 230 away from the silicon substrate 210.

[0072] refer to Figure 5 As shown, the solar cell further includes a third doped silicon layer 290, a first passivation layer 310, and a second electrode 320. The third doped silicon layer 290 and the first passivation layer 310 are stacked on the front side of the silicon substrate 210, and the second electrode 320 contacts the third doped silicon layer 290 through the first passivation layer 310. The third doped silicon layer 290 may be P-type doped silicon formed by boron diffusion.

[0073] The solar cell may further include a second passivation layer 330 disposed on the first doped silicon layer 230 and the pyramid structure 270. The first passivation layer 310 and the second passivation layer 330 may include aluminum oxide and silicon nitride.

[0074] For other descriptions about the solar cell of the present application, please refer to the relevant part of the above description of the preparation method, which will not be elaborated here.

[0075] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0076] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0077] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of this application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0078] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0079] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: include: forming a first tunneling layer, a first doped silicon layer, a second tunneling layer and a second doped silicon layer in sequence on a silicon substrate; forming a patterned mask, wherein the patterned mask exposes at least a portion of the second doped silicon layer; Etching the exposed second doped silicon layer using an etching solution to form a pyramid structure, wherein the second tunneling layer acts as an etching barrier layer, and the height of at least part of the pyramid structure is equal to the thickness of the second doped silicon layer; and A paste is printed on the pyramid structure and the paste is sintered to form an electrode.

2. The method for preparing a solar cell according to claim 1, characterized in that: The first doped silicon layer is doped polysilicon, and / or the second doped silicon layer is doped polysilicon, wherein the thickness of the second doped silicon layer is 60 nm to 100 nm.

3. The method for preparing a solar cell according to claim 2, characterized in that: The height of the pyramid structure is 60nm-100nm.

4. The method for preparing a solar cell according to claim 1, wherein: The method of forming the second doped silicon layer includes: forming an intrinsic silicon layer on the second tunneling layer; The second doped silicon layer is formed on the intrinsic silicon layer.

5. The method for preparing a solar cell according to claim 1, wherein: The method of forming the patterned mask comprises: forming phosphorus-doped silicon oxide on the second doped silicon layer; A portion of the phosphorus-doped silicon oxide is removed by using a laser to expose at least a portion of the second doped silicon layer to form the patterned mask.

6. The method for preparing a solar cell according to claim 5, characterized in that: The phosphorus-doped silicon oxide is used as a mask, and an alkaline solution is used to etch the second doped silicon layer exposed by the phosphorus-doped silicon oxide to form the pyramid structure.

7. A solar cell, characterized in that: include: Silicon substrate; A first tunneling layer, a first doped silicon layer, a second tunneling layer, and a second doped silicon layer are stacked on the silicon substrate; At least a portion of the second doped silicon layer has a pyramid structure, and a height of at least a portion of the pyramid structure is equal to a thickness of the second doped silicon layer; as well as An electrode is in contact with the pyramid structure.

8. The solar cell according to claim 7, wherein: The first doped silicon layer is doped polysilicon, and / or the second doped silicon layer is doped polysilicon, wherein the thickness of the second doped silicon layer is 60 nm to 100 nm.

9. The solar cell according to claim 8, characterized in that The height of the pyramid structure is 60nm-100nm.

10. The solar cell according to claim 7, wherein: The doping concentration of the second doped silicon layer is greater than the doping concentration of the first doped silicon layer.

11. The solar cell according to claim 7, wherein: The second tunneling layer covers a local area of ​​the first doped silicon layer, and the second doped silicon layer is located on the second tunneling layer.

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