Preparation process of poly laminated double-passivation structure of TOPCon battery and TOPCon battery

Abstract

The invention discloses a preparation process of a poly laminated double-passivation structure of a TOPCon battery and the TOPCon battery, and belongs to the technical field of solar cells, the preparation process of the poly laminated double-passivation structure of the TOPCon battery comprises the following steps: S1, a pretreatment process; s2, preparation of a laminated double-passivation structure: feeding the silicon wafer subjected to the pretreatment process into a furnace tube of a PECVD (Plasma Enhanced Chemical Vapor Deposition) machine, preparing a tunneling oxide layer on the back of the silicon wafer, and preparing the laminated double-passivation structure on the tunneling oxide layer, the laminated double-passivation structure sequentially comprising a buffer layer, a barrier layer and an N-type amorphous silicon layer; the buffer layer is an intrinsic amorphous silicon layer, and the barrier layer is a tunneling oxidation barrier layer. According to the poly laminated double-passivation structure, the controllability of phosphorus doping distribution can be improved, the doping uniformity is further improved, the contact performance can be improved through high phosphorus doping concentration, meanwhile, the N / N high-low junction phenomenon caused by too high phosphorus doping concentration is avoided, the passivation contact performance of a battery piece is improved, and high battery conversion efficiency is obtained.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a poly stacked double-passivation structure preparation process of a TOPCon cell and a TOPCon cell. Background Art

[0002] At present, the core of the existing TOPCon battery adopts the passivation contact technology of tunneling silicon oxide layer + doped polysilicon layer, hereinafter referred to as passivation contact technology. There are two process routes for the preparation of TOPCon batteries, LP and PE routes. The PE route uses PECVD equipment to deposit a tunneling oxide layer on the silicon substrate and then deposit doped amorphous silicon before annealing. This process route is prone to phosphorus diffusion into the silicon substrate when phosphorus doping is high, and the concentration of activated phosphorus is low. The internal expansion of phosphorus increases carrier recombination, affecting the conversion efficiency of the battery. When phosphorus doping is insufficient, the film explosion problem is prone to affect the passivation contact performance on the back, which also affects the conversion efficiency.

[0003] Therefore, in view of the above technical problems, it is necessary to provide a poly stacked double passivation structure preparation process of a TOPCon battery and a TOPCon battery.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to overcome the problem of insufficient passivation stability in the above-mentioned prior art and to provide a process scheme with a dense film layer and no film explosion, so as to improve the battery start-up voltage and conversion efficiency.

[0006] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0007] A poly stacked double passivation structure preparation process for a TOPCon battery comprises the following steps:

[0008] S1, pre-treatment process;

[0009] S2, preparation of a laminated double passivation structure: sending the silicon wafer after the pre-treatment process into the furnace tube of the PECVD machine, preparing a tunneling oxide layer on the back of the silicon wafer, and then preparing a laminated double passivation structure on the tunneling oxide layer, wherein the laminated double passivation structure includes a buffer layer, a barrier layer and an N-type amorphous silicon layer in sequence;

[0010] The buffer layer is an intrinsic amorphous silicon layer, and the barrier layer is a tunneling oxidation barrier layer;

[0011] S3, mask preparation: preparing a mask layer on the stacked double passivation structure;

[0012] S4, annealing treatment: annealing at a high temperature to transform the intrinsic amorphous silicon layer into a polycrystalline silicon layer, while activating the doped phosphorus and promoting the diffusion of phosphorus;

[0013] S5, post-processing process.

[0014] In one or more embodiments of the present invention, in S2, the specific steps of sequentially preparing a tunneling oxide layer, a buffer layer, a barrier layer and an N-type amorphous silicon layer on the back of the silicon wafer are:

[0015] S2.1, introduce laughing gas (N2O) into the furnace tube, and utilize its oxidizing property to oxidize the back surface of the silicon wafer to form a tunneling oxide layer;

[0016] S2.2, using nitrogen to purge the furnace tube, and then introducing silane (SiH4) and hydrogen (H2) to react and deposit an undoped intrinsic amorphous silicon layer, i.e., a buffer layer, on the tunnel oxide layer;

[0017] S2.3, purge the furnace tube with nitrogen again, and then introduce laughing gas (NO2) to oxidize the intrinsic amorphous silicon layer to form a tunneling oxide barrier layer;

[0018] S2.4. Continue to use nitrogen to purge the furnace tube, then introduce silane (SiH4), hydrogen (H2) and phosphine (PH3) to decompose them in a plasma atmosphere, and deposit a phosphorus-doped N-type amorphous silicon layer on the tunneling oxide barrier layer.

[0019] In one or more embodiments of the present invention, in S2, the thickness of the tunneling oxidation barrier layer is adjusted and matched according to the doping amount of phosphorus in the N-type amorphous silicon layer.

[0020] In one or more embodiments of the present invention, in S1, the pre-treatment steps include cleaning and texturing, diffusion bonding and back-side alkali polishing in sequence.

[0021] In one or more embodiments of the present invention, in S3, the specific steps of preparing a mask layer on the stacked double passivation structure are:

[0022] After the stacked double passivation structure is obtained, nitrogen is used to purge the furnace tube, and silane (SiH4) and laughing gas (N2O) are introduced to form a mask layer on the stacked double passivation structure.

[0023] In one or more embodiments of the present invention, in S4, the annealing time and temperature are matched with the doping amount of phosphorus and the thickness of the barrier layer and the buffer layer.

[0024] In one or more embodiments of the present invention, in S5, the post-processing steps include PSG removal, RCA, ALD, coating, screen printing and testing and sorting in sequence.

[0025] In one or more embodiments of the present invention, a TOPCon battery includes a silicon substrate, a tunneling oxide layer is provided on the back surface of the silicon substrate, a stacked double passivation structure is provided on the tunneling oxide layer, a passivation film is provided on the stacked double passivation structure, and a silver electrode is provided on the passivation film.

[0026] In one or more embodiments of the present invention, the stacked double passivation structure includes an intrinsic amorphous silicon buffer layer, a tunneling oxidation barrier layer and an N-type amorphous silicon layer, and the intrinsic amorphous silicon buffer layer, the tunneling oxidation barrier layer and the N-type amorphous silicon layer are arranged in sequence along the back surface direction away from the silicon substrate.

[0027] In one or more embodiments of the present invention, the thickness of the tunneling oxidation barrier layer is smaller than the thickness of the tunneling oxide layer.

[0028] Compared with the prior art, the present invention adds two oxide layers, wherein the second tunnel oxide layer, due to its compactness, can block phosphorus atoms by utilizing the tunnel effect without affecting carrier transmission, and to a certain extent block the inward expansion of phosphorus in the subsequent high-temperature process, making its doping more uniform;

[0029] At the same time, compared with the prior art, the structure adds an intrinsic amorphous silicon layer, which plays a buffering role on the advancement of phosphorus, slowing down the rate of phosphorus advancement. The thickness of the film layer can improve the controllability of the overall phosphorus doping distribution on the back side, avoiding the problem of over-doping.

[0030] Under this stacked double passivation structure, the overall phosphorus doping concentration can be increased, which improves the contact and avoids the strong inward diffusion of phosphorus when the high doping concentration is promoted at high temperature, thereby avoiding the N / N high-low junction caused by the accumulation of phosphorus in the silicon body near the crystalline silicon surface;

[0031] In summary, the poly stacked double passivation structure can improve the controllability of phosphorus doping distribution, thereby improving the uniformity of doping, and can use high phosphorus doping concentration to improve contact performance while avoiding the N / N high-low junction phenomenon caused by excessive phosphorus doping concentration, thereby improving the passivation contact performance of the battery cell and obtaining a higher battery conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 This is a process flow chart of a poly stacked double passivation structure preparation process of a TOPCon battery in one embodiment of the present invention;

[0034] Figure 2 Schematic diagram of the structure of a TOPCon battery in one embodiment of the present invention.

[0035] Description of main reference numerals:

[0036] 1. Silicon substrate; 2. Tunneling oxide layer; 3. Intrinsic amorphous silicon buffer layer; 4. Tunneling oxide barrier layer; 5. N-type amorphous silicon layer; 6. Passivation film; 7. Silver electrode. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0038] like Figure 1 As shown, a poly stacked double passivation structure preparation process of a TOPCon battery in one embodiment of the present invention includes the following steps:

[0039] S1, pre-treatment process: cleaning and texturing, diffusion and bonding, and back-side alkaline polishing of the silicon wafer in sequence;

[0040] S2, preparation of a laminated double passivation structure: sending the silicon wafer after the pre-treatment process into the furnace tube of the PECVD machine, preparing a tunneling oxide layer on the back of the silicon wafer, and then preparing a laminated double passivation structure on the tunneling oxide layer, wherein the laminated double passivation structure includes a buffer layer, a barrier layer and an N-type amorphous silicon layer in sequence;

[0041] Wherein, the buffer layer is an intrinsic amorphous silicon layer, and the barrier layer is a tunneling oxidation barrier layer;

[0042] S3, mask preparation: preparing a mask layer on the stacked double passivation structure;

[0043] S4, annealing treatment: annealing at a high temperature to transform the intrinsic amorphous silicon layer into a polycrystalline silicon layer, while activating the doped phosphorus and promoting the diffusion of phosphorus;

[0044] S5, post-processing process: carry out PSG removal, RCA, ALD, coating, screen printing and testing sorting processes in sequence.

[0045] In S2, the specific steps of sequentially preparing a tunnel oxide layer, a buffer layer, a barrier layer and an N-type amorphous silicon layer on the back of the silicon wafer are:

[0046] S2.1, introduce laughing gas (N2O) into the furnace tube, and utilize its oxidizing property to oxidize the back surface of the silicon wafer to form a tunneling oxide layer;

[0047] Specifically, the reaction temperature was set at 445°C and the reaction pressure was set at 1940 bar. The nitrous oxide was pre-flowed for 30 seconds to place the furnace tube in a nitrous oxide atmosphere with a flow rate of 1000 sccm. The gas was continuously introduced, and the pulsed glow discharge was performed at a power of 15000 W. The reaction time was 97 seconds, and a tunneling oxide layer of about 2 nm thick was generated.

[0048] S2.2, purge the furnace tube with nitrogen, and then introduce silane (SiH4) and hydrogen (H2) to react and deposit an undoped intrinsic amorphous silicon layer, i.e., a buffer layer, on the tunnel oxide layer;

[0049] Specifically, at a reaction temperature of 425°C and a reaction pressure of 3000 bar, silane and hydrogen were introduced for 30 seconds to place the furnace tube in a silane and hydrogen atmosphere, wherein the silane flow rate was 2700 sccm and the hydrogen flow rate was 8100 sccm. The gas was continuously introduced to perform glow discharge, with a power of 12000 W and a reaction time of 60 seconds, to deposit an intrinsic amorphous silicon layer.

[0050] S2.3, purge the furnace tube with nitrogen again, and then introduce laughing gas (NO2) to oxidize the intrinsic amorphous silicon layer to form a tunneling oxide barrier layer;

[0051] Specifically, the reaction temperature was set at 445°C and the reaction pressure was set at 1940 bar. The nitrous oxide was pre-flowed for 30 seconds to place the furnace tube in a nitrous oxide atmosphere with a flow rate of 1000 sccm. The gas was continuously introduced, and the pulsed glow discharge was performed at a power of 15000 W and a reaction time of 50 seconds to generate a tunneling oxide layer of about 1 nm thick.

[0052] S2.4, continue to use nitrogen to purge the furnace tube, then introduce silane (SiH4), hydrogen (H2) and phosphine (PH3), decompose them in a plasma atmosphere, and deposit a phosphorus-doped N-type amorphous silicon layer on the tunneling oxide barrier layer;

[0053] Specifically, the reaction temperature was set at 425°C, the reaction pressure was set at 3100 bar, silane, hydrogen and phosphine were pre-flowed for 30 seconds, and the furnace tube was placed in a three-gas atmosphere, wherein the silane flow rate was 2700 sccm, the hydrogen flow rate was 8100 sccm, and the phosphine flow rate was 1050 sccm. The gas was continuously introduced, the pulsed glow discharge was performed, the power was 14700 W, the reaction time was 560 seconds, and a layer of N-type amorphous silicon layer was deposited.

[0054] In S2, the thickness of the tunneling oxide barrier layer is adjusted and matched according to the phosphorus doping amount in the N-type amorphous silicon layer. If the thickness is too thick or too thin, the barrier effect will be too strong, which will affect the distribution of back doping. In the case of mismatch, the square resistance will be too low or too high. The tunneling oxide barrier layer allows carriers to pass through the carrier quantum tunneling effect, and also blocks the outer phosphorus atoms from diffusing inward.

[0055] In S3, the specific steps of preparing a mask layer on the stacked double passivation structure are:

[0056] After obtaining the stacked double passivation structure, the furnace tube is purged with nitrogen, and silane (SiH4) and laughing gas (N2O) are introduced to form a mask layer on the stacked double passivation structure;

[0057] Specifically, the reaction temperature was set at 425°C and the reaction pressure was set at 3100 bar. Silane and nitrous oxide were pre-flowed to place the furnace tube in two gas atmospheres, with a silane flow rate of 2000 sccm and a nitrous oxide flow rate of 9800 sccm. Gas was continuously introduced to perform pulsed glow discharge at a power of 14700 W and a reaction time of 560 s to deposit a mask layer.

[0058] In S4, the annealing time is 1700-2700 seconds, and the maximum annealing temperature is between 900-920°C. The process needs to be matched according to the doping amount of the back surface and the thickness of the tunneling oxide barrier layer and the intrinsic amorphous silicon layer. Preferably, the annealing time is 1750 seconds and the temperature is 908°C.

[0059] like Figure 2 As shown, a TOPCon battery includes a silicon substrate 1, a tunneling oxide layer 2 is arranged on the back surface of the silicon substrate, a stacked double passivation structure is arranged on the tunneling oxide layer 2, and the stacked double passivation structure includes an intrinsic amorphous silicon buffer layer 3, a tunneling oxide barrier layer 4 and an N-type amorphous silicon layer 5. The intrinsic amorphous silicon buffer layer 3, the tunneling oxide barrier layer 4 and the N-type amorphous silicon layer 5 are arranged in sequence along the direction away from the back surface of the silicon substrate 1.

[0060] A passivation film 6 is disposed on the surface of the N-type amorphous silicon layer 5 away from the silicon substrate 1, and a silver electrode 7 is printed on the surface of the passivation film 6 away from the silicon substrate 1. The passivation film includes but is not limited to a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer.

[0061] Among them, the thickness of the tunneling oxide barrier layer 4 and the tunneling oxide layer 2 are both 1-2nm, and the thickness of the tunneling oxide barrier layer 4 is less than the thickness of the tunneling oxide layer 2. The tunneling oxide barrier layer 4 and the tunneling oxide layer 2 are essentially the same, but the two play different roles in the structure. The tunneling oxide layer 2 mainly uses the quantum tunneling effect to select carriers, and the tunneling oxide barrier layer 4 allows carriers to pass through the carrier quantum tunneling effect, and also blocks the outer phosphorus atoms from diffusing inward.

[0062] Compared with the prior art, the present invention adds two oxide layers, wherein the second tunnel oxide layer, due to its compactness, can block phosphorus atoms by utilizing the tunnel effect without affecting carrier transmission, and to a certain extent block the inward expansion of phosphorus in the subsequent high-temperature process, making its doping more uniform;

[0063] At the same time, compared with the prior art, the structure adds an intrinsic amorphous silicon layer, which plays a buffering role on the advancement of phosphorus, slowing down the rate of phosphorus advancement. The thickness of the film layer can improve the controllability of the overall phosphorus doping distribution on the back side, avoiding the problem of over-doping.

[0064] Under this stacked double passivation structure, the overall phosphorus doping concentration can be increased, which improves the contact and avoids the strong inward diffusion of phosphorus when the high doping concentration is promoted at high temperature, thereby avoiding the N / N high-low junction caused by the accumulation of phosphorus in the silicon body near the crystalline silicon surface;

[0065] In summary, the poly stacked double passivation structure can improve the controllability of phosphorus doping distribution, thereby improving the uniformity of doping, and can use high phosphorus doping concentration to improve contact performance while avoiding the N / N high-low junction phenomenon caused by excessive phosphorus doping concentration, thereby improving the passivation contact performance of the battery cell and obtaining a higher battery conversion efficiency.

[0066] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0067] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A poly stacked double passivation structure preparation process for a TOPCon battery, characterized in that: The following steps are involved: S1, pre-treatment process; S2, preparation of a laminated double passivation structure: sending the silicon wafer after the pre-treatment process into the furnace tube of the PECVD machine, preparing a tunneling oxide layer on the back of the silicon wafer, and then preparing a laminated double passivation structure on the tunneling oxide layer, wherein the laminated double passivation structure includes a buffer layer, a barrier layer and an N-type amorphous silicon layer in sequence; The buffer layer is an intrinsic amorphous silicon layer, and the barrier layer is a tunneling oxidation barrier layer; S3, mask preparation: preparing a mask layer on the stacked double passivation structure; S4, annealing treatment: annealing at a high temperature to transform the intrinsic amorphous silicon layer into a polycrystalline silicon layer, while activating the doped phosphorus and promoting the diffusion of phosphorus; S5, post-processing process.

2. The poly stacked double passivation structure preparation process of a TOPCon battery according to claim 1, characterized in that: In S2, the specific steps of sequentially preparing a tunneling oxide layer, a buffer layer, a barrier layer and an N-type amorphous silicon layer on the back of the silicon wafer are: S2.1, introduce laughing gas into the furnace tube, and utilize its oxidizing property to oxidize the back surface of the silicon wafer to form a tunneling oxide layer; S2.2, using nitrogen to purge the furnace tube, and then introducing silane and hydrogen to react and deposit an undoped intrinsic amorphous silicon layer, i.e., a buffer layer, on the tunnel oxide layer; S2.3, purge the furnace tube with nitrogen again, and then introduce nitrous oxide to oxidize the intrinsic amorphous silicon layer to form a tunneling oxide barrier layer; S2.

4. Continue to use nitrogen to purge the furnace tube, then introduce silane, hydrogen and phosphine to decompose them in a plasma atmosphere, and deposit a phosphorus-doped N-type amorphous silicon layer on the tunneling oxide barrier layer.

3. The poly stacked double passivation structure preparation process of a TOPCon battery according to claim 2, characterized in that: In S2, the thickness of the tunneling oxidation barrier layer is adjusted and matched according to the doping amount of phosphorus in the N-type amorphous silicon layer.

4. The poly stacked double passivation structure preparation process of a TOPCon battery according to claim 1, characterized in that: In S1, the pre-treatment steps include cleaning and texturing, diffusion bonding and back-side alkali polishing in sequence.

5. The poly stacked double passivation structure preparation process of a TOPCon battery according to claim 1, characterized in that: In S3, the specific steps of preparing a mask layer on the stacked double passivation structure are: After the stacked double-passivation structure is obtained, nitrogen is used to purge the furnace tube, and silane and laughing gas are introduced to form a mask layer on the stacked double-passivation structure.

6. The poly stacked double passivation structure preparation process of a TOPCon battery according to claim 1, characterized in that: In S4, the annealing time and temperature are matched with the doping amount of phosphorus and the thickness of the barrier layer and the buffer layer.

7. The poly stacked double passivation structure preparation process of a TOPCon battery according to claim 1, characterized in that: In S5, the post-processing steps include PSG removal, RCA, ALD, coating, screen printing and testing and sorting in sequence.

8. A TOPCon battery, prepared by the poly laminated double passivation structure preparation process of a TOPCon battery according to any one of claims 1 to 7, characterized in that: The invention comprises a silicon substrate, wherein a tunnel oxide layer is arranged on the back surface of the silicon substrate, a stacked double passivation structure is arranged on the tunnel oxide layer, a passivation film is arranged on the stacked double passivation structure, and a silver electrode is arranged on the passivation film.

9. A TOPCon battery according to claim 8, characterized in that: The stacked double passivation structure comprises an intrinsic amorphous silicon buffer layer, a tunneling oxidation barrier layer and an N-type amorphous silicon layer, which are arranged in sequence along a back surface direction away from a silicon substrate.

10. A TOPCon battery according to claim 9, characterized in that: The thickness of the tunneling oxide barrier layer is smaller than the thickness of the tunneling oxide layer.

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