Preparation method of back structure of heterojunction cell and heterojunction cell

Abstract

The invention relates to a preparation method of a back surface structure of a heterojunction cell and the heterojunction cell, and the method comprises the steps: providing a substrate, and enabling the back surface of the substrate to be at least provided with a transparent conductive oxide film; depositing a dielectric layer on the transparent conductive oxide film, and partially corroding the dielectric layer; and depositing a metal layer on the dielectric layer, so that the metal layer is in partial contact with the transparent conductive oxide film. According to the technology, the dielectric layer is precisely deposited and locally corroded on the transparent conductive oxide thin film, so that the metal layer is partially contacted with the transparent conductive oxide thin film. The design of the heterojunction back surface structure enables the metal layer to enhance the internal reflection of light, and meanwhile, the metal layer is used as a back surface electrode of the cell, so that carriers are effectively led out, and short-circuit current is enhanced. Therefore, the technology optimizes the management and utilization of the light in the battery, improves the photoelectric conversion efficiency of the battery, and improves the overall performance and economic benefits of the HJT battery.

Description

Technical Field

[0001] The present application relates to the field of solar energy, and specifically provides a method for preparing a back structure of a heterojunction cell and a heterojunction cell. Background Art

[0002] Heterojunction (HJT) solar cell technology has taken a leading position in the solar industry with its excellent efficiency and extremely high yield rate. However, the widespread application and large-scale mass production of HJT cells are still limited by high production costs. In order to reduce the cost of HJT cells, the industry is promoting thin-film technology. Although this technology can effectively reduce material costs, it also brings about an increase in incident light escape loss, resulting in a reduction in short-circuit current.

[0003] Therefore, how to improve the utilization rate of incident light in thin-layer HJT cells has become a key issue that needs to be solved in current technological development.

[0004] Accordingly, the art needs a new heterojunction battery preparation solution to solve the above problems. Summary of the invention

[0005] In order to overcome the above-mentioned defects, the present application is proposed to provide a solution or at least partially solve the technical problem of low utilization rate of incident light when heterojunction cells are made thinner and lighter.

[0006] In a first aspect, the present application provides a method for preparing a back structure of a heterojunction battery, comprising: providing a substrate, wherein the back side of the substrate is provided with at least a back transparent conductive oxide film, the front side of the substrate is closer to the light-facing side of the battery, and the back side of the substrate is closer to the backlight side of the battery; depositing a dielectric layer on the back transparent conductive oxide film, and partially corroding the dielectric layer; depositing a metal layer on the dielectric layer so that the metal layer is partially in contact with the back transparent conductive oxide film.

[0007] In a technical solution of the method for preparing the back structure of the above-mentioned heterojunction battery, the step of "depositing a dielectric layer on the transparent conductive oxide film on the back side and partially corroding the dielectric layer" includes: coating a selective corrosion mediating layer on the dielectric layer, wherein the selective corrosion mediating layer does not completely cover the dielectric layer, so that part of the dielectric layer is exposed; corroding the part of the dielectric layer in the exposed state using a first solution; and removing the selective corrosion mediating layer.

[0008] In a technical solution of the above-mentioned method for preparing the back structure of a heterojunction battery, coating the selective corrosion mediating layer on the dielectric layer includes: forming the selective corrosion mediating layer on the dielectric layer by spin coating.

[0009] In a technical solution of the method for preparing the rear structure of the heterojunction battery, there are multiple exposed dielectric layers, and the total area of ​​the multiple exposed dielectric layers accounts for 10%-20%.

[0010] In a technical solution of the method for preparing the rear structure of the heterojunction battery, the orthographic projection of the exposed portion of the dielectric layer on the substrate is located within the orthographic projection of the metal layer on the substrate.

[0011] In one technical solution of the method for preparing the rear structure of the heterojunction battery, the rotation rate during spin coating is 150-300 r / min, and the curing temperature is 110-150°C.

[0012] In a technical solution of the above-mentioned method for preparing the back structure of a heterojunction battery, the selective corrosion mediating layer is removed using a second solution, wherein the selective corrosion mediating layer is a HMDS layer and the second solution is an organic solvent.

[0013] In one technical solution of the method for preparing the rear structure of the heterojunction battery, 2-5 mL of a selective corrosion mediating medium is spin-coated on the dielectric layer to form the selective corrosion mediating layer.

[0014] In a technical solution of the above-mentioned method for preparing the back structure of a heterojunction battery, the material of the dielectric layer is silicon oxide, and the first solution is a NaOH solution.

[0015] In a technical solution of the preparation method of the back structure of the above-mentioned heterojunction battery, the thickness of the dielectric layer is 130-170nm, the concentration of the first solution is 10% to 40%, the etching time in the first solution is 30-60min, and the etching temperature is 40-80°C.

[0016] In one technical solution of the above-mentioned method for preparing the back structure of a heterojunction battery, the thickness of the metal layer is 200-400 nm.

[0017] In a second aspect, the present application provides a heterojunction battery, which includes a front electrode, a front transparent conductive oxide film, a substrate, a back transparent conductive oxide film and a back structure arranged in sequence, and the back structure includes: a dielectric layer and a metal layer, wherein there are holes in the dielectric layer, and the metal layer penetrates the holes to contact the back transparent conductive oxide film.

[0018] The above one or more technical solutions of this application have at least one or more of the following Beneficial effects:

[0019] In the technical solution for implementing the present application, a partial contact between the metal layer and the transparent conductive oxide film is achieved by precisely depositing and partially etching the dielectric layer on the transparent conductive oxide film. The design of the back structure of this heterojunction enables the metal layer to enhance the internal reflection of light, and at the same time, as the back electrode of the battery, it effectively extracts carriers and enhances the short-circuit current. Therefore, this technology optimizes the management and utilization of light in the battery, improves the photoelectric conversion efficiency of the battery, and enhances the overall performance and economic benefits of the HJT battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The disclosure of the present application will become more easily understood with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present application. In addition, similar numbers in the drawings are used to represent similar components, among which:

[0021] Figure 1 is a schematic diagram of a heterojunction battery structure according to an embodiment of the present application;

[0022] Figure 2 It is a schematic flow chart of the main steps of a method for preparing a rear surface structure of a heterojunction battery according to an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of a specific structure of a substrate according to an embodiment of the present application;

[0024] Figure 4 is a schematic diagram of a selectively corroding mediating layer according to an embodiment of the present application;

[0025] Figure 5 is a schematic diagram after removing the selective corrosion mediating layer according to an embodiment of the present application;

[0026] Figure 6 It is a schematic flow chart of the secondary steps of a method for preparing a rear structure of a heterojunction battery according to an embodiment of the present application;

[0027] List of reference numerals:

[0028] 1. Substrate; 2. Transparent conductive oxide film; 3. Dielectric layer; 4. Metal layer; 5. Front electrode; 6. Front transparent conductive oxide film; 11. N-type doped amorphous silicon layer; 12. First intrinsic amorphous silicon layer; 13. Base; 14. Second intrinsic amorphous silicon layer; 15. P-type doped amorphous silicon layer; 7. Selective etching mediator layer. DETAILED DESCRIPTION

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0030] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0031] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0032] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0033] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0034] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0035] Here we first explain some terms involved in this application.

[0036] Back transparent conductive oxide film 2: Transparent conductive oxide 2 is TCO film. Back transparent conductive oxide film 2 is a material with high electrical conductivity and good light transmittance, usually composed of tin oxide (SnO2), indium tin oxide (ITO) or zinc oxide (ZnO).

[0037] HJT cells: Solar cells using heterojunction technology combine the advantages of single crystal silicon and amorphous silicon. Through its unique "sandwich" structure (p-type amorphous silicon layer, n-type single crystal silicon substrate 13 and n-type amorphous silicon layer), it provides a higher photoelectric conversion efficiency than traditional crystalline silicon cells, and has a lower temperature coefficient and good low-light performance.

[0038] See attached Figure 2 , Figure 2 1 is a schematic flow chart of the main steps of a method for preparing a rear structure of a heterojunction battery according to an embodiment of the present application. Figure 2 As shown, the method for preparing the rear structure of a heterojunction battery in the embodiment of the present application mainly includes the following steps S10 to S40.

[0039] Step S10: providing a substrate 1, wherein at least a back transparent conductive oxide film 2 is disposed on the back side of the substrate 1.

[0040] In one embodiment, the front side of the substrate 1 is closer to the light-facing side of the battery, and the back side of the substrate 1 is closer to the backlight side of the battery.

[0041] In one embodiment, the substrate 1 comprises a plurality of layer structures, such as Figure 3 As shown, the substrate 1 includes an N-type doped amorphous silicon layer 11, a first intrinsic amorphous silicon layer 12, a base 13, a second intrinsic amorphous silicon layer 14 and a P-type doped amorphous silicon layer 15. At this time, the substrate 1 has been textured.

[0042] The side where the N-type doped amorphous silicon layer 11 is located is called the front side of the substrate 1, because this side is provided with the front electrode 5. The side where the P-type doped amorphous silicon layer 15 is located is the back side of the substrate 1, and the back transparent conductive oxide film 2 is deposited on the P-type doped amorphous silicon layer 15.

[0043] In one embodiment, the back transparent conductive oxide film 2 is a part of the battery, and its main function is to be used as an extension of the electrode. It not only needs to have good conductivity, but also needs to have high light transmittance to allow more light energy to penetrate into the active layer. Secondly, the back transparent conductive oxide film 2 acts as a connecting layer in the battery structure, collecting the current generated by the photogenerated carriers while transmitting it to the external circuit.

[0044] In HJT cells, for example, by depositing a back transparent conductive oxide film 2 on the back side of the substrate 1, the optimization of the photoelectric conversion efficiency in the solar cell design is achieved. Especially at present, with the phenomenon that HJT cells are becoming thinner and thinner, the use of transparent conductive oxides maximizes the utilization of light. By providing a back transparent conductive oxide film 2, the reflection and absorption of light can be reduced, ensuring that more light energy is absorbed and converted into electrical energy. In this embodiment, the back deposition method helps to simplify the design of the front end of the cell, so that the front side can focus on light capture and carrier generation, while the current collection and transmission are mainly completed by the TCO layer on the back side.

[0045] In summary, the deposition of the transparent conductive oxide film 2 on the back side not only improves the structural stability and durability of the battery, but also optimizes the electro-optical conversion path, thereby improving the overall performance of the battery.

[0046] Step S20: depositing a dielectric layer 3 on the back transparent conductive oxide film 2 .

[0047] In this embodiment, the dielectric layer 3 is a silicon oxide layer.

[0048] In one embodiment, the material of the dielectric layer 3 is silicon oxide (SiO2) because silicon oxide has relatively good electrical insulation, chemical stability and optical transparency. In one embodiment, the dielectric layer 3 is 130-170nm.

[0049] In this embodiment, the main function of the dielectric layer 3 is to suppress the plasma absorption of light by the metal layer 4, thereby improving the photoelectric conversion efficiency of the solar cell.

[0050] In order to better understand the present technology, the plasma absorption of light by the metal layer 4 is explained here as follows: Plasmon absorption is a phenomenon that occurs when metal receives light, in which the metal can absorb the energy in the light, thereby reducing the amount of light reaching the active area of ​​the solar cell. In solar cells, this absorption, if not controlled, will lead to reduced cell efficiency. The introduction of the dielectric layer 3 effectively reduces this phenomenon because it acts as an optical buffer between the metal reflective layer and the light absorbing layer.

[0051] In this embodiment, the dielectric layer 3 adopts chemical vapor deposition (CVD) technology, which can provide a high-purity and uniform back transparent conductive oxide film 2, ensuring that the quality and performance of the dielectric layer 3 meet the requirements of solar cells. By precisely controlling the thickness and density of the silicon oxide layer, its optical properties can be optimized to meet the transmission requirements of specific wavelengths of light.

[0052] In this embodiment, the dielectric layer 3 serves as an optical buffer layer, which not only effectively suppresses the photoplasmonic absorption of the metal layer 4, but also enhances the capture and conversion efficiency of the solar cell for light energy.

[0053] Step S30: Partially corroding the dielectric layer 3.

[0054] In one embodiment, this step partially etches the deposited dielectric layer 3, and the corroded portion can leak out a portion of the back transparent conductive oxide film 2, so that the metal layer 4 subsequently deposited on the dielectric layer 3 can establish electrical contact with the leaked back transparent conductive oxide film 2. In this embodiment, the dielectric layer 3 and the metal layer 4 together constitute the back structure. In this embodiment, the back structure of the heterojunction battery not only plays a role in light reflection, but also serves as an electrode, thereby effectively conducting out the carriers excited by light.

[0055] In one embodiment, during the preparation process, since the dielectric layer 3 is usually composed of electrically insulating materials such as silicon oxide, it does not have conductive properties. Therefore, if the back metal layer 4 is to function as an electrode, it is necessary to perform an opening process on the dielectric layer 3 to create a window that allows the metal layer 4 to contact the back transparent conductive oxide film 2. In the prior art, the implementation of the patterning process usually relies on opening the dielectric film layer using a burn-through high-temperature slurry, or using photolithography or laser etching technology to selectively remove part of the area on the dielectric layer 3.

[0056] In this embodiment, the metal layer 4 serves as the back electrode of the battery.

[0057] However, the above-mentioned hole-opening methods will damage the amorphous silicon layer of the HJT battery, thereby reducing the passivation effect.

[0058] In this embodiment, a partial etching method is selected to open the hole. Specifically, the dielectric layer 3 is partially etched through steps S301-S303. Figure 6 As shown, the details are as follows:

[0059] Step S301 : coating a selective etching mediating layer 7 on the dielectric layer 3 .

[0061] In one embodiment, a selective etching mediating layer 7 is coated on the dielectric layer 3, such as Figure 4 As shown, the selective etching medium layer 7 does not completely cover the dielectric layer 3 so that part of the dielectric layer 3 is in a bare state. The main function of this layer is to allow accurate partial etching processing on the dielectric layer 3. In one embodiment, there are multiple exposed parts of the dielectric layer 3, and the total area of ​​the multiple exposed parts of the dielectric layer 3 accounts for 10%-20%, wherein the orthographic projection of the exposed part of the dielectric layer 3 on the substrate 1 is located within the orthographic projection of the metal layer 4 on the substrate 1, and is randomly and evenly distributed over the orthographic projection of the metal layer 4 on the substrate 1, as shown in FIG. Figure 4 By adopting such a layout, it can be ensured that only the exposed area exists in the area corresponding to the gate.

[0062] It should be noted that Figure 4 The arrangement and shape of the orthographic projection of the exposed portion of the dielectric layer 3 on the substrate 1 are only exemplary. In practical applications, other methods may also be used. For example, the orthographic projection shapes of the exposed portion of the dielectric layer 3 on the substrate 1 are all the same, and the shapes after arrangement are relatively regular, such as rectangles, squares, circles, etc., which are not specifically limited in this embodiment. Examples are not given one by one here. .

[0063] In this embodiment, the selective corrosion mediating layer 7 is formed of a special transparent conductive oxide material, which is used to protect specific parts of the dielectric layer 3 from the influence of the corrosive solution, while exposing other parts for subsequent corrosion processes. The selective corrosion mediating layer 7 is that it can accurately control the area of ​​corrosion by forming mesopores, thereby realizing complex electrode structures and connection paths. Among them, the method of forming mesopores may include using different mesoporous materials to form mesopores by ion exchange under certain conditions. It is also possible to use some methods of blocking the flow of materials to block the flow of related materials in the area where corrosion is required to form mesopores, which will not be explained one by one here.

[0064] In one embodiment, the selective etching mediator layer 7 is made of hexamethyldisilazane (HMDS). HMDS is a surface modifier, and its main advantages include being able to form a uniform and stable mesoporous film on the surface of the dielectric layer 3. The HMDS layer has good chemical stability and unique surface tension characteristics, so HMDS is selected as the material for creating a selective etching window. When coated on the dielectric layer 3, HMDS can quickly form a mesoporous film. By controlling the spin coating rate and the curing temperature of HMDS, the area desired to be etched is exposed.

[0065] In this embodiment, HMDS is selected as the selective etching mediating layer 7 because of its high resistance to many chemicals and easy handling. HMDS is not easy to decompose when it contacts some etchants, which ensures that the boundary of the etching window remains clear and precise during the etching process.

[0066] In one embodiment, the selective etching mediating layer 7 is formed on the dielectric layer 3 by spin coating. Spin coating is a high-speed film forming method, which uses the centrifugal force generated by rotation to evenly spread the sol, solution or suspension onto the surface of the substrate 1.

[0067] In one embodiment, the selective etching mediating layer 7 is formed on the dielectric layer 3 by a spin coating method, specifically a liquid dynamic spin coating technology.

[0068] In one embodiment, the rotation rate during the spin coating process is set at 150 to 300 revolutions per minute. Within this speed range, uniform distribution of corrosion holes and appropriate pore size can be achieved, which is crucial for the effective contact between the subsequent metal layer 4 and the transparent conductive oxide film 2 on the back side, thereby ensuring the overall performance of the battery. If the rotation rate is too slow, the corrosion holes will be unevenly distributed, and this unevenness may affect the formation of the metal electrode. On the contrary, if the rotation rate is too fast, it may cause the solution to be unstable during the spin coating process, such as HMDS may have a local debonding problem.

[0069] In one embodiment, the curing temperature is between 110 and 150 degrees Celsius. Within this temperature range, proper curing of HMDS can be ensured, and neither incomplete curing due to too low a temperature nor excessive internal cross-linking due to too high a temperature will be caused. Curing at too low a temperature will result in incomplete curing of HMDS, affecting the stability of its structure and the realization of its functions; while too high a temperature may result in excessive internal cross-linking of HMDS, resulting in the disappearance of local corrosion holes, which will also affect the formation and performance of the subsequent metal layer 4.

[0070] In one embodiment, 2-5 mL of a selective corrosion mediating medium is spin-coated on the dielectric layer (3) to form the selective corrosion mediating layer. In this embodiment, the selective corrosion mediating medium may be HMDS.

[0071] In this embodiment, by precisely controlling these parameters, the quality and functionality of the selective corrosion mediating layer 7 can be ensured, thereby optimizing the manufacturing process and performance of the entire HJT cell.

[0072] In this embodiment, HMDS is applied on the dielectric layer 3 to selectively etch the intermediate layer 7 , thereby achieving partial etching of the dielectric layer 3 in this step.

[0073] Step S302: using a first solution to corrode a portion of the dielectric layer 3 that is in a bare state.

[0074] In one embodiment, the concentration of the first solution is 10% to 40%, the first solution is used for etching for 30-60 minutes, the dielectric layer 3 is a silicon oxide layer, the first solution is a NaOH solution, and the etching temperature is 40-80°C.

[0075] Specifically, in this embodiment, a sodium hydroxide (NaOH) solution is used to etch the exposed dielectric layer 3 (silicon oxide material). In this step, the NaOH solution is used as an alkaline solution, mainly to remove the silicon oxide portion not covered by the HMDS layer, thereby forming an area where the metal layer 4 will be deposited. Sodium hydroxide can effectively etch silicon oxide due to its strong alkalinity.

[0076] In this embodiment, the concentration of the first solution is set between 10% and 40%, and the etching temperature is 40-80° C. This concentration range and temperature range provide sufficient etching activity to ensure that silicon oxide can be completely removed in a relatively short time without causing damage to the equipment in the process or the unexposed back transparent conductive oxide film 2. In this embodiment, when the dielectric layer 3 is 130-170nm, the etching time is set to 30 to 60 minutes. This time range takes into account the concentration of the first solution and the thickness of the dielectric layer 3.

[0077] Through this step, the dielectric layer 3 is precisely and controlledly removed locally, providing the necessary physical space for the subsequent deposition of the metal layer 4. In addition, the application of this method ensures the efficiency and controllability of the process flow, and improves the photoelectric performance of the final HJT cell.

[0078] Step S303: removing the selective corrosion mediating layer 7.

[0079] In one embodiment, a second solution is used to remove the selective corrosion mediating layer 7. In this embodiment, the second solution is an organic solvent, such as acetone or isopropyl alcohol. The second solution can effectively remove the hexamethyldisilazane (HMDS) layer without damaging the back transparent conductive oxide film 2.

[0080] In this step, the exposed silicon oxide areas (dielectric layer 3) ensure correct deposition of the metal layer 4 and establishment of electrical contact through this treatment.

[0081] In this embodiment, if Figure 5 FIG. 4 is a schematic diagram showing the state after the selective etching mediating layer 7 is removed.

[0082] Step S40: depositing a metal layer 4 on the dielectric layer 3 .

[0083] In one embodiment, this step deposits a metal layer 4 on the treated dielectric layer 3. The metal layer 4 has a dual function in the back structure: first, as a metal reflector, it reflects light that is not absorbed by the front active layer back to the light capture area of ​​the battery, thereby improving the efficiency of light energy utilization; second, as a back electrode, it effectively collects and exports electrons, thereby optimizing the electrical performance of the battery.

[0084] In this embodiment, the metal material selected for the metal layer 4 includes silver (Ag), aluminum (Al), copper (Cu), etc. The deposition method may include physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. In this embodiment, a layer of 200-400nm of silver is deposited as the metal layer 4.

[0085] In this embodiment, the deposition technology of the metal layer 4 can use other deposition technologies such as evaporation and sputtering. Evaporation technology can be performed at a lower temperature, which helps to protect the material from thermal damage. Sputtering can provide coating uniformity and can also bring good electrical effects when applied to the deposition of the metal layer 4. These deposition methods ensure that the metal layer 4 has good adhesion and long-term environmental stability.

[0086] By depositing a metal layer 4 on the dielectric layer 3, this step achieves a significant improvement in both photoelectric conversion efficiency and energy capture in the HJT cell. The metal reflector increases the path length of light inside the cell by reflecting more light energy back to the active layer, thereby improving absorption and power generation. At the same time, as the back electrode, the design and position of the metal layer 4 optimizes the current collection path, reduces the loss of electrons during transmission, and improves the overall cell output power and efficiency.

[0087] In addition, the introduction of the metal layer 4 also enhances the structural strength of the battery and provides additional protection against potential damage caused by environmental factors, thereby extending the operating life of the battery. This structural design not only optimizes the performance of the battery, but also improves its reliability and stability in various operating environments. These improvements are of great significance to enhancing the commercial application value of solar cells.

[0088] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art can understand that in order to achieve the effects of the present invention, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present invention.

[0089] Reference Figure 1 , Figure 1 It is a schematic diagram of the heterojunction battery structure finally obtained in this embodiment.

[0090] Specifically, Figure 1 The present application also provides a heterojunction battery, comprising: a front electrode 5, a front transparent conductive oxide film 6, a substrate 1, a back transparent conductive oxide film 2 and a back structure arranged in sequence, wherein the back structure comprises: a dielectric layer 3 and a metal layer 4, wherein the dielectric layer 3 has a hole, and the metal layer 4 penetrates through the hole to contact the back transparent conductive oxide film 2.

[0091] In this embodiment, the substrate 1 includes a plurality of layer structures, including an N-type doped amorphous silicon layer 11 , a first intrinsic amorphous silicon layer 12 , a base 13 , a second intrinsic amorphous silicon layer 14 and a P-type doped amorphous silicon layer 15 .

[0092] Specifically, the front N-type doped amorphous silicon layer 11 is doped by adding a fifth group element such as phosphorus, which makes the layer have additional electrons and forms a high electron concentration area. The main function of this layer is to promote the collection of electrons and transfer them to the front electrode 5, so it is placed on the outermost side of the substrate 1. In addition, the N-type doped layer also helps to form a built-in electric field, which is extremely important for driving and managing the separation and transportation of photogenerated carriers.

[0093] Next is the first intrinsic amorphous silicon layer 12, which is a hydrogen-doped amorphous silicon layer. As a passivation layer, its function is to passivate the surface dangling bonds of the substrate 13 and reduce the surface defect state density, thereby inhibiting the recombination loss of carriers when transmitting between the N-type doped amorphous silicon layer and the substrate 13, and effectively improving the open circuit voltage of the HJT battery.

[0094] The substrate 13 layer is made of n-type doped crystalline silicon (nc-Si) as a light absorption layer and is the main photoelectric conversion region.

[0095] The second intrinsic amorphous silicon layer 14 is located between the substrate 13 and the P-type doped amorphous silicon layer 15. Similar to the first intrinsic layer, it is also a hydrogen-doped amorphous silicon layer. Its function is to further optimize the electric field, reduce the useless recombination of carriers before they are transmitted to the electrode, and ensure that the photogenerated carriers can be effectively utilized.

[0096] Finally, the back side of the substrate 1 is covered with a P-type doped amorphous silicon layer 15, which is doped with boron and other group III elements to achieve P-type doping, so that the layer is rich in holes. The hole-rich region of the P-type doped amorphous silicon layer 15 forms a PN junction with the N-type layer, which greatly promotes the electric field strength inside the battery and the effective separation of photogenerated carriers, and is more likely to receive light returned by the back structure.

[0097] In this embodiment, the front electrode 5 is usually made of a highly conductive material, such as silver or aluminum, which can effectively collect and conduct electrons excited by sunlight. The design of the front electrode 5 can be a grid or stripe shape. In one embodiment, the front electrode 5 is formed by screen printing. Then, the front transparent conductive oxide film 6 is formed, and the same process is used as the back transparent conductive oxide film 2.

[0098] In this embodiment, the back structure is used to enhance the utilization rate of light by the cell, and the structure includes a dielectric layer 3 and a metal layer 4. The dielectric layer 3 is usually made of silicon oxide or silicon nitride. The dielectric layer 3 not only provides good electrical insulation, but also reflects light that is not absorbed by the upper layer back to the active area. In this embodiment, the dielectric layer 3 is designed with a plurality of holes.

[0099] The metal layer 4 penetrates the holes in the dielectric layer 3 and directly contacts the back transparent conductive oxide film 2. This design enables the metal layer 4 to not only reflect light as a back reflector, but also to collect and transmit electrons as a back electrode.

[0100] In this embodiment, the active region refers to the region that directly participates in the generation, separation and transport of photogenerated carriers (electrons and holes). In this embodiment, the active region includes a portion of the substrate 1.

[0101] Overall, the design of this layered structure not only optimizes the management of light and the transmission path of electrons, but also significantly improves the performance of solar cells through fine engineering adjustments. Such a detailed description helps provide a clear visual and functional definition in technical implementation and potential infringement determination.

[0102] Furthermore, a heterojunction battery includes a back structure, wherein the back structure is prepared based on the preparation method of the heterojunction battery back structure in the above embodiment.

[0103] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0104] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0105] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of this application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0106] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0107] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A method for preparing a rear structure of a heterojunction battery, characterized in that: include, A substrate (1) is provided, wherein at least a back transparent conductive oxide film (2) is provided on the back side of the substrate (1), the front side of the substrate (1) is closer to the light-facing side of the battery, and the back side of the substrate (1) is closer to the backlight side of the battery; Depositing a dielectric layer (3) on the back transparent conductive oxide film (2), and partially etching the dielectric layer (3); A metal layer (4) is deposited on the dielectric layer (3) so that the metal layer (4) is partially in contact with the back transparent conductive oxide film (2).

2. The method for preparing the back structure of a heterojunction battery according to claim 1, characterized in that: The step of “depositing a dielectric layer (3) on the back transparent conductive oxide film (2) and partially etching the dielectric layer (3)” includes: Coating a selective etching mediating layer (7) on the dielectric layer (3), wherein the selective etching mediating layer (7) does not completely cover the dielectric layer (3), so that part of the dielectric layer (3) is in a bare state; Using a first solution to etch a portion of the dielectric layer (3) that is in a bare state; The selective etching mediating layer (7) is removed.

3. The method for preparing the back structure of a heterojunction battery according to claim 2, characterized in that: The method of coating a selective etching mediating layer (7) on the dielectric layer (3) comprises: A selective etching mediating layer (7) is formed on the dielectric layer (3) by spin coating.

4. The method for preparing the back structure of a heterojunction battery according to claim 2, characterized in that: There are multiple exposed portions of the dielectric layer (3), and the total area of ​​the multiple exposed portions of the dielectric layer (3) accounts for 10%-20%.

5. The method for preparing the back structure of a heterojunction battery according to claim 4, characterized in that: in, The orthographic projection of the exposed portion of the dielectric layer (3) on the substrate (1) is located within the orthographic projection of the metal layer (4) on the substrate (1).

6. The method for preparing the back structure of a heterojunction battery according to claim 3, characterized in that: The rotation rate in the spin coating is 150-300 r / min and the curing temperature is 110-150°C.

7. The method for preparing a rear structure of a heterojunction battery according to any one of claims 2 to 6, characterized in that: The selective corrosion mediating layer (7) is removed using a second solution, wherein the selective corrosion mediating layer (7) is a HMDS layer and the second solution is an organic solvent.

8. The method for preparing a heterojunction battery back structure according to any one of claims 2 to 6, characterized in that: A selective etching mediating layer (7) is coated on the dielectric layer (3), comprising: 2-5 mL of a selective etching medium is spin-coated on the dielectric layer (3) to form the selective etching medium layer (7).

9. The method for preparing a rear structure of a heterojunction battery according to any one of claims 2 to 5, characterized in that: The material of the dielectric layer (3) is silicon oxide, and the first solution is a NaOH solution.

10. The method for preparing the rear surface structure of a heterojunction battery according to claim 8, characterized in that: The thickness of the dielectric layer (3) is 130-170 nm, the concentration of the first solution is 10%-40%, the etching time in the first solution is 30-60 minutes, and the etching temperature is 40-80°C.

11. The method for preparing a rear surface structure of a heterojunction battery according to claim 1, characterized in that: The thickness of the metal layer (4) is 200-400 nm.

12. A heterojunction battery, characterized in that: include: A front electrode (5), a front transparent conductive oxide film (6), a substrate (1), a back transparent conductive oxide film (2) and a back structure are arranged in sequence, wherein the back structure comprises a dielectric layer (3) and a metal layer (4), wherein the dielectric layer (3) has a hole, and the metal layer (4) penetrates through the hole to contact the back transparent conductive oxide film (2).

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