Hybrid bonding of semiconductor structures with advanced substrate panels

Abstract

A method for bonding semiconductor surfaces utilizes a hybrid bonding process to implement a heterogeneous integrated architecture. In some embodiments, the method may include forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of exposed conductive connections on a top surface of the semiconductor structure. The first set of exposed conductive connections has a pitch of less than about 10 microns. An advanced rectangular substrate panel having a second set of exposed conductive connections is formed. The second set of exposed conductive connections has a pitch of less than about 10 microns. A top surface of the semiconductor structure is bonded to a top surface of the advanced rectangular substrate panel using a hybrid bonding process to bond the semiconductor structure to the advanced rectangular substrate panel.

Description

Technical Field

[0001] Embodiments of the present principles relate generally to semiconductor processing of semiconductor substrates. Background Art

[0002] In traditional processes, semiconductor chips are manufactured in the front end of the line (FEOL) process, and a redistribution layer (RDL) is formed in a subsequent packaging process to allow electrical connection to the chip. However, RDL reduces the input / output (IO) density of the chip because additional space is required to connect to the RDL. In some cases, a fan-out method that provides connections can further reduce the IO density of the chip. In order to allow correct connections, similar low IO density connections are formed on the substrate to align with the RDL connections on the chip in the back end of the line (BEOL) process. The chip is then bonded to the substrate using a thermal compression bonding process, and the RDL is connected to the printed circuit board (PCB) using solder bumps. The formation of RDL and the reduced IO density increase the cost and number of parts of the manufacturing process. In addition, the circular shape of the silicon substrate limits the effective area on the substrate where rectangular chips can be bonded, further increasing the unit manufacturing cost.

[0003] Thus, the inventors have provided a method for increasing IO density, allowing for higher chip connection bandwidth, while reducing manufacturing component count and cost. Summary of the invention

[0004] This article provides an architecture and method for increasing IO connection density through hybrid bonding of chips to advanced rectangular substrate panels.

[0005] In some embodiments, a method for bonding semiconductor surfaces may include: forming a first semiconductor structure on a silicon-based substrate, the first semiconductor structure having a first group of exposed conductive connections on a first top surface of the semiconductor structure, wherein the first group of exposed conductive connections are dispersed in a first non-conductive material layer, and wherein the first group of exposed conductive connections have a pitch less than about 10 microns; forming an advanced rectangular substrate panel, the advanced rectangular substrate panel having a second group of exposed conductive connections on the top surface of the advanced rectangular substrate panel, wherein the second group of exposed conductive connections are dispersed in a second non-conductive material layer different from the first non-conductive material layer, and wherein the second group of exposed conductive connections have a pitch less than about 10 microns; and bonding the first top surface of the first semiconductor structure to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first non-conductive material layer to the second non-conductive material layer, and to directly bond the first group of exposed conductive connections to the second group of exposed conductive connections.

[0006] In some embodiments, the method may further include: wherein the second non-conductive material layer is polyimide; wherein the hybrid bonding process is performed at a temperature of about 200°C or lower; wherein the advanced rectangular substrate panel has no core, organic core or glass core; wherein the first non-conductive material layer is a first dielectric material different from the second dielectric material of the second non-conductive material layer; before performing the hybrid bonding process, the advanced rectangular substrate panel is chemically mechanically polished (CMP) to a surface roughness (RA) of about 0.5nm or less; wherein the advanced rectangular substrate panel is about 510mm×about 515mm; wherein the advanced rectangular substrate panel is about 205mm×about 257.5mm; wherein the first semiconductor structure is formed without a controlled collapse chip connection (C4) layer; wherein the first semiconductor structure is a chip or chiplet formed using a front-end of line (FEOL) process; wherein the advanced rectangular substrate panel is formed using a front-end of line (FEOL) process; and / or wherein the method is used to form a heterogeneous integrated architecture on both sides of the advanced rectangular substrate panel.

[0007] In some embodiments, the method may further include: forming a second semiconductor structure on a silicon-based substrate, the second semiconductor structure having a third group of exposed conductive connections on a second top surface of the second semiconductor structure, wherein the third group of exposed conductive connections are dispersed in a third non-conductive material layer, and wherein the third group of exposed conductive connections have a pitch of less than about 10 microns; forming an advanced rectangular substrate panel to have a fourth group of exposed conductive connections on the bottom surface of the advanced rectangular substrate panel, wherein the fourth group of exposed conductive connections are dispersed in a fourth non-conductive material layer different from the third non-conductive material layer; and using a hybrid bonding process to bond the second top surface of the second semiconductor structure to the bottom surface of the advanced rectangular substrate panel to directly bond the third non-conductive material layer to the fourth non-conductive material layer, and directly bond the third group of exposed conductive connections to the fourth group of exposed conductive connections, wherein the first semiconductor structure bonded to the top surface of the advanced rectangular substrate and the second semiconductor structure bonded to the bottom surface of the advanced rectangular substrate are in high-bandwidth electrical communication.

[0008] In some embodiments, a method for bonding semiconductor surfaces may include: forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of exposed conductive connections on a top surface of the semiconductor structure, wherein the first set of exposed conductive connections are dispersed in a first non-conductive material layer, and wherein the semiconductor structure is a chip or chiplet formed using a front-end-of-line (FEOL) process without a controlled collapse chip connection (C4) layer; forming an advanced rectangular substrate panel, the advanced rectangular substrate panel having a second set of exposed conductive connections on a top surface of the advanced rectangular substrate panel, wherein the second set of exposed conductive connections are dispersed in a second non-conductive material layer different from the first non-conductive material layer; and bonding the top surface of the semiconductor structure to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first non-conductive material layer to the second non-conductive material layer, and to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections.

[0009] In some embodiments, the method may further include: wherein the first group of exposed conductive connections have a pitch less than about 10 microns, and wherein the second group of exposed conductive connections have a pitch less than about 10 microns; wherein the hybrid bonding process is performed at a temperature of about 200°C or less; and / or wherein the advanced rectangular substrate panel has no core, organic core or glass core.

[0010] In some embodiments, a non-transitory computer-readable medium having instructions stored thereon, the instructions, when executed, causing execution of a method for bonding a semiconductor surface, the method may include forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of exposed conductive connections on a top surface of the semiconductor structure, wherein the first set of exposed conductive connections are interspersed in a first non-conductive material layer, and wherein the first set of exposed conductive connections have a pitch of less than about 10 microns; forming an advanced rectangular substrate panel, the advanced rectangular substrate panel having a second set of exposed conductive connections on a top surface of the advanced rectangular substrate panel, wherein the second set of exposed conductive connections are interspersed in a second non-conductive material layer different from the first non-conductive material layer, and wherein the second set of exposed conductive connections have a pitch of less than about 10 microns; and bonding the top surface of the semiconductor structure to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first non-conductive material layer to the second non-conductive material layer, and to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections.

[0011] In some embodiments, the method of the non-transitory computer readable medium may further include: chemically mechanically polishing (CMP) the advanced rectangular substrate panel to a surface roughness (RA) of about 0.5 nm or less before performing the hybrid bonding process; or activating the top surface of the advanced rectangular substrate panel using a plasma process; wherein the semiconductor structure is a chip or chiplet formed using a front-end-of-line (FEOL) process without a controlled collapse chip connection (C4) layer; and / or wherein the advanced rectangular substrate panel is formed using a front-end-of-line (FEOL) process.

[0012] Other and further embodiments are disclosed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments of the present principles, briefly summarized above and discussed in more detail below, can be understood by referring to the illustrative embodiments of the principles depicted in the accompanying drawings. However, the accompanying drawings illustrate only typical embodiments of the present principles and are therefore not to be considered limiting of scope, as the present principles may admit to other equally effective embodiments.

[0014] Figure 1 Depicted are top and cross-sectional views of a conventional circular silicon substrate.

[0015] Figure 2 Depicted are top and cross-sectional views of an advanced rectangular substrate panel, according to some embodiments of the present principles.

[0016] Figure 3 Depicted is a cross-sectional view of a conventional semiconductor structure and a conventional silicon substrate.

[0017] Figure 4 Depicted are cross-sectional views of semiconductor structures and advanced rectangular substrate panels, according to some embodiments of the present principles.

[0018] Figure 5 Depicted are methods of hybrid bonding of semiconductor structures with advanced rectangular substrate panels in accordance with some embodiments of the present principles.

[0019] Figure 6 Depicted is a heterogeneous integration architecture achieved through a hybrid bonding approach in accordance with some embodiments of the present principles.

[0020] Figure 7 Depicted is a cross-sectional view of a semiconductor structure connected to a silicon substrate via an interposer.

[0021] Figure 8 Depicted are cross-sectional views of illustrative semiconductor devices according to some embodiments of the present principles.

[0022] Fig. 9Methods of forming semiconductor structures using double-sided advanced rectangular substrates according to some embodiments of the present principles.

[0023] FIG. 10A to FIG. 10J Depicted is a cross-sectional view of a double-sided advanced rectangular substrate, according to some embodiments of the present principles.

[0024] To facilitate understanding, the same reference numerals have been used, where possible, to denote the same elements common to the drawings. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without repetition. DETAILED DESCRIPTION

[0025] The method provides a high-quality hybrid bonding process, attaching individual chips or chiplets directly to a packaging substrate (such as an advanced rectangular substrate panel) at a very high density (e.g., a pitch of less than 10 microns), thereby realizing an advanced architecture for semiconductor manufacturing. The present principle realizes direct chip-to-substrate integration with ultra-fine pitch, eliminates the need for using an interposer for chip-to-chip and chip-to-substrate to printed circuit board (PCB) interconnection, and realizes a multi-chip module with high-bandwidth chip-to-chip and chip-to-substrate communication. In addition, the method and architecture provide the benefits of a smaller interconnect length in the absence of an underfill (UF) and / or interface material to enhance reliability, thermal efficiency, and minimize resistance / capacitance (RC) losses, etc. (i.e., minimize interface materials). By realizing the use of an advanced rectangular substrate panel, the substrate area is maximized (e.g., rectangular / square chip to rectangular / square substrate compared to rectangular / square chip to circular substrate, etc.). Compared to silicon wafers, such panels also provide economies of scale when processing larger areas.

[0026] Conventional processes use solder-assisted flip-chip processes, in which thermocompression bonding (TCB) is used to connect conventional chips at much larger pitches. Bottom fillers are typically used between solder bumps as dielectrics and for mechanical stability in conventional processes. Conventional wire bonding / flip-chip architectures have long interconnect lengths, produce high impedance, Joule heating, RF interference, etc., and have limited input / output (IO) density. The method of the present principle uses a direct molecular bonding process for non-conductive interfaces and conductive interfaces for chips with advanced rectangular substrate panels. The implementation of this bonding process is achieved by reducing surface roughness, design optimization, and material selection. The reduced interface length provided by the present principle provides better electrical performance and significantly higher IO density. Since hybrid bonding does not require bottom fillers, mechanical reliability is greatly improved. The enhanced process also enables the potential reduction of the number of metal layers or redistribution layers (RDL) on the chip (e.g., the minimum possible elimination of "C4" or controlled collapse chip connection layers on the chip, etc.). Similarly, the enhanced process has the potential to reduce the number of process steps in the packaging process and reduce packaging time (i.e., improve cycle time). The present principles also provide greater flexibility and improved electrical performance for the design of chip-to-substrate integration (eg, direct copper-to-copper bonding with minimal or no electrometallurgical interference, etc.).

[0027] The architecture and methods of the present principles utilize advanced substrates and hybrid bonding to form high bandwidth, high reliability and high density semiconductor chip packages. Hybrid bonding is a process in which a chip is directly bonded to a substrate using, for example but not limited to, direct metal-to-metal interconnect bonding and direct non-conductive-to-non-conductive material bonding between the chip and the substrate. The non-conductive materials bonded together can be the same material or different materials. An annealing process can then be used to bond metal-to-metal contacts. In some embodiments, the metal contacts can be recessed below the uppermost surface of the non-conductive material, and the annealing process expands the metal in the metal contacts to overcome the recess and bond the contacts. In some embodiments, the metal contacts can be roughly flush with the uppermost surface of the non-conductive material, and an annealing process may not be required after bonding.

[0028] The present principles utilize the use of advanced rectangular substrate panels to facilitate high IO density connections. The high IO density connections enable the advanced architecture disclosed herein. The advanced rectangular substrate panels have non-silicon cores formed as rectangular panels. The connections of the advanced rectangular substrate panels can be formed by processes associated with front-end of line (FEOL) processes. The semiconductor structures used herein are typically structures formed during FEOL manufacturing, which require high precision and complex manufacturing, and then packaged with other structures or chips in a back-end of line (BEOL) process involving simpler processing with much lower precision.

[0029] In the industry, FEOL semiconductor manufacturers are equipped for standard round silicon substrates, while panel producers do not have equipment to perform FEOL processing. The architecture described herein using the present principles will require a large investment in tools and significant changes in the overall semiconductor manufacturing process flow to enable such high IO density and high bandwidth device manufacturing.

[0030] Figure 1 1 is a top view 100A of a semiconductor structure 104, such as a chip or chiplet, positioned on a silicon substrate 102 having a circular shape. Because the semiconductor structure 104 is rectangular and the silicon substrate 102 is circular, a large amount of surface area 106 of the silicon substrate 102 is wasted due to the shape mismatch. In addition, the semiconductor structure 104 typically utilizes an interposer 108 to allow the semiconductor structure 104 to be attached to the silicon substrate 102, such as Figure 1 The cross-section is depicted in FIG100B. Figure 7 7 is a magnified view of the connections between semiconductor structure 104, interposer 108, and silicon substrate 102. Interposer 108 takes the higher density connections 702 of the circuitry from within semiconductor structure 104 and expands (making the connections less dense) to form interposer-substrate connections 704. Interposer-substrate connections 704 are typically solder ball connections. Interposer 108 is very expensive to manufacture, and the complexity of the interconnections between semiconductor structure 104 and silicon substrate 102 requires high precision, which is difficult and time consuming to achieve.

[0031] In some embodiments of the method of the present principles, the complete substrate panel 202 can be used as Figure 2 200A shows an advanced rectangular substrate panel. In some embodiments, the complete substrate panel 202 may have a width 206 of approximately 510 mm and a length 208 of 515 mm, etc. In some embodiments, the complete substrate panel 202 may have a width 206 greater than approximately 510 mm and a length greater than approximately 515 mm. A cross-section of the complete substrate panel 202 is depicted in view 200B. In some embodiments, the complete substrate panel 202 may be cut into quarter substrate panels 204 to allow for easier handling and / or assembly into a manufacturing apparatus, etc. In some embodiments, the quarter substrate panel 204 has a width 210 of approximately 255 mm and a length 212 of approximately 257.5 mm, etc. (depending on the size of the complete substrate panel 202). Figure 2In top view 200C of FIG. 1 , a quarter substrate panel 204 is depicted with four semiconductor structures 214 to illustrate the significant reduction in lossy surface area 216 of a flat substrate panel relative to silicon substrate 102. Cross-sectional view 200D depicts a quarter substrate panel 204 with semiconductor structures 214 mounted directly to the quarter substrate panel 204 without using an interposer or the like commonly found in silicon substrates, significantly reducing material cost and manufacturing time.

[0032] exist Figure 3 300, a semiconductor structure 302 on bulk silicon 304 includes a FEOL structure 306 and a C4 layer 308, the C4 layer 308 including an RDL 312 and solder bumps 310. An underfill 326 is used between the solder bumps 310 to stabilize the solder bumps, and the underfill 326 requires additional processing, time, and cost to be formed on the semiconductor structure 302. A silicon substrate 314 is formed with an interface layer 316 to interface with the C4 layer 308 of the semiconductor structure 302. Through silicon vias (TSVs) 318 provide internal connections to backside connections 320 to allow connection of the silicon substrate to a PCB (not shown) or the like, the backside connections 320 incorporating the RDL 324 and solder bumps 322. The connection between the semiconductor structure 302 and the silicon substrate 314 is achieved through the solder bumps 310 and the RDL 312 on the semiconductor structure 302. The RDL 312 typically extends the connection to the FEOL structure 306 in a fan-out layout that increases the connection area (reduces the connection density) to allow connection to the silicon substrate 314, which also includes the RDL in the interface layer 316 to allow connection to the semiconductor structure 302. Therefore, both the semiconductor structure 302 and the silicon substrate 314 have an expanded connection area and fewer connections (resulting in a low IO connection density with low bandwidth).

[0033] The inventors have observed the low connection density of conventional semiconductor structures attached to silicon substrates, and have found that using advanced rectangular substrate panels instead of silicon substrates will help increase the available chip placement area relative to conventional silicon substrates and enable new advanced architectures. In addition, the inventors have also observed that the C4 layer of conventionally formed semiconductor structures drastically reduces the IO connection density. Figure 4In the cross-sectional view 400 of FIG. 4 , a FEOL structure 406 of a semiconductor structure 402 is formed on bulk silicon 404 without any C4 layer in accordance with the present principles. Direct connections to the FEOL structure 406 are exposed on a top surface 426 of the semiconductor structure 402. By eliminating the C4 layer, no underfill or other supporting dielectric is required because RDL and solder bumps are not required when the methods and architectures of the present principles are used. The elimination of the C4 layer reduces process time and cost while allowing for increased IO density. In some embodiments, the pitch on the top surface 426 of the semiconductor structure 402 can be less than about 10 microns, thereby significantly increasing the IO density of the semiconductor structure 402.

[0034] The inventors have discovered that using an advanced rectangular substrate panel 414 formed using a FEOL process will allow for an IO density similar to that achievable with the semiconductor structure 402, thereby eliminating the need for an interposer between the semiconductor structure 402 and the printed circuit board. In some embodiments, the advanced rectangular substrate panel 414 is a non-silicon-based substrate panel, such as but not limited to an organic-based substrate panel, a glass-based substrate panel, and / or a non-core substrate panel, etc., which can be processed by the FEOL to produce an IO density several orders of magnitude higher than a conventional silicon-based substrate (such as a substrate used for BEOL packaging processes). The use of an ultra-smooth core material in the advanced rectangular substrate panel 414 helps to further increase the IO density by reducing the pitch.

[0035] In some embodiments, the advanced rectangular substrate panel 414 has a core 418, which may contain through-core vias (TCVs) 430 to transfer connections from the high IO density layer 416 to the PCB via a connection layer 420, which may include RDLs 424 and solder bumps 422. The panel top surface 428 has exposed connections, which have an IO density that matches or is greater than the IO density of the top surface 426 of the semiconductor structure 402. In some embodiments, the advanced rectangular substrate panel 414 can be formed using organic materials to electrically isolate high-density IO connections. For example, but not limited to, polymers such as polyimide can be used. Therefore, it is difficult for the inventors to provide a process that allows non-organic materials such as dielectrics used in semiconductor structures to be bonded to organic materials such as polyimide used in advanced rectangular substrate panel 414. In some embodiments, the dielectric material used for electrical isolation can be made from Ajinomoto Build-up (ABF) and the like provide for advanced rectangular substrate panels 414.

[0036] The inventors have discovered that by utilizing the ultra-high IO density and high bandwidth achievable between the semiconductor structure 402 and the advanced rectangular substrate panel 414, the following can be achieved: Figure 6 A new chip functional architecture based on heterogeneous integration is depicted in the cross-sectional view 600 of FIG. The heterogeneous integration architecture allows the functions of traditional chip devices to be combined between multiple chips, which are interconnected by high-bandwidth connections 602 in the high IO density layer 416 of the advanced rectangular substrate panel 414. Using the method of the present principle, the speed and bandwidth required for the heterogeneous integration architecture are now possible. The chips can be manufactured in different wafer fab facilities to allow for optimal manufacturing of different aspects of what used to be a single chip - due to the need to produce all functions in a single chip (e.g., reducing space, heat load, etc.), which may cause damage to the performance of a single chip. Taking into account the high IO density and high bandwidth, the present principle overcomes the need to produce all functions in a single chip without the traditional disadvantages (low bandwidth and high latency, etc.). In some embodiments, the advanced rectangular substrate panel 414 provides a high IO density layer 416 that can be used for high-bandwidth connections 602 between chips, and provides a connection layer 420 that allows external IO connections 604 to allow the combined chip to be connected to a PCB, etc.

[0037] exist Figure 8 800, an exemplary architecture using the present principles described above is depicted. A first semiconductor structure is hybridly bonded to an advanced rectangular substrate panel 804 along with a second semiconductor structure, such as a graphics processing unit (GPU) 806, and a logic die 808 with a stacked dynamic random access memory (DRAM) 810. The advanced rectangular substrate panel 804 allows high bandwidth communication between the GPU 806, the logic die 808, and the stacked DRAM 810. In addition, the advanced rectangular substrate panel 804 allows communication with the PCB 802 via solder bumps 812 on opposite sides of the semiconductor structure. The architecture not only produces a significant increase in communication between semiconductor structures, but also the complete process of manufacturing the device has fewer process steps and lower costs than the traditional architecture process. One of the factors that reduce cost is that the rectangular panel can achieve a 50% or more reduction in substrate waste due to the matching of the rectangular substrate architecture with the rectangular panel. In addition, typically, during the manufacture of semiconductor devices, the processing of round silicon chips requires six or more additional processes than a single advanced rectangular substrate panel.

[0038] Figure 5A method 500 for forming and hybrid bonding a semiconductor structure and an advanced rectangular substrate panel is depicted in FIG. Prior to hybrid bonding, the formation and preparation of the semiconductor structure and the advanced rectangular substrate panel for hybrid bonding may occur sequentially, in parallel, or as a combination in a previous process. In box 502, the semiconductor structure is formed to have a direct connection to the underlying structure, for example, without a C4 layer that reduces the IO density, etc. In some embodiments, the semiconductor structure can be formed to have an IO density of about 10,000 IOs per square micron or more. The semiconductor structure is typically formed using a FEOL process and may be formed on bulk silicon, etc. using conductive materials such as, but not limited to, copper and / or aluminum, and / or non-conductive materials (e.g., dielectric materials) such as, but not limited to, silicon dioxide (SiO2), silicon carbonitride (SiCN), etc. In box 504, the semiconductor structure is wet cleaned to reduce particles from the formation process.

[0039] In box 506, the semiconductor structure is planarized using a chemical mechanical process (CMP) to allow high-density IO connections. The planarization process allows a pitch of about 10 microns or less. In some embodiments, the semiconductor structure is planarized to a surface roughness or RA of about 0.1 nm or less per 10 mm×10 mm area. In some embodiments, the semiconductor structure is planarized to a surface roughness or RA of about 0.5 nm or less per 10 mm×10 mm area. In box 508, metrology is performed on the semiconductor structure to determine whether there are any defects, such as depressions and other defects. In box 510, a back grinding tape is applied to the semiconductor structure to prepare the semiconductor structure for back grinding. In box 512, a back grinding process is performed on the semiconductor structure to reduce the thickness of the semiconductor structure by removing multiple portions of the bulk silicon on which the semiconductor structure is formed. In box 514, the semiconductor structure is cut / separated / singled to allow each semiconductor structure in the semiconductor structure to be picked up, placed and bonded individually. In box 516, the semiconductor structure undergoes another cleaning process to remove any particles generated by the previous process. In block 518, the semiconductor structure undergoes plasma activation to prepare the semiconductor structure for hybrid bonding. In block 520, the semiconductor structure is wetted with deionized water before undergoing a hybrid bonding process with the advanced rectangular substrate panel.

[0040] As described above, the processes 522 to 536 for preparing an advanced rectangular substrate panel for hybrid bonding may occur in parallel with the processes 502 to 520 for preparing a semiconductor substrate, or before or after the processes 502 to 520 for preparing a semiconductor substrate. In frame 522, an advanced rectangular substrate panel is formed. The formation is generally some process that produces the final advanced rectangular substrate panel. The non-conductive material used in the bonding surface of the advanced rectangular substrate panel to be bonded to the bonding surface of the semiconductor structure may be the same as the non-conductive material in the bonding surface of the semiconductor structure, or different from the non-conductive material in the bonding surface of the semiconductor structure. Since the hybrid bonding of the advanced rectangular substrate panel with the semiconductor structure does not require packaging processes such as RDL and solder bumps, the advanced rectangular substrate panel can be formed in whole or at least in part by a FEOL process. In some embodiments, the formation process may include forming a complete substrate panel, and / or forming a complete substrate panel, and then reducing the complete substrate panel to a quarter substrate panel, etc. Therefore, as used in method 500 herein, the advanced rectangular substrate panel may be a complete substrate panel or a portion of a complete substrate panel (e.g., a quarter panel, etc.).

[0041] In some embodiments, the size of the complete substrate panel can be about 510 mm×about 515 mm, or can be larger or smaller. In optional box 524, the complete substrate panel can be cut or cut into smaller parts, such as a quarter substrate panel, etc. In some embodiments, based on the size of the complete substrate panel, the quarter substrate panel can be about 205 mm×about 257.5 mm or smaller / larger. In some embodiments, the complete substrate panel can also be cut into more than four smaller panels (for example, a large panel is cut into 6, 8 or 10 or more smaller panels, etc.). In box 526, the advanced rectangular substrate panel is cleaned to remove any residues and / or particles generated. In box 528, the advanced rectangular substrate panel is flattened. The flattening process of the rectangular substrate panel is different from the flattening of the circular substrate (such as the substrate used to form the semiconductor structure during the FEOL process). The flattening of the rectangular substrate panel requires an advanced CMP process similar to the process used for FEOL, which achieves a surface roughness or RA of about 1.0 nm or less to allow a pitch of about 10 microns or less.

[0042] In some embodiments, the CMP process produces a surface roughness or RA of about 0.5 nm or less. The RA is typically achieved on a surface area of ​​the advanced rectangular substrate panel associated with the field of view of the main mask, which is a surface area of ​​about 10 mm×10 mm. In some embodiments, the total thickness variation of the advanced rectangular substrate panel after planarization can be 1 micron or less between the minimum thickness and the maximum thickness of the panel. Since the surface area of ​​the semiconductor structure hybrid-bonded to the advanced rectangular panel is typically much smaller than the panel, the local surface roughness of the panel is more critical to the hybrid bonding than the overall full surface quality of the panel. Because the advanced rectangular substrate panel is not circular, the polishing surface used for CMP is typically rotated, and the edges of the rectangular panel must be carefully protected during the CMP process. Specialized fixtures can be used to protect the edges and maintain the overall panel thickness.

[0043] In box 530, metrology is performed on the advanced rectangular substrate panel to detect defects such as, but not limited to, depressions of the substrate panel. In box 532, the advanced rectangular substrate panel is cleaned to remove any residues and / or particles. In box 534, the advanced rectangular substrate panel undergoes a plasma activation process to prepare the advanced rectangular substrate panel for hybrid bonding with a semiconductor structure. In some embodiments, due to the use of alternative materials with higher temperature sensitivity (such as polymers, etc.), the advanced rectangular substrate panel can use a plasma activation process different from the plasma activation process for semiconductor substrates. In some embodiments, the plasma used in the activation process may be lower in intensity for polymer-based materials than for non-polymer-based materials. The plasma activation process performs activation at a temperature close to room temperature of about 15°C to about 25°C. In box 536, in some cases, the advanced rectangular substrate panel can be wetted with deionized water. In other cases, other ionic solutions can be used to wet the advanced rectangular substrate panel so as not to passivate the materials used in the advanced rectangular substrate panel.

[0044] In block 538, in a hybrid bonding process between the semiconductor structure and the advanced rectangular substrate panel, the semiconductor structure is picked up and placed on the advanced rectangular substrate panel. In block 540, an annealing process is performed to complete the hybrid bonding process by expanding the metal surface connections on the semiconductor structure and the advanced rectangular substrate panel until the surface connections are bonded together. The linear coefficient of thermal expansion (CTE) of the metal materials used in the semiconductor substrate and the advanced rectangular substrate panel can be used to determine the parameters required to connect the metal materials. In some embodiments, the metal contacts can be approximately flush with the uppermost (or lowermost) surface of the non-conductive material, and an annealing process after hybrid bonding may not be required.

[0045] If organic materials (such as, but not limited to, polymers, etc.) are used in the advanced rectangular substrate panel, the hybrid bonding process temperature may be limited. In some embodiments, the annealing process may be limited to a process temperature of about 90°C to about 200°C to protect the integrity of certain types of non-conductive materials (e.g., based on polymer materials, etc.). The inventors have discovered that by using processes such as selective laser annealing, microwave annealing, and / or high pressure environments, etc., lower annealing temperatures can be achieved as needed to preserve the materials used in the advanced rectangular substrate panel. In block 542, metrology is performed on the hybrid bonding to detect any defects, such as misalignment and / or bonding gaps, etc.

[0046] The architecture and method of the present principles described above can be further modified to produce advanced rectangular substrate panels with high IO density connections on both sides of the substrate panel. FEOL processing is used to form high-density connections on both sides to allow high-bandwidth processing between semiconductor structures bonded on the same side and with semiconductor sub-architectures bonded on the opposite side, thereby significantly increasing the possible chip density of a single advanced rectangular substrate panel. This high IO density and chip density with high-bandwidth connections allows for a substantial increase in the performance of products such as advanced supercomputers. FEOL processing on both sides of the advanced rectangular substrate panel increases the production cost of the panel and may be more suitable for small batches, extreme performance products, etc.

[0047] Fig. 9 A method 900 of forming a double-sided advanced rectangular substrate panel having interconnected semiconductor structures on both sides is depicted. During the discussion of the method 900, reference may be made to views 1000A through 1000J of FIG. 10 . In block 902, an advanced rectangular substrate panel 1002 (see FIG. 10 ) is formed. Fig. 10A ) is formed with a first side connection 1004 located on a first side 1014 (e.g., top side) and a second side connection 1006 located on a second side 1016 (e.g., bottom side). The first side connection 1004 and the second side connection 1006 are high IO density connections that allow high bandwidth connections on each side. A through core via (TCV) 1008 is formed to connect the first side connection 1004 to the second side connection 1006 via the core 1010 of the advanced rectangular substrate panel 1002. The first side connection 1004 is formed using the FEOL process for single-sided panels as described above. The second side connection 1006 is formed using the FEOL process for single-sided panels as described above. The first side connection 1004 and the second side connection 1006 can be formed to have an IO density of about 10,000 IOs per square micron or more, and have interconnected TCVs.

[0048] In block 904, Fig. 10BAs depicted in view 1000B of FIG. 1000B , at least one first semiconductor structure 1012 (e.g., a chip, a chiplet, etc.) is hybrid bonded to a first side 1014 of an advanced rectangular substrate panel 1002. Hybrid bonding processes for single-sided advanced rectangular substrates and semiconductor structures are described above. After bonding has occurred, the IO connections of the at least one first semiconductor structure 1012 are connected to the IO connections of the first side connections 1004 and can be used for high bandwidth connections to other semiconductor structures on the first side 1014 and to the second side 1016 via TCVs. In block 906, as shown in FIG. Fig. 10C As depicted in view 1000C of FIG. 1000A , at least one first semiconductor structure 1012 on the first side 1014 is encapsulated by a first encapsulation material 1022. The first encapsulation material 1022 protects the at least one first semiconductor structure 1012 during subsequent processing, and may also provide a base for mounting a carrier (not shown) to the first side 1014 of the advanced rectangular substrate panel 1002 to provide stability for further processing. The first encapsulation material 1022 may be a molding type material and / or a dielectric type material, etc.

[0049] In optional block 908, if Fig. 10D As depicted in view 1000D of FIG. 1000B , an upper surface 1018 of the first packaging material 1022 may be planarized in a CMP process. In some embodiments, planarization may be performed to level the upper surface 1018 for application of a carrier or the like for subsequent handling and processing. In some embodiments, planarization may remove the first packaging material 1022 to a level 1020 that exposes one or more uppermost surfaces of the at least one first semiconductor structure 1012 to enable placement of a thermal control device or the like (e.g., a thermal pad, a heat sink, a heat spreader, etc.). In block 910 , as shown in FIG. Fig. 10E As depicted in view 1000E of FIG. 1 , the advanced rectangular substrate panel 1002 is flipped over so that the second side 1016 is at the top and the first side 1014 is at the bottom. In block 912, as shown in FIG. Fig.10F As depicted in view 1000F of FIG. 1000A , at least one second semiconductor structure 1024 (e.g., a chip, a chiplet, etc.) is hybrid bonded to the second side 1016 of the advanced rectangular substrate panel 1002. The hybrid bonding process for single-sided advanced rectangular substrates and semiconductor structures is described above. After bonding has occurred, the IO connections of the at least one second semiconductor structure 1024 are connected to the IO connections of the second side connection 1006 and can be used for high bandwidth connections to other semiconductor structures on the second side 1016 and to the first side 1014 via TCVs.

[0050] In block 914, Figure 10GAs depicted in view 1000G of FIG. 1002 , at least one second semiconductor structure 1024 on the second side 1016 is encapsulated by a second encapsulation material 1026. The second encapsulation material 1026 protects the at least one second semiconductor structure 1024 during subsequent processing and may also provide a base for building external connections (e.g., vias, RDLs, etc.) to the second side 1016 of the advanced rectangular substrate panel 1002. In some embodiments, the first encapsulation material 1022 and the second encapsulation material 1026 may be the same material or different materials. The second encapsulation material 1026 may be a molding type material and / or a dielectric type material, etc. In block 916, as Fig. 10H 1000H, external connections 1028 are formed on the second side 1016 of the advanced rectangular substrate 1002. The external connections 1028 may include RDLs and through-mold vias (TMVs) 1030 that provide connections to the second side connections 1006 and subsequently to the first side connections 1004 via TCVs 1008. In some embodiments, the second packaging material 1026 may be planarized in a CMP process to allow fine pitch RDL formation.

[0051] In block 918, if Fig.10I As depicted in view 1000I of , PCB connections 1032 (e.g., solder balls, etc.) are formed on the second side 1016 of the advanced rectangular substrate panel 1002. The PCB connections 1032 enable external connections to at least one first semiconductor structure 1012 and / or at least one second semiconductor structure 1024, etc. Fig.10J In view 1000J, the advanced rectangular substrate panel 1002 has been flipped and mounted to the PCB 1034. The architecture of the present principles allows the construction of components with high bandwidth capabilities between semiconductor structures on each side of the advanced rectangular substrate panel 1002 and between the two sides, while maintaining compatibility with PCB type external connections and having fewer components (e.g., no interposer, etc.), improved reliability and performance. In fact, the architecture will enable heterogeneous integration architectures and next generation supercomputers.

[0052] Embodiments according to the present principles may be implemented in hardware, firmware, software, or any combination thereof. Embodiments may also be implemented as instructions stored using one or more computer-readable media, which may be read and executed by one or more processors. Computer-readable media may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing platform or "virtual machine" running on one or more computing platforms). For example, a computer-readable medium may include any suitable form of volatile or non-volatile memory. In some embodiments, a computer-readable medium may include a non-temporary computer-readable medium.

[0053] While the foregoing is directed to embodiments of the present principles, other and further embodiments of the present principles may be devised without departing from the basic scope thereof.

Claims

1. A method for bonding a semiconductor surface, comprising the steps of: forming a first semiconductor structure on a silicon-based substrate, the first semiconductor structure having a first set of exposed conductive connections on a first top surface of the first semiconductor structure, wherein the first set of exposed conductive connections is interspersed in a first non-conductive material layer, and wherein the first set of exposed conductive connections has a pitch of less than about 10 microns; forming an advanced rectangular substrate panel having a second set of exposed conductive connections on a top surface of the advanced rectangular substrate panel, wherein the second set of exposed conductive connections is interspersed in a second non-conductive material layer different from the first non-conductive material layer, and wherein the second set of exposed conductive connections has a pitch of less than about 10 microns; as well as The first top surface of the first semiconductor structure is bonded to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first non-conductive material layer to the second non-conductive material layer and to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections.

2. The method of claim 1, wherein the second non-conductive material layer is polyimide.

3. The method of claim 1, wherein the hybrid bonding process is performed at a temperature of about 200°C or less.

4. The method of claim 1, wherein the advanced rectangular substrate panel has no core, an organic core, or a glass core. 5 . The method of claim 1 , wherein the first non-conductive material layer is a first dielectric material different from a second dielectric material of the second non-conductive material layer.

6. The method of claim 1, further comprising the steps of: Prior to performing the hybrid bonding process, the advanced rectangular substrate panel is chemically mechanically polished (CMP) to a surface roughness (RA) of about 0.5 nm or less.

7. The method of claim 1, further comprising the steps of: forming a second semiconductor structure on a silicon-based substrate, the second semiconductor structure having a third set of exposed conductive connections on a second top surface of the second semiconductor structure, wherein the third set of exposed conductive connections is interspersed in a third non-conductive material layer, and wherein the third set of exposed conductive connections has a pitch of less than about 10 microns; forming the advanced rectangular substrate panel to have a fourth set of exposed conductive connections on a bottom surface of the advanced rectangular substrate panel, wherein the fourth set of exposed conductive connections is interspersed in a fourth non-conductive material layer different from the third non-conductive material layer; as well as The second top surface of the second semiconductor structure is bonded to the bottom surface of the advanced rectangular substrate panel using the hybrid bonding process to directly bond the third non-conductive material layer to the fourth non-conductive material layer, and to directly bond the third group of exposed conductive connections to the fourth group of exposed conductive connections, wherein the first semiconductor structure bonded to the top surface of the advanced rectangular substrate panel and the second semiconductor structure bonded to the bottom surface of the advanced rectangular substrate panel are in high-bandwidth electrical communication.

8. The method of claim 1, wherein the advanced rectangular substrate panel is about 510 mm by about 515 mm.

9. The method of claim 1, wherein the advanced rectangular substrate panel is about 205 mm by about 257.5 mm.

10. The method of claim 1, wherein the first semiconductor structure is formed without a controlled collapse chip connect (C4) layer.

11. The method of claim 1, wherein the first semiconductor structure is a chip or chiplet formed using a front end of line (FEOL) process.

12. The method of claim 1, wherein the advanced rectangular substrate panel is formed using a front end of line (FEOL) process.

13. The method of claim 1 for forming a heterogeneous integrated architecture on both sides of the advanced rectangular substrate panel.

14. A method for bonding a semiconductor surface, comprising the steps of: forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of exposed conductive connections on a top surface of the semiconductor structure, wherein the first set of exposed conductive connections are interspersed in a first non-conductive material layer, and wherein the semiconductor structure is a chip or chiplet formed using a front end of line (FEOL) process without a controlled collapse chip connection (C4) layer; forming an advanced rectangular substrate panel having a second set of exposed conductive connections formed on a top surface of the advanced rectangular substrate panel, wherein the second set of exposed conductive connections is interspersed in a second non-conductive material layer different from the first non-conductive material layer; as well as The top surface of the semiconductor structure is bonded to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first non-conductive material layer to the second non-conductive material layer and to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections.

15. The method of claim 14, wherein the first set of exposed conductive connections has a pitch less than about 10 microns, and wherein the second set of exposed conductive connections has a pitch less than about 10 microns.

16. The method of claim 14, wherein the hybrid bonding process is performed at a temperature of about 200°C or less.

17. The method of claim 14, wherein the advanced rectangular substrate panel has no core, an organic core, or a glass core.

18. A non-transitory computer readable medium having stored thereon instructions which, when executed, cause a method for bonding a semiconductor surface to be performed, the method comprising the steps of: forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of exposed conductive connections on a top surface of the semiconductor structure, wherein the first set of exposed conductive connections are interspersed in a first non-conductive material layer, and wherein the first set of exposed conductive connections has a pitch of less than about 10 microns; forming an advanced rectangular substrate panel having a second set of exposed conductive connections on a top surface of the advanced rectangular substrate panel, wherein the second set of exposed conductive connections is interspersed in a second non-conductive material layer different from the first non-conductive material layer, and wherein the second set of exposed conductive connections has a pitch of less than about 10 microns; as well as The top surface of the semiconductor structure is bonded to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first non-conductive material layer to the second non-conductive material layer and to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections.

19. The non-transitory computer readable medium of claim 18, the method further comprising the steps of: Prior to performing the hybrid bonding process, chemically mechanically polishing (CMP) the advanced rectangular substrate panel to a surface roughness (RA) of about 0.5 nm or less; or The top surface of the advanced rectangular substrate panel is activated using a plasma process.

20. The non-transitory computer readable medium of claim 18, wherein The semiconductor structure is a chip or chiplet formed using a front end of line (FEOL) process without a controlled collapse chip connect (C4) layer; or The advanced rectangular substrate panel is formed using a front-end of line (FEOL) process.

Images