SPLIT primary signal path and pre-distortion signal path with independent digital-to-analog converter for supporting digital pre-distortion in transmitter

Abstract

Methods and apparatus for wireless communication use a transmitter capable of digital pre-distortion (DPD) and having a primary signal path separate from a pre-distorted signal path, the pre-distorted signal path and the primary signal path each comprising a digital-to-analog converter (DAC). An example apparatus generally includes a main signal path including a first DAC, a power amplifier, and a combiner disposed in the main signal path between an output of the first DAC and an input of the power amplifier. The apparatus also includes a pre-distorted signal path including a second DAC, wherein the combiner is configured to combine a pre-distorted signal in the pre-distorted signal path with a primary signal in the primary signal path.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Israel Patent Application No. 294994, filed on July 24, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits and, more particularly, to wireless transmission devices with digital predistortion (DPD) processing capabilities. Background Art

[0004] Wireless communication devices are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, etc. Such wireless communication devices may send and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to fifth generation (5G) New Radio (NR), long term evolution (LTE), code division multiple access (CDMA), time division multiple access (TDMA), wideband CDMA (WCDMA), global system for mobile (GSM), Bluetooth, Bluetooth low energy (BLE), ZigBee, wireless local area network (WLAN) RATs (e.g., WiFi), etc.

[0005] A wireless communication network may include multiple base stations that can support communications for multiple mobile stations. A mobile station (MS) can communicate with a base station (BS) via a downlink and an uplink. A downlink (or forward link) refers to a communication link from a base station to a mobile station, while an uplink (or reverse link) refers to a communication link from a mobile station to a base station. A base station can send data and control information to a mobile station on a downlink and / or can receive data and control information from a mobile station on an uplink. A base station and / or a mobile station may include a transmit digital-to-analog converter (TxDAC) that can be used, for example, to convert a digital signal into an analog signal for signal processing (e.g., filtering, up-conversion, and amplification) before being transmitted by one or more antennas. Summary of the Invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable properties. Without limiting the scope of the disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description," one will understand how the features of the present disclosure provide advantages, including reduced power and area consumption and relaxed thermal design specifications for a digital-to-analog conversion architecture supporting digital predistortion (DPD) in a transmitter, which can also result in reduced overall cost.

[0007] Certain aspects of the present disclosure relate to a DPD-capable transmitter in which a main signal path and a predistortion signal path have been separated to route the main signal through a main digital-to-analog converter (DAC) and to route the predistortion signal through a predistortion DAC.

[0008] Certain aspects of the present disclosure provide an apparatus for wireless communication. The apparatus generally includes a main signal path comprising a first digital-to-analog converter (DAC), a power amplifier, and a combiner. The combiner is disposed in the main signal path between an output of the first DAC and an input of the power amplifier. The apparatus generally also includes a predistortion signal path comprising a second DAC, wherein the combiner is configured to combine a predistortion signal in the predistortion signal path with a main signal in the main signal path.

[0009] Certain aspects of the present disclosure provide a wireless communication method. The method generally includes: converting a digital main signal into an analog main signal via a first DAC in a main signal path; converting the digital predistortion signal into an analog predistortion signal via a second DAC in a predistortion signal path; combining the analog main signal or a processed version of the analog main signal with an analog predistortion signal or a processed version of the analog predistortion signal via a combiner disposed in the main signal path to form an analog combined signal; and amplifying the analog combined signal or the processed version of the analog combined signal via a power amplifier disposed in the main signal path.

[0010] Certain aspects of the present disclosure provide an apparatus for wireless communication. The apparatus generally includes a first component for converting a digital main signal into an analog main signal, the first component for converting being disposed in a main signal path; a second component for converting a digital predistortion signal into an analog predistortion signal, the second component for converting being disposed in the predistortion signal path; a component for combining the analog main signal or a processed version of the analog main signal with the analog predistortion signal or a processed version of the analog predistortion signal to form an analog combined signal, the component for combining being disposed in the main signal path; and a component for amplifying the analog combined signal or the processed version of the analog combined signal, the component for amplifying being disposed in the main signal path.

[0011] Certain aspects of the present disclosure provide a wireless communication method. The method generally includes: converting a digital main signal into an analog main signal via a first DAC in a main signal path; converting the digital predistortion signal into an analog predistortion signal via a second DAC in a predistortion signal path; combining the analog main signal and the analog predistortion signal via a combiner disposed in the main signal path to form an analog combined signal; processing the analog combined signal; and amplifying the processed analog combined signal via a power amplifier disposed in the main signal path.

[0012] To accomplish the foregoing and related ends, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features are indicative of but a few of the various ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order that the manner in which the above-described features of the present disclosure are understood in detail, a more particular description, briefly summarized above, may be obtained by reference to the various aspects, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only certain typical aspects of the disclosure and are therefore not to be considered limiting of its scope, as the description may admit to other equally effective aspects.

[0014] Figure 1 is an illustration of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0015] Figure 2 is a block diagram conceptually illustrating designs of example base stations (BSs) and user equipment (UEs) in which aspects of the present disclosure may be practiced.

[0016] Figure 3 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced.

[0017] Figure 4 is a block diagram of an example transmitter in which a predistortion signal is combined with a main signal before a digital-to-analog converter (DAC).

[0018] Figure 5 is a block diagram of an example transmitter having a predistortion signal path separate from a main signal path, the main signal path and the predistortion signal path each having a DAC, and wherein the predistortion signal is combined with the main signal after the DAC, in accordance with certain aspects of the present disclosure.

[0019] Figure 6A According to certain aspects of the present disclosure Figure 5 A block diagram of an example implementation of a transmitter is shown.

[0020] Figure 6B is a diagram illustrating a predistortion signal and a main signal as a combined signal and as separate signals, according to certain aspects of the present disclosure.

[0021] Figure 6C According to certain aspects of the present disclosure Figure 5 A block diagram of another example implementation of a transmitter is shown.

[0022] Figure 7 is a flow diagram of example operations for wireless communications in accordance with certain aspects of the present disclosure.

[0023] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0024] Certain aspects of the present disclosure relate to techniques and apparatus for wireless communications, such as a transmitting device with digital predistortion (DPD) capabilities. The transmitting device may have separate processing paths for a main signal and a predistortion signal. That is, separate digital-to-analog converters (DACs) (and potentially other separate components) may be used to process the main signal and the predistortion signal. Thus, the operating characteristics of the DACs (and other components) may be designed so that the circuit can process the signals more efficiently (e.g., with lower power) than a single signal path (where one DAC processes a combination of signals).

[0025] The various aspects of the disclosure are described more fully below with reference to the accompanying drawings. However, the disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the disclosure. Rather, these aspects are provided so that the disclosure will be thorough and complete, and the scope of protection of the disclosure will be fully conveyed to those skilled in the art. Based on the teachings herein, it will be understood by those skilled in the art that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the disclosure is intended to cover such devices or methods that are practiced using other structures, functionality, or structure and functionality in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein can be embodied by one or more elements of the claims.

[0026] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0027] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0028] Example Wireless System

[0029] Figure 1 An example wireless communication network 100 in which aspects of the present disclosure may be practiced is illustrated. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a fifth generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a fourth generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a second generation / third generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured for communication according to IEEE standards such as one or more of the 802.11 standards.

[0030] like Figure 1 As shown in FIG, a wireless communication network 100 may include several base stations (BSs) 110 a to 110 z (each also referred to herein individually as BS 110 or collectively as BS 110) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB), or some other terminology.

[0031] BS 110 may provide communication coverage for a particular geographic area (sometimes referred to as a "cell"), which may be stationary or mobile depending on the location of mobile BS 110. In some examples, BS 110 may be interconnected with each other and / or connected to one or more other BSs or network nodes (not shown) in wireless communication network 100 through various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.) using any suitable transport network. Figure 1In the example shown, BSs 110a, 110b, and 110c may be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x may be a pico BS for pico cell 102x. BSs 110y and 110z may be femto BSs for femto cells 102y and 102z, respectively. A BS may support one or more cells.

[0032] BS 110 communicates with one or more user equipment (UE) 120a to 120y (each also referred to herein individually as UE 120 or collectively as UE 120) in wireless communication network 100. A UE may be fixed or mobile and may also be referred to as a user terminal (UT), a mobile station (MS), an access terminal, a station (STA), a client, a wireless device, a mobile device, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a smartphone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet computer, a personal computer, or the like.

[0033] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a "transmitting entity" is an independently operated device or apparatus capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript "dn" indicates downlink, and the subscript "up" indicates uplink. N may be selected. up UEs are used for simultaneous transmission on the uplink, N dn UEs are used for simultaneous transmission on the downlink. up May or may not be equal to N dn , and N up and N dn It may be a static value or may change for each scheduling interval.Beam steering or some other spatial processing technique may be used at the BS 110 and the UE 120.

[0034] UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include relay stations (e.g., relay station 110r) (also referred to as relays, etc.) that receive transmissions of data and / or other information from an upstream station (e.g., BS 110a or UE 120r) and transmit the transmissions of data and / or other information to a downstream station (e.g., UE 120 or BS 110), or relay transmissions between UEs 120 to facilitate communication between the devices.

[0035] At any given moment, BS 110 can communicate on the downlink and uplink with one or more UEs 120. The downlink (i.e., forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., reverse link) is the communication link from UE 120 to BS 110. A UE 120 can also communicate peer-to-peer with another UE 120.

[0036] The wireless communication network 100 may use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. The BS 110 may be equipped with several (N ap A group of (N) antennas can be used to implement transmit diversity for downlink transmission and / or receive diversity for uplink transmission. u Each UE 120 may receive downlink transmissions and send uplink transmissions. Each UE 120 may send user-specific data to and / or receive user-specific data from the BS 110. Typically, each UE 120 may be equipped with one or more antennas. u The UEs 120 may have the same or different numbers of antennas.

[0037] The wireless communication network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to reduce costs) or multiple antennas (e.g., where the additional cost can be supported).

[0038] The network controller 130 (sometimes also referred to as a "system controller") can communicate with a group of BSs 110 and provide coordination and control for these BSs 110 (e.g., via backhaul). In some cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and / or a distributed unit (DU). In some aspects, the network controller 130 may communicate with a core network 132 (e.g., a 5G core network (5GC)), which provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network exposure functions, network repository functions, network slice selection functions, etc.

[0039] NR can use orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) on the uplink and downlink. NR can use time division duplexing (TDD) to support half-duplex operation. OFDM and single-carrier frequency division multiplexing (SC-FDM) divide the system bandwidth into multiple orthogonal subcarriers, which are also commonly called tones, frequency bins, etc. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers can depend on the system bandwidth. The system bandwidth can also be divided into multiple subbands. For example, one subband can cover multiple resource blocks (RBs).

[0040] In certain aspects of the present disclosure, BS 110 and / or UE 120 may include a transmitting device having a main signal path with a main digital-to-analog converter (DAC) and a predistortion signal path with a predistortion DAC, wherein the main signal in the main signal path after the main DAC may be combined with the predistortion signal in the predistortion path after the predistortion DAC, as described in more detail herein.

[0041] Figure 2 1 illustrates a BS 110a and a UE 120a (e.g., from Figure 1 Example components of a wireless communication network 100).

[0042] On the downlink, at BS 110a, transmit processor 220 may receive data from data source 212, control information from controller / processor 240, and / or possibly other data (e.g., from scheduler 244). Various types of data may be transmitted on different transport channels. For example, control information may be designated for the physical broadcast channel (PBCH), the physical control format indicator channel (PCFICH), the physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), the physical downlink control channel (PDCCH), the group common PDCCH (GCPDCCH), etc. Data may be designated for the physical downlink shared channel (PDSCH), etc. A medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for the exchange of control commands between wireless nodes. A MAC-CE may be carried in a shared channel, such as the PDSCH, the physical uplink shared channel (PUSCH), or the physical sidelink shared channel (PSSCH).

[0043] The processor 220 may process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols such as for a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a PBCH demodulation reference signal (DMRS), and a channel state information reference signal (CSI-RS).

[0044] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 may perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols, where applicable, and may provide an output symbol stream to a modulator (MOD) in a transceiver 232a-232t. Each modulator 232a-232t in the transceiver may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM) or the like) to obtain an output sample stream. Each transceiver 232a-232t may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. The downlink signals from the transceivers 232a-232t may be transmitted via antennas 234a-234t, respectively.

[0045] At UE 120a, antennas 252a-252r may receive downlink signals from BS 110a and may provide received signals to transceivers 254a-254r, respectively. Transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 may obtain received symbols from all demodulators in transceivers 254a-254r, perform MIMO detection on the received symbols (if applicable), and provide detected symbols. Receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE 120a to data sink 260, and provide decoded control information to controller / processor 280.

[0046] On the uplink, at UE 120a, a transmit processor 264 may receive and process data from a data source 262 (e.g., for a physical uplink shared channel (PUSCH)) and control information from a controller / processor 280 (e.g., for a physical uplink control channel (PUCCH)). The transmit processor 264 may also generate reference symbols for reference signals (e.g., for a sounding reference signal (SRS)). The symbols from the transmit processor 264 may be pre-decoded by a TX MIMO processor 266 (if applicable), further processed by a modulator (MOD) in transceivers 254a through 254r (e.g., for single carrier frequency division multiplexing (SC-FDM) etc.), and transmitted to BS 110a. At BS 110a, the uplink signal from UE 120a may be received by antenna 234, processed by demodulators in transceivers 232a-232t, detected by MIMO detector 236 (if applicable), and further processed by receive processor 238 to obtain decoded data and control information transmitted by UE 120a. Receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to a controller / processor 240.

[0047] Memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. Memories 242 and 282 may also interface with controllers / processors 240 and 280, respectively. Scheduler 244 may schedule UEs for data transmission on the downlink and / or uplink.

[0048] The antennas 252, processors 258, 264, 266 and / or controller / processor 280 of the UE 120a and / or the antennas 234, processors 220, 230, 238 and / or controller / processor 240 of the BS 110a may be used to perform the various techniques and methods described herein.

[0049] In certain aspects of the present disclosure, transceiver 232 and / or transceiver 254 may include a main signal path having a main digital-to-analog converter (DAC) and a predistortion signal path having a predistortion DAC, wherein the main signal in the main signal path following the main DAC may be combined with the predistortion signal in the predistortion path following the predistortion DAC, as described in more detail herein.

[0050] Example RF Transceiver

[0051] Figure 3is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of the present disclosure. RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a "transmit chain") for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a "receive chain") for receiving signals via antenna 306. When TX path 302 and RX path 304 share antenna 306, these paths can connect to the antenna via interface 308, which can include any of various suitable RF devices, such as switches, duplexers, diplexers, multiplexers, etc.

[0052] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC.

[0053] For certain aspects, DAC 310 can be implemented using any of a variety of suitable high-speed DAC topologies, such as a current-steering DAC. BBF 312 filters the baseband signal received from DAC 310, and mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to radio frequency). This frequency conversion process generates sum and difference frequencies between the LO frequency and the frequency of the baseband signal of interest. These sum and difference frequencies are referred to as "beat frequencies." The beat frequencies are typically in the RF range, so that the signal output by mixer 314 is typically an RF signal, which can be amplified by DA 316 and / or PA 318 before being transmitted by antenna 306. Although one mixer 314 is illustrated, multiple mixers can be used to upconvert the filtered baseband signal to one or more intermediate frequencies and then upconvert the intermediate frequency (IF) signal to a frequency for transmission.

[0054] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC that includes the TX path components, or may be a different RFIC. The RF signal received via the antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., downconvert). The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to a digital I and / or Q signal by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0055] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by TX frequency synthesizer 320, which may be buffered or amplified by amplifier 322 before being mixed with the baseband signal in mixer 314. Similarly, the receive LO may be generated by RX frequency synthesizer 332, which may be buffered or amplified by amplifier 334 before being mixed with the RF signal in mixer 326. For certain aspects, a single frequency synthesizer may be used for both TX path 302 and RX path 304. In certain aspects, TX frequency synthesizer 320 and / or RX frequency synthesizer 332 may include a frequency multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0056] Controller 336 (e.g., Figure 2 The controller / processor 280 in the RF transceiver circuit 300 may direct the operation of the RF transceiver circuit 300, such as transmitting signals via the TX path 302 and / or receiving signals via the RX path 304. The controller 336 may be a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. The memory 338 (e.g., Figure 2 Memory 282 in RF transceiver circuit 300 may store data and / or program code for operating RF transceiver circuit 300. Controller 336 and / or memory 338 may include control logic (eg, complementary metal oxide semiconductor (CMOS) logic).

[0057] Although Figure 1 、 Figure 2 and Figure 3A wireless communication network and components are provided as example applications in which certain aspects of the present disclosure may be implemented to facilitate understanding, although certain aspects described herein may be employed in any of a variety of other suitable systems.

[0058] Example transmitter with predistortion

[0059] Wireless communication devices can use digital predistortion (DPD) processing to mitigate device nonlinearities. For example, DPD can be used to effectively linearize the nonlinearities of power amplifiers in some transmitting devices. DPD works by sensing the nonlinearity at the output of the power amplifier and feeding this back into DPD logic, which generates an inverse nonlinearity in the digital domain. This inverse nonlinearity is applied to the digital input signal, effectively eliminating or at least reducing the nonlinear effects of the power amplifier in the transmitting device.

[0060] Figure 4 is a block diagram of an example transmitter 400. For certain aspects, transmitter 400 may be part of a transceiver and may have components similar to some components in RF transceiver circuit 300.

[0061] The transmitter 400 may include a combiner stage 404 configured to combine in-phase (I) and quadrature (Q) digital input signals 402 (labeled “I in [n]” and “Q in [n]”) is combined with the output signal from the digital predistortion (DPD) logic 406. Therefore, the combiner stage 404 may include two combiners, such as Figure 4 The digital input signals 402 may each be represented by a number (n) of bits (eg, n=14 bits), and the output signals from the DPD logic 406 may each be represented by a number (m) of bits (eg, m=9 bits).

[0062] The transmitter 400 may also include a DAC stage 408 (which may be similar to Figure 3 DAC 310). As shown, DAC stage 408 may include at least one quadrature DAC (labeled “DACQ”) for converting the combined quadrature digital signals from combiner stage 404 into quadrature analog signals, and at least one in-phase DAC (labeled “DACI”) for converting the combined in-phase digital signals from combiner stage 404 into in-phase analog signals. Thus, DAC stage 408 may have an input coupled to the output of combiner stage 404.

[0063] Transmitter 400 may also include a filter stage 410 (which may be similar to Figure 34. The DAC stage 408 may be coupled to a filter stage 410 (BBF 312) having an input coupled to the output of the DAC stage 408. The filter stage 410 may include at least one filter for the in-phase analog signal and at least one filter for the quadrature analog signal. The filters in the filter stage 410 may be any suitable type of filter, such as a baseband filter (BBF) or an intermediate frequency (IF) filter.

[0064] Transmitter 400 may also include a mixer stage 412 (which may be similar to Figure 3 The mixer stage 412 may include an in-phase mixer and a quadrature mixer, such as Figure 4 The I / Q local oscillator (LO) input of mixer stage 412 may be controlled based on a control signal (labeled “LO”) at a frequency synthesizer 414 (which may be similar to Figure 3 The in-phase LO for mixer stage 412 may be an unshifted version of the output of frequency synthesizer 414, and the quadrature LO for mixer stage 412 may be a phase-shifted version of the output of frequency synthesizer 414 that has been shifted by 90° using phase shifter 416.

[0065] Transmitter 400 may also include a combiner 418 to combine the in-phase and quadrature RF signals from mixer stage 412. Combiner 418 may have an input coupled to the output of mixer stage 412 and an input coupled to a RF mixer 418 that may be similar to Figure 3 The output of PA 318 is connected to the input of a power amplifier 420 (labeled "PA"). Power amplifier 420 may be configured to amplify the combined RF signal at the output of combiner 418 (eg, for transmission via one or more antennas).

[0066] In some aspects, as shown, transmitter 400 may further include a feedback receive path including an attenuator 422, another mixer stage 424, and an analog-to-digital converter (ADC) stage 428. Although not shown, the feedback receive path may also include one or more filter stages.

[0067] Attenuator 422 may have an input (optionally) coupled to the output of power amplifier 420 and may be configured to reduce the amplitude of the signal from the output of power amplifier 420 by 1 / G. Mixer stage 424 may have an I / Q LO input from the output of frequency synthesizer 414. The in-phase LO of the in-phase mixer of mixer stage 424 may be an unshifted version of the output of frequency synthesizer 414, and the quadrature LO of the quadrature mixer of mixer stage 424 may be a phase-shifted version of the output of frequency synthesizer 414 shifted by 90° using phase shifter 426. ADC stage 428 may have an input coupled to the output of mixer stage 424 and an output coupled to the feedback input of DPD logic 406. ADC stage 428 may be configured to convert the attenuated and downconverted RF signal from the output of power amplifier 420 into a digital I / Q signal.

[0068] The DPD logic 406 can effectively adjust the in-phase and quadrature digital input signals 402 to cancel or at least reduce the nonlinearity of the power amplifier 420. This can enable the transmitter 400 to push the power amplifier 420 closer to saturation and improve the efficiency of the transmitter 400. The DPD logic 406 generally operates by generating the inverse nonlinearity of the power amplifier 420 and applying this inverse nonlinearity as a predistortion signal to be combined with the digital input signal 402 by the combiner stage 404, thereby canceling or at least reducing the nonlinearity. Depending on the power amplifier type and power level, the DPD logic 406 can be implemented with different DPD algorithms and architectures.

[0069] The nonlinear operation in the DPD logic 406 extends the bandwidth of the combined signal by a factor of 3-5 compared to the bandwidth of the digital input signal 402 (also referred to as the "primary signal") alone. Because the predistortion signal should propagate to the power amplifier 420 with low dropout and high dynamic range, the bandwidth of other components in the transmitter 400 (e.g., the DAC in the DAC stage 408) should be designed to cover the wider bandwidth of the predistortion signal in addition to the bandwidth of the primary signal.

[0070] However, the increased bandwidth specification may create problems in other components in transmitter 400. For example, the increased bandwidth specification may place a lower limit on the sampling rate of the DAC in DAC stage 408 and / or other processing components in the transmit path. This may increase the power consumption of transmitter 400 (e.g., due to the use of high digital voltages to support high sampling rate operation).

[0071] Therefore, to reduce power consumption in such devices, certain aspects of the present disclosure are directed to wireless transmitting devices with DPD capability in which the main signal path and the predistortion signal path have been separated to route the main signal through a main DAC and the predistortion signal through a predistortion DAC.

[0072] Figure 5 is a block diagram of an example transmitter 500 according to certain aspects of the present disclosure. Transmitter 500 may be similar to transmitter 400, but has a main signal path 510 and a separate predistortion signal path 512, where the predistortion signal path has its own predistortion signal DAC.

[0073] As shown, the main signal path 510 generally includes a first DAC stage 502 (also referred to as a "main signal DAC stage"), a power amplifier 508, and a combiner stage 506. In some aspects, the power amplifier 508 can be similar to Figure 4 According to certain aspects, the combiner stage 506 can be disposed in the main signal path 510 between the output of the first DAC stage 502 and the input of the power amplifier 508.

[0074] According to certain aspects, the main signal path 510 may also include a transmit chain 504 coupled between the output of the first DAC stage 502 and the input of the power amplifier 508. For certain aspects, a combiner stage 506 may be disposed in the main signal path 510 between the output of the first DAC stage 502 and the input of the transmit chain 504. In certain other aspects, such as Figure 5 In the aspect shown in , a combiner stage 506 may be provided in the transmit chain 504 .

[0075] The predistortion signal path 512 may include DPD logic 514 and a second DAC stage 516 (also referred to as a "predistortion signal DAC stage" or a "supplemental DAC stage"). In some aspects, the DPD logic 514 may be similar to Figure 4 5. For certain aspects, the input of the first DAC stage 502 can be coupled to the input of the DPD logic 514, and the output of the DPD logic 514 can be coupled to the input of the second DAC stage 516. According to certain aspects, the transmitter 500 can also include a feedback path 518 configured to feed the output of the power amplifier 508 back to the feedback input of the DPD logic 514. The DPD logic 514 can be configured to adjust for nonlinearities of the power amplifier 508.

[0076] The combiner stage 506 can be configured to combine the main signal with the predistortion signal in the predistortion signal path 512 and the main signal in the main signal path 510 after they have passed through separate DACs (e.g., the first DAC stage 502 and the second DAC stage 516, respectively). That is, the combiner stage 506 can combine the analog main signal (or a processed version of the analog main signal) with the analog predistortion signal (or a processed version of the analog predistortion signal) to form an analog combined signal. As used herein, a "processed version" of an analog signal generally refers to an analog signal that has undergone additional signal processing (e.g., filtering, upconversion, downconversion, amplification, attenuation, phase shifting, etc.).

[0077] By separating the main signal from the predistortion signal during digital-to-analog conversion, power consumption of the transmitter 500 (and more specifically, the first DAC stage 502 compared to the DAC stage 408 ) may be reduced, as discussed in more detail below.

[0078] The implementation described below may be similar to transmitter 400, but wherein the main signal path 510 has a first DAC stage 502 and the predistortion signal path 512 has a second DAC stage, wherein the analog main signal and the analog predistortion signal are combined after digital-to-analog conversion in their separate paths. Therefore, the above description of the Figure 4 Description of some of the components discussed.

[0079] Figure 6A According to certain aspects of the present disclosure Figure 5 8 is a block diagram of an example implementation 600A of the transmitter 500.

[0080] As shown, in some aspects, the first DAC stage 502 and the second DAC stage 516 can each include multiple DACs. For example, the first DAC stage 502 and the second DAC stage 516 can each include at least one DAC (labeled "DACQ") for converting a quadrature digital input signal and at least one DAC (labeled "DACI") for converting an in-phase digital input signal. In some aspects, the DACs in the first DAC stage 502 can be of the same DAC type (e.g., having the same DAC architecture or topology) as the DACs in the second DAC stage 516. For example, the DACs in the first DAC stage 502 and the DACs in the second DAC stage 516 can be current steering DACs.

[0081] Figure 6B Conceptually illustrates splitting the spectrum of a combined signal into a main signal and a predistortion signal according to certain aspects of the present disclosure.The x-axis of each graph represents frequency, and the y-axis of each graph represents signal power level.

[0082] Graph 650 illustrates an example combined signal spectrum, illustrating the bandwidth of the main portion of the combined signal (labeled "BW") and the wider bandwidth of the predistortion portion of the combined signal (labeled "3BW to 5BW"). This combined signal spectrum in graph 650 is an example of the high-bandwidth and high-dynamic-range signal that DAC stage 408 should be designed to handle. However, according to aspects of the present invention, the combined signal represented by graph 650 can be split into two signals: the main signal represented by the spectrum in graph 660 and the predistortion signal (e.g., a DPD signal) represented by the spectrum in graph 670. Thus, the main DAC in the main signal path can be designed to handle the higher power, higher dynamic range, and narrower bandwidth of the main signal in graph 660, while the supplementary DAC in the predistortion signal path can be designed (e.g., with lower resolution than the main DAC, but with a higher operating frequency) to handle the lower power, lower dynamic range, and wider bandwidth signal in graph 670.

[0083] In implementation 600A, the main signal can propagate along the main signal path 510, and the predistortion signal can propagate along the predistortion signal path 512. That is, the main signal can be converted from a digital signal to an analog signal by the first DAC stage 502, and the predistortion signal can be converted from a digital signal to an analog signal by the second DAC stage 516. The combiner stage 506 can then combine the analog versions of the main signal and the predistortion signal.

[0084] As shown in graph 670, the predistortion signal has a bandwidth that is approximately 3 to 5 times wider than the bandwidth of the main signal (labeled "BW"). Therefore, the second DAC stage 516 can be configured to have a wider bandwidth than the first DAC stage 502 to allow the second DAC stage 516 to process the predistortion signal. For example, in some aspects, the bandwidth of the second DAC stage 516 can be 3 to 5 times wider than the bandwidth of the first DAC stage 502.

[0085] On the other hand, because the bandwidth of the main signal is smaller than the bandwidth of the combined signal, the first DAC stage 502 may be configured with a reduced operating frequency (eg, a reduced sampling frequency or sampling rate compared to the operating frequency used to process the combined signal).

[0086] Additionally, as shown in graph 670, the power level of the predistortion signal is significantly lower than the power level of the main signal. For example, the peak power level of the predistortion signal may be approximately 20 dBm / MHz lower than the peak power level of the main signal. Therefore, in some aspects, the second DAC stage 516 may be configured to have a lower operating power than the first DAC stage 502. The second DAC stage 516 may also be configured to have a lower resolution than the first DAC stage 502. For example, the DAC in the first DAC stage 502 may be a 12-bit DAC, while the DAC in the second DAC stage 516 may be a 6-bit DAC. In some aspects, the second DAC stage 516 may be configured to use a lower full-scale current than the first DAC stage 502. Because the second DAC stage 516 has reduced performance specifications (e.g., lower resolution), the second DAC stage 516 may be implemented with one or more smaller DACs, thereby reducing area consumption (e.g., the area occupied by the transmitter circuit).

[0087] Additionally, the number of bits output by the DPD logic 514 may be reduced, which may reduce the power consumption of the DPD logic 514. For example, because the DAC stage 408 is configured to convert high bandwidth signals, Figure 4 The DPD logic 406 in the DPD logic 406 may perform a large amount of digital arithmetic operations to output a high-resolution predistortion signal so as not to corrupt the main signal during digital-to-analog conversion. The digital arithmetic operations contribute to the power consumption of the DPD logic 406. However, because the second DAC stage 516 can be configured to process signals with lower power levels (e.g., lower dynamic range), the DPD logic 514 can output fewer bits. Therefore, the DPD logic 514 may consume less power and / or have a smaller footprint than the DPD logic 406.

[0088] As shown, the transmit chain 504 may be coupled between the output of the first DAC stage 502 and the input of the power amplifier 508. In some aspects, the transmit chain 504 may include filters, mixers, and combiners, such as Figure 3 BBF 312, mixer 314 and DA 316 or Figure 4 The filter stage 410, the mixer stage 412, and the combiner 418. In some aspects, the feedback path 518 may include an attenuator, a mixer, and an ADC, such as, for example Figure 4 attenuator 422, mixer stage 424 and ADC stage 428.

[0089] In the example implementation 600A, the combiner stage 506 is disposed in the main signal path 510 between the output of the first DAC stage 502 and the transmit chain 504. In this case, the combiner stage 506 can be coupled between the output of the first DAC stage 502 and the input of the filter stage 410, and the combiner stage 506 can be configured to combine the analog I / Q main signal at the output of the first DAC stage 502 with the analog I / Q predistortion signal at the output of the second DAC stage 516.

[0090] Figure 6C According to certain aspects of the present disclosure Figure 5 Implementation 600C is a block diagram of another example implementation 600C of transmitter 500. Implementation 600C may be similar to implementation 600A, but wherein combiner stage 506 has a first set of inputs coupled to the outputs (as opposed to the inputs) of filter stage 410. Implementation 600C may also include an additional filter stage 632 in predistortion signal path 512. In this case, combiner stage 506 may have a second set of inputs coupled to the outputs of filter stage 632 and may be configured to combine filtered (e.g., processed) versions of the analog main signal and the analog predistortion signal. Additionally, in this case, filter stage 410 may include a narrowband filter to filter out noise outside the bandwidth of the main signal, and filter stage 632 may include a filter wider than the bandwidth (e.g., a wideband filter).

[0091] Although not illustrated, persons of ordinary skill in the relevant art will appreciate that, in another specific implementation, the combiner stage 506 may be coupled between the output of the mixer stage 412 and the input of the power amplifier 508. In this case, the predistortion signal path 512 may also include another mixer stage having an input coupled to the output of the filter stage 632, and the output of this another mixer stage may be coupled from the predistortion signal path 512 to the input of the combiner stage 506.

[0092] Aspects of the present disclosure can provide reduced power consumption compared to some other transmitter architectures.The reduced power consumption can also reduce the overall heat generated by the transmitter, allowing for thermal design relaxation.

[0093] Example Operations for Wireless Communications

[0094] Figure 7 is a flow diagram of example operations 700 for wireless communication, in accordance with certain aspects of the present disclosure. Operations 700 may be performed, for example, by a transmitter (eg, transmitter 500, or implementations 600A or 600C) having digital predistortion (DPD) processing capabilities.

[0095] Operations 700 may begin at block 702 by converting a digital main signal into an analog main signal via a first digital-to-analog converter (DAC) (e.g., a DAC in first DAC stage 502) in a main signal path (e.g., main signal path 510). Operations 700 may also involve, at block 704, converting the digital predistortion signal into an analog predistortion signal via a second DAC (e.g., a DAC in second DAC stage 516) in a predistortion signal path (e.g., predistortion signal path 512). Operations 700 may also involve, at block 706, combining the analog main signal or a processed version of the analog main signal with the analog predistortion signal or a processed version of the analog predistortion signal via a combiner disposed in the main signal path (e.g., a combiner in combiner stage 506) to form an analog combined signal. Operations 700 may also involve amplifying the analog combined signal or the processed version of the analog combined signal via a power amplifier disposed in the main signal path (e.g., power amplifier 508) at block 708.

[0096] According to certain aspects, operations 700 also include filtering the analog main signal (e.g., using the filter in filtering stage 410) to generate a filtered version of the analog main signal, and filtering the analog predistortion signal (e.g., using the filter in filtering stage 632) to generate a filtered version of the analog predistortion signal. In this case, the combining at block 706 may involve combining the filtered version of the analog main signal with the filtered version of the analog predistortion signal to form an analog combined signal.

[0097] According to certain aspects, operations 700 also include: filtering the analog main signal (e.g., using the filter in filtering stage 410) to generate a filtered version of the analog main signal; filtering the analog predistortion signal (e.g., using the filter in filtering stage 632) to generate a filtered version of the analog predistortion signal; upconverting the filtered version of the analog main signal (e.g., using a first mixer in the main signal path, such as the mixer in mixer stage 412) to generate an upconverted version of the analog main signal; and upconverting the filtered version of the analog predistortion signal (e.g., using a second mixer in the predistortion signal path) to generate an upconverted version of the analog predistortion signal. In this case, the combining at block 706 may involve combining the upconverted version of the analog main signal with the upconverted version of the analog predistortion signal to form an analog combined signal.

[0098] According to certain aspects, the first DAC is a different DAC type than the second DAC.For other aspects, the first DAC is the same DAC type as the second DAC.

[0099] According to certain aspects, the second DAC has a wider bandwidth than the first DAC.

[0100] According to certain aspects, the second DAC has lower operating power than the first DAC, has a higher sampling rate than the first DAC, has a lower resolution than the first DAC, and / or uses a lower full-scale current than the first DAC.

[0101] According to certain aspects, operations 700 further include applying digital predistortion to the digital primary signal to generate a digital predistortion signal using digital predistortion logic (eg, DPD logic 514) in a predistortion signal path. For certain aspects, the applied digital predistortion is based on the amplified analog combined signal.

[0102] Example aspects

[0103] In addition to the above aspects, specific combinations of the aspects are also within the scope of the present disclosure, and details of some of the specific combinations are as follows:

[0104] Aspect 1: An apparatus for wireless communication, comprising: a main signal path, the main signal path including a first digital-to-analog converter (DAC), a power amplifier, and a combiner, the combiner being arranged in the main signal path between the output of the first DAC and the input of the power amplifier; and a predistortion signal path, the predistortion signal path including a second DAC, wherein the combiner is configured to combine a predistortion signal in the predistortion signal path with a main signal in the main signal path.

[0105] Aspect 2: An apparatus according to Aspect 1, wherein the main signal path further comprises a transmission chain coupled between the output of the first DAC and the input of the power amplifier, and wherein the combiner is arranged in the main signal path between the output of the first DAC and the transmission chain.

[0106] Aspect 3: The apparatus of aspect 1, wherein the main signal path further comprises a transmit chain coupled between the output of the first DAC and the input of the power amplifier, and wherein the combiner is disposed in the transmit chain.

[0107] Aspect 4: The apparatus of aspect 3, wherein the transmit chain comprises a filter, and wherein an input of the combiner is coupled to an output of the filter.

[0108] Aspect 5: The apparatus of aspect 3 or aspect 4, wherein the transmit chain comprises a mixer, and wherein an input of the combiner is coupled to an output of the mixer.

[0109] Aspect 6: The apparatus of any preceding aspect, wherein the first DAC is the same DAC type as the second DAC.

[0110] Aspect 7: The apparatus of aspect 6, wherein the first DAC and the second DAC comprise current steering DACs.

[0111] Aspect 8: The apparatus of any preceding aspect, wherein the second DAC is configured to have a wider bandwidth than the first DAC.

[0112] Aspect 9: The apparatus of any preceding aspect, wherein a bandwidth of the second DAC is 3 to 5 times wider than a bandwidth of the first DAC.

[0113] Aspect 10: The apparatus of any preceding aspect, wherein the second DAC is configured to have at least one of: lower operating power than the first DAC; a higher sampling rate than the first DAC; or a lower resolution than the first DAC.

[0114] Aspect 11: The apparatus of any preceding aspect, wherein the second DAC is configured to use a lower full-scale current than the first DAC.

[0115] Aspect 12: An apparatus according to any of the preceding aspects, wherein the predistortion signal path further comprises digital predistortion (DPD) logic, wherein an input of the first DAC is coupled to an input of the DPD logic, wherein the DPD logic is configured to adjust for nonlinearity of the power amplifier, and wherein an output of the DPD logic is coupled to an input of the second DAC.

[0116] Aspect 13: A wireless communication method, comprising: converting a digital main signal into an analog main signal via a first digital-to-analog converter (DAC) in a main signal path; converting a digital predistortion signal into an analog predistortion signal via a second DAC in a predistortion signal path; combining the analog main signal or a processed version of the analog main signal with the analog predistortion signal or a processed version of the analog predistortion signal to form an analog combined signal via a combiner provided in the main signal path; and amplifying the analog combined signal or the processed version of the analog combined signal via a power amplifier provided in the main signal path.

[0117] Aspect 14: The method according to Aspect 13 further includes: filtering the analog main signal to generate a filtered version of the analog main signal; and filtering the analog predistortion signal to generate a filtered version of the analog predistortion signal, wherein the combination includes combining the filtered version of the analog main signal with the filtered version of the analog predistortion signal to form the analog combined signal.

[0118] Aspect 15: The method according to Aspect 13 further includes: filtering the analog main signal to generate a filtered version of the analog main signal; filtering the analog predistortion signal to generate a filtered version of the analog predistortion signal; up-converting the filtered version of the analog main signal to generate an up-converted version of the analog main signal; and up-converting the filtered version of the analog predistortion signal to generate an up-converted version of the analog predistortion signal, wherein the combining includes combining the up-converted version of the analog main signal with the up-converted version of the analog predistortion signal to form the analog combined signal.

[0119] Aspect 16: The method of any one of aspects 13 to 15, wherein the first DAC is a different DAC type than the second DAC.

[0120] Aspect 17: The method of any one of aspects 13 to 16, wherein the second DAC has a wider bandwidth than the first DAC.

[0121] Aspect 18: The method of any one of aspects 13 to 17, wherein the second DAC has at least one of: lower operating power than the first DAC; a higher sampling rate than the first DAC; or a lower resolution than the first DAC.

[0122] Aspect 19: The method according to any one of Aspects 13 to 18 further includes: utilizing digital predistortion logic in the predistortion signal path to apply digital predistortion to the digital main signal to generate the digital predistortion signal, wherein the applied digital predistortion is based on the amplified analog combined signal.

[0123] Aspect 20: An apparatus for wireless communication, comprising: a first component for converting a digital main signal into an analog main signal, the first component for converting being arranged in a main signal path; a second component for converting a digital predistortion signal into an analog predistortion signal, the second component for converting being arranged in a predistortion signal path; a component for combining the analog main signal or a processed version of the analog main signal with the analog predistortion signal or a processed version of the analog predistortion signal to form an analog combined signal, the component for combining being arranged in the main signal path; and a component for amplifying the analog combined signal or the processed version of the analog combined signal, the component for amplifying being arranged in the main signal path.

[0124] in conclusion

[0125] This paper describes an architecture for addressing increased power consumption in transmitters with digital predistortion (DPD) processing. Certain aspects of the present disclosure provide techniques and circuits for wireless communication using a transmitter capable of DPD and having a main signal path separate from the DPD signal path, with the DPD signal path and the main signal path each including a different digital-to-analog converter (DAC). By separating the signal paths, the operating characteristics of the respective DACs used to process the signals can be designed so that each DAC can process its respective signal more efficiently and with better overall performance and lower power consumption and real estate than a single DAC processing a combination of the main and DPD signals.

[0126] The above description provides examples and does not limit the scope, applicability or examples set forth in the claims. Without departing from the scope of this disclosure, the functions and arrangements of the elements discussed may be changed. Various examples may omit, replace or add various processes or components as appropriate. For example, the methods described may be performed in a different order than described, and various steps may be added, omitted or combined. In addition, the features described with respect to some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement an apparatus or practice method. In addition, the scope of this disclosure is intended to cover such apparatus or methods practiced using other structures, functional functions or structures and functionality in addition to or different from the various aspects of the disclosure given herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims.

[0127] The various operations of the above methods may be performed by any suitable means capable of performing the corresponding functions. Such means may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where there are operations illustrated in the accompanying drawings, these operations may have corresponding corresponding means plus functional components. For example, a means for converting a digital primary signal into an analog primary signal may include a DAC, such as a Figure 5 、 Figure 6A or Figure 6C As another example, the component for converting the digital predistortion signal into an analog predistortion signal may include a DAC such as Figure 5 、 Figure 6A or Figure 6C The DAC (eg, DACI or DACQ) in the second DAC stage 516 of FIG. The means for combining may include a combiner such as Figure 5 、 Figure 6A or Figure 6C and the means for amplifying may comprise an amplifier such as Figure 5 、 Figure 6A or Figure 6C power amplifier 508.

[0128] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). By way of example, "at least one of a, b, or c" is intended to encompass: a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and cCc, or any other ordering of a, b, and c).

[0129] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0130] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A device for wireless communication, the device comprising: a main signal path comprising a first digital-to-analog converter (DAC), a power amplifier, and a combiner disposed in the main signal path between an output of the first DAC and an input of the power amplifier; and A predistortion signal path includes a second DAC, wherein the combiner is configured to combine a predistortion signal in the predistortion signal path with a main signal in the main signal path.

2. The apparatus of claim 1 , wherein the main signal path further comprises a transmit chain coupled between the output of the first DAC and the input of the power amplifier, and wherein the combiner is disposed in the main signal path between the output of the first DAC and the transmit chain.

3. The apparatus of claim 1, wherein the main signal path further comprises a transmit chain coupled between the output of the first DAC and the input of the power amplifier, and wherein the combiner is disposed in the transmit chain.

4. The apparatus of claim 3, wherein the transmit chain comprises a filter, and wherein an input of the combiner is coupled to an output of the filter.

5. The apparatus of claim 3, wherein the transmit chain comprises a mixer, and wherein an input of the combiner is coupled to an output of the mixer.

6. The apparatus of claim 1, wherein the first DAC is the same DAC type as the second DAC. 7 . The apparatus of claim 6 , wherein the first DAC and the second DAC comprise current steering DACs. 8 . The apparatus of claim 1 , wherein the second DAC is configured to have a wider bandwidth than the first DAC. 9 . The device of claim 8 , wherein a bandwidth of the second DAC is 3 to 5 times wider than a bandwidth of the first DAC.

10. The apparatus of claim 1 , wherein the second DAC is configured to have at least one of the following: Lower operating power than the first DAC; A higher sampling rate than the first DAC; or Lower resolution than the first DAC. 11 . The apparatus of claim 1 , wherein the second DAC is configured to use a lower full-scale current than the first DAC.

12. The apparatus of claim 1 , wherein the predistortion signal path further comprises digital predistortion (DPD) logic, wherein an input of the first DAC is coupled to an input of the DPD logic, wherein the DPD logic is configured to adjust for nonlinearities of the power amplifier, and wherein an output of the DPD logic is coupled to an input of the second DAC.

13. A method of wireless communication, the method comprising: converting the digital main signal into an analog main signal via a first digital-to-analog converter (DAC) in the main signal path; converting the digital predistortion signal into an analog predistortion signal via a second DAC in the predistortion signal path; combining the analog main signal or a processed version of the analog main signal with the analog predistortion signal or a processed version of the analog predistortion signal via a combiner disposed in the main signal path to form an analog combined signal; and The analog combined signal or a processed version of the analog combined signal is amplified via a power amplifier disposed in the main signal path.

14. The method according to claim 13, further comprising: filtering the analog host signal to generate a filtered version of the analog host signal; as well as The analog predistortion signal is filtered to generate a filtered version of the analog predistortion signal, wherein the combining includes combining the filtered version of the analog main signal with the filtered version of the analog predistortion signal to form the analog combined signal.

15. The method according to claim 13, further comprising: filtering the analog host signal to generate a filtered version of the analog host signal; filtering the analog predistortion signal to generate a filtered version of the analog predistortion signal; upconverting the filtered version of the analog host signal to generate an upconverted version of the analog host signal; as well as The filtered version of the analog predistortion signal is upconverted to generate an upconverted version of the analog predistortion signal, wherein the combining comprises combining the upconverted version of the analog main signal with the upconverted version of the analog predistortion signal to form the analog combined signal.

16. The method of claim 13, wherein the first DAC is a different DAC type than the second DAC.

17. The method of claim 13, wherein the second DAC has a wider bandwidth than the first DAC.

18. The method of claim 13, wherein the second DAC has at least one of the following: Lower operating power than the first DAC; A higher sampling rate than the first DAC; or Lower resolution than the first DAC.

19. The method according to claim 13, further comprising: Digital predistortion is applied to the digital primary signal to generate the digital predistortion signal using digital predistortion logic in the predistortion signal path, wherein the applied digital predistortion is based on the amplified analog combined signal.

20. An apparatus for wireless communication, the apparatus comprising: a first component for converting a digital main signal into an analog main signal, the first component for converting being arranged in a main signal path; a second component for converting the digital predistortion signal into an analog predistortion signal, the second component for converting being arranged in the predistortion signal path; means for combining the analog main signal or a processed version of the analog main signal with the analog predistortion signal or a processed version of the analog predistortion signal to form an analog combined signal, the means for combining being arranged in the main signal path; and Means for amplifying the analogue combined signal or a processed version of the analogue combined signal, the means for amplifying being arranged in the main signal path.

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