A peak current detection circuit applied to a BUCK

Abstract

The application provides a peak current detection circuit applied to a BUCK, which detects the current I flowing through the inductor of the BUCK chip by detecting the potential of the SW output terminal between the upper power tube and the lower power tube of the power tube of the BUCK chip L The peak current detection circuit comprises a connected reference current source, a current mirror circuit, a bias circuit, a reference voltage circuit, an adjusting circuit and a high voltage protection circuit. The application converts the slight voltage change of SW into significant current change for detection by the MOS tube working in the saturation region with large transconductance, thereby improving the sensitivity of the circuit detection. The protection circuit is protected from being burned by large voltage by the reasonable design of introducing DMOS, and is applicable to wide input voltage. The application can be applied to the case of wide input voltage, and the current detection sensitivity is high. In practical application, the circuit can normally work under the input of 3-40V.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and particularly relates to a peak current detection circuit applied to BUCK. BACKGROUND

[0002] Peak current detection is of great significance in the work of power management chip. For the power management chip BUCK, the span of input voltage is very large, which may be from several volts to several tens of volts, so the detection circuit suitable for wide input voltage is very important in practical application. In addition, the sensitivity of peak current detection is also crucial, and too low sensitivity may lead to reduced performance of the chip, or even chip burnout.

[0003] Therefore, it is very important to design a peak current detection circuit with wide input and high sensitivity. SUMMARY

[0004] The present application is to solve the problem of peak current detection sensitivity of BUCK, and provides a peak current detection circuit applied to BUCK, which converts the small voltage change of SW into significant current change for detection by using MOS tube working in saturation region with large transconductance, thereby improving the sensitivity of circuit detection; by introducing DMOS through reasonable design, the circuit is protected from being burned by large voltage, and is suitable for wide input voltage. The present application can be applied to the case of wide input voltage, and the current detection sensitivity is high; in practical application, the circuit can work normally under 3-40V input.

[0005] The present application provides a peak current detection circuit applied to BUCK, which detects the current I flowing through the BUCK chip inductor by detecting the potential of the SW output end between the upper power tube and the lower power tube of the BUCK chip power tube. L The drain of the upper power tube is connected to the PVIN pin of the BUCK chip, the source of the upper power tube is connected to the SW output end, one end of the BUCK chip inductor is connected to the SW output end, and the other end outputs VOUT and is connected to the capacitor C L which is grounded.

[0006] The peak current detection circuit includes a connected reference current source, a current mirror circuit, a bias circuit and a reference voltage circuit connected to the output end of the current mirror circuit, a trimming circuit, an input comparison circuit connected to the reference voltage circuit and the SW output end, and a high voltage protection circuit connected to the input comparison circuit, and the bias circuit, the reference voltage circuit and the input comparison circuit are connected to the PVIN pin of the BUCK chip.

[0007] The reference current source provides a reference current I0, the current mirror circuit proportionally replicates the reference current I0 to the bias circuit, the reference voltage circuit and the trimming circuit, the bias circuit provides a static working point, the reference voltage circuit provides a reference voltage for comparison, the input comparison circuit compares the voltages and judges whether the peak current of the BUCK chip exceeds a preset value, the trimming circuit is connected with a Trim pin and adjusts the peak current detection circuit, and the high-voltage protection circuit avoids high-voltage damage to elements in the input comparison circuit.

[0008] The current mirror circuit comprises gate-interconnected NMOS tubes NM1, NM2, NM3 and NM4; the gate and the drain of the tube NM1 are connected after being interconnected, the source is grounded; the sources of the tubes NM2, NM3 and NM4 are grounded, the drain of the tube NM2 is connected with the bias circuit, the drain of the tube NM3 is connected with the trimming circuit, and the drain of the tube NM4 is connected with the reference voltage circuit; the currents flowing through the tubes NM1, NM2, NM3 and NM4 are I1, I2, I3 and I4 respectively;

[0009] The reference voltage circuit comprises a resistor R1 connected with a PVIN pin and an NDMOS tube NMd2 connected with the other end of the resistor R1, the current of the resistor R1 is I5, the gate of the tube NMd2 is connected with a working voltage VDD, the drain is connected with the resistor R1, and the source is connected with the drain of the tube NM4;

[0010] The resistor R1 and the tube NMd2 are connected at a point C, and the input comparison circuit compares the potentials of the point C and the SW output end to judge whether the peak current of the BUCK chip exceeds a preset value; when the output OC_OUT of the input comparison circuit is a high level, the peak current of the BUCK chip exceeds the preset value; when the output OC_OUT of the input comparison circuit is a low level, the peak current of the BUCK chip is lower than the preset value;

[0011] The high-voltage protection circuit is a PDMOS tube.

[0012] As a preferred mode, the input comparison circuit comprises NMOS tubes NM7 and NM8 whose drains are connected with a PVIN pin respectively, PMOS tubes PM3 and PM4 whose sources are connected with the PVIN pin respectively, a comparator U1 connected with the tubes PM3 and PM4 respectively, a resistor R2 connected with the drain of the tube PM3 at one end and grounded at the other end, and a resistor R3 connected with the drain of the tube PM4 at one end and grounded at the other end.

[0013] The tube NM7 is connected with the C point, and the source is connected with the tube PM3 gate and the drain; the tube PM3 drain is connected with the comparator U1 positive input end and the resistor R2 connection intersection point A, and the tube PM4 drain is connected with the comparator U1 negative input end and the resistor R3 connection intersection point B; the tube NM8 gate is connected with the SW output end, and the source is connected with the tube PM4 gate and the drain;

[0014] The tube PM3 and the tube PM4 provide the static working point for the tube NM7 and the tube NM8 respectively;

[0015] R2=R3=R0, the current flowing through the tube NM7 and the tube PM3 is combined and then flows through the resistor R2, and the current is I A ; the current flowing through the tube NM8 and the tube PM4 is combined and then flows through the resistor R3, and the current is I B ;

[0016] The potential of the C point is PVIN-I5*R1, and the potential of the SW output end is PVIN-I L R top , wherein R top is the on-resistance of the BUCK chip power tube upper tube;

[0017] When the potential of the SW output end is greater than the potential of the C point, PVIN-I L R top >PVIN-I5*R1, I B >I A , the potential of the B point is greater than the potential of the A point, the current flowing through the inductor does not exceed I5*R1 / R top , and the output OC_OUT is low level;

[0018] When the potential of the SW output end is less than the potential of the C point, PVIN-I L R top <PVIN-I5*R1, I A >I B , the potential of the A point is greater than the potential of the B point, the current flowing through the inductor exceeds I5*R1 / R top , and the output OC_OUT is high level;

[0019] The peak current detected by the peak current detection circuit is I5*R1 / R top .

[0020] The peak current detection circuit applied to the BUCK, as a preferred mode, the high-voltage protection circuit includes the PDMOS tube PMd1 connected between the C point and the tube NM7, the PDMOS tube PMd2 connected between the SW output end and the tube NM8, the PDMOS tube PMd4 connected between the tube PM3 and the A point, and the PDMOS tube PMd5 connected between the tube PM4 and the B point;

[0021] The drain of the tube PMd1 is connected with point C, the source is connected with the gate of the tube NM7, and the gate is connected with the source of the tube NM7; the drain of the tube PMd2 is connected with the SW output end, the source is connected with the gate of the tube NM8, and the gate is connected with the source of the tube NM8; the drain of the tube PMd4 is connected with point A, the source is connected with the drain of the tube PM3, and the gate is connected with the bias circuit; the drain of the tube PMd5 is connected with point B, the source is connected with the drain of the tube PM4, and the gate is connected with the gate of the tube PMd4 and the bias circuit.

[0022] The tube PMd1 and the tube PMd2 protect the tube NM7 and the tube NM8 respectively, and the tube PMd4 and the tube PMd5 protect the tube NM7, the tube PM3, the tube NM8 and the tube PM4 respectively.

[0023] The current flowing through the tube NM7 and the tube PM3 is merged and then flows through the tube PMd4 and the resistance R2 in sequence, and the current is I A ; the current flowing through the tube NM8 and the tube PM4 is merged and then flows through the tube PMd5 and the resistance R3 in sequence, and the current is I B .

[0024] The peak current detection circuit applied to the BUCK, as a preferred mode, the bias circuit comprises a PMOS tube PM2, a PDMOS tube PMd3 and an NDMOS tube NMd1 connected with the PVIN pin in sequence.

[0025] The source of the tube PM2 is connected with the PVIN pin, and the drain and the gate are connected with the source of the tube PMd3; the gate and the drain of the tube PMd3 are connected with the drain of the tube NMd1, and the gate of the tube PMd3 is connected with the gate of the tube PMd4 and the gate of the tube PMd5.

[0026] The gate of the tube NMd1 is connected with the voltage VDD, and the source is connected with the drain of the tube NM2.

[0027] The peak current detection circuit applied to the BUCK, as a preferred mode, I1=I2=kI3=I4=I0, wherein, k is a proportional coefficient.

[0028] The peak current detection circuit applied to the BUCK, as a preferred mode, the trimming circuit comprises a PMOS tube PM1 with the gate connected with the Trim pin, and the source of the tube PM1 is connected with the source of the tube NMd2 and the drain of the tube NM3.

[0029] When the Trim pin outputs a high level, the tube PM1 is turned off, the current I5=I4=I0 flowing through the tube NMd2 and the resistance R1, and the detected peak current is I0*R1 / R top .

[0030] When the Trim pin outputs a low level, the tube PM1 is turned on, and the current flowing through the tube NMd2 and the resistor R1 is:

[0031]

[0032] The peak current detection circuit applied to the BUCK has the following advantages:

[0033]

[0034] The preset peak current value is improved:

[0035]

[0036] The peak current detection circuit applied to the BUCK has the following advantages: by adjusting the value of k, at least one trimming circuit is additionally added to perform multi-stage trimming.

[0037] The peak current detection circuit applied to the BUCK has the following advantages: the gate of the upper power tube is connected to the upper tube driver, the source is connected to the drain of the lower power tube, the gate of the lower power tube is connected to the lower tube driver, the source is connected to the ground, and the source of the upper power tube and the drain of the lower power tube are both connected to the SW output end.

[0038] The peak current detection circuit applied to the BUCK has the following advantages:

[0039] The peak current detection circuit applied to the BUCK has the following advantages: by adjusting the value of k, at least one trimming circuit is additionally added to perform multi-stage trimming. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 The BUCK chip circuit framework diagram of the peak current detection circuit applied to the BUCK;

[0041] Figure 2 The specific circuit diagram of the peak current detection circuit applied to the BUCK. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments.

[0043] Embodiment 1

[0044] As shown in Figure 1 , 2 , a peak current detection circuit applied to a BUCK, the principle of the circuit is that the potential of SW can correspond to the current flowing through the inductor. When the upper power tube is turned on and the lower power tube is turned off, the current flowing through the upper power tube is equal to the current flowing through the inductor, that is, I top =I L . Therefore, the potential of SW is PVIN-I L R top , I L is the current flowing through the inductor, and R top is the on-resistance of the upper power tube, see Figure 1 . If the values of PVIN and R to p are known, the corresponding relationship between SW and I L can be known. The voltage value of SW is detected, that is, the inductor current I L is detected.

[0045] The current source is a reference current source, and the current of the current source is I0.

[0046] NM1, NM2, NM3, and NM4 constitute a current mirror circuit, and the currents flowing through them are I1, I2, I3, and I4, respectively. The size parameters satisfy the relationship:

[0047]

[0048] k is a proportional coefficient, so I1=I2=kI3=I4=I0.

[0049] NM2, NMd1, PMd3, and PM2 constitute a bias circuit. NMd1 is an NDMOS, and the gate voltage is VDD. VDD is the working voltage of the internal module of the chip. NMd1 can prevent the source and drain of NM2 and PM2 from appearing a large voltage, thereby protecting the elements. The gate and drain of PMd3 are connected together to provide a bias voltage for PMd1 and PMd2.

[0050] NM4, NMd2, and R1 provide a reference voltage. NMd2 is an NDMOS, and the gate voltage is VDD. NMd2 can prevent the source and drain of NM4, NM3, and PM1 from appearing a large voltage, thereby protecting the elements. The current flowing through NMd2 and R1 is I5, and the resistance value of R1 is R1. Therefore, the voltage across R1 is I5*R1, and the potential of point C is PVIN-I5*R1. Given the values of PVIN and R1, the corresponding relationship between the potential of point C and I5 can be known.

[0051] NM7, PM3, NM8, PM4, R2, R3, U1 constitute an input comparison circuit for comparing the potential of SW and C. The resistance values of R2 and R3 are R2 and R3 respectively.

[0052] The gates of NM7 and NM8 are the input terminals of the comparison circuit, and the input is a voltage signal. The gate voltage of NM7 and NM8 is less than the drain voltage, so they work in the saturation region. According to the characteristics of MOS tubes, NM7 and NM8 working in the saturation region have a large transconductance, which can convert a small voltage change at the gate into a significant current change. After the conversion by this circuit, the voltage signal that was originally difficult to measure becomes an easy-to-measure current signal, so the circuit has high sensitivity.

[0053] PMd1 and PMd2 are PDMOS, which can prevent large voltage from being input to NM7 and NM8, and can protect NM7 and NM8.

[0054] PM3 and PM4 provide a static operating point for NM7 and NM8.

[0055] The current flowing through NM7 and PM3 is merged and then flows through PMd4 and R2, and the current is I A The current flowing through NM8 and PM4 is merged and then flows through PMd5 and R3, and the current is I B , and R2 = R3 = R0, so the voltages across resistors R2 and R3 are R0*I A and R0*I B , and the potential at point A is R0*I A , so the potential at point B is R0*I B . PMd4 and PMd5 are PDMOS, which can prevent large voltage from appearing at the source and drain of NM7, PM3, NM8, and PM4, and protect the elements.

[0056] The comparator U1 is used to compare the potentials of points A and B. When the potential at point A is greater than the potential at point B, the output OC_OUT is high, indicating that the peak current exceeds the preset value. When the potential at point A is less than the potential at point B, the output OC_OUT is low, indicating that the peak current is lower than the preset value.

[0057] When SW is greater than the potential at point C, i.e. PVIN-I L R top > PVIN-I5*R1, there is I A < I B , the potential at point A is less than the potential at point B, and the current flowing through the inductor does not exceed I5*R1 / R top , and the output OC_OUT is low. When SW is less than the potential at point C, i.e. PVIN-I L R top < PVIN-I5*R1, there is IA I B , A point potential greater than the potential of point B, the current through the inductance exceeds I5*R1 / R top , output OC_OUT is high. So, the detected peak current size is I5*R1 / R top .

[0058] PM1, NM3 constitute trim circuit. When Trim is high, PM1 off, the current I5=I4=I0 through NMd2, R1, so the detected peak current is I0*R1 / R top When Trim is low, PM1 on, the current through NMd2, R1 is:

[0059]

[0060] The detected peak current is:

[0061]

[0062] The peak current preset value is increased:

[0063]

[0064] In application, the value of k can be adjusted according to actual situation, and more trim branches and control circuits can be added to realize multi-stage trimming.

[0065] In practical application, the circuit can work normally under 3-40V input, and the current sensitivity is also high.

[0066] The above is only the preferred specific embodiment of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can make equivalent replacement or change according to the technical scheme and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A peak current detection circuit for use in BUCK, characterized in that: The current I flowing through the inductor of the BUCK chip is detected by measuring the potential at the output terminal SW, located between the upper and lower power transistors of the BUCK chip. L To perform peak current detection of the BUCK chip, the drain of the power transistor is connected to the PVIN pin of the BUCK chip, and the source of the power transistor is connected to the output terminal of the SW. One end of the BUCK chip inductor is connected to the output terminal of the SW, and the other end outputs VOUT and is connected to capacitor C. L Rear grounding; The peak current detection circuit includes a reference current source and a current mirror circuit connected to each other, a bias circuit, a reference voltage circuit, and a trimming circuit connected to the output terminal of the current mirror circuit respectively, an input comparator circuit connected to the reference voltage circuit and the output terminal of the SW, and a high voltage protection circuit connected to the input comparator circuit. The bias circuit, the reference voltage circuit, and the input comparator circuit are all connected to the PVIN pin of the BUCK chip. The reference current source provides a reference current I0. The current mirror circuit replicates the reference current I0 proportionally to the bias circuit, the reference voltage circuit, and the trimming circuit. The bias circuit provides a static operating point. The reference voltage circuit provides a reference voltage for comparison. The input comparison circuit compares the voltages and determines whether the peak current of the BUCK chip exceeds a preset value. The trimming circuit is connected to the Trim pin and adjusts the peak current detection circuit. The high-voltage protection circuit prevents high voltage from damaging the components in the input comparison circuit. The current mirror circuit includes NMOS transistors NM1, NM2, NM3, and NM4 with interconnected gates; the gate and drain of transistor NM1 are interconnected and connected to the reference current source, with its source grounded; the sources of transistors NM2, NM3, and NM4 are all grounded; the drain of transistor NM2 is connected to the bias circuit; the drain of transistor NM3 is connected to the adjustment circuit; and the drain of transistor NM4 is connected to the reference voltage circuit; the currents flowing through transistors NM1, NM2, NM3, and NM4 are I1, I2, I3, and I4, respectively. The reference voltage circuit includes a resistor R1 connected to the PVIN pin and an NDMOS transistor NMd2 connected to the other end of the resistor R1. The current in the resistor R1 is I5. The gate of the transistor NMd2 is connected to the operating voltage VDD, the drain is connected to the resistor R1, and the source is connected to the drain of the transistor NM4. Point C is located between resistor R1 and transistor NMd2. The input comparator circuit determines whether the peak current of the BUCK chip exceeds a preset value by comparing the potential at point C with that at the output of SW. When the output OC_OUT of the input comparator circuit is high, the peak current of the BUCK chip exceeds the preset value; when the output OC_OUT of the input comparator circuit is low, the peak current of the BUCK chip is lower than the preset value.

2. The peak current detection circuit for BUCK according to claim 1, characterized in that: The input comparator circuit includes NMOS transistors NM7 and NM8 whose drains are respectively connected to the PVIN pin, PMOS transistors PM3 and PM4 whose sources are respectively connected to the PVIN pin, comparator U1 connected to transistors PM3 and PM4, resistor R2 with one end connected to the drain of transistor PM3 and the other end grounded, and resistor R3 with one end connected to the drain of transistor PM4 and the other end grounded. The gate of transistor NM7 is connected to point C, and its source is connected to both the gate and drain of transistor PM3. The intersection of the drain of transistor PM3 with the positive input terminal of comparator U1 and resistor R2 is point A, and the intersection of the drain of transistor PM4 with the negative input terminal of comparator U1 and resistor R3 is point B. The gate of transistor NM8 is connected to the output terminal of SW, and its source is connected to both the gate and drain of transistor PM4. Pipes PM3 and PM4 provide static operating points to pipes NM7 and NM8, respectively. R2 = R3 = R0. The currents flowing through tubes NM7 and PM3 are combined and then flow through resistor R2, resulting in a current I. A The currents flowing through tubes NM8 and PM4 are combined and then flow through resistor R3, resulting in a current I. B ; The potential at point C is PVIN-I5*R1, and the potential at the output terminal of SW is PVIN-I. L R top , where R top The on-resistance of the power transistor in the BUCK chip; When the potential at the output terminal of SW is greater than the potential at point C, PVIN-I L R top When PVIN-I5*R1, I B >I A The potential at point B is greater than the potential at point A, and the current flowing through the inductor does not exceed I5*R1 / R. top The output OC_OUT is low. When the potential of the SW output terminal is less than the potential of point C, PVIN - I L R top When <PVIN - I5 * R1, I A >I B , the potential of point A is greater than the potential of point B, and the current flowing through the inductor exceeds I5 * R1 / R top , and the output OC_OUT is at a high level; The peak current detected by the peak current detection circuit is I5*R1 / R top .

3. The peak current detection circuit for BUCK according to claim 2, characterized in that: The high-voltage protection circuit includes a PDMOS transistor PMd1 connected between point C and transistor NM7, a PDMOS transistor PMd2 connected between the output terminal of SW and transistor NM8, a PDMOS transistor PMd4 connected between transistor PM3 and point A, and a PDMOS transistor PMd5 connected between transistor PM4 and point B. The drain of transistor PMd1 is connected to point C, the source is connected to the gate of transistor NM7, and the gate is connected to the source of transistor NM7. The drain of transistor PMd2 is connected to the output terminal of SW, the source is connected to the gate of transistor NM8, and the gate is connected to the source of transistor NM8. The drain of transistor PMd4 is connected to point A, the source is connected to the drain of transistor PM3, and the gate is connected to the bias circuit. The drain of transistor PMd5 is connected to point B, the source is connected to the drain and gate of transistor PM4, and the gate is connected to the gate of transistor PMd4 and the bias circuit. Pipes PMd1 and PMd2 protect pipes NM7 and NM8 respectively, and pipes PMd4 and PMd5 protect pipes NM7, PM3, NM8 and PM4 respectively. The currents flowing through tubes NM7 and PM3 are combined and then flow sequentially through tube PMd4 and resistor R2, with a current of I. A The currents flowing through tubes NM8 and PM4 are combined and then flow sequentially through tube PMd5 and resistor R3, with a current of I. B .

4. The peak current detection circuit for BUCK according to claim 3, characterized in that: The bias circuit includes a PMOS transistor PM2, a PDMOS transistor PMd3, and an NDMOS transistor NMd1 connected in sequence to the PVIN pin; The source of transistor PM2 is connected to the PVIN pin, and the drain and gate of transistor PM2 are connected to the source of transistor PM3. The gate and drain of transistor PM3 are connected to the drain of transistor NMd1. The gate of transistor PM3 is connected to the gate of transistor PM4 and the gate of transistor PM5. The gate voltage of transistor NMd1 is connected to VDD, and the source is connected to the drain of transistor NM2.

5. A peak current detection circuit for BUCK according to claim 2, characterized in that: I1=I2=kI3=I4=I0, where k is the proportionality coefficient.

6. A peak current detection circuit for BUCK according to claim 5, characterized in that: The tuning circuit includes a PMOS transistor PM1 with its gate connected to the Trim pin, the source of transistor PM1 connected to the source of transistor NMd2, and the drain connected to the drain of transistor NM3. When the Trim pin outputs a high level, transistor PM1 is turned off, and the current flowing through transistor NMd2 and resistor R1 is I5 = I4 = I0. The detected peak current is I0 * R1 / R top ; When the Trim pin outputs a low level, transistor PM1 is turned on, and the current flowing through transistor NMd2 and resistor R1 is:

7. A peak current detection circuit for BUCK according to claim 6, characterized in that: When the Trim pin outputs a low level, the detected peak current is: The peak current preset value has been increased:

8. A peak current detection circuit for BUCK according to claim 6, characterized in that: By adjusting the value of k, at least one additional tuning circuit can be added to perform multi-stage tuning.

9. A peak current detection circuit for BUCK according to claim 1, characterized in that: The gate of the upper power transistor is connected to the upper power transistor driver, and the source is connected to the drain of the lower power transistor. The gate of the lower power transistor is connected to the lower power transistor driver, and the source is grounded. The source of the upper power transistor and the drain of the lower power transistor are both connected to the output terminal of SW.

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