A SIP interconnect output driver fault testing method and system based on FPGA
Through the configuration vector and test system of FPGA and DSP modules, combined with transmission delay and current and voltage measurement, the problem of rapid location of internal interconnection faults in SIP circuits is solved, and production efficiency and design accuracy are improved.
Patent Information
- Application Number
- CN202411829470.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2044-12-12
AI Technical Summary
It is difficult to quickly and accurately locate faults in the internal interconnect output drivers of SIP circuits, resulting in low production efficiency and extended design backtracking time.
Configuration vectors are generated through simulation software of FPGA and DSP modules. Signal generation modules and automatic production test systems are used to measure transmission delays and applied drive currents. Combined with AC and DC parameter information, interconnect failure points can be quickly located and indicate substrate design or micro-component problems.
It achieves the rapid location of internal interconnection faults in SIP circuits, improves production efficiency and the accuracy of design back-checking, and reduces the time cost of the design department.
Smart Images
Figure CN119575137B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip fault testing, and in particular relates to a FPGA-based SIP interconnect output driver fault testing method and system. Background Art
[0002] SIP circuits contain numerous chip units, such as FPGAs and DSPs. These interconnected FPGAs and DSPs are integrated through a minimal packaging process, enabling system miniaturization. However, this also reduces the yield of SIP circuits. When an interconnect output driver failure occurs in a SIP circuit, destructive testing is costly due to the circuit's complex internal structure. Consequently, testing and production processes cannot accurately determine whether the issue lies with the SIP substrate design or the micro-components within the SIP, reducing production efficiency and delaying design verification by the design department. Summary of the Invention
[0003] The present invention aims to provide an FPGA-based SIP interconnect output driver fault testing method and system. This testing method can quickly locate interconnect fault points within a SIP circuit. By corroborating AC and DC parameter information, it can simulate SIP substrate lead differences in the FPGA interconnect portion, guiding designers to accurately determine whether the current chip problem is a SIP substrate design issue or a problem with the SIP's internal microcomponents.
[0004] To solve the above technical problems, the present invention provides a method for testing SIP interconnect output driver faults based on FPGA, comprising the following steps:
[0005] Step 1: Generate FPGA and DSP configuration vectors using the corresponding simulation software for the FPGA and DSP modules, and import the FPGA and DSP configuration vectors into the FPGA and DSP modules respectively through the automatic production test system;
[0006] Step 2: Connect the signal generation module to the pulse signal generated by the automatic production test system. Connect the input signal to the input pins specified by different banks of the FPGA of the circuit under test and the A1 channel of the transmission delay measurement channel of the automatic production test system. Connect the output pins specified by different banks of the FPGA of the circuit under test to the A2 channel of the transmission delay measurement channel. The transmission delay measurement channel calculates the transmission delay time based on different banks of the FPGA based on the A1 and A2 channels through the time measurement unit, and obtains the AC parameter information. This AC parameter information can be used to locate chip interconnection problems.
[0007] Step 3: Configure the port driver through the FPGA, apply the drive current through the automatic production test system, measure the current voltage of different FPGA-based banks, and analyze the DC parameter information between different FPGA-based banks. This DC parameter information can be used to analyze the design defects of the SIP-based substrate.
[0008] Preferably, the step one specifically includes: through the FPGA and DSP modules, according to the internal interconnection relationship, each FPGA-based Bank only provides one signal, the signal enters from the FPGA, exits from the DSP, and is then transmitted back to the FPGA, the signal path passes through all interconnection channels of the current Bank, each Bank has an input and output port, and ensures that the switches through which the internal signals of different Banks of the FPGA and DSP pass are the same, generates FPGA and DSP configuration vectors, and imports the FPGA and DSP configuration vectors into the FPGA and DSP modules respectively through the automatic production test system.
[0009] Preferably, in step 2, if the AC parameter information is consistent, the routing of different banks under the FPGA of the SIP substrate is basically consistent, which indicates that the micro-component driver inside the SIP chip has a fault; if the AC parameter information is inconsistent, jump to step 3 to configure the port driver through the FPGA.
[0010] Preferably, in step 3, if the port voltages under different banks are inconsistent, it indicates that there is a fault in the FPGA-based driver.
[0011] Preferably, the step three also includes: according to the DC parameter information, by driving the current I and the port voltage V, according to the formula, the internal resistance R is obtained; and the lead-related information of the substrate is obtained by using the resistivity of the lead material, the lead cross-sectional area S, the internal resistance R and the lead length L; since the resistivity and the lead cross-sectional area S between different banks are consistent, it is only necessary to determine whether there is a difference in the lead length of different banks of the FPGA based on the substrate based on the internal resistance R, that is, according to the formula, and then guide the designer to accurately locate whether the current chip problem is a SIP substrate design problem or a SIP internal micro-component problem, and quickly generate a reliability analysis report.
[0012] Preferably, the configuration process of the microcomponent FPGA and the microcomponent DSP includes: according to the FPGA priority PN terminal principle, the same PN terminal in each Bank is preferentially selected, following N in P out or P in N out, and connected with the corresponding microcomponent DSP, which can ensure that the internal signal transmission distance of the microcomponent is the shortest, and generate an NCD file through simulation software. According to the information provided by the NCD file, the total signal transmission time of each Bank of the microcomponent will be different, and the total signal transmission time of each Bank is controlled to be the same through IODELAY constraints.
[0013] Preferably, it also includes: constraining the port of the micro-component DSP to an input state or a high-impedance state through simulation software, and then constraining the corresponding micro-component FPGA port to an output drive mode through simulation software, and selecting the driving current and port voltage of the current output drive mode as the maximum driving current and port voltage that the FPGA port can withstand, and applying the driving current to the PAD corresponding to the SIP substrate through an automatic production test system to obtain the current accurate driving voltage.
[0014] The present invention also provides an FPGA-based SIP interconnect output driver fault test system, which adopts the above-mentioned FPGA-based SIP interconnect output driver fault test method. The test system includes FPGA and DSP configuration vectors, a signal generation module, an automatic production test system, a time measurement unit, a load current module unit, a voltage measurement unit, an automatic production test board, and a signal generation and receiving program;
[0015] The circuit under test is placed in an automated production test board. The FPGA and DSP configuration vectors are converted into 0 / 1 binary codes recognized by the automated production test system and a signal is generated. This signal is converted into an excitation signal by a signal generation module and sent to the time measurement unit of the automated production test system. The signal generation and reception program uses this signal to mark the start time of the test. The measured current generates two output signals, which are sent to the time measurement unit of the automated production test system. The signal generation and reception program uses this signal to mark the end time of multiple tests. The signal generation and reception program subtracts the end time of the two tests from the start time to obtain the test time of channel A1 and channel A2.
[0016] The circuit under test is placed in the automatic production test board, the load current module unit of the automatic production test system applies a driving current to the circuit under test, and the test voltage of the circuit under test in the current state is obtained through the voltage measurement unit.
[0017] Compared with the prior art, the present invention has the following beneficial effects:
[0018] The present invention provides an FPGA-based SIP interconnect output driver fault test and system thereof, which aims to quickly locate the interconnection fault point within the SIP circuit. According to this method, the SIP substrate lead difference of the FPGA interconnection part can be simulated, guiding designers to accurately locate whether the current chip problem is a problem with the SIP substrate design or a problem with the SIP internal microcomponent. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 The present invention is a schematic diagram of an FPGA-based SIP interconnect output drive fault AC test circuit.
[0020] Figure 2 The present invention is a schematic diagram of a SIP interconnect output drive fault DC test circuit based on FPGA.
[0021] Figure 3 This is a schematic diagram of AC parameter testing of FPGA-based SIP interconnection and FPGA and DSP configuration principles of the present invention.
[0022] Figure 4 This is a schematic diagram of a DC parameter test principle of an FPGA-based SIP interconnection according to the present invention. DETAILED DESCRIPTION
[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.
[0024] like Figure 1 and Figure 2 As shown, the present invention provides an FPGA-based SIP interconnect output driver fault testing method. The analysis method targets the test conditions that affect chip faults and includes the following steps:
[0025] Step a: Through the FPGA and DSP modules, based on the internal interconnection relationship, each FPGA-based bank only provides one signal. This signal enters the FPGA, exits the DSP, and then returns to the FPGA. The signal path passes through all interconnection channels of the current bank. Each bank has an input and output port, and the switches through which the internal signals of different FPGA and DSP banks pass are the same. FPGA and DSP configuration vectors are generated and imported into the FPGA and DSP through the production test system. The signal generation module connects the pulse signal FFF generated by the automatic production test system to the input pins specified by different FPGA banks of the circuit under test and the transmission delay measurement channel A1 of the automatic test system. The output pins specified by different FPGA banks of the circuit under test are connected to the transmission delay measurement channel A2. The transmission delay measurement channel uses the time measurement unit to determine the transmission delay time based on different FPGA banks based on channels A1 and A2. If the AC parameters are consistent, the routing of different banks under the FPGA of the SIP substrate is basically consistent, indicating a microcomponent driver failure within the SIP chip.
[0026] Step b: If the AC parameters in step a are inconsistent, configure the port driver through the FPGA. Apply the drive current I through the production test system to measure the current port voltage V on different FPGA-based banks to obtain DC parameter information. If the port voltages under different banks are inconsistent, it indicates that there is a fault in the FPGA-based driver.
[0027] Step c: According to the analysis of the DC parameter information and transmission delay time in step a and step b, it can be analyzed that the current SIP interconnection has a fault according to the transmission delay time, and then according to the DC parameter information, the driving current I and the port voltage V are used to determine the fault. The internal resistance R is obtained by using the relevant information of the substrate lead, the lead material resistivity ρ, the lead cross-sectional area S, the internal resistance R, and the lead length L. According to the formula Because the resistivity and lead cross-sectional area are consistent across banks, the internal resistance R alone can be used to determine whether lead lengths vary across FPGA banks on the substrate. This helps designers pinpoint whether chip issues lie with the SIP substrate design or the SIP's internal microcomponents, allowing for rapid generation of reliability analysis reports.
[0028] like Figure 3 As shown in the figure, the configuration principle of the microcomponent FPGA and microcomponent DSP is as follows. According to the principle of FPGA prioritizing PN terminals, the same PN terminal in each bank is preferred, following N-in P-out or P-in N-out, and connected with the corresponding microcomponent DSP. This can ensure that the signal transmission distance within the microcomponent is the shortest. The NCD file is generated by simulation software. According to the information provided by the NCD file, the total signal transmission time of each bank of the microcomponent will be different. The IODELAY constraint is used to control the total signal transmission time of each bank to be the same.
[0029] like Figure 4 As shown, the port of the microcomponent DSP is constrained to an input state or a high-impedance state through simulation software, and then the corresponding microcomponent FPGA port is constrained to an output drive mode through simulation software, and the driving current and port voltage of the current output drive mode are selected as the maximum driving current and port voltage that the FPGA port can withstand. The driving current is applied to the PAD corresponding to the SIP substrate through the automatic production test system to obtain the current accurate driving voltage.
[0030] Table 1 below shows the DC parameter test results of the FPGA-based SIP interconnection of the present invention.
[0031] Table 1
[0032] Bank Location Bank1 Bank2 Measured results (V) 0.390842 0.261520
[0033] The embodiment of the present invention also provides an FPGA-based SIP interconnect output driver fault test system, which includes an FPGA and DSP configuration vector, a signal generation module, an automatic production test system, a time measurement unit, a load current module unit, a voltage measurement unit, an automatic production test board, and a signal generation and reception program;
[0034] The circuit under test is placed in an automated production test board. The FPGA and DSP configuration vectors are converted into 0 / 1 binary codes recognized by the automated production test system and a signal is generated. This signal is converted into an excitation signal by a signal generation module and sent to the time measurement unit of the automated production test system. The signal generation and reception program uses this signal to mark the start time of the test. The measured current generates two output signals, which are sent to the time measurement unit of the automated production test system. The signal generation and reception program uses this signal to mark the end time of multiple tests. The signal generation and reception program subtracts the end time of the two tests from the start time to obtain the test time of channel A1 and channel A2.
[0035] The circuit under test is placed in the automatic production test board, the load current module unit of the automatic production test system applies a driving current to the circuit under test, and the test voltage of the circuit under test in the current state is obtained through the voltage measurement unit.
[0036] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for testing SIP interconnect output driver faults based on FPGA, characterized in that: The steps include: Step 1: Generate FPGA and DSP configuration vectors using the corresponding simulation software for the FPGA and DSP modules, and import the FPGA and DSP configuration vectors into the FPGA and DSP modules respectively through the automatic production test system; Step 2: Connect the signal generation module to the pulse signal generated by the automatic production test system. Connect the input signal to the input pins specified by different banks of the FPGA of the circuit under test and the A1 channel of the transmission delay measurement channel of the automatic production test system. Connect the output pins specified by different banks of the FPGA of the circuit under test to the A2 channel of the transmission delay measurement channel. The transmission delay measurement channel calculates the transmission delay time based on different banks of the FPGA based on the A1 and A2 channels through the time measurement unit, and obtains the AC parameter information. This AC parameter information can be used to locate chip interconnection problems. Step 3: Configure the port driver through the FPGA, apply the drive current through the automatic production test system, measure the current voltage of different FPGA-based banks, and analyze the DC parameter information between different FPGA-based banks. This DC parameter information can be used to analyze the design defects of the SIP-based substrate.
2. A method for testing SIP interconnect output driver faults based on FPGA as claimed in claim 1, characterized in that: The step 1 specifically includes: through the FPGA and DSP modules, according to the internal interconnection relationship, each bank based on the FPGA only provides one signal, the signal enters the FPGA, exits the DSP, and then is transmitted back to the FPGA. The signal path passes through all interconnection channels of the current bank. Each bank has an input and output port, and ensures that the switches through which the internal signals of different banks of the FPGA and DSP pass are the same, generates FPGA and DSP configuration vectors, and imports the FPGA and DSP configuration vectors into the FPGA and DSP modules respectively through the automatic production test system.
3. The FPGA-based SIP interconnect output driver fault testing method according to claim 1, wherein: In step 2, if the AC parameter information is consistent, the routing of different banks under the FPGA of the SIP substrate is consistent, indicating that the micro-component driver inside the SIP chip has a fault; if the AC parameter information is inconsistent, jump to step 3 to configure the port driver through the FPGA.
4. The FPGA-based SIP interconnect output driver fault testing method according to claim 1, wherein: In step 3, if the port voltages under different banks are inconsistent, it indicates that there is a fault in the FPGA-based driver.
5. The FPGA-based SIP interconnect output driver fault testing method according to claim 1, wherein: The step three also includes: according to the DC parameter information, by driving the current I and the port voltage V, according to the formula Obtain the internal resistance R; and use the lead material resistivity ρ, lead cross-sectional area S, internal resistance R and lead length L substrate lead related information; Since the resistivity ρ and lead cross-sectional area S between different banks are consistent, it is only necessary to calculate based on the internal resistance R, that is, according to the formula It can be determined whether there are differences in the lead lengths of different banks of the FPGA on the substrate, thereby guiding designers to accurately locate whether the current chip problem is a problem with the SIP substrate design or the SIP internal microcomponents, and quickly generate a reliability analysis report.
6. A method for testing SIP interconnect output driver faults based on FPGA as claimed in claim 5, characterized in that: The configuration process of the microcomponent FPGA and microcomponent DSP includes: according to the FPGA priority PN terminal principle, the same PN terminal in each bank is preferred, following N in P out or P in N out, and connected with the corresponding microcomponent DSP, which can ensure the shortest signal transmission distance within the microcomponent. The NCD file is generated by simulation software. According to the information provided by the NCD file, the total signal transmission time of each bank of the microcomponent will be different. The IODELAY constraint is used to control the total signal transmission time of each bank to be the same.
7. A method for testing SIP interconnect output driver faults based on FPGA as claimed in claim 6, characterized in that: Also includes: Through simulation software, the port of the micro-component DSP is constrained to the input state or high-impedance state, and then the corresponding micro-component FPGA port is constrained to the output drive mode through simulation software. The driving current and port voltage of the current output drive mode are selected as the maximum driving current and port voltage that the FPGA port can withstand. The driving current is applied to the PAD corresponding to the SIP substrate through the automatic production test system to obtain the current accurate driving voltage.
8. A SIP interconnect output driver fault test system based on FPGA, characterized in that: A method for testing SIP interconnect output driver faults based on FPGA as claimed in any one of claims 1 to 7 is used, wherein the test system includes FPGA and DSP configuration vectors, a signal generation module, an automatic production test system, a time measurement unit, a load current module unit, a voltage measurement unit, an automatic production test board, and a signal generation and reception program; The circuit under test is placed in an automated production test board. The FPGA and DSP configuration vectors are converted into 0 / 1 binary codes recognized by the automated production test system and a signal is generated. This signal is converted into an excitation signal by a signal generation module and sent to the time measurement unit of the automated production test system. The signal generation and reception program uses this signal to mark the start time of the test. The measured current generates two output signals, which are sent to the time measurement unit of the automated production test system. The signal generation and reception program uses this signal to mark the end time of multiple tests. The signal generation and reception program subtracts the end time of the two tests from the start time to obtain the test time of channel A1 and channel A2. The circuit under test is placed in the automatic production test board, the load current module unit of the automatic production test system applies a driving current to the circuit under test, and the test voltage of the circuit under test in the current state is obtained through the voltage measurement unit.