Input buffer, analog-to-digital converter and receiver

Abstract

The invention provides an input buffer. The input buffer comprises a first current mirror module, a first source following module, a first common gate amplification module, a first tail current source module and a first coupling capacitor, the first current mirror module is connected with a first common level end, a first node and a second node, and is used for distributing the current proportion of the first source following module and the first common gate amplification module; the first source following module is connected with the second node, the first input end and the first output end; the first common-gate amplification module is connected with the first node, the first output end and a first bias voltage end; the first tail current source module is connected with a second common level end, a second bias voltage end and the first output end, and is used for providing current bias for the first source following module and the first common gate amplification module; the first coupling capacitor is connected with the first input end and the first node. The invention also provides an analog-to-digital converter and a receiver.

Description

Technical Field

[0001] The present disclosure relates to the technical field of communication equipment, and in particular to an input buffer, an analog-to-digital converter, and a receiver. Background Art

[0002] With the rapid development of high-speed communication technology, the throughput of communication equipment is getting higher and higher, and the speed requirements for the serializer and deserializer (SerDes) system of the receiver are also getting higher and higher. In order to support the increase in speed, the use of advanced integrated circuit technology is an inevitable trend.

[0003] However, advanced processes generally use low power supply voltage designs, which do not match the power supply requirements of the input buffers of high-speed analog-to-digital converters. Summary of the invention

[0004] Embodiments of the present disclosure provide an input buffer, an analog-to-digital converter, and a receiver.

[0005] In the first aspect, the embodiment of the present disclosure provides an input buffer, including: a first current mirror module, a first source follower module, a first common gate amplifier module, a first tail current source module, and a first coupling capacitor; the first current mirror module is connected to the first common level terminal, the first node, and the second node, and is used to distribute the current ratio of the first source follower module and the first common gate amplifier module; the first source follower module is connected to the second node, the first input terminal, and the first output terminal; the first common gate amplifier module is connected to the first node, the first output terminal, and the first bias voltage terminal; the first tail current source module is connected to the second common level terminal, the second bias voltage terminal, and the first output terminal, and is used to provide current bias for the first source follower module and the first common gate amplifier module; the first coupling capacitor is connected to the first input terminal and the first node.

[0006] In a second aspect, an embodiment of the present disclosure provides an analog-to-digital converter, comprising the input buffer described in the first aspect of the embodiment of the present disclosure.

[0007] In a third aspect, an embodiment of the present disclosure provides a receiver, comprising the analog-to-digital converter described in the second aspect of the embodiment of the present disclosure.

[0008] In the disclosed embodiment, the input signal is divided into two paths after being input from the first input terminal, one path passes through the first source follower module and is output to the first output terminal, and the other path passes through the first coupling capacitor to couple to the first common gate amplifier module and is output to the first output terminal, and the output signal is the sum of the outputs of the first source follower module and the first common gate amplifier module, and the outputs of the first source follower module and the first common gate amplifier module are superimposed and output through the first output terminal. The disclosed embodiment can reduce the input and output voltages by respectively setting the first source follower module and the first common gate amplifier module in two branches to form a parallel relationship, so that it can be applied to low-voltage input design, which is conducive to the realization of advanced integrated circuit technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of a common gate amplifier structure;

[0010] Figure 2 is a schematic diagram of an input buffer in an embodiment of the present disclosure;

[0011] Figure 3 is a schematic diagram of another input buffer in an embodiment of the present disclosure;

[0012] Figure 4 is a schematic diagram of another input buffer in an embodiment of the present disclosure;

[0013] Figure 5 is a schematic diagram of another input buffer in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the input buffer, analog-to-digital converter, and receiver provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0015] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0016] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0017] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0018] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0020] Using a common-gate amplifier structure to compensate for the insertion loss of a source-follower structure is an economical and effective solution. This solution places the common-gate amplifier tube below the source follower, and the two are in the same branch. Figure 1 As shown, the gate of source follower tube M11 is connected to the input terminal V in Connect the first pole to the output terminal V out Connect the second pole to the power supply terminal V DD Connect the gate of the common gate amplifier tube M12 to the bias voltage terminal V G connection, the first pole is grounded, the second pole is connected to the output terminal V out Connection, capacitor C L One pole and output terminal V out Connect, the other pole is grounded, the resistor R s One end is connected to the input terminal V s Connect the other end to the input terminal V in Connection, capacitor C R One terminal and input terminal V in Connect, the other pole is grounded, I B ,I CR ,I ZL Indicates current; the common gate amplifier tube M12 is placed below the source follower tube M11, and M12 compensates for the high-frequency insertion loss of the M11 structure to achieve bandwidth expansion. To ensure that the structure can work normally, the source follower tube M11, the common gate amplifier tube M12, and the MOS tube as a micro-current source must all work in the saturation region. This requires the input voltage to be high enough to ensure sufficient voltage margin, which is difficult to achieve in low-voltage design.

[0021] In view of this, firstly, refer to Figures 2 to 5, the embodiment of the present disclosure provides an input buffer, comprising: a first current mirror module 101, a first source follower module 102, a first common gate amplifier module 103, a first tail current source module 104, and a first coupling capacitor C1;

[0022] The first current mirror module 101 is connected to the first common level terminal, the first node Q1, and the second node Q2, and is used to distribute the current ratio of the first source follower module 102 and the first common gate amplifier module 103;

[0023] The first source follower module 102 is connected to the second node Q2 and the first input terminal V in,p , the first output terminal V out,p connect;

[0024] The first common-gate amplifier module 103 is connected to the first node Q1 and the first output terminal V out,p , the first bias voltage terminal V bcg connect;

[0025] The first tail current source module 104 is connected to the second common level terminal and the second bias voltage terminal V b , the first output terminal V out,p connected to provide current bias for the first source follower module 102 and the first common gate amplifier module 103;

[0026] The first coupling capacitor C1 and the first input terminal V in,p , the first node is connected to Q1.

[0027] In the embodiment of the present disclosure, the input signal Vinp is provided by the first input terminal V in,p After the input, it is divided into two paths, one of which passes through the first source follower module 102 and is output to the first output terminal V out,p The other path is coupled to the first common-gate amplifier module 103 through the first coupling capacitor C1 and output to the first output terminal V out,p The output signal Voutp is the sum of the outputs of the first source follower module 102 and the first common gate amplifier module 103. The outputs of the first source follower module 102 and the first common gate amplifier module 103 are transmitted through the first output terminal V out,p Overlay output.

[0028] The disclosed embodiment arranges the first source follower module 102 and the first common gate amplifier module 103 in two branches respectively to form a parallel relationship, which can reduce the input and output voltages, so that it can be applied to low-voltage input design, which is conducive to the realization of advanced integrated circuit technology.

[0029] In the disclosed embodiment, the source follower structure and the common gate amplifier structure are implemented with two branches respectively. By adjusting the common gate amplifier's ability to compensate for the buffer circuit bandwidth, in addition to adjusting the size of the common gate tube, the current mirror current size and ratio can also be changed, increasing the design freedom and flexibility.

[0030] In some embodiments, the input buffer is a fully differential structure.

[0031] Accordingly, in some embodiments, reference Figure 3 , the input buffer further includes: a second current mirror module 201, a second source follower module 202, a second common gate amplifier module 203, a second tail current source module 204, and a second coupling capacitor C2;

[0032] The second current mirror module 201 is connected to the first common level terminal, the third node Q3, and the fourth node Q4, and is used to distribute the current ratio of the second source follower module 202 and the second common gate amplifier module 203;

[0033] The second source follower module 202 is connected to the fourth node Q4 and the second input terminal V in,n , the second output terminal V out,n connect;

[0034] The second common-gate amplifier module 203 is connected to the third node Q3 and the second output terminal V out,n , the first bias voltage terminal V bcg connect;

[0035] The second tail current source module 204 is connected to the second common level terminal and the second bias voltage terminal V b , the second output terminal V out,n connected to provide current bias for the second source follower module 202 and the second common gate amplifier module 203;

[0036] The second coupling capacitor C2 is connected to the second input terminal V in,n , the third node Q3 is connected.

[0037] In the embodiment of the present disclosure, the input signal Vinn is provided by the second input terminal V in,n After the input, it is divided into two paths, one of which passes through the second source follower module 202 and is output to the second output terminal V out,n The other path is coupled to the second common-gate amplifier module 203 through the second coupling capacitor C2 and output to the second output terminal V out,n The output signal Voutn is the sum of the outputs of the second source follower module 202 and the second common gate amplifier module 203. The outputs of the second source follower module 202 and the second common gate amplifier module 203 are transmitted through the second output terminal V out,n Overlay output.

[0038] Accordingly, in some embodiments, the first input terminal V in,p The second input terminal V in,n Differential input, the first output terminal V out,p The second output terminal V out,n They are differential outputs.

[0039] In some embodiments, reference Figure 4 , Figure 5 , the first current mirror module 101 includes a first transistor M1 and a second transistor M2;

[0040] The gate of the first transistor M1 is connected to the second node Q2, the first electrode is connected to the first common level terminal, and the second electrode is connected to the second node Q2;

[0041] The gate of the second transistor M2 is connected to the second node Q2 , the first electrode is connected to the first common level terminal, and the second electrode is connected to the first node Q1 .

[0042] In some embodiments, the first source follower module 102 includes a third transistor M3;

[0043] The gate of the third transistor M3 is connected to the first input terminal V in,p , the first electrode is connected to the first output terminal V out,p , the second electrode is connected to the second node Q2.

[0044] In some embodiments, the first common-gate amplification module 103 includes a fourth transistor M4;

[0045] The gate of the fourth transistor M4 is connected to the first bias voltage terminal V bcg , the first electrode is connected to the first node Q1, and the second electrode is connected to the first output terminal V out,p .

[0046] In some embodiments, the first tail current source module 104 includes a fifth transistor M5;

[0047] The gate of the fifth transistor M5 is connected to the second bias voltage terminal V b , the first electrode is connected to the second common level terminal, and the second electrode is connected to the first output terminal V out,p .

[0048] In some embodiments, reference Figure 4 , Figure 5 , the second current mirror module 201 includes a sixth transistor M6 and a seventh transistor M7;

[0049] The sixth transistor M6 has a gate connected to the fourth node Q4, a first electrode connected to the first common level terminal, and a second electrode connected to the fourth node Q4;

[0050] The seventh transistor M7 has a gate connected to the fourth node Q4 , a first electrode connected to the first common level terminal, and a second electrode connected to the third node Q3 .

[0051] In some embodiments, the second source follower module 102 includes an eighth transistor M8;

[0052] The gate of the eighth transistor M8 is connected to the second input terminal V in,n , the first electrode is connected to the second output terminal V out,n , and the second electrode is connected to the fourth node Q4.

[0053] In some embodiments, the second common-gate amplification module 103 includes a ninth transistor M9;

[0054] The gate of the ninth transistor M9 is connected to the first bias voltage terminal V bcg , the first electrode is connected to the third node Q3, and the second electrode is connected to the second output terminal V out,n .

[0055] In some embodiments, the second tail current source module 104 includes a tenth transistor M10;

[0056] The gate of the tenth transistor M10 is connected to the second bias voltage terminal V b , the first electrode is connected to the second common level terminal, and the second electrode is connected to the second output terminal V out,n .

[0057] In some embodiments, reference Figure 4 , the first common level terminal is the power supply voltage terminal VDD, the second common level terminal is the ground terminal, the first transistor M1, the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the ninth transistor M9 are N-type transistors; the third transistor M3, the fifth transistor M5, the eighth transistor M8, and the tenth transistor M10 are P-type transistors.

[0058] In some embodiments, reference Figure 5 , the first common level terminal is the ground terminal, the second common level terminal is the power supply voltage terminal VDD, the first transistor M1, the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the ninth transistor M9 are P-type transistors; the third transistor M3, the fifth transistor M5, the eighth transistor M8, and the tenth transistor M10 are N-type transistors.

[0059] In a second aspect, an embodiment of the present disclosure provides an analog-to-digital converter, comprising the input buffer described in the first aspect of the embodiment of the present disclosure.

[0060] In a third aspect, an embodiment of the present disclosure provides a receiver, comprising the analog-to-digital converter described in the second aspect of the embodiment of the present disclosure.

[0061] In some embodiments, the receiver is a high-speed SerDes receiver.

[0062] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. An input buffer, comprising: A first current mirror module, a first source follower module, a first common gate amplifier module, a first tail current source module, and a first coupling capacitor; The first current mirror module is connected to the first common level terminal, the first node, and the second node, and is used to distribute the current ratio of the first source follower module and the first common gate amplifier module; The first source follower module is connected to the second node, the first input terminal, and the first output terminal; The first common-gate amplification module is connected to the first node, the first output terminal, and the first bias voltage terminal; The first tail current source module is connected to the second common level terminal, the second bias voltage terminal, and the first output terminal, and is used to provide current bias for the first source follower module and the first common gate amplifier module; The first coupling capacitor is connected to the first input terminal and the first node.

2. The input buffer according to claim 1, wherein: The input buffer further includes: a second current mirror module, a second source follower module, a second common gate amplifier module, a second tail current source module, and a second coupling capacitor; The second current mirror module is connected to the first common level terminal, the third node, and the fourth node, and is used to distribute the current ratio of the second source follower module and the second common gate amplifier module; The second source follower module is connected to the fourth node, the second input terminal, and the second output terminal; The second common-gate amplification module is connected to the third node, the second output terminal, and the first bias voltage terminal; The second tail current source module is connected to the second common level terminal, the second bias voltage terminal, and the second output terminal, and is used to provide current bias for the second source follower module and the second common gate amplifier module; The second coupling capacitor is connected to the second input terminal and the third node.

3. The input buffer according to claim 2, wherein: The first input terminal and the second input terminal are differential inputs to each other, and the first output terminal and the second output terminal are differential outputs to each other.

4. The input buffer according to claim 1 or 2, wherein: The first current mirror module includes a first transistor and a second transistor; The gate of the first transistor is connected to the second node, the first electrode is connected to the first common level terminal, and the second electrode is connected to the second node; The second transistor has a gate connected to the second node, a first electrode connected to the first common level terminal, and a second electrode connected to the first node.

5. The input buffer according to claim 4, wherein: The first source follower module includes a third transistor; The third transistor has a gate connected to the first input terminal, a first electrode connected to the first output terminal, and a second electrode connected to the second node.

6. The input buffer according to claim 5, wherein: The first common-gate amplification module includes a fourth transistor; The fourth transistor has a gate connected to the first bias voltage terminal, a first electrode connected to the first node, and a second electrode connected to the first output terminal.

7. The input buffer according to claim 6, wherein: The first tail current source module includes a fifth transistor; The gate of the fifth transistor is connected to the second bias voltage terminal, the first electrode is connected to the second common level terminal, and the second electrode is connected to the first output terminal.

8. The input buffer according to claim 7, wherein: The second current mirror module includes a sixth transistor and a seventh transistor; The gate of the sixth transistor is connected to the fourth node, the first electrode is connected to the first common level terminal, and the second electrode is connected to the fourth node; The gate of the seventh transistor is connected to the fourth node, the first electrode is connected to the first common level end, and the second electrode is connected to the third node.

9. The input buffer according to claim 8, wherein: The second source follower module includes an eighth transistor; The gate of the eighth transistor is connected to the second input terminal, the first electrode is connected to the second output terminal, and the second electrode is connected to the fourth node.

10. The input buffer according to claim 9, wherein: The second common-gate amplification module includes a ninth transistor; The gate of the ninth transistor is connected to the first bias voltage terminal, the first electrode is connected to the third node, and the second electrode is connected to the second output terminal.

11. The input buffer according to claim 10, wherein: The second tail current source module includes a tenth transistor; The gate of the tenth transistor is connected to the second bias voltage terminal, the first electrode is connected to the second common level terminal, and the second electrode is connected to the second output terminal.

12. The input buffer according to claim 11, wherein The first common level terminal is a power supply voltage terminal, the second common level terminal is a ground terminal, the first transistor, the second transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are N-type transistors; the third transistor, the fifth transistor, the eighth transistor, and the tenth transistor are P-type transistors.

13. The input buffer according to claim 11, wherein The first common level terminal is a ground terminal, the second common level terminal is a power supply voltage terminal, the first transistor, the second transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are P-type transistors; the third transistor, the fifth transistor, the eighth transistor, and the tenth transistor are N-type transistors.

14. An analog-to-digital converter comprising an input buffer according to any one of claims 1 to 13.

15. A receiver comprising the analog-to-digital converter according to claim 14.

Images