Data reading method of memory bank interleaving mode memory based on memory blocks
By adopting a memory block-based repository interleaving mode and emerging memory in memory, the existing repository interleaving mode has solved the problems of large power consumption and reduced data rate during high bandwidth operation, and efficient data reading and maximum data rate are achieved.
Patent Information
- Application Number
- CN202411433640.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2025-03-07
AI Technical Summary
The existing repository interleaving mode consumes a lot of power during high bandwidth operation, resulting in a significant reduction in data rates, especially in DDR3 and DDR4. Due to tFAW limitations, the data I/O interface cannot be fully utilized, resulting in the data rates reaching only 4/5 or 4/7 of the maximum value.
Using memory block-based repository interleaving mode memory, using emerging memories such as PCM, ReRAM or STT-MRAM, data reading is realized through predecoder and global data bus, and the memory block group is electrically connected to the data input and output interface to achieve seamless continuous bursts.
The data reading speed of the memory is improved, the power consumption is reduced, the tFAW limit is avoided, and the maximum data rate is achieved.
Smart Images
Figure CN119580796A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and in particular to a data reading method of a memory bank interleaving mode memory based on a storage block. Background Art
[0002] SDRAM (Synchronous Dynamic Random Access Memory) is a commonly used memory at present. It uses a bank-interleaved mode for data reading and writing. This mode brings a better probability of seamless continuous burst, thereby maintaining the maximum achievable data rate. It is one of the most effective ways to achieve high-bandwidth operation. However, this mode consumes a lot of power. For example, a x16 SDRAM needs to turn on 16K (16000) SAs (Sense Amplifiers) at a time, and multiple banks need to be activated. Once activated, the WL (WordLine) must be kept open to keep these SAs activated. Due to the high current of the memory bank interleaving mode, starting from DDR3 (3rd generation double data rate synchronous dynamic random access memory), JEDEC (Joint Electron Device Engineering Council, Solid State Technology Association) introduced tFAW (Four Active Window) to limit the number of consecutively activated memory banks to 4, that is, after activating 4 memory banks consecutively with a minimum tRRD (Row Address Strobe to Row Address Strobe Delay), the time to activate the 5th memory bank must meet tFAW. Therefore, if more than 5 memory banks are included, the data rate of the memory bank interleaving mode will be significantly reduced.
[0003] Figure 7 and Figure 8 The effect of tFAW on DDR3 and DDR4 is shown. Figure 7As shown, in the 8-bit burst (8-bitburst) of 400MHz DDR3, tFAW is 50ns, tRRD is 10ns, and after 4 memory banks (Bank a, Bank b, Bank c, Bank d) are activated continuously with tRRD, when the fifth memory bank (Bank e) needs to be activated, it cannot be activated immediately, and tFAW must be met. That is, only 4 memory banks can be activated within 50ns. In this way, the data I / O (input and output interface) cannot be fully utilized, and only 4 8-bit bursts can be performed continuously during the time span of 5 8-bit bursts. This means that the data rate can only reach 4 / 5 of the maximum rate. The maximum data rate of DDR3 is 1600MB / s, so for Figure 7 In the case of , the data rate can only reach 4 / 5×1600MB / s=1280Mb / s.
[0004] like Figure 8 As shown in the figure, the data rate of DDR4 drops even more. In an 8-bit burst of 800MHz DDR4, tFAW is 35ns and tRRD is 5ns. This means that only 4 8-bit bursts can be performed in the time of 7 8-bit bursts, so the data rate can only reach 4 / 7 of the maximum value, that is, 4 / 7×3200MB / s=1828MB / s.
[0005] In recent years, some emerging memories have emerged, such as PCM (Phase Change Memory), ReRAM (Resistive Random Access Memory), and STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory). These emerging memories do not require as many SA activations as SDRAM, so they consume less power and do not require tFAW. Therefore, if the memory bank interleaving mode can be implemented with these emerging memories, the data rate can be maximized. Summary of the invention
[0006] The present invention aims to provide a data reading method of a memory bank interleaving mode memory based on a memory block using an emerging memory, wherein the data reading method can achieve a maximum data rate and consumes less electric energy.
[0007] The data reading method of the storage block-based memory bank interleaving mode memory of the present invention comprises: providing the storage block-based memory bank interleaving mode memory, comprising: a plurality of storage bank groups arranged in the vertical direction, a horizontal spacing area is arranged between the storage bank groups, a plurality of data input and output interfaces arranged in the horizontal direction are arranged in the horizontal spacing area, a vertical spacing area is arranged in the middle of the storage bank group in the horizontal direction, an address bus extending in the vertical direction is arranged in the vertical spacing area; the storage bank group comprises a plurality of storage banks arranged in the vertical direction, each of the storage banks comprises: a plurality of storage block groups arranged in the horizontal direction, a predecoder arranged in the vertical spacing area, the predecoder is electrically connected to the plurality of storage block groups through a predecoder line extending in the horizontal direction, the predecoder line is electrically connected to the address bus, and the storage block group of each storage bank is electrically connected to the corresponding storage block group of other storage banks through a global data bus extending in the vertical direction and the corresponding data input and output interface ; The storage block group includes a plurality of storage blocks, and the plurality of storage blocks are electrically connected to a local data bus and the pre-decoder line, respectively, and the local data bus is electrically connected to the global data bus; the storage block includes: a row decoder, a column decoder, and a plurality of storage sub-blocks, and the number of storage sub-blocks in each of the storage blocks is equal to half of the burst length; the storage sub-block includes: a storage array, a first DC sense amplifier electrically connected to the storage array, a second DC sense amplifier, a first write head and a second write head, a first data latch electrically connected to the first DC sense amplifier, the first write head and the local data bus, respectively, and a second data latch electrically connected to the second DC sense amplifier, the second write head and the local data bus, respectively; the first DC sense amplifier, the first write head and the first data latch are arranged at the top of the storage array, and the second DC sense amplifier, the second write head and the second data latch are arranged at the bottom of the storage array.
[0008] The step of activating a memory bank is as follows: sending row addresses to the plurality of memory banks in sequence through the address bus, sending one row address every other burst time, and latching the row address in the pre-decoder after receiving the row address; the step of address latching: sending column addresses to the memory banks through the address bus after a specific time after the row address is sent, and latching the column addresses in the pre-decoder after receiving the column addresses, and then transmitting the row addresses and column addresses to the corresponding memory blocks of the memory banks through the pre-decoder lines, and the memory blocks latching the row addresses in the row decoders and the column addresses in the column decoders, and then the memory blocks disconnect from the pre-decoder lines. Data reading step: selecting the storage unit to be read according to the row address and the column address, the corresponding first DC sensing amplifier or the second DC sensing amplifier reads the read data stored in the selected storage unit, and latches the read data in the corresponding first data latch or the second data latch, and then sends the read data to the local data bus; standby step: the storage block reconnects the pre-decoder line, enters the standby state, and waits for the pre-decoder line to transmit the next row address and the column address. Transmission step: transmitting the read data to the data input and output interface through the local data bus and the global data bus.
[0009] The data reading method of the memory bank interleaving mode memory based on the storage block of the present invention can improve the data reading speed of the memory and save electric energy. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 is a schematic block diagram of a memory of the present invention.
[0011] Figure 2 is a schematic block diagram of a storage repository of the memory of the present invention.
[0012] Figure 3 It is a schematic block diagram of a storage block group of the memory of the present invention.
[0013] Figure 4 It is a schematic block diagram of a storage block and a storage sub-block of the memory of the present invention.
[0014] Figure 5 It is a flow chart of the method for reading data from the memory of the present invention.
[0015] Figure 6 is a timing diagram of a read operation of the memory of the present invention.
[0016] Figure 7 It is a timing diagram of the read and write operations of DDR3 in the prior art.
[0017] Figure 8 It is a timing diagram of the read and write operations of DDR4 in the prior art.
[0018] Explanation of symbols
[0019] 10 storage blocks
[0020] 11 Storage sub-blocks
[0021] 12 First DC SA
[0022] 13 First WH
[0023] 14First data latch
[0024] 15 Storage Array
[0025] 22nd DC SA
[0026] 23 Second WH
[0027] 24 Second data latch
[0028] 30 Pre-decoder
[0029] 100 storage block groups
[0030] 101 Local Data Bus
[0031] 102 pre-decoder line
[0032] 103 Global Data Bus
[0033] 104 Address bus
[0034] 200 data I / O
[0035] 300 Repositories
[0036] 301 vertical partition
[0037] 302 horizontal spacer
[0038] 400 Repository Group DETAILED DESCRIPTION
[0039] The memory and data reading and writing method thereof of the present invention will be described in detail below with reference to the accompanying drawings. Figure 1 is a schematic block diagram of the memory of the present invention. Figure 1As shown, the memory of the present invention includes: a plurality of memory bank groups 400 arranged in a vertical direction, a horizontal spacing area 302 is arranged between the memory bank groups 400, a plurality of data I / Os 200 arranged in a horizontal direction are arranged in the horizontal spacing area 302, a vertical spacing area 301 is arranged in the middle of the memory bank group 400 in the horizontal direction, and an address bus 104 extending in the vertical direction is arranged in the vertical spacing area 301.
[0040] The memory in this embodiment is PCM, but the present invention is not limited thereto. In other embodiments, it may be other emerging memories. The memory in this embodiment is a memory of the class x16 SDRAM DDR4, so it includes two memory bank groups 400, 16 data I / Os 200 are arranged in the horizontal spacing area 302, and 8 data I / Os 200 are arranged on both sides of the vertical spacing area 301. However, the present invention is not limited thereto. In other embodiments, the number of memory bank groups 400 and data I / Os 200 may also be other values. In addition, a chip pad is also arranged in the horizontal spacing area 302.
[0041] Figure 2 Schematic diagram of the storage library of the present invention. Figure 1 and Figure 2 As shown, the memory bank group 400 includes a plurality of memory banks 300 arranged in a vertical direction, each memory bank 300 includes: a plurality of memory block groups 100 arranged in a horizontal direction, a predecoder 30 arranged in a vertical spacing area 301, the predecoder 30 is electrically connected to the plurality of memory block groups 100 via a predecoder line 102 extending in a horizontal direction, the predecoder line 102 is electrically connected to an address bus 104, and the memory block group 100 of each memory bank 300 is electrically connected to the corresponding memory block group 100 of other memory banks 300 via a global data bus 103 extending in a vertical direction and a corresponding data I / O 200.
[0042] In this embodiment, each memory bank group 400 includes 4 memory banks 300, so the entire memory has a total of 8 memory banks 300. Each memory bank 300 includes 16 memory block groups 100, and 8 memory block groups 100 are respectively arranged on both sides of the vertical spacing area 301. These 16 memory block groups 100 are electrically connected to a corresponding data I / O 200 through a global data bus 103, so there are a total of 16 global data buses 103. The corresponding memory block groups 100 in the 8 memory banks 300 share a global data bus 103, so 8 memory block groups 100 share a global data bus 103. In this embodiment, the global data bus 103 is universal for reading and writing, but the present invention is not limited to this. In other embodiments, it can also be a separate read bus and write bus. Each memory bank 300 includes 2 pre-decoders 30, and these 2 pre-decoders 30 are electrically connected to the 16 memory block groups 100 in the memory bank 300 through a pre-decoder line 102.
[0043] Figure 3 Schematic block diagram of the storage block group of the present invention. Figure 3 As shown, the storage block group 100 includes a plurality of storage blocks 10, and the plurality of storage blocks 10 are electrically connected to a local data bus 101 and a pre-decoder line 102, respectively, and the local data bus 101 is electrically connected to a global data bus 103. In this embodiment, each storage block group 100 includes 8 storage blocks 10. However, the present invention is not limited thereto, and in other embodiments, the number of storage blocks 10 may also be other values.
[0044] Figure 4 Schematic block diagram of a memory block and a memory sub-block of the memory of the present invention. Figure 4 As shown, the storage block 10 includes: a row decoder, a column decoder, and a plurality of storage sub-blocks 11. The number of storage sub-blocks 11 in each storage block 10 is equal to half of the burst length. The memory of this embodiment adopts a DDR4-like mode, and the burst length is 8, so each storage block 10 of the memory of this embodiment includes 4 storage sub-blocks 11.
[0045] The storage sub-block 11 includes: a storage array 15, a first direct current SA 12 and a second direct current SA 22 electrically connected to the storage array 15, a first WH (write head) 13 and a second WH 23, a first data latch 14 electrically connected to the first direct current SA 12, the first WH 13 and a local data bus 101, and a second data latch 14 electrically connected to the second direct current SA 12, the second WH 13 and the local data bus 101.
[0046] The first direct current SA 12 , the first WH 13 and the first data latch 14 are disposed at the top of the memory array 15 , and the second direct current SA 22 , the second WH 23 and the second data latch 24 are disposed at the bottom of the memory array 15 .
[0047] Because the first direct current SA 12 and the second direct current SA 22 are both relatively large, if they are both arranged at the top of the storage array 15 or at the bottom of the storage array 15, it will take up more space and increase the size of the entire storage. Therefore, the first direct current SA 12 and the second direct current SA 22 are arranged alternately, which can save space and reduce the size of the entire storage.
[0048] Specifically, the memory block 10 further includes: a plurality of WLs, a plurality of first BLs (Bit Lines), a plurality of second BLs, a control circuit and a timing circuit.
[0049] The memory cells of each row in the memory array 15 are electrically connected to a WL, and the memory cells of each column are electrically connected to a first BL or a second BL. The row decoder is electrically connected to the plurality of WLs, and is used to select the WL according to the row address transmitted from the pre-decoder line 102. The column decoder is electrically connected to the plurality of first BLs and the plurality of second BLs, and is used to select the first BL or the second BL according to the column address transmitted from the pre-decoder line 102. The memory cell to be read or the memory cell to be written is selected according to the selected WL and the first BL or the second BL.
[0050] The number of BLs in each storage sub-block 11 depends on the density of the memory chip, which is in the mega (Mb) level or the giga (Gb) level. Usually, there are 64 to 512 first BLs and 64 to 512 second BLs in each storage sub-block 11. These first BLs share one first direct current SA 12 and one first WH 13, and these second BLs share one second direct current SA 12 and one second WH 13.
[0051] The following describes the method for reading and writing data in the memory of the present invention.
[0052] First, the method of data reading is described. Figure 5 is a flow chart of a method for reading data from a memory of the present invention, such as Figure 5 As shown, the data reading method of the memory of the present invention includes:
[0053] The memory bank activation step S100 is to send row addresses to the multiple memory banks 300 in sequence through the address bus 104 , with one row address sent every burst time. After receiving the row address, the memory bank 300 latches the row address in the pre-decoder 30 .
[0054] Address latching step S101: After the row address is issued, after a specific time, the column address is sent to the memory bank 300 through the address bus 104. After receiving the column address, the memory bank 300 latches the column address in the pre-decoder 30, and then transmits the row address and column address to the corresponding storage block 10 of the memory bank 300 through the pre-decoder line 102. The storage block 10 latches the row address in the row decoder and the column address in the column decoder, and then the storage block 10 disconnects from the pre-decoder line 102.
[0055] Data reading step S102: The storage unit to be read is selected according to the row address and the column address, and the corresponding first DC SA 12 or second DC SA 22 reads the read data stored in the selected storage unit, and latches the read data in the corresponding first data latch 14 or second data latch 24, and then sends the read data to the local data bus 101.
[0056] In this embodiment, the row decoder selects a WL of the storage block 10 according to the row address, such as Figure 4 The column decoder selects the four first BLs and the four second BLs of the storage block 10 according to the column address, as shown in FIG. Figure 4 As shown by the vertical dotted line in . Because the memory of this embodiment adopts a DDR4-like mode, there are 4 first BLs and 4 second BLs in this embodiment. However, the present invention is not limited to this, and in other embodiments, it can also be other numbers. In this way, 8 storage cells can be selected on the selected WL. Then the 4 first DC SA 12 and 4 second DC SA 22 corresponding to these 8 storage cells read the data stored in these 8 storage cells, and latch the read 8 data in the corresponding 4 first data latches 14 and 4 second data latches 24 respectively, and then send these 8 data to the local data bus 101.
[0057] Standby step S103: the memory block 10 reconnects to the pre-decoder line 102 and enters a standby state, waiting for the pre-decoder line 102 to transmit the next row address and column address.
[0058] Transmission step S104: 8 read data are transmitted to the data I / O 200 via the local data bus 101 and the global data bus 103. Because the memory of this embodiment adopts a DDR4-like mode, and the global data bus 103 of the DDR4 mode is just 8 bits wide, it can just transmit these 8 read data.
[0059] In this embodiment, the first row address is first sent to the first memory bank group 400 (ie, Figure 1 The first repository 300 (i.e., Figure 1The topmost memory bank 300 is referred to herein as memory bank 300A), and the first row address is latched in the pre-decoder 30 of the memory bank 300A.
[0060] After the first row address is issued, after a specific time (5ns), the first column address is sent to the memory bank 300A through the address bus 104, and the first column address is latched in the pre-decoder 30 of the memory bank 300A. Then, the first row address and the first column address are transmitted to the memory block 10 corresponding to the first row address and the first column address of the memory bank 300A through the pre-decoder line 102, and the memory block 10 latches the row address in the row decoder and the column address in the column decoder, and then the memory block 10 disconnects from the pre-decoder line 102.
[0061] The present invention adopts RAS (Row Address Strobe) / CAS (Column Address Strobe) address multiplexing, because the read operation can only be performed after the row address and the column address are latched in the storage block 10, so the reading can be performed after the CAS. That is, RAS determines a row address, and then CAS determines a column address, and then the reading is performed. Since nothing happens between RAS and CAS, its tRCD (RAS to CAS Delay) does not have to be as long as SDRAM, and only 1-2 clock cycles are needed. This will speed up the reading speed. In this embodiment, tRCD is 5ns.
[0062] Figure 6 is a timing diagram of the memory reading method of the present invention. Figure 6As shown, in this embodiment, after the first column address is issued, after a delay of a period of time, it reaches a storage block 10 (herein referred to as storage block 10A) in the storage bank 300A, and then the data of the relevant storage unit of the storage block 10A is read. After the first column address is issued, after 5ns, the second column address is issued, after a delay of a period of time, the second column address reaches a storage block 10 (herein referred to as storage block 10B) in another storage bank 300, and then the data of the relevant storage unit of the storage block 10B is read. After the second column address is issued, after 5ns, the third column address is issued, after a delay of a period of time, the third column address reaches a storage block 10 (herein referred to as storage block 10C) in another storage bank 300, and then the data of the relevant storage unit of the storage block 10C is read. After the third column address is issued, after 5ns, the fourth column address is issued, after a delay of a period of time, the fourth column address reaches a storage block 10 (herein referred to as storage block 10D) in another storage bank 300, and then the data of the relevant storage unit of the storage block 10D is read. After the fourth column address is issued, 5 ns later, the fifth column address is issued, and after a delay of a period of time, the fifth column address reaches the memory block 10A. And so on.
[0063] In this embodiment, the reading cycle Tr (i.e., the duration of the data reading step S102) is 20 ns. Figure 6 It can be seen that before the data reading step of the storage block 10A is completed, the second column address has reached the storage block 10B, and then the storage block 10B starts the data reading step. However, the operation of the storage block 10B will not affect the storage block 10A, because each storage block 10 is independent. At this time, the storage block 10A has also disconnected from the pre-decoder line 102, so it will not receive the column address again until the storage block 10A completes the data reading step S102.
[0064] A row address is sent every other burst time (5ns), that is, the sending time of the second row address is 5ns later than the first row address. Thus, the sending time of the second column address is also 5ns later than the first column address. The time when the second column address arrives at the storage block 10B is also 5ns later than the time when the first column address arrives at the storage block 10A. Figure 6As shown, after the first column address reaches the storage block 10A, after a read cycle Tr, the storage block 10A completes the data reading step S102 and sends the read data to the local data bus 101. After a delay of a period of time, the read data reaches the data I / O 200. The burst time is 5ns. After 5ns, the read data transmitted by the storage block 10B just arrives at the data I / O 200. After another 5ns, the read data transmitted by the storage block 10C arrives at the data I / O 200. And so on. In this way, seamless continuous burst is achieved, so the maximum data rate, that is, 3200MB / s, can be obtained.
[0065] In this embodiment, the read cycle Tr is 20ns, that is, 4 times the burst time, so it is necessary to activate 4 storage blocks 10 in the 4 storage banks 300 during the reading process. Then, the 4 storage blocks 10 are read in an interleaved mode. However, the present invention is not limited thereto, and if the read cycle Tr is another multiple of the burst time, for example, 8 times, it is necessary to activate 8 storage blocks 10 in the 8 storage banks 300 during the reading process.
[0066] Preferably, when the storage block 10A of the storage bank 300A enters the standby step S103, the row address and column address latched in the row decoder and column decoder of the storage block 10A are released. However, the row address latched in the pre-decoder 30 of the storage bank 300A is not released and remains valid. Therefore, if the next address transmitted to the storage bank 300A is a different column address on the same row, the storage bank 300A can directly read the data of these columns without re-latching the row address. If it is a different row address, the storage bank 300A first replaces the previously latched row address with a new row address, and then reads it.
[0067] This means that, in the present invention, a series of commands in SDRAM DDR can be performed without precharge commands, for example, row activation, precharge of a memory bank 300, and activation of another row of the same memory bank 300. That is, the present invention implements a memory bank interleaving mode that is exactly the same as SDRAM DDR without the selected WL remaining activated. In the present invention, the selected row address remains activated in the predecoder 30, and the memory block 10 is not precharged until CAS, and the WL of the memory block 10 is activated. When the memory bank 300 is activated, the memory block 10 will not activate many SAs, and the memory block 10 is in a standby state when it is not read, so that the power consumed is very low. Therefore, the tFAW specification is not required. In addition, all 8 memory banks 300 of the memory of the present invention can be used for interleaving operations, which increases the probability of seamless continuous 8-bit bursts to maintain the maximum data rate.
[0068] Preferably, the three LSBs (Least Significant Bits) of the column address: CA0, CA1 and CA2 are used to represent eight read data, and the higher three bits: CA3, CA4 and CA5 are used to represent eight memory blocks 10 in the memory block group 100.
[0069] The above describes the reading method of the memory bank interleaving pattern of the present invention. The writing method of the memory bank interleaving pattern of the present invention is similar to the reading method, and will not be described in detail here.
[0070] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any professional and technical personnel in the field may make various necessary changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the attached claims.
Claims
1. A data reading method of a memory bank interleaving pattern memory based on a storage block, characterized in that: include: The memory bank interleaving mode memory based on the memory block is provided, comprising: A plurality of memory bank groups (400) arranged in a vertical direction, a horizontal spacing area (302) being arranged between the memory bank groups (400), a plurality of data input / output interfaces (200) arranged in a horizontal direction being arranged in the horizontal spacing area (302), a vertical spacing area (301) being arranged in the middle of the memory bank groups (400) in a horizontal direction, and an address bus (104) extending in a vertical direction being arranged in the vertical spacing area (301); The memory bank group (400) comprises a plurality of memory banks (300) arranged in a vertical direction, each of the memory banks (300) comprising: a plurality of memory block groups (100) arranged in a horizontal direction, a predecoder (30) arranged in the vertical spacing area (301), the predecoder (30) being electrically connected to the plurality of memory block groups (100) via a predecoder line (102) extending in a horizontal direction, the predecoder line (102) being electrically connected to the address bus (104), the memory block group (100) of each memory bank (300) being electrically connected to the corresponding memory block group (100) of other memory banks (300) via a global data bus (103) extending in a vertical direction and the corresponding data input / output interface (200); The storage block group (100) comprises a plurality of storage blocks (10), the plurality of storage blocks (10) are electrically connected to a local data bus (101) and the pre-decoder line (102) respectively, and the local data bus (101) is electrically connected to the global data bus (103); The storage block (10) comprises: a row decoder, a column decoder, and a plurality of storage sub-blocks (11), wherein the number of storage sub-blocks (11) in each storage block (10) is equal to half of the burst length; The storage sub-block (11) comprises: a storage array (15), a first DC sense amplifier (12) electrically connected to the storage array (15), a second DC sense amplifier (22), a first write head (13) and a second write head (23), a first data latch (14) electrically connected to the first DC sense amplifier (12), the first write head (13) and the local data bus (101), respectively, and a second data latch (24) electrically connected to the second DC sense amplifier (22), the second write head (23) and the local data bus (101), respectively; The first DC sense amplifier (12), the first write head (13) and the first data latch (14) are arranged at the top of the storage array (15), and the second DC sense amplifier (22), the second write head (23) and the second data latch (24) are arranged at the bottom of the storage array (15); The memory bank activation step S100: sending row addresses to the plurality of memory banks (300) in sequence through the address bus (104), sending one row address every other burst time, and after receiving the row address, the memory bank (300) locks the row address in the pre-decoder (30); Address latching step S101: after the row address is sent, after a specific time, the column address is sent to the memory bank (300) through the address bus (104); after the memory bank (300) receives the column address, it latches the column address in the pre-decoder (30), and then transmits the row address and the column address to the corresponding memory block (10) of the memory bank (300) through the pre-decoder line (102); the memory block (10) latches the row address in the row decoder and latches the column address in the column decoder, and then the memory block (10) disconnects from the pre-decoder line (102); Data reading step S102: selecting the storage unit to be read according to the row address and the column address, the corresponding first DC sensing amplifier (12) or the second DC sensing amplifier (22) reading the read data stored in the selected storage unit, latching the read data in the corresponding first data latch (14) or the second data latch (24), and then sending the read data to the local data bus (101); Standby step S103: the storage block (10) reconnects to the pre-decoder line (102), enters a standby state, and waits for the pre-decoder line (102) to transmit the next row address and the column address; Transmission step S104: transmitting the read data to the data input-output interface (200) via the local data bus (101) and the global data bus (103).
2. The data reading method of the memory bank interleaving pattern memory based on the memory block according to claim 1, characterized in that: In the standby step S103, the row address and the column address latched in the row decoder and the column decoder of the storage block (10) are released, and the row address latched in the pre-decoder (30) of the storage bank (300) is not released.
3. The data reading method of the memory bank interleaving pattern memory based on the memory block according to claim 1, characterized in that: The three least significant bits of the column address are used to represent the read data, and the three higher significant bits are used to represent a memory block (10) in the memory block group (100).
4. The data reading method of the memory bank interleaving pattern memory based on the memory block according to claim 1, characterized in that: The storage block (10) further comprises: a plurality of word lines, a plurality of first bit lines, a plurality of second bit lines, a control circuit and a timing circuit. The memory cells in each row of the memory array (15) are electrically connected to one of the word lines, and the memory cells in each column are electrically connected to one of the first bit lines or one of the second bit lines; The first bit line and the second bit line are arranged at intervals, the first bit line is electrically connected to the first DC sensing amplifier (12) and the first write head (13), and the second bit line is electrically connected to the second DC sensing amplifier (22) and the second write head (23); The row decoder is electrically connected to the plurality of word lines and is used to select the word line according to the row address transmitted from the pre-decoder line (102); The column decoder is electrically connected to the plurality of first bit lines and the plurality of second bit lines, and is used to select the first bit line or the second bit line according to the column address transmitted by the pre-decoder line (102); The memory cell to be read or the memory cell to be written is selected according to the selected word line and the first bit line or the second bit line.